TWI654725B - Package with a film adhered on a die for reducing stress borne by the die - Google Patents
Package with a film adhered on a die for reducing stress borne by the dieInfo
- Publication number
- TWI654725B TWI654725B TW106114580A TW106114580A TWI654725B TW I654725 B TWI654725 B TW I654725B TW 106114580 A TW106114580 A TW 106114580A TW 106114580 A TW106114580 A TW 106114580A TW I654725 B TWI654725 B TW I654725B
- Authority
- TW
- Taiwan
- Prior art keywords
- die
- conductive
- substrate
- film
- package structure
- Prior art date
Links
Abstract
一種封裝結構，包含一第一晶粒、一第一薄膜、一第二晶粒、一第二薄膜、一導電凸塊及一封膠層。該第一晶粒可包含一第一面、一第二面、及一導電腳位，形成於該第一晶粒之該第二面。該第一薄膜係耦接於該第一晶粒之該第一面，以減低該第一晶粒承受之應力。該第二晶粒可包含一第一面、一第二面及一導電腳位，形成於該第二晶粒之該第一面。該第二薄膜係耦接於該第二晶粒之該第二面。該導電凸塊可設置於該第一晶粒之該導電腳位及該第二晶粒之該導電腳位之間。該封膠層係形成以包覆該第一晶粒、該第一薄膜、該第二晶粒、該第二薄膜及該導電凸塊。A package structure includes a first die, a first film, a second die, a second film, a conductive bump, and an adhesive layer. The first die may include a first face, a second face, and a conductive pin formed on the second face of the first die. The first film is coupled to the first surface of the first die to reduce the stress on the first die. The second die may include a first face, a second face, and a conductive pin formed on the first face of the second die. The second film is coupled to the second surface of the second die. The conductive bumps may be disposed between the conductive pads of the first die and the conductive pins of the second die. The sealant layer is formed to cover the first die, the first film, the second die, the second film, and the conductive bump.
Description
本發明係關於一種封裝結構，尤指一種以薄膜黏附晶粒從而降低晶粒乘受之應力的封裝結構。The present invention relates to a package structure, and more particularly to a package structure in which a film is adhered to a film to reduce stress on the grain.
在封裝製程中，封膠（molding）係廣泛使用之程序，可固定且保護封裝結構之元件，例如晶粒（die）、導線、焊接凸塊（bump）等。封膠材料可例如為樹脂或塑化物，其起初可被加熱而成為液態，然後灌注於封裝結構中，直到包圍元件，最後凝固而形成封膠層。雖然封膠層可藉由包覆元件以達到保護之功效，但可靠度（reliability）仍是待解的問題。舉例而言，熱應力將導致封裝結構的可靠性下降。由於晶粒的熱膨脹係數（coefficients of thermal expansion，CTE）係相異於包圍晶粒的封膠層的熱膨脹係數，當溫度變化時，晶粒及封膠層之接觸面會產生熱應力。當此熱應力大於晶片可承受之強度，則晶粒可能受損。因此，本領域實須一解決方案，以改善封裝結構的可靠度。In the packaging process, molding is a widely used procedure for fixing and protecting components of the package structure, such as die, wires, bumps, and the like. The sealant material can be, for example, a resin or a plasticizer that can be initially heated to a liquid state and then poured into the package structure until it surrounds the component and finally solidifies to form a sealant layer. Although the sealant layer can achieve the protective effect by coating the component, reliability is still a problem to be solved. For example, thermal stress will result in a decrease in the reliability of the package structure. Since the coefficient of thermal expansion (CTE) of the crystal grain is different from the thermal expansion coefficient of the sealant layer surrounding the crystal grain, when the temperature changes, the contact surface of the crystal grain and the sealant layer generates thermal stress. When this thermal stress is greater than the strength that the wafer can withstand, the die may be damaged. Therefore, there is a need in the art for a solution to improve the reliability of the package structure.
本發明實施例提供一種封裝結構，包含一第一晶粒、一第一薄膜、一第二晶粒、一第二薄膜、一導電凸塊及一封膠層。該第一晶粒可包含一第一面、一第二面、及一導電腳位，該第一晶粒之該導電腳位係形成於該第一晶粒之該第二面。該第一薄膜係物理性耦接於該第一晶粒之該第一面，從而減低該第一晶粒承受之一應力。該第二晶粒可包含一第一面、一第二面及一第一導電腳位，該第二晶粒之該第一導電腳位係形成於該第二晶粒之該第一面。該第二薄膜係物理性耦接於該第二晶粒之該第二面。該導電凸塊可設置於該第一晶粒之該導電腳位及該第二晶粒之該第一導電腳位之間。該封膠層可用以包覆該第一晶粒、該第一薄膜、該第二晶粒、該第二薄膜及該導電凸塊。Embodiments of the present invention provide a package structure including a first die, a first film, a second die, a second film, a conductive bump, and an adhesive layer. The first die may include a first face, a second face, and a conductive pin. The conductive pin of the first die is formed on the second face of the first die. The first film is physically coupled to the first surface of the first die to reduce stress on the first die. The second die may include a first surface, a second surface, and a first conductive pin. The first conductive pin of the second die is formed on the first surface of the second die. The second film is physically coupled to the second side of the second die. The conductive bumps may be disposed between the conductive pads of the first die and the first conductive pin of the second die. The sealant layer can be used to coat the first die, the first film, the second die, the second film, and the conductive bump.
本發明另一實施例提供一種封裝結構，包含一晶粒、一薄膜、一基板、一導電凸塊、一封膠層。該晶粒可包含第一面、一第二面、及一導電腳位，該晶粒之該導電腳位係形成於該晶粒之該第二面。該薄膜係物理性耦接於該晶粒之該第一面，從而減低該晶粒承受之一應力。該基板可包含一第一面、一第二面，位於該基板之該第一面之對立位置、一電路結構，形成於該基板之該第一面及該基板之該第二面之間、及一導電介面，形成於該基板之該第一面，電連接於該基板之該電路結構。該導電凸塊可設置於該晶粒之該導電腳位及該基板之該導電介面之間。該封膠層可形成於該基板的該第一面，用以包覆該晶粒、該薄膜及該導電凸塊。Another embodiment of the present invention provides a package structure including a die, a film, a substrate, a conductive bump, and an adhesive layer. The die may include a first surface, a second surface, and a conductive pin. The conductive pin of the die is formed on the second side of the die. The film is physically coupled to the first side of the die to reduce stress on the die. The substrate may include a first surface and a second surface opposite to the first surface of the substrate, and a circuit structure formed between the first surface of the substrate and the second surface of the substrate. And a conductive interface formed on the first surface of the substrate and electrically connected to the circuit structure of the substrate. The conductive bumps may be disposed between the conductive pads of the die and the conductive interface of the substrate. The sealant layer may be formed on the first side of the substrate to cover the die, the film and the conductive bump.
第1圖係本發明實施例的封裝結構100之示意圖。封裝結構100可包含第一晶粒110、第一薄膜115、第二晶粒120、第二薄膜125、第一導電凸塊155及封膠層188。第一晶粒110可包含第一面110a、第二面110b、及導電腳位1101。導電腳位1101係形成於第一晶粒110之第二面110b。第一薄膜115可物理性耦接於第一晶粒110之第一面110a，從而減低第一晶粒110承受之應力。第二晶粒120可包含第一面120a、第二面120b及第一導電腳位1201，第一導電腳位1201可形成於第二晶粒120之第一面120a。第二薄膜125可物理性黏合於第二晶粒120之第二面120b。導電腳位1101可為輸入/輸出介面，用以存取第一晶粒110。導電腳位1201可為輸入/輸出（Input/Output，I/O）介面，用以存取第二晶粒120。第一導電凸塊155可設置於第一晶粒110之導電腳位1101及第二晶粒120之第一導電腳位1201之間，以使第一晶粒110電連接於第二晶粒120。封膠層188可用以包覆第一晶粒110、第一薄膜115、第二晶粒120、第二薄膜125及第一導電凸塊155。封膠層188之材質，可使用環氧模壓化合物（epoxy molding compound，EMC）或其他適宜之樹脂、塑化物、或樹脂及/或塑化物之合成材料等。1 is a schematic view of a package structure 100 in accordance with an embodiment of the present invention. The package structure 100 can include a first die 110, a first film 115, a second die 120, a second film 125, a first conductive bump 155, and a sealant layer 188. The first die 110 may include a first face 110a, a second face 110b, and a conductive pin 1101. The conductive pin 1101 is formed on the second face 110b of the first die 110. The first film 115 is physically coupled to the first surface 110a of the first die 110 to reduce the stress on the first die 110. The second die 120 may include a first surface 120a, a second surface 120b, and a first conductive pin 1201. The first conductive pin 1201 may be formed on the first surface 120a of the second die 120. The second film 125 can be physically bonded to the second surface 120b of the second die 120. The conductive pin 1101 can be an input/output interface for accessing the first die 110. The conductive pin 1201 can be an input/output (I/O) interface for accessing the second die 120. The first conductive bump 155 can be disposed between the conductive pin 1101 of the first die 110 and the first conductive pin 1201 of the second die 120 to electrically connect the first die 110 to the second die 120. . The sealant layer 188 can be used to coat the first die 110, the first film 115, the second die 120, the second film 125, and the first conductive bumps 155. As the material of the sealant layer 188, an epoxy molding compound (EMC) or other suitable resin, plastic compound, or a synthetic material of a resin and/or a plastic compound may be used.
如第1圖所示，當第一薄膜115黏附於第一晶粒110之第一面110a，第一薄膜115可位於第一晶粒110及封膠層188之間。第一薄膜115可作為緩衝層，吸收第一晶粒110及封膠層188之間不欲發生之熱應力。因此，第一晶粒110及封膠層188之間因溫度變化產生之熱應力可被減少。第一晶粒115與封膠層188相異的變形程度，可被第一薄膜115吸收。所述的應力可因第一晶粒110與封膠層188的熱膨脹係數及/或楊氏係數（Young’s modulus）相異而產生，此應力可被吸收、減緩。因此，第一晶粒110可被更佳地保護，而避免不欲發生之缺陷。As shown in FIG. 1 , when the first film 115 is adhered to the first surface 110 a of the first die 110 , the first film 115 may be located between the first die 110 and the sealant layer 188 . The first film 115 serves as a buffer layer and absorbs thermal stresses that are not to be generated between the first die 110 and the sealant layer 188. Therefore, the thermal stress generated by the temperature change between the first die 110 and the sealant layer 188 can be reduced. The degree of deformation of the first die 115 different from the sealant layer 188 can be absorbed by the first film 115. The stress may be generated by the difference in thermal expansion coefficient and/or Young's modulus of the first die 110 and the sealant layer 188, and the stress may be absorbed and slowed down. Therefore, the first die 110 can be better protected while avoiding defects that do not occur.
如第1圖所示，於封裝結構100中，第二晶粒120可另包含第二導電腳位1202。第二導電腳位1202可形成於第二晶粒120之第一面120a。相似於第一導電腳位1201，第二導電腳位1202可為存取第二晶粒120的輸入/輸出介面。封裝結構100可另包含基板130、第二導電凸塊156及導線166。基板130可包含第一面130a、第二面130b、電路結構130c、第一導電介面1301及第二導電介面1302。第二薄膜125可位於基板130之第一面130a。換言之，透過第一導電凸塊155電連接於第一晶粒110的第二晶粒120，可設置於第一面130a之上。電路結構130c可形成於基板130，舉例而言，當基板130係四層基板，電路結構130c可形成於基板130的四層結構。基板130之導電層中的至少一導電層，可於基板130之表層被佈局繞線。第一導電介面1301可形成於基板130之第一面130a，電連接於電路結構130c，以作為存取電路結構130c之輸入/輸出介面。每條導線166可連接第二晶粒120的一第二導電腳位1202及基板130的一第一導電介面1301，以形成第二晶粒120及基板130之間的通訊路徑。第二導電介面1302可形成於基板130的第二面130b，且電連接於電路結構130c。第二導電凸塊156可被焊接於第二導電介面1302。防焊層130sr可用以保護基板130，以避免基板130氧化，且可防止不欲發生之焊橋結構形成於複數個第二導電介面1302之間，造成錯誤之電連接路徑。As shown in FIG. 1 , in the package structure 100 , the second die 120 may further include a second conductive pin 1202 . The second conductive pin 1202 can be formed on the first face 120a of the second die 120. Similar to the first conductive pin 1201, the second conductive pin 1202 can be an input/output interface for accessing the second die 120. The package structure 100 can further include a substrate 130, a second conductive bump 156, and a wire 166. The substrate 130 can include a first surface 130a, a second surface 130b, a circuit structure 130c, a first conductive interface 1301, and a second conductive interface 1302. The second film 125 can be located on the first side 130a of the substrate 130. In other words, the second die 120 electrically connected to the first die 110 through the first conductive bump 155 may be disposed on the first face 130a. The circuit structure 130c may be formed on the substrate 130. For example, when the substrate 130 is a four-layer substrate, the circuit structure 130c may be formed in a four-layer structure of the substrate 130. At least one of the conductive layers of the substrate 130 may be laid on the surface of the substrate 130. The first conductive interface 1301 can be formed on the first surface 130a of the substrate 130 and electrically connected to the circuit structure 130c to serve as an input/output interface of the access circuit structure 130c. Each of the wires 166 can connect a second conductive pin 1202 of the second die 120 and a first conductive interface 1301 of the substrate 130 to form a communication path between the second die 120 and the substrate 130. The second conductive interface 1302 can be formed on the second surface 130b of the substrate 130 and electrically connected to the circuit structure 130c. The second conductive bump 156 can be soldered to the second conductive interface 1302. The solder resist layer 130sr can be used to protect the substrate 130 from oxidation of the substrate 130, and can prevent the undesired solder bridge structure from being formed between the plurality of second conductive interfaces 1302, resulting in an erroneous electrical connection path.
第二導電凸塊150可用以電連接外部裝置，以使外部裝置透過第二導電凸塊150存取第一晶粒110、第二晶粒120及電路結構130c。The second conductive bump 150 can be used to electrically connect the external device, so that the external device accesses the first die 110, the second die 120, and the circuit structure 130c through the second conductive bump 150.
根據本案之一實施例，一第二導電介面1302可對應於一第一導電介面1301。一對相互對應之第一導電介面1301及第二導電介面1302可彼此電連接。根據另一實施例，一第二導電介面1302可電連接於多個第一導電介面1301。此可根據基板130之架構而定。According to an embodiment of the present disclosure, a second conductive interface 1302 may correspond to a first conductive interface 1301. A pair of mutually corresponding first conductive interfaces 1301 and second conductive interfaces 1302 are electrically connectable to each other. According to another embodiment, a second conductive interface 1302 can be electrically connected to the plurality of first conductive interfaces 1301. This may depend on the architecture of the substrate 130.
所述的導電腳位1101、第一導電腳位1201、第二導電腳位1202、第一導電介面1301及第二導電介面1302，於第1圖中，係繪示為凸出於第一晶粒110、第二晶粒120及基板130的表面。然而，此僅為示例圖，用以解釋封裝結構100的架構，而非用以限制本發明的範圍。根據本發明實施例，導電腳位1101、第一導電腳位1201、第二導電腳位1202、第一導電介面1301及第二導電介面1302亦可被製造為平坦的導電部位，外露於第一晶粒110、第二晶粒120及基板130的表面。The conductive pin 1101, the first conductive pin 1201, the second conductive pin 1202, the first conductive interface 1301 and the second conductive interface 1302 are shown as protruding from the first crystal in FIG. The surface of the pellet 110, the second die 120, and the substrate 130. However, this is merely an example diagram to explain the architecture of the package structure 100, and is not intended to limit the scope of the invention. According to an embodiment of the invention, the conductive pin 1101, the first conductive pin 1201, the second conductive pin 1202, the first conductive interface 1301 and the second conductive interface 1302 can also be fabricated as a flat conductive portion, exposed to the first The surface of the die 110, the second die 120, and the substrate 130.
根據本發明實施例，第一薄膜115的厚度可介於5微米（micrometer）至50微米之間。第一薄膜115可採用晶粒黏附膜（die attach film，DAF）。因為第一薄膜115係作為緩衝層，故第一薄膜115相較於封膠層188及第一晶粒110可更柔軟及/或更具彈性，因此，第一薄膜115可具有比第一晶粒110及封膠層188更低的楊氏係數。此外，第一薄膜115可具有比第一晶粒110及封膠層188更低的熱膨脹係數。第一薄膜115從而可降低第一晶粒110及封膠層188之間，相異的熱膨脹程度或熱收縮程度造成的應力。由於第一晶粒110承受的非預期應力減少，故可改善封裝結構100的可靠度。According to an embodiment of the invention, the thickness of the first film 115 may range from 5 micrometers to 50 micrometers. The first film 115 may employ a die attach film (DAF). Because the first film 115 serves as a buffer layer, the first film 115 can be softer and/or more elastic than the sealant layer 188 and the first die 110. Therefore, the first film 115 can have a first crystal. The pellets 110 and the sealant layer 188 have a lower Young's modulus. In addition, the first film 115 may have a lower coefficient of thermal expansion than the first die 110 and the sealant layer 188. The first film 115 can thereby reduce the stress caused by the degree of thermal expansion or the degree of thermal contraction between the first die 110 and the sealant layer 188. Since the undesired stress experienced by the first die 110 is reduced, the reliability of the package structure 100 can be improved.
第2圖係本發明另一實施例之封裝結構200的示意圖。封裝結構200可包含晶粒210、薄膜215、基板230、導電凸塊255及封膠層288。晶粒210可相似於第1圖的第一晶粒110，基板230可相似於第1圖的基板130。因此，相關細節不另重述。與第1圖之封裝結構100相異的是，第2圖的封裝結構200可包含單一晶粒，而非多個晶粒。導電凸塊255可設置於晶粒210之導電腳位2101、及基板230之第一導電介面2301之間，以形成晶粒210及基板230之間的電連接路徑。形成於基板230的第一面230a的第一導電介面2301，可電連接於基板230的電路結構230c。基板230可包含第二導電介面2302。第二導電介面1302可形成於基板230之第二面230b，及電連接於電路結構230c。封裝結構200可另包含第二導電凸塊256，例如以焊接方式設置於第二導電介面2302，且用以電連接於外部裝置。防焊層230sr可用以保護基板230，以避免基板230氧化，且可防止不欲發生之焊橋結構形成於複數個第二導電介面2302之間，造成錯誤之電連接路徑。同理於封裝結構100，封裝結構200之晶粒210可能因晶粒210及封膠層288的熱膨脹係數及/或楊氏係數之差異，而被不欲發生之應力損毀。薄膜215可作為緩衝層，吸收應力並保護晶粒210不致破損。相似於第一薄膜115，薄膜215可為晶粒黏附膜，具有比晶粒210及封膠層288更低的楊氏係數及/或熱膨脹係數。2 is a schematic view of a package structure 200 in accordance with another embodiment of the present invention. The package structure 200 can include a die 210, a film 215, a substrate 230, a conductive bump 255, and a sealant layer 288. The die 210 may be similar to the first die 110 of FIG. 1, and the substrate 230 may be similar to the substrate 130 of FIG. Therefore, the relevant details are not repeated. Different from the package structure 100 of FIG. 1, the package structure 200 of FIG. 2 may comprise a single die instead of a plurality of die. The conductive bump 255 can be disposed between the conductive pin 2101 of the die 210 and the first conductive interface 2301 of the substrate 230 to form an electrical connection path between the die 210 and the substrate 230. The first conductive interface 2301 formed on the first surface 230a of the substrate 230 can be electrically connected to the circuit structure 230c of the substrate 230. The substrate 230 can include a second conductive interface 2302. The second conductive interface 1302 can be formed on the second surface 230b of the substrate 230 and electrically connected to the circuit structure 230c. The package structure 200 may further include a second conductive bump 256, for example, soldered to the second conductive interface 2302, and electrically connected to the external device. The solder resist layer 230sr can be used to protect the substrate 230 from oxidation of the substrate 230, and prevents the undesired solder bridge structure from being formed between the plurality of second conductive interfaces 2302, resulting in an erroneous electrical connection path. In the same manner as the package structure 100, the die 210 of the package structure 200 may be damaged by undesired stress due to the difference in thermal expansion coefficient and/or Young's modulus of the die 210 and the sealant layer 288. The film 215 acts as a buffer layer to absorb stress and protect the die 210 from damage. Similar to the first film 115, the film 215 can be a die attach film having a lower Young's modulus and/or thermal expansion coefficient than the die 210 and the sealant layer 288.
第3圖係本發明實施例之封裝方法300的流程圖。封裝方法300可用以形成封裝結構100。第4-11圖可對應於形成封裝結構100的製程步驟。封裝方法300可包含：FIG. 3 is a flow chart of a packaging method 300 of an embodiment of the present invention. Packaging method 300 can be used to form package structure 100. Figures 4-11 may correspond to the process steps of forming package structure 100. The encapsulation method 300 can include:
步驟305：焊接第一導電凸塊155至第一晶粒110的導電腳位1101；Step 305: soldering the first conductive bump 155 to the conductive pin 1101 of the first die 110;
步驟307：黏貼第一薄膜115至第一晶粒110的第一面110a，進入步驟340；Step 307: pasting the first film 115 to the first surface 110a of the first die 110, proceeds to step 340;
步驟310：黏貼第二薄膜125至第二晶粒120的第二面120b；Step 310: Adhering the second film 125 to the second surface 120b of the second die 120;
步驟320：將第二晶粒120設置於基板130的第一面130a；Step 320: The second die 120 is disposed on the first surface 130a of the substrate 130;
步驟330：將導線166打線連接於第二導電腳位1202及第一導電介面1301之間；Step 330: wire 166 is connected between the second conductive pin 1202 and the first conductive interface 1301;
步驟340：將第一導電凸塊155焊接於第二晶粒120的第一導電腳位1201，從而電連接第一晶粒110至第二晶粒120；Step 340: The first conductive bump 155 is soldered to the first conductive pin 1201 of the second die 120, thereby electrically connecting the first die 110 to the second die 120;
步驟350：注入封膠材料以形成封膠層188，封膠層188可包覆第一薄膜115、第一晶粒110、第一導電凸塊155、第二晶粒120及導線166；及Step 350: Injecting a sealing material to form a sealing layer 188, the sealing layer 188 may cover the first film 115, the first die 110, the first conductive bumps 155, the second die 120, and the wires 166;
步驟360：將第二導電凸塊156焊接於基板130之第二導電介面1302。Step 360: Solder the second conductive bump 156 to the second conductive interface 1302 of the substrate 130.
步驟305及307可對應於第4-5圖。步驟310-360可對應於第6-11圖。第3圖之順序僅為舉例，其他可製作封裝結構100的合理製程步驟順序，亦屬於本發明之範圍。Steps 305 and 307 may correspond to Figures 4-5. Steps 310-360 may correspond to Figures 6-11. The order of FIG. 3 is merely an example, and other sequences of suitable process steps for fabricating the package structure 100 are also within the scope of the present invention.
第12圖係本發明實施例之封裝方法1200的流程圖。封裝方法1200可用以形成封裝結構200。見第2、12圖，封裝方法1200可包含：Figure 12 is a flow diagram of a packaging method 1200 in accordance with an embodiment of the present invention. Packaging method 1200 can be used to form package structure 200. Referring to Figures 2 and 12, the packaging method 1200 can include:
步驟1210：將第一導電凸塊255焊接於晶粒220的導電接腳2101；Step 1210: soldering the first conductive bump 255 to the conductive pin 2101 of the die 220;
步驟1220：黏貼薄膜215於晶粒210的第一面210a；Step 1220: Adhesive film 215 on the first side 210a of the die 210;
步驟1230：將第一導電凸塊255焊接於基板230的第一導電介面2301，從而電連接晶粒220及基板230；Step 1230: The first conductive bump 255 is soldered to the first conductive interface 2301 of the substrate 230, thereby electrically connecting the die 220 and the substrate 230;
步驟1240：注入封膠材料以形成封膠層288，封膠層288可包覆薄膜215、晶粒210及第一導電凸塊255；及Step 1240: Injecting a sealing material to form a sealing layer 288, the sealing layer 288 can cover the film 215, the die 210, and the first conductive bump 255;
步驟1250：將第二導電凸塊256焊接於基板230的第二導電介面2302。Step 1250: Solder the second conductive bump 256 to the second conductive interface 2302 of the substrate 230.
綜上所述，經使用本發明實施例提供的封裝結構及封裝方法，可黏附薄膜於晶粒，此薄膜可位於晶粒與封膠層之間。肇因於相異的物理特性，例如熱膨脹係數及/或楊氏係數而產生的多餘應力可被有效地減低。晶粒可被更妥善地保護而避免被應力毀損，封裝結構的可靠度及良率均可改善。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。In summary, by using the package structure and the packaging method provided by the embodiments of the present invention, the film can be adhered to the die, and the film can be located between the die and the sealant layer.多余 Excessive stress due to different physical properties such as coefficient of thermal expansion and/or Young's modulus can be effectively reduced. The die can be better protected from stress damage and the reliability and yield of the package structure can be improved. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100、200‧‧‧封裝結構100,200‧‧‧Package structure
110‧‧‧第一晶粒110‧‧‧First grain
120‧‧‧第二晶粒120‧‧‧Second grain
130、230‧‧‧基板130, 230‧‧‧ substrate
110a、120a、130a、210a、230a‧‧‧第一面110a, 120a, 130a, 210a, 230a‧‧‧ first side
110b、120b、130b、230b‧‧‧第二面110b, 120b, 130b, 230b‧‧‧ second side
1101、2101‧‧‧導電腳位1101, 2101‧‧‧ conductive feet
1201‧‧‧第一導電腳位1201‧‧‧First conductive pin
1202‧‧‧第二導電腳位1202‧‧‧Second conductive pin
166‧‧‧導線166‧‧‧ wire
130c、230c‧‧‧電路結構130c, 230c‧‧‧ circuit structure
115‧‧‧第一薄膜115‧‧‧First film
125‧‧‧第二薄膜125‧‧‧Second film
188、288‧‧‧封膠層188, 288‧‧ ‧ sealant layer
1301、2301‧‧‧第一導電介面1301, 2301‧‧‧ first conductive interface
1302、2302‧‧‧第二導電介面1302, 2302‧‧‧ second conductive interface
155、255‧‧‧第一導電凸塊155, 255‧‧‧ first conductive bump
156、256‧‧‧第二導電凸塊156, 256‧‧‧ second conductive bump
130sr、230sr‧‧‧防焊層130sr, 230sr‧‧‧ solder mask
215‧‧‧薄膜215‧‧‧film
210‧‧‧晶粒210‧‧‧ grain
300、1200‧‧‧封裝方法300, 1200‧‧‧Packing method
305-360、1210-1250‧‧‧步驟 305-360, 1210-1250‧‧‧ steps
第1圖係本發明實施例的封裝結構之示意圖。 第2圖係本發明另一實施例之封裝結構的示意圖。 第3圖係本發明實施例中，形成第1圖的封裝結構之封裝方法的流程圖。 第4-11圖係對應於形成第1圖之封裝結構的製程示意圖。 第12圖係本發明實施例中，形成第2圖的封裝結構之封裝方法的流程圖。1 is a schematic view showing a package structure of an embodiment of the present invention. Figure 2 is a schematic illustration of a package structure in accordance with another embodiment of the present invention. Fig. 3 is a flow chart showing a method of packaging the package structure of Fig. 1 in the embodiment of the present invention. 4-11 are schematic views of a process corresponding to the package structure forming the first figure. Figure 12 is a flow chart showing a method of packaging the package structure of Figure 2 in the embodiment of the present invention.
Claims (8)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201615393225A | 2016-12-28 | 2016-12-28 | |
| US15/393,225 | 2016-12-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201836086A TW201836086A (en) | 2018-10-01 |
| TWI654725B true TWI654725B (en) | 2019-03-21 |
Family
ID=64797006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106114580A TWI654725B (en) | 2016-12-28 | 2017-05-03 | Package with a film adhered on a die for reducing stress borne by the die |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI654725B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200843066A (en) | 2007-04-30 | 2008-11-01 | Chipmos Technologies Inc | Chip stacked package structure and applications thereof |
| US20100102435A1 (en) | 2008-10-28 | 2010-04-29 | Advanced Micro Devices, Inc. | Method and apparatus for reducing semiconductor package tensile stress |
| TW201631735A (en) | 2014-12-04 | 2016-09-01 | 英帆薩斯公司 | Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies |
-
2017
- 2017-05-03 TW TW106114580A patent/TWI654725B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200843066A (en) | 2007-04-30 | 2008-11-01 | Chipmos Technologies Inc | Chip stacked package structure and applications thereof |
| US20100102435A1 (en) | 2008-10-28 | 2010-04-29 | Advanced Micro Devices, Inc. | Method and apparatus for reducing semiconductor package tensile stress |
| TW201631735A (en) | 2014-12-04 | 2016-09-01 | 英帆薩斯公司 | Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201836086A (en) | 2018-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107742630B (en) | Image sensor packaging structure | |
| JP4705784B2 (en) | Manufacturing method of image sensor device | |
| US6455354B1 (en) | Method of fabricating tape attachment chip-on-board assemblies | |
| KR101398404B1 (en) | Plastic overmolded packages with mechanically decoupled lid attach attachment | |
| US10170508B2 (en) | Optical package structure | |
| US11031356B2 (en) | Semiconductor package structure for improving die warpage and manufacturing method thereof | |
| US8664775B2 (en) | Semiconductor device | |
| TWI648848B (en) | Optical component package structure | |
| TWI654725B (en) | Package with a film adhered on a die for reducing stress borne by the die | |
| TW202109776A (en) | Fan-out semiconductor package structure and packaging method thereof | |
| WO2006079104A2 (en) | Encapsulation of circuit components to reduce thermal cycling stress | |
| TWI546914B (en) | Partial glob-top encapsulation technique | |
| JP3568402B2 (en) | Semiconductor device | |
| TW591727B (en) | Method for producing a protection for chip edges and arrangement for the protection of chip edges | |
| JPH03201463A (en) | Post-mold cavity type package for integrated circuit having internal dam bar | |
| KR100766498B1 (en) | Semiconductor package and method for manufacturing the same | |
| JPH0345542B2 (en) | ||
| CN108321142A (en) | Semiconductor package part and its manufacturing method | |
| US20220148955A1 (en) | Semiconductor package | |
| KR20070007607A (en) | Resin molding type bga package having solder resist dam | |
| JP2003051511A (en) | Semiconductor device and method of manufacturing it | |
| TWI591707B (en) | Packaging structure for thin die and method for manufacturing the same | |
| JP2009152341A (en) | Semiconductor device | |
| CN105072826A (en) | Printed circuit board, manufacturing method thereof, and method for manufacturing semiconductor packaging piece | |
| KR100468024B1 (en) | Loc package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |