TWI654676B - Method of forming semiconductor device - Google Patents
Method of forming semiconductor deviceInfo
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Abstract
一種半導體元件的製造方法。提供已形成有第一導體層的基底，且第一導體層具有至少一開口。於第一導體層上形成第一介電層，且第一介電層順應地覆蓋開口的表面。對第一介電層進行削角步驟，削去位於開口的頂角的第一介電層的一部分，且所述部分以間隙壁形式留在開口的側壁上。於第一介電層上形成第二介電層。對第二介電層進行回蝕刻步驟。 A method of manufacturing a semiconductor device. A substrate having a first conductor layer formed thereon is provided, and the first conductor layer has at least one opening. A first dielectric layer is formed on the first conductor layer, and the first dielectric layer conformably covers the surface of the opening. A chamfering step is performed on the first dielectric layer, a portion of the first dielectric layer at the top corner of the opening is cut away, and the portion remains as a spacer on the sidewall of the opening. A second dielectric layer is formed on the first dielectric layer. An etch back step is performed on the second dielectric layer.
Description
本發明是有關於一種積體電路的製造方法，且特別是有關於一種半導體元件的製造方法。 The present invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a semiconductor device.
半導體製程中，密集區與周邊區的層間介電層常會產生相當大的厚度差異，而輪廓高低起伏(topography)的變化，將導致十分嚴重的問題，例如最上層金屬層的頸縮現象(necking)。 In the semiconductor process, the interlayer dielectric layer between the dense region and the peripheral region often produces a considerable thickness difference, and the change in the topography of the contour will cause very serious problems, such as necking of the uppermost metal layer (necking) ).
圖1為習知的一種半導體元件的掃描式電子顯微鏡(SEM)影像。如圖1所示，當於基底10上的第一金屬層11上形成層間介電層12時，由於輪廓高低起伏的變化，層間介電層12於第一金屬層11的開口13處無法完全填入，因此會於開口處形成V形輪廓。此種V行輪廓會影響後續第二金屬層14與於其上方光阻層16的填入效果，因而會於開口13處產生孔隙17。因此，當以光阻層16為罩幕，對第二金屬層14進行濕蝕刻時，蝕刻液會滲入孔隙17，使得第二金屬層14於開口13處發生頸縮甚至斷裂現象。 1 is a scanning electron microscope (SEM) image of a conventional semiconductor device. As shown in FIG. 1, when the interlayer dielectric layer 12 is formed on the first metal layer 11 on the substrate 10, the interlayer dielectric layer 12 cannot be completely formed at the opening 13 of the first metal layer 11 due to the variation of the contour height fluctuation. Fill in, thus forming a V-shaped profile at the opening. Such a V-line profile affects the subsequent filling effect of the second metal layer 14 and the photoresist layer 16 thereover, thereby creating voids 17 at the opening 13. Therefore, when the second metal layer 14 is wet-etched with the photoresist layer 16 as a mask, the etching liquid penetrates into the pores 17, so that the second metal layer 14 is necked or even broken at the opening 13.
有鑒於此，本發明提供一種半導體元件的製造方法，可避免習知的層間介電層因填入效果不佳而造成的V行輪廓，進而避免後續金屬層的頸縮現象。 In view of the above, the present invention provides a method for fabricating a semiconductor device, which can avoid the V-line profile caused by the poor interlayer filling effect of the conventional interlayer dielectric layer, thereby avoiding the necking phenomenon of the subsequent metal layer.
本發明提供一種半導體元件的製造方法。提供已形成有第一導體層的基底，且第一導體層具有至少一開口。於第一導體層上形成第一介電層，且第一介電層順應地覆蓋開口的表面。以惰性氣體對第一介電層進行第一處理步驟。於第一介電層上形成第二介電層。對第二介電層進行第二處理步驟，且第二處理步驟不使用含氫氣體。 The present invention provides a method of manufacturing a semiconductor device. A substrate having a first conductor layer formed thereon is provided, and the first conductor layer has at least one opening. A first dielectric layer is formed on the first conductor layer, and the first dielectric layer conformably covers the surface of the opening. The first dielectric layer is subjected to a first processing step with an inert gas. A second dielectric layer is formed on the first dielectric layer. A second processing step is performed on the second dielectric layer, and the second processing step does not use a hydrogen containing gas.
在本發明的一實施例中，上述第一處理步驟削去位於開口的頂角處的第一介電層的一部分。 In an embodiment of the invention, the first processing step removes a portion of the first dielectric layer at the top corner of the opening.
在本發明的一實施例中，上述惰性氣體包括氦氣(He)、氖氣(Ne)、氬氣(Ar)、氮氣(N2)或其組合。 In an embodiment of the invention, the inert gas includes helium (He), helium (Ne), argon (Ar), nitrogen (N 2 ), or a combination thereof.
在本發明的一實施例中，上述第二處理步驟所使用的氣體包括氧氣與氟烴氣體CxFy，其中x與y均大於零。 In an embodiment of the invention, the gas used in the second processing step comprises oxygen and a fluorocarbon gas C x F y , wherein x and y are both greater than zero.
在本發明的一實施例中，上述氧氣與氟烴氣體CxFy的流量比為約1：1至1：20之間。 In an embodiment of the invention, the flow ratio of the oxygen to the fluorocarbon gas C x F y is between about 1:1 and 1:20.
在本發明的一實施例中，上述開口的深寬比為約1：5至10：1之間。 In an embodiment of the invention, the opening has an aspect ratio of between about 1:5 and 10:1.
在本發明的一實施例中，形成上述第一導體層的步驟包括：於基底上依序形成第一導體材料層以及第一圖案化光阻層；以及以第一圖案化光阻層為罩幕，對第一導體材料層進行乾蝕刻步驟。 In an embodiment of the invention, the step of forming the first conductive layer comprises: sequentially forming a first conductive material layer and a first patterned photoresist layer on the substrate; and masking the first patterned photoresist layer The curtain performs a dry etching step on the first conductor material layer.
在本發明的一實施例中，於第二處理步驟之後，上述方法更包括：於第二介電層上依序形成第二導體材料層以及第二圖案化光阻層；以及以第二圖案化光阻層為罩幕，對第二導體材料層進行濕蝕刻步驟。 In an embodiment of the invention, after the second processing step, the method further includes: sequentially forming a second conductive material layer and a second patterned photoresist layer on the second dielectric layer; and forming the second pattern The photoresist layer is a mask, and the second conductor material layer is subjected to a wet etching step.
在本發明的一實施例中，上述第二導體材料層的材料包括金屬。 In an embodiment of the invention, the material of the second conductive material layer comprises a metal.
本發明另提供一種半導體元件的製造方法。提供已形成有第一導體層的基底，且第一導體層具有至少一開口。於第一導體層上形成第一介電層，且第一介電層順應地覆蓋開口的表面。對第一介電層進行削角步驟，削去位於開口的頂角的第一介電層的一部分，且所述部分以間隙壁形式留在開口的側壁上。於第一介電層上形成第二介電層。對第二介電層進行回蝕刻步驟。 The present invention further provides a method of fabricating a semiconductor device. A substrate having a first conductor layer formed thereon is provided, and the first conductor layer has at least one opening. A first dielectric layer is formed on the first conductor layer, and the first dielectric layer conformably covers the surface of the opening. A chamfering step is performed on the first dielectric layer, a portion of the first dielectric layer at the top corner of the opening is cut away, and the portion remains as a spacer on the sidewall of the opening. A second dielectric layer is formed on the first dielectric layer. An etch back step is performed on the second dielectric layer.
在本發明的一實施例中，上述削角步驟所使用的氣體包括氦氣(He)、氖氣(Ne)、氬氣(Ar)、氮氣(N2)或其組合。 In an embodiment of the invention, the gas used in the chamfering step includes helium (He), helium (Ne), argon (Ar), nitrogen (N 2 ), or a combination thereof.
在本發明的一實施例中，上述回蝕刻步驟所使用的氣體包括氧氣與氟烴氣體CxFy，其中x與y均大於零。 In an embodiment of the invention, the gas used in the etch back step includes oxygen and a fluorocarbon gas C x F y , wherein x and y are both greater than zero.
在本發明的一實施例中，上述氧氣與氟烴氣體CxFy的流量比為約1：1至1：10之間。 In an embodiment of the invention, the flow ratio of the oxygen to the fluorocarbon gas C x F y is between about 1:1 and 1:10.
在本發明的一實施例中，上述開口的深寬比為約1：5至10：1之間。 In an embodiment of the invention, the opening has an aspect ratio of between about 1:5 and 10:1.
在本發明的一實施例中，形成上述第一導體層的步驟包括：於基底上依序形成第一導體材料層以及第一圖案化光阻層；以及以第一圖案化光阻層為罩幕，對第一導體材料層進行乾蝕刻步驟。 In an embodiment of the invention, the step of forming the first conductive layer comprises: sequentially forming a first conductive material layer and a first patterned photoresist layer on the substrate; and masking the first patterned photoresist layer The curtain performs a dry etching step on the first conductor material layer.
在本發明的一實施例中，於回蝕刻步驟之後，上述方法更包括：於第二介電層上依序形成第二導體材料層以及第二圖案化光阻層；以及以第二圖案化光阻層為罩幕，對第二導體材料層進行濕蝕刻步驟。 In an embodiment of the invention, after the etch back step, the method further includes sequentially forming a second conductive material layer and a second patterned photoresist layer on the second dielectric layer; and patterning the second The photoresist layer is a mask, and the second conductor material layer is subjected to a wet etching step.
在本發明的一實施例中，上述第二導體材料層的材料包括金屬。 In an embodiment of the invention, the material of the second conductive material layer comprises a metal.
基於上述，在本發明的方法中，利用削角步驟使得位於下層導體層之開口頂角處的第一介電層圓化，因而後續的第二介電層可輕易地填滿開口而不會產生習知的孔隙或孔洞缺陷。以此方式，可避免後續上層導體層的頸縮現象，進而提升元件的效能。 Based on the above, in the method of the present invention, the first dielectric layer located at the top corner of the opening of the lower conductor layer is rounded by the chamfering step, so that the subsequent second dielectric layer can easily fill the opening without Produces conventional pore or void defects. In this way, the necking of the subsequent upper conductor layer can be avoided, thereby improving the performance of the component.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
10‧‧‧基底 10‧‧‧Base
11‧‧‧第一金屬層 11‧‧‧First metal layer
12‧‧‧層間介電層 12‧‧‧Interlayer dielectric layer
13‧‧‧開口 13‧‧‧ openings
14‧‧‧第二金屬層 14‧‧‧Second metal layer
16‧‧‧光阻層 16‧‧‧ photoresist layer
17‧‧‧孔隙 17‧‧‧ pores
100‧‧‧基底 100‧‧‧Base
102‧‧‧第一導體層 102‧‧‧First conductor layer
103‧‧‧開口 103‧‧‧ openings
104‧‧‧第一介電層 104‧‧‧First dielectric layer
104a‧‧‧經處理的第一介電層 104a‧‧‧Processed first dielectric layer
105‧‧‧部分 105‧‧‧Parts
106‧‧‧第一處理步驟 106‧‧‧First processing steps
108‧‧‧第二介電層 108‧‧‧Second dielectric layer
108a‧‧‧經處理的第二介電層 108a‧‧‧Processed second dielectric layer
110‧‧‧第二處理步驟 110‧‧‧Second processing steps
112‧‧‧第二導體層 112‧‧‧Second conductor layer
S200~S208‧‧‧步驟 S200~S208‧‧‧Steps
圖1為習知的一種半導體元件的掃描式電子顯微鏡(SEM)影像。 1 is a scanning electron microscope (SEM) image of a conventional semiconductor device.
圖2A至圖2E為依照本發明的一實施例所繪示的一種半導體元件的製造方法的剖面示意圖。 2A-2E are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the invention.
圖3為依照本發明的一實施例所繪示的一種半導體元件的製造方法的流程圖。 3 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the invention.
圖2A至圖2E為依照本發明的一實施例所繪示的一種半 導體元件的製造方法的剖面示意圖。 2A to 2E illustrate a half according to an embodiment of the invention. A schematic cross-sectional view of a method of manufacturing a conductor element.
首先，請參照圖2A，提供基底100。基底100上已形成有第一導體層102，且第一導體層102具有至少一開口103。基底100可為半導體基底，例如含矽基底。第一導體層102的形成方法包括於基底100上先形成第一導體材料層與第一圖案化光阻層。在一實施例中，第一導體材料層的材料包括金屬或金屬矽化物，如鋁、銅、鎢、鎳、鈷、鈦、鈦化鎢、氮化鈦、氮化鉭、矽化鈦、矽化鉭、矽化鎳、矽化鈷或其組合。在另一實施例中，第一導體材料層的材料包括摻雜多晶矽。此外，第一導體材料層的形成方法包括進行合適的沉積製程，如化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程或原子層沉積(ALD)製程等等。接著，以第一圖案化光阻層為罩幕，對第一導體材料層進行乾蝕刻步驟，以形成具有至少一開口103的第一導體層102。在一實施例中，第一導體層102具有交替配置的多條第一導線與多個開口103，且第一導線沿第一方向延伸。此外，開口103的深寬比可介於約1：5(1/5)至10：1(1/0.1)之間，例如約1：2(1/2)。在一實施例中，第一導體層102的厚度例如為約1微米，且開口103的寬度例如為約2微米，但本發明並不以此為限。 First, referring to FIG. 2A, a substrate 100 is provided. A first conductor layer 102 has been formed on the substrate 100, and the first conductor layer 102 has at least one opening 103. Substrate 100 can be a semiconductor substrate, such as a germanium containing substrate. The method of forming the first conductor layer 102 includes first forming a first conductive material layer and a first patterned photoresist layer on the substrate 100. In an embodiment, the material of the first conductive material layer comprises a metal or a metal halide such as aluminum, copper, tungsten, nickel, cobalt, titanium, tungsten titanate, titanium nitride, tantalum nitride, titanium telluride, tantalum telluride , nickel telluride, cobalt telluride or a combination thereof. In another embodiment, the material of the first layer of conductor material comprises doped polysilicon. In addition, the method of forming the first conductive material layer includes performing a suitable deposition process such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. Next, the first patterned material layer is subjected to a dry etching step using the first patterned photoresist layer as a mask to form the first conductor layer 102 having at least one opening 103. In an embodiment, the first conductor layer 102 has a plurality of first wires and a plurality of openings 103 alternately arranged, and the first wires extend in the first direction. Further, the aspect ratio of the opening 103 may be between about 1:5 (1/5) to 10:1 (1/0.1), for example about 1:2 (1/2). In one embodiment, the thickness of the first conductor layer 102 is, for example, about 1 micrometer, and the width of the opening 103 is, for example, about 2 micrometers, but the invention is not limited thereto.
在一實施例中，基底100與第一導體層102之間還可配置有閘極、接觸窗、絕緣層等本領域具有通常知識者所熟知的構件，然而為了清楚說明起見，並未繪示於圖示中。 In an embodiment, a gate, a contact window, an insulating layer, etc., which are well known to those skilled in the art, may be disposed between the substrate 100 and the first conductor layer 102. However, for the sake of clarity, it is not depicted. Shown in the illustration.
請繼續參照圖2A，於第一導體層102上形成第一介電層104。第一介電層104順應地覆蓋開口103的表面以及第一導體層102的頂面。第一介電層104的材料包括四乙氧基矽氧烷形成的二 氧化矽(TEOS-SiO2)、硼磷矽玻璃(BPSG)、磷矽玻璃(PSG)、氫化矽倍半氧化物(HSQ)、氟矽玻璃(FSG)、無摻雜矽玻璃(USG)、氮化矽、氮氧化矽、介電常數小於4的低介電材料或其組合。第一介電層104的形成方法包括進行合適的沉積製程，如化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程或原子層沉積(ALD)製程等等。第一介電層104的厚度例如為約0.5微米，但本發明並不以此為限。 Referring to FIG. 2A, a first dielectric layer 104 is formed on the first conductor layer 102. The first dielectric layer 104 conformally covers the surface of the opening 103 and the top surface of the first conductor layer 102. The material of the first dielectric layer 104 includes cerium oxide (TEOS-SiO 2 ), borophosphoquinone glass (BPSG), phosphorous bismuth glass (PSG), hydrogenated sesquioxide sesquioxide formed by tetraethoxy siloxane. HSQ), fluorocarbon glass (FSG), undoped bismuth glass (USG), tantalum nitride, bismuth oxynitride, low dielectric materials having a dielectric constant of less than 4, or combinations thereof. The method of forming the first dielectric layer 104 includes performing a suitable deposition process such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. The thickness of the first dielectric layer 104 is, for example, about 0.5 micrometers, but the invention is not limited thereto.
接著，請參照圖2B，以惰性氣體對第一介電層104進行第一處理步驟106。惰性氣體包括氦氣(He)、氖氣(Ne)、氬氣(Ar)、氮氣(N2)或其組合。在一實施例中，惰性氣體可為氬氣。具體言之，第一處理步驟106削去位於開口103的頂角處的第一介電層104的一部分105，且所述部分105以間隙壁形式留在開口103的側壁上，如圖2B所示。如上述所討論，由於間隙壁形式的所述部分105來自於第一介電層104，故部分105與第一介電層104/104a的材料相同。 Next, referring to FIG. 2B, the first dielectric layer 104 is subjected to a first processing step 106 with an inert gas. The inert gas includes helium (He), helium (Ne), argon (Ar), nitrogen (N 2 ), or a combination thereof. In an embodiment, the inert gas may be argon. Specifically, the first processing step 106 cuts off a portion 105 of the first dielectric layer 104 at the top corner of the opening 103, and the portion 105 remains as a spacer on the sidewall of the opening 103, as shown in FIG. 2B. Show. As discussed above, since the portion 105 in the form of a spacer is from the first dielectric layer 104, the portion 105 is the same material as the first dielectric layer 104/104a.
換言之，第一處理步驟106可視為第一介電層104的削角步驟，使位於開口103頂角處的第一介電層104圓化，以形成經處理的第一介電層104a(例如經圓化的第一介電層104a)，因而後續的第二介電層108可輕易地填滿開口103而不會產生習知的孔隙或孔洞缺陷。 In other words, the first processing step 106 can be considered as a chamfering step of the first dielectric layer 104, rounding the first dielectric layer 104 at the top corner of the opening 103 to form the processed first dielectric layer 104a (eg, The rounded first dielectric layer 104a), and thus the subsequent second dielectric layer 108, can easily fill the opening 103 without creating conventional void or void defects.
繼之，請參照圖2C，於經處理的第一介電層104a上形成第二介電層108。第二介電層108的材料包括四乙氧基矽氧烷形成的二氧化矽(TEOS-SiO2)、硼磷矽玻璃(BPSG)、磷矽玻璃(PSG)、氫化矽倍半氧化物(HSQ)、氟矽玻璃(FSG)、無摻雜矽玻璃 (USG)、氮化矽、氮氧化矽、介電常數小於4的低介電材料或其組合。第二介電層108的形成方法包括進行合適的沉積製程，如化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程或原子層沉積(ALD)製程等等。第二介電層108的厚度例如為約2.9微米，但本發明並不以此為限。 Next, referring to FIG. 2C, a second dielectric layer 108 is formed on the processed first dielectric layer 104a. The material of the second dielectric layer 108 includes cerium oxide (TEOS-SiO 2 ), bisphosphonium bismuth glass (BPSG), phosphoric bismuth glass (PSG), hydrogenated sesquioxide sesquioxide formed by tetraethoxy siloxane. HSQ), fluorocarbon glass (FSG), undoped bismuth glass (USG), tantalum nitride, bismuth oxynitride, low dielectric materials having a dielectric constant of less than 4, or combinations thereof. The method of forming the second dielectric layer 108 includes performing a suitable deposition process such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. The thickness of the second dielectric layer 108 is, for example, about 2.9 microns, but the invention is not limited thereto.
此外，第二介電層108與第一介電層104的材料可相同或不同。在一實施例中，第二介電層108與第一介電層104的材料不同，其中第二介電層108的材料為TEOS-SiO2而為與第一介電層104的材料為PSG，但本發明並不以此為限。 In addition, the materials of the second dielectric layer 108 and the first dielectric layer 104 may be the same or different. In one embodiment, the second dielectric layer 108 is different from the material of the first dielectric layer 104, wherein the material of the second dielectric layer 108 is TEOS-SiO 2 and the material of the first dielectric layer 104 is PSG. However, the invention is not limited thereto.
接下來，請參照圖2D，對第二介電層108進行第二處理步驟110。在一實施例中，第二處理步驟110例如是回蝕刻步驟，以移除部分第二介電層108，使經處理的第二介電層108a具有預定厚度。經蝕刻的第二介電層108a的厚度例如為約1.3微米，但本發明並不以此為限。經處理的第二介電層108a於開口103處具有U形的平滑輪廓，如圖2D所示。 Next, referring to FIG. 2D, a second processing step 110 is performed on the second dielectric layer 108. In an embodiment, the second processing step 110 is, for example, an etch back step to remove a portion of the second dielectric layer 108 such that the processed second dielectric layer 108a has a predetermined thickness. The thickness of the etched second dielectric layer 108a is, for example, about 1.3 microns, but the invention is not limited thereto. The treated second dielectric layer 108a has a U-shaped smooth profile at the opening 103, as shown in Figure 2D.
第二處理步驟110不使用含氫氣體，以避免含氫氣體在第二處理步驟110中產生聚合物等殘留物而影響蝕刻效能。在一實施例中，第二處理步驟110所使用的氣體包括氧氣與氟烴氣體CxFy，其中x與y均大於零，例如x是介於1~5之間的整數，y是介於4~8之間的整數。氟烴氣體CxFy可包括氟烷類、氟烯類或氟炔類氣體。此外，氧氣與氟烴氣體CxFy的流量比介於約1：1至1：20之間，例如約1：9。在一實施例中，第二處理步驟110所使用的氣體包括氧氣和四氟甲烷(CF4)，氧氣的流量為約10sccm，且四氟甲烷(CF4)的流量為約90sccm。 The second processing step 110 does not use a hydrogen-containing gas to prevent the hydrogen-containing gas from generating a residue such as a polymer in the second processing step 110 to affect the etching efficiency. In one embodiment, the gas used in the second processing step 110 includes oxygen and a fluorocarbon gas CxFy, wherein x and y are both greater than zero, for example, x is an integer between 1 and 5, and y is between 4 and 4. An integer between 8. The fluorocarbon gas C x F y may include a fluorocarbon, a fluoroolefin or a fluoroacetylene gas. Further, the flow ratio of oxygen to the fluorocarbon gas C x F y is between about 1:1 and 1:20, for example about 1:9. In one embodiment, the gas used in the second processing step 110 includes oxygen and tetrafluoromethane (CF 4 ), the flow rate of oxygen is about 10 sccm, and the flow rate of tetrafluoromethane (CF 4 ) is about 90 sccm.
然後，請參照圖2E，於經處理的第二介電層108a上形成第二導體層112。第二導體層112的形成方法包括以下步驟。首先，於經處理的第二介電層108a上依序形成第二導體材料層以及第二圖案化光阻層。在一實施例中，第二導體材料層的材料包括金屬，如鋁、銅、鎢、鎳、鈷、鈦或其合金，且其形成方法包括進行合適的沉積製程，如化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程或原子層沉積(ALD)製程等等。然後，以第二圖案化光阻層為罩幕，對第二導體材料層進行濕蝕刻步驟，以形成第二導體層112。濕蝕刻步驟的蝕刻液可包括鋁酸。第二導體層112的厚度例如為約1.6微米，但本發明並不以此為限。 Then, referring to FIG. 2E, a second conductor layer 112 is formed on the processed second dielectric layer 108a. The method of forming the second conductor layer 112 includes the following steps. First, a second conductive material layer and a second patterned photoresist layer are sequentially formed on the processed second dielectric layer 108a. In one embodiment, the material of the second layer of conductor material comprises a metal such as aluminum, copper, tungsten, nickel, cobalt, titanium or alloys thereof, and the method of forming comprises performing a suitable deposition process, such as chemical vapor deposition (CVD). Process, physical vapor deposition (PVD) process or atomic layer deposition (ALD) process, and the like. Then, the second patterned material layer is subjected to a wet etching step with the second patterned photoresist layer as a mask to form the second conductor layer 112. The etching solution of the wet etching step may include alumina acid. The thickness of the second conductor layer 112 is, for example, about 1.6 μm, but the invention is not limited thereto.
在一實施例中，第一導體層102具有多條沿第一方向延伸的第一導線，第二導體層112具有沿第二方向延伸的多條第二導線，且第一方向與第二方向不同，例如是彼此垂直。 In an embodiment, the first conductor layer 102 has a plurality of first wires extending in the first direction, and the second conductor layer 112 has a plurality of second wires extending in the second direction, and the first direction and the second direction Different, for example, are perpendicular to each other.
特別要注意的是，在本發明中，藉由對第一介電層104的第一處理步驟106(即削角步驟)，可使第一介電層104圓化而使得後續的第二介電層108a於開口103處具有U形的平滑輪廓。因此，後續的第二導體材料層與第二圖案化光阻層於開口103處亦具有平滑輪廓而非習知的V形輪廓，且開口103處未產生習知的孔隙或孔洞缺陷。因此，不會產生由於蝕刻液滲入孔隙而造成第二導體層112於開口103處的習知頸縮現象。 It is particularly noted that in the present invention, the first dielectric layer 104 can be rounded by the first processing step 106 of the first dielectric layer 104 (ie, the chamfering step) so that the subsequent second dielectric The electrical layer 108a has a U-shaped smooth profile at the opening 103. Thus, the subsequent second layer of conductor material and the second patterned photoresist layer also have a smooth profile at the opening 103 rather than the conventional V-shaped profile, and conventional apertures or void defects are not created at the opening 103. Therefore, the conventional necking phenomenon of the second conductor layer 112 at the opening 103 due to the penetration of the etching liquid into the pores does not occur.
此外，本發明所提出之半導體元件的製造方法亦可參照圖3的流程圖以及圖2A至圖2D的剖面圖說明如下。 Further, the method of manufacturing the semiconductor device proposed by the present invention can also be explained as follows with reference to the flowchart of FIG. 3 and the cross-sectional views of FIGS. 2A to 2D.
首先，請參照圖3以及圖2A，進行步驟S200，提供基底100，基底100上已形成第一導體層102，且第一導體層102具有 至少一開口103。 First, referring to FIG. 3 and FIG. 2A, step S200 is performed to provide a substrate 100 on which a first conductor layer 102 has been formed, and the first conductor layer 102 has At least one opening 103.
接著，進行步驟S202，於第一導體層102上形成第一介電層104，且第一介電層104順應地覆蓋開口103的表面。 Next, in step S202, a first dielectric layer 104 is formed on the first conductor layer 102, and the first dielectric layer 104 conformally covers the surface of the opening 103.
然後，請參照圖3以及圖2B，進行步驟S204，對第一介電層104進行削角步驟(即第一處理步驟106)，削去位於開口103的頂角處的第一介電層104的一部分105，且所述部分105以間隙壁形式留在開口103的側壁上。 Then, referring to FIG. 3 and FIG. 2B, step S204 is performed to perform a chamfering step on the first dielectric layer 104 (ie, the first processing step 106), and the first dielectric layer 104 located at the top corner of the opening 103 is removed. A portion 105 is present and the portion 105 remains in the form of a spacer on the sidewall of the opening 103.
繼之，請參照圖3以及圖2C，進行步驟S206，於第一介電層104a上形成第二介電層108。 Then, referring to FIG. 3 and FIG. 2C, step S206 is performed to form a second dielectric layer 108 on the first dielectric layer 104a.
接下來，請參照圖3以及圖2D，進行步驟S208，對第二介電層108進行回蝕刻步驟(即第二處理步驟110)。 Next, referring to FIG. 3 and FIG. 2D, step S208 is performed to perform an etch back step on the second dielectric layer 108 (ie, the second processing step 110).
在上述的實施例中，步驟S202與步驟S204各自僅進行一次之後，就進行步驟S206與步驟S208，然其僅僅是作為示範性說明，並不用以限定本發明。在另一實施例中，視製程需要，也可以進行兩次或多次的步驟S202與步驟S204之後，才進行步驟S206與步驟S208。 In the above-mentioned embodiment, after step S202 and step S204 are each performed only once, step S206 and step S208 are performed, which are merely exemplary and are not intended to limit the present invention. In another embodiment, step S206 and step S208 are performed only after step S202 and step S204 are performed two or more times as needed for the process.
舉例來說，進行步驟S202與步驟S204之後，可於第一介電層104a上形成第三介電層以及對第三介電層進行削角步驟，使得開口103之頂角處的介電層更加圓化，以利後續膜層的填入。待開口103之頂角處的介電層圓化至滿意程度時，方進行步驟S06以及步驟S208。 For example, after performing step S202 and step S204, a third dielectric layer may be formed on the first dielectric layer 104a and a third dielectric layer may be chamfered so that the dielectric layer at the top corner of the opening 103 It is more rounded to facilitate the filling of subsequent layers. When the dielectric layer at the top corner of the opening 103 is rounded to a satisfactory level, step S06 and step S208 are performed.
綜上所述，本發明的方法中，利用削角步驟使得位於下層導體層之開口頂角處的第一介電層圓化，因而後續的第二介電層可輕易地填滿開口而不會產生習知的孔隙或孔洞缺陷。以此方 式，當以濕蝕刻定義上層導體層(如厚度約1~3微米的最上層金屬層)時，不會產生由於蝕刻液滲入孔隙而造成上層導體層的習知頸縮現象，進而提升元件的效能。 In summary, in the method of the present invention, the first dielectric layer located at the top corner of the opening of the lower conductor layer is rounded by the chamfering step, so that the subsequent second dielectric layer can easily fill the opening without Conventional pore or void defects can occur. This side When the upper conductor layer (for example, the uppermost metal layer having a thickness of about 1 to 3 μm) is defined by wet etching, the conventional necking phenomenon of the upper conductor layer due to the penetration of the etching liquid into the pores is not generated, thereby improving the component. efficacy.
換言之，只要第一導體層具有開口，且第二導體層用濕蝕刻定義時，均可使用本發明的方法使第一導體層、第二導體層之間的介電層於開口處具有平滑的U形輪廓，因此所定義出的第二導體層不會發生習知的頸縮甚至斷裂現象。 In other words, as long as the first conductor layer has an opening and the second conductor layer is defined by wet etching, the method of the present invention can be used to make the dielectric layer between the first conductor layer and the second conductor layer smooth at the opening. The U-shaped profile, so that the defined second conductor layer does not suffer from conventional necking or even fracture.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
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| TW200623259A (en) | 2004-12-29 | 2006-07-01 | United Microelectronics Corp | Method for fabricating a dual damascene and polymer removal |
| TW201250864A (en) | 2008-10-24 | 2012-12-16 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
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| TW200623259A (en) | 2004-12-29 | 2006-07-01 | United Microelectronics Corp | Method for fabricating a dual damascene and polymer removal |
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