TWI652818B - Silicon carbide semiconductor element - Google Patents
Silicon carbide semiconductor element Download PDFInfo
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- TWI652818B TWI652818B TW106105440A TW106105440A TWI652818B TW I652818 B TWI652818 B TW I652818B TW 106105440 A TW106105440 A TW 106105440A TW 106105440 A TW106105440 A TW 106105440A TW I652818 B TWI652818 B TW I652818B
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- heavily doped
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- silicon carbide
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 31
- 230000005669 field effect Effects 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 86
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- -1 aluminum-silicon-copper Chemical compound 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- LKTZODAHLMBGLG-UHFFFAOYSA-N alumanylidynesilicon;$l^{2}-alumanylidenesilylidenealuminum Chemical compound [Si]#[Al].[Si]#[Al].[Al]=[Si]=[Al] LKTZODAHLMBGLG-UHFFFAOYSA-N 0.000 claims description 2
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 claims description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 9
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 6
- 150000004706 metal oxides Chemical class 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 210000004027 cell Anatomy 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 210000004508 polar body Anatomy 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
一種碳化矽半導體元件,利用一碳化矽基板形成一整合結構,該整合結構具有一金屬氧化物半導體場效應電晶體以及一反向並聯該金屬氧化物半導體場效應電晶體的接面能障蕭基二極體。A silicon carbide semiconductor device uses a silicon carbide substrate to form an integrated structure. The integrated structure has a metal oxide semiconductor field effect transistor and a junction energy barrier of the metal oxide semiconductor field effect transistor in antiparallel. Diode.
Description
本發明為有關一種碳化矽半導體元件,尤指一種低導通電阻比的碳化矽半導體元件。The invention relates to a silicon carbide semiconductor device, in particular to a silicon carbide semiconductor device with a low on-resistance ratio.
半導體功率元件在特性上,要求在設計的耐壓 (Breakdown voltage),應具備盡量小的導通電阻、低反向漏電流以及較快的開關速度,以減少操作時的導通損耗(Conduction loss)及切換損耗(Switching loss)。由於碳化矽(Silicon carbide,簡稱SiC)具有寬能隙(BandgapEg=3.26eV)、高臨界崩潰電場強度(2.2MV/cm)及高熱導係數(4.9W/cm-K)等特性,被認為是功率開關元件的極佳材料。而在相同崩潰電壓條件下,以碳化矽為基材製成之功率元件的耐壓層(低摻雜濃度之漂移層(Drift layer))厚度僅為矽(Si)功率元件厚度的十分之一;且理論上的導通電阻可達矽的數百分之一。In terms of characteristics, semiconductor power components are required to have a breakdown voltage that is designed to have as small an on-resistance, a low reverse leakage current, and a fast switching speed as possible to reduce the conduction loss and the conduction loss during operation. Switching loss. Because silicon carbide (SiC) has a wide energy gap (BandgapEg = 3.26eV), high critical collapse electric field strength (2.2MV / cm), and high thermal conductivity (4.9W / cm-K), it is considered to be Excellent material for power switching components. Under the same breakdown voltage condition, the thickness of the voltage-resistant layer (drift layer with low doping concentration) of the power device made of silicon carbide is only one tenth of the thickness of the silicon (Si) power device. One; and the theoretical on-resistance can reach several hundredths of silicon.
然而碳化矽因其寬能隙,使碳化矽金屬氧化物半導體場效電晶體(SiC MOSFET)之本體二極體(Body diode)導通之臨界電壓約為3V,造成切換時逆向電流回流時產生較大的功率損耗,且限制切換速度。除此之外,碳化矽在沉積漂移層時所產生的磊晶基面差排(Basal plane dislocation),在本體二極體導通時會因為載子的復合(Recombination)而擴張成堆積缺陷 (stacking fault),嚴重時會造成SiC MOSFET失效。因此半導體廠商在製作SiC MOSFET時,會多設計一顆並聯的蕭特基二極體(Schottky diode),以提高操作速度、降低切換損失並避免堆積缺陷擴張所造成的可靠度問題。However, due to its wide energy gap, the critical voltage at which the body diode of a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) is turned on is about 3V, which causes a relatively reverse current flow during switching. Large power loss and limited switching speed. In addition, the basal plane dislocation generated during the deposition of the drift layer in SiC will expand into stacking defects due to the recombination of carriers when the body diode is turned on. fault), which can cause SiC MOSFET failure. Therefore, when manufacturing a SiC MOSFET, a semiconductor manufacturer will design an additional Schottky diode in parallel to increase the operating speed, reduce switching losses, and avoid reliability problems caused by the expansion of stacked defects.
如中華民國發明專利公告第I521718號,提出一種接面位障蕭特基(JBS)二極體嵌於金氧半(MOS)場效電晶體單元陣列之整合元件,包括多個區域,每一區域包括:多數個MOS電晶體單元,其中相鄰的該些MOS電晶體以多數個分隔道分隔,其中一第一MOS電晶體單元與在第一方向上相鄰的一第二MOS電晶體單元之間以一第一分隔道分隔,且該第一MOS電晶體單元與在第二方向上相鄰的一第三MOS電晶體單元之間以一第二分隔道分隔,其中每一區之該些MOS電晶體單元包括多數個井區,其具有一第二導電型,相鄰的兩個井區之間以上述分隔道分隔;一漂移層,其具有一第一導電型,位於一基底上,該些井區位於該漂移層中;至少一JBS二極體,位於該第一分隔道與該第二分隔道的一交界處的該漂移層中,該JBS二極體與該第一、該第二以及該第三MOS電晶體單元反向並聯,其中至少該JBS二極體包括多個第一接面能障區域,具有第二導電型,位於該交界處的該漂移層之中,且該些第一接面能障區域延伸至該些井區的轉角之中;多數個源極區,具有該第一導電型,位於該些井區之中;多數個基本層,具有該第二導電型,位於該些井區之中的該些源極區內;以及多數個源極接觸窗,位於該些基本層與部分該些源極區上並與其電性連接;一第一陽極接觸窗,覆蓋部分該些第一接面能障區域與部分該漂移層,且與該些源極接觸窗及該些第一接面能障區域電性連接;以及一陰極,位於該漂移層下方的該基底中。For example, the Republic of China Invention Patent Bulletin No. I521718 proposes an integrated component of a junction barrier Schottky (JBS) diode embedded in a metal-oxide-semiconductor (MOS) field-effect transistor cell array, including multiple regions, each The area includes: a plurality of MOS transistor units, wherein the adjacent MOS transistors are separated by a plurality of dividing lines, and a first MOS transistor unit and a second MOS transistor unit adjacent in the first direction. The first MOS transistor unit and the third MOS transistor unit adjacent to each other in the second direction are separated by a first divided channel, and each region is separated by a second divided channel. These MOS transistor units include a plurality of well regions, which have a second conductivity type, and two adjacent well regions are separated by the above-mentioned separation lanes; a drift layer, which has a first conductivity type, is located on a substrate The well areas are located in the drift layer; at least one JBS diode is located in the drift layer at an interface between the first partition and the second partition, and the JBS diode and the first, The second and the third MOS transistor units are connected in antiparallel, where The JBS diode includes a plurality of first interface barrier regions having a second conductivity type and is located in the drift layer at the junction, and the first interface barrier regions extend to the well regions. In the corner; most of the source regions, having the first conductivity type, are located in the well areas; most of the basic layers, having the second conductivity type, are located in the source areas among the well areas Inside; and a plurality of source contact windows, which are located on and electrically connected to the base layers and part of the source regions; a first anode contact window covering part of the first interface barrier regions and part of the The drift layer is electrically connected to the source contact windows and the first interface barrier regions; and a cathode is located in the substrate below the drift layer.
又如中華民國發明專利公告第I352421號,係於 金氧半場效電晶體單元之外,額外設置面積以形成反向並聯之接面位障蕭特基二極體。Another example is the Republic of China Invention Patent Bulletin No. I352421, which is outside the metal-oxide half-field-effect transistor unit, and an additional area is provided to form an antiparallel junction barrier Schottky diode.
於以上先前技術之中,第I521718號專利之該JBS二極體係設置於該些MOS電晶體單元之間所形成的該交界處,換言之,該JBS二極體分別佔用該井區和該分隔道的一部分面積,此設置方式會讓每該MOS電晶體單元的通道寬度(Channel width,Wçh,單位μm)減少;而第I352421號專利則因需額外配置晶片面積給JBS,而該部分晶片面積並無電晶體導通所需要之通道;兩種方式皆會減少晶片每單位面積下的總通道寬度 (μm/cm2 ),造成流過該整合元件的電流密度降低,提高元件整體的導通電阻比(specific on-resistance,即導通電阻與晶片面積之乘積RA,(on-resistance)*(area),單位為mΩ.cm2 ),故有改善之處。In the above prior art, the JBS diode system of the No. I521718 patent is disposed at the junction formed between the MOS transistor units, in other words, the JBS diode occupies the well area and the divider, respectively. Part of the area, this setting method will reduce the channel width (Channel width, Wçh, unit μm) of each MOS transistor unit; while the patent No. I352421 requires additional allocation of chip area to JBS, and Channels required for non-transistor conduction; both methods will reduce the total channel width (μm / cm 2 ) per unit area of the chip, resulting in a reduction in the current density flowing through the integrated component and an increase in the specific on-resistance ratio of the component. On-resistance, which is the product of the on-resistance and the chip area RA, (on-resistance) * (area), the unit is mΩ.cm 2 ), so there is improvement.
本發明的主要目的,在於解決習知整合JBS二極體之碳化矽半導體元件需犧牲部分通道寬度以設置,進而造成導通電阻比較高的問題。The main purpose of the present invention is to solve the problem that the conventional silicon carbide semiconductor device integrated with JBS diodes needs to sacrifice part of the channel width to be set, thereby causing a relatively high on-resistance.
為達上述目的,本發明提供一種碳化矽半導體元件,包含一基板、一n型漂移層、複數個摻雜區域、一閘極介電層、一閘電極、一層間介電層、複數個源極開口、複數個接面開口、複數個閘極開口、一第一金屬層以及一第二金屬層,該基板具有一n型重摻雜,該n型漂移層設置於該基板上並具有一第一摻雜濃度,該摻雜區域間隔設置於該n型漂移層,該摻雜區域間形成一第一接面場效應區域,該摻雜區域包含有一p型井、複數個設置於該p型井中的n型重摻雜區、複數個鄰接該n型重摻雜區並與部分該p型井重疊的p型重摻雜區以及複數個由該p型井環繞的一第二接面場效應區域,該閘極介電層設置於該n型漂移層上,該閘電極設置於該閘極介電層上,該層間介電層設置於該閘極介電層與該閘電極上,該源極開口穿過該層間介電層與該閘極介電層直至接觸部分該n型重摻雜區與部分該p型重摻雜區,該接面開口穿過該層間介電層與該閘極介電層直至接觸該第二接面場效應區域、部分該p型井以及部分該p型重摻雜區,該閘極開口穿過該層間介電層至該閘電極,該第一金屬層設置於該源極開口的一底側並與部分該n型重摻雜區以及部分該p型重摻雜區形成一歐姆接觸,該第二金屬層包含一第一部分與一第二部分,該第一部分覆蓋該源極開口而與該第一金屬層電性連接,該第一部分覆蓋該接面開口而與該第二接面場效應區域形成一蕭基接觸,該第二部分覆蓋該閘極開口並與該第一部分電性絕緣。To achieve the above object, the present invention provides a silicon carbide semiconductor device including a substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an interlayer dielectric layer, and a plurality of sources. Electrode opening, a plurality of interface openings, a plurality of gate openings, a first metal layer and a second metal layer, the substrate has an n-type heavy doping, and the n-type drift layer is disposed on the substrate and has a A first doping concentration, the doped regions are spaced from the n-type drift layer, a first junction field effect region is formed between the doped regions, the doped region includes a p-type well, and a plurality of p-type wells are disposed on the p-type well; N-type heavily doped region in a type-type well, a plurality of p-type heavily-doped regions adjacent to the n-type heavily-doped region and overlapping with part of the p-type well, and a plurality of second junctions surrounded by the p-type well In a field effect region, the gate dielectric layer is disposed on the n-type drift layer, the gate electrode is disposed on the gate dielectric layer, and the interlayer dielectric layer is disposed on the gate dielectric layer and the gate electrode. , The source opening passes through the interlayer dielectric layer and the gate dielectric layer until a contact portion of the n-type The heavily doped region and part of the p-type heavily doped region, the junction opening passes through the interlayer dielectric layer and the gate dielectric layer until it contacts the second junction field effect region, part of the p-type well, and part In the p-type heavily doped region, the gate opening passes through the interlayer dielectric layer to the gate electrode, the first metal layer is disposed on a bottom side of the source opening and part of the n-type heavily doped region and Part of the p-type heavily doped region forms an ohmic contact. The second metal layer includes a first portion and a second portion. The first portion covers the source opening and is electrically connected to the first metal layer. The first portion Covering the junction opening to form a Schottky contact with the second junction field effect region, the second portion covers the gate opening and is electrically insulated from the first portion.
由以上可知,本發明相較於習知技藝可達到之功效在於,將該n型重摻雜區、該p型重摻雜區、該源極開口以及該接面開口分別對應地設置於同一個該p型井中,並非佔用該p型井和該第一接面場效應區域的部分面積,亦非額外配置晶片面積以形成蕭基二極體,因此,相較於傳統的該整合元件在面積相同的情況下,本案的該碳化矽半導體元件的總通道寬度不受影響,相對地,流過該碳化矽半導體元件的電流也不受影響而達到降低導通電阻比的功效。It can be known from the above that the effect that the present invention can achieve compared with the conventional technique is that the n-type heavily doped region, the p-type heavily doped region, the source opening, and the junction opening are respectively disposed in the same A p-type well does not occupy a part of the area of the p-type well and the first interface field effect area, nor does it additionally configure the chip area to form a Schottky diode. Therefore, compared with the traditional integrated component, When the area is the same, the total channel width of the silicon carbide semiconductor device in this case is not affected. In contrast, the current flowing through the silicon carbide semiconductor device is also not affected, and the effect of reducing the on-resistance ratio is achieved.
有關本發明的詳細說明及技術內容,現就配合圖式說明如下:The detailed description and technical contents of the present invention are described below with reference to the drawings:
請搭配參閱『圖1』至『圖3B』所示,分別為本發明的俯視示意圖、本發明一實施例中於『圖1』的X區域放大示意圖、於『圖2A』的X’區域放大示意圖、『圖2B』的A-A剖面示意圖、『圖2B』的B-B剖面示意圖、『圖2B』的C-C剖面示意圖、本發明一實施例中於『圖1』的Y區域放大示意圖以及『圖3A』的D-D剖面示意圖。本發明為一種碳化矽半導體元件,包含一基板10、一n型漂移層20、複數個摻雜區域30、一閘極介電層40、一閘電極50、一層間介電層60、複數個源極開口70、複數個接面開口80、複數個閘極開口90、一第一金屬層100以及一第二金屬層110。該基板10為一4H-碳化矽(4H-SiC)基板,於一實施例中,該基板10為一n型重摻雜且具有一小於0.3 Ω·cm的電阻率(Resistivity)。該n型漂移層20設置於該基板10上,於一實施例中,該n型漂移層20為一n型輕摻雜且具有一第一摻雜濃度,該第一摻雜濃度小於5E17 cm-3 ;於較佳實施例中,例如額定電壓為650V時,該第一摻雜濃度為1E16 cm-3 ,該n型漂移層20的厚度為5μm;例如額定電壓為1200V時,該第一摻雜濃度為6E15 cm-3 ,該n型漂移層20的厚度為11μm。Please refer to "Figure 1" to "Figure 3B" for a schematic plan view of the present invention, an enlarged schematic view of the X area in "Figure 1", and an enlarged view of the X 'area in "Figure 2A" in an embodiment of the present invention. Schematic diagram, AA cross-section schematic diagram of FIG. 2B, BB cross-sectional schematic diagram of FIG. 2B, CC cross-sectional schematic diagram of FIG. 2B, an enlarged schematic view of the Y region in FIG. 1 in an embodiment of the present invention, and FIG. 3A. DD section diagram. The invention is a silicon carbide semiconductor device, which comprises a substrate 10, an n-type drift layer 20, a plurality of doped regions 30, a gate dielectric layer 40, a gate electrode 50, an interlayer dielectric layer 60, and a plurality of The source opening 70, the plurality of interface openings 80, the plurality of gate openings 90, a first metal layer 100 and a second metal layer 110. The substrate 10 is a 4H-silicon carbide (4H-SiC) substrate. In one embodiment, the substrate 10 is an n-type heavily doped and has a resistivity of less than 0.3 Ω · cm. The n-type drift layer 20 is disposed on the substrate 10. In one embodiment, the n-type drift layer 20 is an n-type lightly doped and has a first doping concentration, and the first doping concentration is less than 5E17 cm. -3; in the preferred embodiment, for example, when the rated voltage is 650V, the first doping concentration of 1E16 cm -3, thickness 20 of the n-type drift layer is 5 m; for example, when the rated voltage of 1200V, the first The doping concentration is 6E15 cm -3 , and the thickness of the n-type drift layer 20 is 11 μm.
該摻雜區域30間隔設置於該n型漂移層20,且該些摻雜區域30間形成一第一接面場效應(Junction field effect)區域31,於一實施例中,該第一接面場效應區域31具有一第二摻雜濃度,該第二摻雜濃度小於1E18 cm-3 ;於較佳實施例,該第二摻雜濃度介於1E16 cm-3 至2E17 cm-3 之間。該摻雜區域30包含有一p型井32、複數個n型重摻雜區33、複數個p型重摻雜區34以及複數個第二接面場效應區域35。請參閱『圖2A』所示,該p型井32、該n型重摻雜區33、該p型重摻雜區34以及該第二接面場效應區域35的俯視形狀之一外輪廓可為正方形、長方形、六邊形或其組合,於本實施例中,該些外輪廓係以長方形作為舉例,該長方形的短軸平行於x軸,長軸平行於y軸。The doped regions 30 are disposed at intervals on the n-type drift layer 20, and a first junction field effect region 31 is formed between the doped regions 30. In an embodiment, the first junction FET region having a second doping concentration 31, the second dopant concentration is less than 1E18 cm -3; in the preferred embodiment, the second doping concentration of between 1E16 cm -3 to 2E17 cm -3. The doped region 30 includes a p-type well 32, a plurality of n-type heavily doped regions 33, a plurality of p-type heavily doped regions 34, and a plurality of second junction field effect regions 35. Please refer to “FIG. 2A”, an outer contour of one of the top shapes of the p-type well 32, the n-type heavily doped region 33, the p-type heavily doped region 34, and the second junction field effect region 35 may be It is a square, a rectangle, a hexagon, or a combination thereof. In this embodiment, the outer contours are exemplified by rectangles. The short axis of the rectangle is parallel to the x-axis, and the long axis is parallel to the y-axis.
請搭配參閱『圖2B』至『圖2E』所示,從俯視來看,該p型井32形成一長方環狀,該n型重摻雜區33設置於該p型井32中;該p型重摻雜區34鄰接該n型重摻雜區33並與部分的該p型井32重疊,該第二接面場效應區域35被該p型井32環繞,於一實施例中,該第二接面場效應區域35具有一第三摻雜濃度,該第三摻雜濃度小於1E18 cm-3 ;於較佳實施例,該第三摻雜濃度介於1E16 cm-3 至2E17 cm-3 之間。本實施例中,該第二接面場效應區域35的一部分係被該p型井32所環繞,另一部分鄰接該p型重摻雜區34;於其他實施例中,該第二接面場效應區域35亦可以完全被該p型井32所環繞;或完全被該p型重摻雜區34所環繞,均可達本發明之功效。Please refer to FIG. 2B to FIG. 2E for reference. From a top view, the p-type well 32 forms a rectangular ring, and the n-type heavily doped region 33 is disposed in the p-type well 32. The A p-type heavily doped region 34 is adjacent to the n-type heavily doped region 33 and overlaps a portion of the p-type well 32. The second junction field effect region 35 is surrounded by the p-type well 32. In one embodiment, The second junction field effect region 35 has a third doping concentration which is less than 1E18 cm -3 ; in a preferred embodiment, the third doping concentration is between 1E16 cm -3 and 2E17 cm. -3 . In this embodiment, a part of the second junction field effect region 35 is surrounded by the p-type well 32, and another part is adjacent to the p-type heavily doped region 34; in other embodiments, the second junction field is The effect region 35 can also be completely surrounded by the p-type well 32; or completely surrounded by the p-type heavily doped region 34, which can achieve the effect of the present invention.
於本發明中,該第二摻雜濃度和該第三摻雜濃度分別大於等於該第一摻雜濃度。於一實施例中,該第一接面場效應區域31具有一介於0.5μm至1μm之間的第一深度D1,該p型井32具有一介於0.5μm至1μm之間的第二深度D2,該第二接面場效應區域35具有一介於0.5μm至1μm之間的第三深度D3,於本實施例中,該第一深度D1與該第三深度D3大於等於該第二深度D2,例如『圖2D』所示,該第一深度D1與該第三深度D3相等,且均大於該第二深度D2。該p型井32、該n型重摻雜區33、該p型重摻雜區34分別具有一介於5E17cm-3 至3E18 cm-3 之間的第四摻雜濃度、一介於5E18 cm-3 至1E20 cm-3 之間的第五摻雜濃度以及一介於5E18 cm-3 至5E19 cm-3 之間的第六摻雜濃度;該n型重摻雜區33的摻雜可植入磷(Phosphorous)或氮(Nitrogen),而該p型井32和該p型重摻雜區34的摻雜可植入鋁(Aluminum)或硼(Boron),而所使用的能量介於10keV至1400keV 之間。In the present invention, the second doping concentration and the third doping concentration are respectively greater than or equal to the first doping concentration. In an embodiment, the first junction field effect region 31 has a first depth D1 between 0.5 μm and 1 μm, and the p-type well 32 has a second depth D2 between 0.5 μm and 1 μm. The second junction field effect region 35 has a third depth D3 between 0.5 μm and 1 μm. In this embodiment, the first depth D1 and the third depth D3 are greater than or equal to the second depth D2, for example [Fig. 2D], the first depth D1 is equal to the third depth D3, and both are greater than the second depth D2. The p-type well 32, the n-type heavily doped region 33, and the p-type heavily doped region 34 have a fourth doping concentration between 5E17cm -3 to 3E18 cm -3 , and a between 5E18 cm -3 to a fifth doping concentration of between 1E20 cm -3 and a sixth doping concentration interposed between 5E18 cm -3 to 5E19 cm -3; doping the n-type heavily doped region 33 may be implanted phosphorus ( Phosphorous or Nitrogen, and the p-type well 32 and the p-type heavily doped region 34 are doped with implantable aluminum or boron, and the energy used is between 10 keV to 1400 keV between.
請續參『圖2C』,該閘極介電層40設置於該n型漂移層20上,該閘極介電層40可為氧化矽、含氮之氧化矽或氧化鋁等材料,以熱氧化、化學氣相沉積(Chemical vapor deposition,簡稱CVD)或原子層沉積(Atomic layer deposition,簡稱ALD)等方式製成。該閘電極50設置於該閘極介電層40上,為對應於該第一接面場效應區域31之上,該閘電極50的材質例如可為以磷為摻質的n型重摻雜多晶矽(poly-Si)或以硼為摻質的p型重摻雜多晶矽。該層間介電層60為設置於該閘極介電層40與該閘電極50上,其材質可為四乙氧基矽烷(Tetraethylorthosilicate,簡稱TEOS)、硼磷矽玻璃(Borophosphorsilicateglass,簡稱BPSG)、氮氧化物(Oxynitride)、未掺雜矽玻璃(Undoped silicate glass,簡稱USG)、氮化矽 (Silicon rich nitride,簡稱SRN)或上述組合。Please continue to refer to "Fig. 2C". The gate dielectric layer 40 is disposed on the n-type drift layer 20. The gate dielectric layer 40 can be silicon oxide, nitrogen-containing silicon oxide, or aluminum oxide. It is made by oxidation, chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate electrode 50 is disposed on the gate dielectric layer 40 and corresponds to the first junction field effect region 31. The material of the gate electrode 50 may be, for example, an n-type heavy doping with phosphorus as a dopant. Polycrystalline silicon (poly-Si) or p-type heavily doped polycrystalline silicon with boron as a dopant. The interlayer dielectric layer 60 is disposed on the gate dielectric layer 40 and the gate electrode 50, and may be made of Tetraethylorthosilicate (TEOS), Borophosphorsilicate glass (BPSG), Oxynitride, undoped silicate glass (USG), silicon rich nitride (SRN) or a combination thereof.
該源極開口70為透過一蝕刻方式而形成,該源極開口70穿過該層間介電層60與該閘極介電層40,直至接觸部分的該n型重摻雜區33與部分的該p型重摻雜區34,而對應於該摻雜區域30之上,該源極開口70與另一該源極開口70a之間被該閘電極50與該層間介電層60間隔開。The source opening 70 is formed by an etching method. The source opening 70 passes through the interlayer dielectric layer 60 and the gate dielectric layer 40 until the contact portion of the n-type heavily doped region 33 and a portion thereof. The p-type heavily doped region 34 corresponds to the doped region 30, and the source opening 70 and another source opening 70 a are separated by the gate electrode 50 and the interlayer dielectric layer 60.
請續參『圖2D』搭配『圖2B』,該接面開口80同樣以該蝕刻方式而形成,該接面開口80穿過該層間介電層60與該閘極介電層40,直至接觸該第二接面場效應區域35、部分該p型井32以及部分該p型重摻雜區34,該接面開口80同樣對應於該摻雜區域30之上,且該接面開口80與另一該接面開口80a之間被該閘電極50與該層間介電層60間隔開。Please continue to refer to "Figure 2D" and "Figure 2B". The interface opening 80 is also formed by the etching method. The interface opening 80 passes through the interlayer dielectric layer 60 and the gate dielectric layer 40 until it contacts. The second junction field effect region 35, part of the p-type well 32, and part of the p-type heavily doped region 34, the junction opening 80 also corresponds to the doped region 30, and the junction opening 80 and The other interface opening 80 a is separated by the gate electrode 50 and the interlayer dielectric layer 60.
於本發明中,該接面開口80與該源極開口70彼此間隔設置於單一個該p型井32的區域面積中且形成一個單位晶胞(Cell),而有效利用該碳化矽半導體元件的面積,如『圖2E』所示。In the present invention, the junction opening 80 and the source opening 70 are disposed at a distance from each other in the area area of a single p-type well 32 and form a unit cell, and effectively utilize the silicon carbide semiconductor device. Area, as shown in "Figure 2E".
本實施例中,該些摻雜區域30係以類似於『圖2B』尺寸比例的長方形為舉例,於一單位晶胞內分別設置一個該p型井32,一個該n型重摻雜區33、一個該p型重摻雜區34,一個該第二接面場效應區域35以及一個該源極開口70與一個該接面開口80。但於其他實施例中,該些摻雜區域30亦可以為長邊與短邊比更大的長條狀,而於一單位晶胞內分別設置一個該p型井32,一個連續之該n型重摻雜區33或複數個間隔設置之該n型重摻雜區33、複數個間隔設置之該p型重摻雜區34,複數個間隔設置之該第二接面場效應區域35以及複數個間隔設置之該源極開口70與複數個間隔設置之該接面開口80。In this embodiment, the doped regions 30 are rectangles similar to the size ratio of FIG. 2B. For example, one p-type well 32 and one n-type heavily doped region 33 are provided in a unit cell. A p-type heavily doped region 34, a second junction field effect region 35, a source opening 70 and a junction opening 80. However, in other embodiments, the doped regions 30 may also be long strips with a larger ratio of long sides to short sides, and one p-type well 32 and one continuous n Type doped regions 33 or a plurality of spaced-apart n-type heavily doped regions 33, a plurality of spaced-apart p-type heavily doped areas 34, a plurality of spaced-apart second interface field effect regions 35, and The source openings 70 are arranged at intervals and the interface openings 80 are arranged at intervals.
如『圖2C』及『圖2E』所繪示,該第一金屬層100設置於該源極開口70的一底側,該第一金屬層100的材質可為鎳、鈦、鋁或其組合所形成的矽化物(Silicides),較佳實施例為包含有鎳之矽化物,在此先以物理氣相沉積(Physical vapor deposition,簡稱PVD)或化學氣相沉積方式沉積後再施以退火(Annealing) 等方式所形成,該第一金屬層100與部分該n型重摻雜區33及部分該p型重摻雜區34接觸,而形成一歐姆接觸。As shown in FIG. 2C and FIG. 2E, the first metal layer 100 is disposed on a bottom side of the source opening 70. The material of the first metal layer 100 may be nickel, titanium, aluminum, or a combination thereof. The formed silicide (Silicides) is preferably a silicide containing nickel, which is firstly deposited by physical vapor deposition (PVD) or chemical vapor deposition and then annealed ( Annealing), and the first metal layer 100 is in contact with part of the n-type heavily doped region 33 and part of the p-type heavily doped region 34 to form an ohmic contact.
請續參考『圖2C』及『圖2E』,並搭配『圖1』,該第二金屬層110的材質可為鈦、鉬、鎳、鋁、矽化鈦、矽化鉬、矽化鎳、矽化鋁、氮化鈦、鋁-銅(AlCu)合金及鋁矽銅合金等,為使用物理氣相沉積或化學氣相沉積方式形成。於本發明中,該第二金屬層110包含一第一部分1101與一第二部分1102,該第一部分1101覆蓋該源極開口70而與該第一金屬層100電性連接,該第一部分1101覆蓋該接面開口80而與該第二接面場效應區域35形成一蕭基接觸(Schottky contact),該蕭基接觸可形成一接面能障蕭基二極體,該第二部分1102,請參見圖3B,則覆蓋該閘極開口90並與該第一部分1101非接觸而電性絕緣。Please continue to refer to "Figure 2C" and "Figure 2E" and match "Figure 1". The material of the second metal layer 110 may be titanium, molybdenum, nickel, aluminum, titanium silicide, molybdenum silicide, nickel silicide, aluminum silicide, Titanium nitride, aluminum-copper (AlCu) alloy, and aluminum-silicon-copper alloy are formed by physical vapor deposition or chemical vapor deposition. In the present invention, the second metal layer 110 includes a first portion 1101 and a second portion 1102. The first portion 1101 covers the source opening 70 and is electrically connected to the first metal layer 100. The first portion 1101 covers The junction opening 80 forms a Schottky contact with the second junction field effect region 35. The Schottky contact can form a junction energy barrier Schottky diode. The second part 1102, please Referring to FIG. 3B, the gate opening 90 is covered and is non-contact and electrically insulated from the first portion 1101.
請參閱『圖3A』及『圖3B』所示,該閘極開口90穿過該層間介電層60至該閘電極50,在本實施例中,該閘極開口90亦可以該蝕刻方式形成,而對應於該閘電極50之上,在此,該閘電極50與該n型漂移層20之間,還設有一場氧化層51(Field oxide)。Please refer to FIG. 3A and FIG. 3B. The gate opening 90 passes through the interlayer dielectric layer 60 to the gate electrode 50. In this embodiment, the gate opening 90 can also be formed by the etching method. Corresponding to the gate electrode 50, a field oxide layer 51 (Field oxide) is further provided between the gate electrode 50 and the n-type drift layer 20.
另外,請參閱『圖4』,為本發明另一實施例的示意圖,『圖4』之視角與『圖2B』相同,於本實施例中,該n型重摻雜區33包括複數個彼此鄰接的圍繞部331,該圍繞部331係形成一連續結構,該第二接面場效應區域35形成於該圍繞部331內,該p型重摻雜區34形成於該圍繞部331之間;請參閱『圖5』,為本發明又一實施例的示意圖,『圖5』之視角與『圖2B』相同,其中該n型重摻雜區33係形成一不連續結構且包括複數個間隔設置的圍繞部331,該第二接面場效應區域35形成於該圍繞部331內,該p型重摻雜區34形成於該圍繞部331之間且隔開該圍繞部331。In addition, please refer to FIG. 4, which is a schematic diagram of another embodiment of the present invention. The perspective of FIG. 4 is the same as that of FIG. 2B. In this embodiment, the n-type heavily doped region 33 includes a plurality of each other. The adjacent surrounding portions 331 form a continuous structure, the second junction field effect region 35 is formed in the surrounding portions 331, and the p-type heavily doped region 34 is formed between the surrounding portions 331; Please refer to FIG. 5 for a schematic diagram of another embodiment of the present invention. The perspective of FIG. 5 is the same as that of FIG. 2B. The n-type heavily doped region 33 forms a discontinuous structure and includes a plurality of spaces. A surrounding portion 331 is provided, the second junction field effect region 35 is formed in the surrounding portion 331, and the p-type heavily doped region 34 is formed between the surrounding portions 331 and separated from the surrounding portion 331.
於本發明中,該碳化矽半導體元件還包含有一汲極120,該汲極120設置於該基板10遠離該n型漂移層20的一側,如圖2C所示。據此,該碳化矽半導體元件即可形成一整合結構,該整合結構具有一金屬氧化物半導體場效應電晶體以及一反向並聯該金屬氧化物半導體場效應電晶體的接面能障蕭基二極體。In the present invention, the silicon carbide semiconductor device further includes a drain electrode 120, which is disposed on a side of the substrate 10 away from the n-type drift layer 20, as shown in FIG. 2C. According to this, the silicon carbide semiconductor element can form an integrated structure, the integrated structure has a metal oxide semiconductor field effect transistor and a junction energy barrier of the metal oxide semiconductor field effect transistor in parallel. Polar body.
綜上所述,由於本案該碳化矽半導體元件係將該n型重摻雜區、該p型重摻雜區、該源極開口以及該接面開口分別對應地設置於同一個該p型井中,並非佔用該p型井和該第一接面場效應區域的部分面積,亦非額外配置一面積予蕭基二極體,因此,相較於傳統的該整合元件在面積相同的情況下,本案的該碳化矽半導體元件的總通道寬度不受影響,相對地,流過該碳化矽半導體元件的電流也不受影響而達到降低導通電阻比的功效。In summary, since the silicon carbide semiconductor device in the present case is the n-type heavily doped region, the p-type heavily doped region, the source opening, and the junction opening are respectively disposed in the same p-type well. Does not occupy a part of the area of the p-type well and the first junction field effect area, nor does it allocate an additional area for the Schottky diode. Therefore, compared with the traditional integrated component, the area is the same, The total channel width of the silicon carbide semiconductor device in this case is not affected. In contrast, the current flowing through the silicon carbide semiconductor device is also not affected, thereby achieving the effect of reducing the on-resistance ratio.
以上已將本發明做一詳細說明,惟以上所述者,僅爲本發明的一較佳實施例而已,當不能限定本發明實施的範圍。即凡依本發明申請範圍所作的均等變化與修飾等,皆應仍屬本發明的專利涵蓋範圍內。The present invention has been described in detail above, but the above is only a preferred embodiment of the present invention, and the scope of implementation of the present invention cannot be limited. That is, all equivalent changes and modifications made in accordance with the scope of the application of the present invention should still fall within the scope of the patent of the present invention.
10‧‧‧基板10‧‧‧ substrate
20‧‧‧n型漂移層20‧‧‧n-type drift layer
30‧‧‧摻雜區域30‧‧‧ doped region
31‧‧‧第一接面場效應區域31‧‧‧The first interface field effect area
32‧‧‧p型井32‧‧‧p well
33‧‧‧n型重摻雜區33‧‧‧n-type heavily doped region
331‧‧‧圍繞部331‧‧‧surrounding
34‧‧‧p型重摻雜區34‧‧‧p-type heavily doped region
35‧‧‧第二接面場效應區域35‧‧‧Second interface field effect area
40‧‧‧閘極介電層40‧‧‧Gate dielectric layer
50‧‧‧閘電極50‧‧‧Gate electrode
51‧‧‧場氧化層51‧‧‧field oxide layer
60‧‧‧層間介電層60‧‧‧ Interlayer dielectric layer
70、70a‧‧‧源極開口70, 70a‧‧‧Source opening
80、80a‧‧‧接面開口80, 80a‧‧‧face opening
90‧‧‧閘極開口90‧‧‧Gate opening
100‧‧‧第一金屬層100‧‧‧ first metal layer
110‧‧‧第二金屬層110‧‧‧Second metal layer
1101‧‧‧第一部分1101‧‧‧Part I
1102‧‧‧第二部分1102‧‧‧Part Two
120‧‧‧汲極120‧‧‧ Drain
D1‧‧‧第一深度D1‧‧‧First Depth
D2‧‧‧第二深度D2‧‧‧Second Depth
D3‧‧‧第三深度D3‧‧‧ third depth
『圖1』,本發明的俯視示意圖。 『圖2A』,本發明一實施例中,於『圖1』的X區域放大示意圖。 『圖2B』,本發明一實施例中,於『圖2A』的X’區域放大示意圖。 『圖2C』,『圖2B』的A-A剖面示意圖。 『圖2D』,『圖2B』的B-B剖面示意圖。 『圖2E』,『圖2B』的C-C剖面示意圖。 『圖3A』,本發明一實施例中,於『圖1』的Y區域放大示意圖。 『圖3B』,『圖3A』的D-D剖面示意圖。 『圖4』,為本發明另一實施例的示意圖。 『圖5』,為本發明又一實施例的示意圖。[Figure 1] A schematic plan view of the present invention. [Fig. 2A], in an embodiment of the present invention, an enlarged view of the X area in [Fig. 1]. [Fig. 2B], in an embodiment of the present invention, an enlarged schematic view of the X 'region in [Fig. 2A]. "Figure 2C", "Figure 2B" A-A cross-sectional view. 『Figure 2D』, 『Figure 2B』 B-B cross-sectional view. 『Figure 2E』, 『Figure 2B』 C-C cross-sectional view. [FIG. 3A] In an embodiment of the present invention, the Y area in FIG. 1 is enlarged. 『Figure 3B』, 『Figure 3A』 D-D cross-sectional view. [Figure 4] is a schematic diagram of another embodiment of the present invention. [Figure 5] is a schematic diagram of another embodiment of the present invention.
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