TWI651728B - Suppression of program disturb with bit line and select gate voltage regulation - Google Patents
Suppression of program disturb with bit line and select gate voltage regulation Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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Abstract
在本文中茲敘述用於抑制記憶體裝置中的程式干擾的技術。在例示實施例中,記憶體裝置包括被耦合到控制電路的快閃記憶體陣列。快閃記憶體陣列包括記憶體單元的列和行,其中每列中的記憶體單元被耦合到源極線路和選擇閘極(SG)線路,並且每行中的記憶體單元被耦合到相應的位元線路(BL)。控制電路被配置為獨立於快閃記憶體陣列的電源電壓來調節選定SG線路的第一電壓和未選定BL中的第二電壓兩者,並且基於記憶體裝置的操作溫度的測量來調整第一電壓及第二電壓中的至少一者。 Techniques for suppressing program interference in a memory device are described herein. In an exemplary embodiment, the memory device includes a flash memory array coupled to a control circuit. The flash memory array includes columns and rows of memory cells, where the memory cells in each column are coupled to a source line and a selection gate (SG) line, and the memory cells in each row are coupled to a corresponding Bit line (BL). The control circuit is configured to adjust both the first voltage of the selected SG line and the second voltage of the unselected BL independently of the power supply voltage of the flash memory array, and adjust the first based on the measurement of the operating temperature of the memory device. At least one of a voltage and a second voltage.
Description
本發明內容通常涉及記憶體裝置,並且具體地涉及減少非揮發性記憶體單元中的程式干擾。 This summary is generally related to memory devices, and in particular to reducing program interference in non-volatile memory units.
優先權priority
本申請案主張於2016年12月13日所提交的美國臨時申請案第62/433,598號的優先權,其全部內容通過引用方式併入本文。 This application claims priority from US Provisional Application No. 62 / 433,598, filed on December 13, 2016, the entire contents of which are incorporated herein by reference.
非揮發性記憶體被廣泛用於在計算裝置中儲存數據,並且通常包括具有以列和行進行排列的大量記憶體單元的記憶體陣列。每個記憶體單元包括非揮發性電荷俘獲電晶體,其通過偏置在其控制閘極與其基板之間的適當極性、大小和持續時間的電壓而被編程或擦除。正性閘極到基板電壓使得電子從基板中的通道穿隧到電荷俘獲介電層而提高電晶體的閾值電壓(VT),並且負性閘極到通道電壓使得電洞從通道穿隧到電荷俘獲介電層而降低閾值電壓。 Non-volatile memory is widely used to store data in computing devices and typically includes a memory array with a large number of memory cells arranged in columns and rows. Each memory cell includes a non-volatile charge-trapping transistor that is programmed or erased by a voltage biased to its appropriate polarity, size, and duration between its control gate and its substrate. The positive gate-to-substrate voltage causes electrons to tunnel from the channel in the substrate to the charge-trapping dielectric layer to increase the threshold voltage (V T ) of the transistor, and the negative gate-to-channel voltage causes the hole to tunnel from the channel to The charge traps the dielectric layer and lowers the threshold voltage.
非揮發性記憶體遭受程式干擾,這是在記憶體單元中的淨電荷量上的無意和有害變化,此增加其VT。程式干擾通常發生在進行記憶體 操作以編程選定記憶體單元期間,與選定單元共享相同的閘極或汲極或源極電壓的未選定記憶體單元被無意地編程的時候。隨著製造技術迅速發展到較小幾何節點(例如40nm和28nm節點等),越來越難以避免程式干擾。此外,由於程式干擾在較高的操作溫度下的幅度增大,所以由於程式干擾所引起的問題隨著非揮發性記憶體的密度增加而變地更差。 Non-volatile memory suffers from program interference, which is an unintentional and harmful change in the amount of net charge in a memory cell, which increases its V T. Program interference typically occurs when an unselected memory cell that shares the same gate or drain or source voltage with the selected cell is unintentionally programmed during a memory operation to program the selected memory cell. With the rapid development of manufacturing technology to smaller geometric nodes (such as 40nm and 28nm nodes, etc.), it becomes increasingly difficult to avoid program interference. In addition, because the amplitude of program interference increases at higher operating temperatures, problems caused by program interference become worse as the density of non-volatile memory increases.
本發明一個實施例是一種記憶體裝置,其包括:快閃記憶體陣列,其包括記憶體單元的列和行快閃記憶體陣列,其中在特定列中的記憶體單元被耦合到特定源極線路和到特定選擇閘極(SG)線路,且其中在特定行中的記憶體單元被耦合到到特定位元線路;及控制電路,其被耦合到快閃記憶體陣列並且被配置為至少:獨立於快閃記憶體陣列的電源電壓來調節選定SG線路的第一電壓和未選定位元線路的第二電壓兩者;且基於記憶體裝置的操作溫度的測量來調整第一電壓和第二電壓中的至少一個。 An embodiment of the present invention is a memory device including a flash memory array including a column and a row of a flash memory array, wherein the memory cells in a specific column are coupled to a specific source. A circuit and to a specific selection gate (SG) circuit, where the memory cells in the specific row are coupled to a specific bit circuit; and a control circuit, which is coupled to the flash memory array and is configured to at least: Adjust both the first voltage of the selected SG circuit and the second voltage of the unselected locator circuit independently of the power supply voltage of the flash memory array; and adjust the first voltage and the second voltage based on the measurement of the operating temperature of the memory device At least one of the voltages.
本發明另一個實施例是一種用於抑制程式干擾的方法,方法包括:對包括記憶體單元的列和行的快閃記憶體陣列中的第一記憶體單元進行編程,其中在特定列中的記憶體單元被耦合到特定源極線路和到特定選擇閘極(SG)線路,並且其中在特定行中的記憶體單元被耦合到特定位元線路;在對第一記憶體單元進行編程期間,獨立於快閃記憶體陣列的電源電壓來調節被耦合到第一記憶體單元的選定SG線路的第一電壓;在對第一記憶體單元進行編程期間,獨立於電源電壓來調節被耦合到快閃記憶體陣列的第二記憶體單元的未選定位元線路的第二電壓,其中第二記憶體單元在快閃記憶體陣列的同一列中相鄰第一記憶體單元;以及基於快閃記憶 體陣列的操作溫度的測量來調整第一電壓和第二電壓中的至少一個。 Another embodiment of the present invention is a method for suppressing program interference. The method includes: programming a first memory cell in a flash memory array including a column and a row of memory cells, wherein Memory cells are coupled to specific source lines and to specific select gate (SG) lines, and wherein the memory cells in a specific row are coupled to specific bit lines; during programming of the first memory cell, The first voltage of the selected SG line coupled to the first memory cell is adjusted independently of the power supply voltage of the flash memory array; during the programming of the first memory cell, the voltage of the coupled to the flash memory is adjusted independently of the power supply voltage. The second voltage of the unselected locator circuit of the second memory cell of the flash memory array, wherein the second memory cell is adjacent to the first memory cell in the same column of the flash memory array; and based on the flash memory Measurement of the operating temperature of the volume array to adjust at least one of the first voltage and the second voltage.
本發明又另一個實施例是一種系統,其包括:電源,被配置為提供電源電壓;以及快閃記憶體陣列,齊備耦合到電源以接收電源電壓,快閃記憶體陣列包括記憶體單元的列和行,其中在特定列中的記憶體單元被耦合到特定源極線路和到特定選擇閘極(SG)線路,並且其中在特定行中的記憶體單元被耦合到特定位元線路;其中快閃記憶體陣列包括控制電路,其經配置以至少:獨立於電源電壓來調節選定SG線路的第一電壓和未選定位元線路的第二電壓兩者;且基於快閃記憶體陣列的操作溫度的測量來調整第一電壓和第二電壓中的至少一個。 Yet another embodiment of the present invention is a system including: a power supply configured to provide a power supply voltage; and a flash memory array that is fully coupled to the power supply to receive the power supply voltage, the flash memory array including a column of memory cells And rows, where the memory cells in a particular column are coupled to a particular source line and to a particular select gate (SG) line, and where the memory cells in a particular row are coupled to a particular bit line; where fast The flash memory array includes a control circuit configured to adjust at least both the first voltage of the selected SG line and the second voltage of the unselected locator line independently of the power supply voltage; and based on the operating temperature of the flash memory array Measurement to adjust at least one of the first voltage and the second voltage.
100‧‧‧(分離閘極非揮發性)記憶體單元 100‧‧‧ (separable gate non-volatile) memory unit
102‧‧‧基板 102‧‧‧ substrate
103‧‧‧通道區域 103‧‧‧Channel area
104‧‧‧(摻雜)汲極區域 104‧‧‧ (doped) drain region
106‧‧‧(摻雜)源極區域 106‧‧‧ (doped) source region
108‧‧‧選擇閘極 108‧‧‧Select gate
110‧‧‧記憶體閘極 110‧‧‧Memory gate
112‧‧‧介電層 112‧‧‧ Dielectric layer
114‧‧‧電荷俘獲介電質 114‧‧‧ charge trapping dielectric
116‧‧‧垂直介電質 116‧‧‧Vertical Dielectric
120‧‧‧(雙電晶體(2T)非揮發性)記憶體單元 120‧‧‧ (Dual Transistor (2T) Non-volatile) Memory Unit
122‧‧‧基板 122‧‧‧ substrate
123a、123b‧‧‧通道區域 123a, 123b‧‧‧ Channel area
124‧‧‧汲極/汲極區域 124‧‧‧ Drain / Drain Region
126‧‧‧源極/源極區域 126‧‧‧source / source area
128‧‧‧選擇閘極 128‧‧‧Select gate
130‧‧‧記憶體閘極 130‧‧‧Memory gate
132‧‧‧選擇閘極介電層 132‧‧‧Select gate dielectric layer
134‧‧‧電荷俘獲層/電荷俘獲介電質 134‧‧‧ charge trap layer / charge trap dielectric
136‧‧‧汲極區域 136‧‧‧Drain region
150‧‧‧處理裝置 150‧‧‧ treatment device
152‧‧‧位址匯流排 152‧‧‧Address Bus
154‧‧‧數據匯流排 154‧‧‧Data Bus
156‧‧‧控制匯流排 156‧‧‧Control bus
158‧‧‧電源(Vcc) 158‧‧‧ Power Supply (Vcc)
160‧‧‧非揮發性記憶體(NVM)裝置 160‧‧‧NVM device
162‧‧‧記憶體陣列 162‧‧‧Memory Array
164‧‧‧列解碼器 164‧‧‧column decoder
166‧‧‧源極線路驅動器 166‧‧‧Source Line Driver
168‧‧‧行解碼器 168‧‧‧line decoder
170‧‧‧命令和控制電路 170‧‧‧ command and control circuit
172‧‧‧感測放大器 172‧‧‧Sense Amplifier
200‧‧‧快閃記憶體陣列 200‧‧‧Flash Memory Array
200(A)、200(B)‧‧‧NVM單元 200 (A), 200 (B) ‧‧‧NVM units
204、204(1)、204(2)‧‧‧位元線路 204, 204 (1), 204 (2) ‧‧‧bit lines
206、206(1)、206(2)‧‧‧源極線路 206, 206 (1), 206 (2) ‧‧‧Source line
208、208(1)、208(2)、208(3)‧‧‧選擇閘極(SG)線路 208, 208 (1), 208 (2), 208 (3) ‧‧‧Select gate (SG) line
210、210(1)、210(2)、210(3)‧‧‧記憶體閘極線路 210, 210 (1), 210 (2), 210 (3) ‧‧‧Memory gate circuit
300、400‧‧‧表 Tables 300, 400‧‧‧
圖1A是說明根據一些實施例的用於記憶體裝置的例示性分離閘極非揮發性記憶體單元的橫截面的方塊圖。 FIG. 1A is a block diagram illustrating a cross-section of an exemplary separation gate non-volatile memory unit for a memory device according to some embodiments.
圖1B是說明根據一些實施例的用於記憶體裝置的例示性雙電晶體(2T)非揮發性記憶體單元的橫截面的方塊圖。 FIG. 1B is a block diagram illustrating a cross-section of an exemplary electric double crystal (2T) non-volatile memory cell for a memory device according to some embodiments.
圖1C是說明根據一些實施例的例示性非揮發性記憶體(NVM)系統的方塊圖。 FIG. 1C is a block diagram illustrating an exemplary non-volatile memory (NVM) system according to some embodiments.
圖2是說明根據例示實施例的快閃記憶體陣列的方塊圖。 FIG. 2 is a block diagram illustrating a flash memory array according to an exemplary embodiment.
圖3是說明在一些快閃記憶體陣列上的程式記憶體操作期間所施加的未經調節電壓的表。 FIG. 3 is a table illustrating unregulated voltages applied during program memory operation on some flash memory arrays.
圖4是說明根據例示性實施例的具有在程式操作期間所施加的經調節位元線路和選擇閘極電壓的表。 FIG. 4 is a table illustrating an adjusted bit line and a selection gate voltage applied during a program operation according to an exemplary embodiment.
圖5是說明根據例示性實施例的用於抑制非揮發性記憶體陣列中的程式干擾的方法的流程圖。 5 is a flowchart illustrating a method for suppressing program interference in a non-volatile memory array according to an exemplary embodiment.
以下描述闡述許多具體細節,諸如特定系統、組件、方法等等的實例,以便對在本文中所述用於抑制記憶體裝置中的程式干擾的技術的各種實施例提供良好理解。然而,對於本領域技術人員將顯而易見的是可在沒有這些具體細節下實踐至少一些實施例。在其它實例中,為避免不必要地模糊在本文中所述的技術,眾所周知的的組件或方法沒有進行詳細敘述或以簡單的方塊圖格式來呈現。因此,在下文中提出的具體細節僅僅是例示性。特定實施方式可從這些例示性細節加以變化,並且仍然被認為落是在本發明的精神和範圍內。 The following description sets forth many specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of various embodiments of the techniques described herein for suppressing programmatic interference in memory devices. However, it will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, to avoid unnecessarily obscuring the techniques described herein, well-known components or methods have not been described in detail or presented in a simple block diagram format. Therefore, the specific details set forth below are merely illustrative. Particular embodiments may vary from these illustrative details and are still considered to fall within the spirit and scope of the invention.
在說明書中對“實施例”,“一個實施例”,“例示性實施例”,“一些實施例”和“各種實施例”的參考意謂結合此(些)實施例所述的特定特徵、結構或特性被包括在本發明的至少一個實施例中。此外,在說明書中各處出現的用語“實施例”,“一個實施例”,“例示性實施例”,“一些實施例”和“各種實施例”不一定全部指代相同的實施例。 References in the specification to "embodiments", "one embodiment", "exemplary embodiments", "some embodiments" and "various embodiments" mean that in connection with specific features described in these embodiments (s), Structures or characteristics are included in at least one embodiment of the present invention. In addition, the terms "embodiment", "one embodiment", "exemplary embodiment", "some embodiments", and "various embodiments" appearing everywhere in the specification do not necessarily all refer to the same embodiment.
說明書包括對形成【實施方式】的一部分的圖式的參考,並且其中類似的元件符號可指代相似的組件或操作。圖式顯示根據例示性實施例的圖示。這些實施例(在本文中也可被稱為“實例”)被足夠詳細地敘述以使得本領域技術人員能夠實踐在本文中所述要求保護標的的實施例。在不悖離所要求保護標的的範圍和精神下,可組合此些實施例、可使用其它實施例、或可進行結構,邏輯和電性改變。應該理解的是,在本文中所述 的實施例並不意圖限制所述標的的範圍,而是使本領域技術人員能夠實踐、製作和/或使用此標的。 The specification includes references to the drawings that form a part of the [Embodiment] , and wherein similar element symbols may refer to similar components or operations. The drawings show diagrams according to an exemplary embodiment. These embodiments (also may be referred to herein as "examples") are described in sufficient detail to enable those skilled in the art to practice the claimed embodiments described herein. Without departing from the scope and spirit of the claimed subject matter, these embodiments may be combined, other embodiments may be used, or structural, logical, and electrical changes may be made. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.
在非揮發性記憶體單元上的程式操作期間,記憶體單元的源極和汲極在適當電壓下進行偏置,以加速在源極和汲極之間的通道區內的電子。隨著電子被加速,其中一些電子獲得被注入的足夠能量並且被俘獲在記憶體單元的電荷俘獲介電質內。如此被稱為熱電子注入。這種通道熱電子(源極側注入)被用於編程非揮發性記憶體單元(例如圖1A中的分離閘極快閃記憶體單元、或圖1B中的2T記憶體單元)。在常規程式操作期間,記憶體單元的記憶體閘極和源極均被偏置在高電壓(例如,記憶體閘極在10V,並且源極在5V)以產生通道熱電子。在這種偏置下,記憶體單元的選擇閘極(SG)需要被偏置在選擇閘極電晶體的閾值電壓(VT)以上,以導通在源極和汲極之間的通道。 During a program operation on a non-volatile memory cell, the source and drain of the memory cell are biased at an appropriate voltage to accelerate electrons in the channel region between the source and the drain. As electrons are accelerated, some of them get enough energy injected and are trapped within the charge-trapping dielectric of the memory cell. This is called hot electron injection. This channel hot electron (source-side injection) is used to program a non-volatile memory cell (such as a split gate flash memory cell in FIG. 1A or a 2T memory cell in FIG. 1B). During normal program operation, the memory gate and source of the memory unit are both biased to a high voltage (for example, the memory gate is at 10V and the source is at 5V) to generate channel hot electrons. Under this bias, the selection gate (SG) of the memory cell needs to be biased above the threshold voltage (VT) of the selection gate transistor to conduct the channel between the source and the drain.
當非揮發性記憶體(NVM)陣列的目標單元被選定為進行編程時,其源極和其選擇閘極被偏置在高電壓以產生通道熱電子,如上所述。然而,NVM陣列的同一列上的未選定記憶體單元可與目標/選定單元共享相同的源極線路和選擇閘極線路,並且因此未選定記憶體單元的源極和選擇閘極也被偏置在與選定單元相同的高電壓。因此,在選定記憶體單元的編程操作期間,未選定記憶體單元(其可與選定單元共享相同的閘極或汲極或源極電壓)可被無意地編程。這通常被稱為程式干擾。為避免這種程式干擾,未選定記憶體單元的通道需要被完全關閉。 When a target cell of a non-volatile memory (NVM) array is selected for programming, its source and its select gate are biased at a high voltage to generate channel hot electrons, as described above. However, unselected memory cells on the same column of the NVM array can share the same source line and selected gate line with the target / selected cell, and therefore the source and selected gate of unselected memory cells are also biased At the same high voltage as the selected cell. Therefore, during a programming operation of a selected memory cell, an unselected memory cell (which may share the same gate or drain or source voltage with the selected cell) may be inadvertently programmed. This is often called program interference. To avoid such program interference, the channels of unselected memory units need to be completely closed.
在用於抑制程式干擾的一些常規技術中,通過在未選定位元線路(BL)上施加NVM陣列的電源電壓(Vcc)來關閉未選定記憶體單元 的選擇閘極次閾值洩漏。這種偏置條件的實例在圖3的表300中示出,其中Vcc=1.8V(如302所示)。選定的選擇閘極(SG)線路被偏置在1.2V(如304所示)。因此,未選定記憶體單元(例如,單元“B”)的SG電晶體在其選擇閘極(SG)與其汲極(D)之間具有-0.6V偏壓(即,1.2V-1.8V=-0.6V)。這種偏置條件足以在選定記憶體單元(單元“A”)的編程期間完全消除未選定單元(例如單元“B”)中的次閾值洩漏,並且因此不存在對於未選定記憶體單元(例如,單元“B”)的程式干擾。然而,製造技術正迅速發展到諸如40nm和28nm的節點的較小幾何節點,其中較小數字表示在記憶體單元中的記憶體電晶體的源極和汲極之間的較窄通道。在具有較短通道的較小幾何節點下,電源電壓Vcc降低至1.1V甚至0.9V。同時,在程式操作期間,記憶體單元的選擇閘極(SG)仍然需要被偏置高到足夠傳遞足夠電流來編程選定單元。然而,當未選定記憶體單元的選擇閘極電壓並未遠低於其汲極電壓時,未選定單元的SG電晶體將具有次閾值洩漏,並且將在未選定記憶體單元上產生程式干擾。當未選定記憶體單元由於在NVM陣列的製造期間的製成變化而具有低選擇閘極閾值電壓VT時以及當NVM陣列在較高溫度下操作時,上述問題變得更糟。因此,通過使用用於程式干擾抑制的傳統技術以在所有必要操作溫度和Vcc操作範圍(其可能變化多達±10%)處避免未選定單元的程式干擾是無法進行的,這依賴於施加電源電壓Vcc於未選定位元線路(BL)上和固定電壓於選擇閘極(SG)線路上。 In some conventional techniques for suppressing program interference, a selected gate subthreshold leakage of an unselected memory cell is turned off by applying a power supply voltage (Vcc) of an NVM array on an unselected locator cell (BL). An example of such a bias condition is shown in table 300 of FIG. 3, where Vcc = 1.8V (as shown at 302). The selected selection gate (SG) line is biased at 1.2V (shown as 304). Therefore, the SG transistor of an unselected memory cell (for example, cell "B") has a -0.6V bias between its selection gate (SG) and its drain (D) (ie, 1.2V-1.8V = -0.6V). This bias condition is sufficient to completely eliminate sub-threshold leakage in unselected cells (e.g., cell "B") during programming of selected memory cells (cell "A"), and therefore there is no such thing as unselected memory cells (e.g., , Program interference of unit "B"). However, manufacturing technology is rapidly advancing to smaller geometric nodes such as the 40nm and 28nm nodes, where smaller numbers represent narrower channels between the source and drain of a memory transistor in a memory cell. With smaller geometry nodes with shorter channels, the supply voltage Vcc is reduced to 1.1V or even 0.9V. At the same time, during program operation, the selection gate (SG) of the memory cell still needs to be biased high enough to pass sufficient current to program the selected cell. However, when the selected gate voltage of the unselected memory cell is not much lower than its drain voltage, the SG transistor of the unselected cell will have a sub-threshold leakage, and program interference will occur on the unselected memory cell. The above problems become worse when unselected memory cells have a low selection gate threshold voltage V T due to fabrication changes during the manufacture of the NVM array and when the NVM array is operated at higher temperatures. Therefore, it is not possible to avoid program interference of unselected units at all necessary operating temperatures and Vcc operating ranges (which may vary by up to ± 10%) by using traditional techniques for program interference suppression, which depends on the applied power The voltage Vcc is on the unselected locating element line (BL) and the fixed voltage is on the selected gate (SG) line.
為解決與程式干擾有關的這些和其它問題,在本文中茲敘述用於抑制非揮發性記憶體單元中的程式干擾的技術的各種實施例。在一個例示性實施例中,記憶體裝置包括快閃記憶體陣列和與其耦合的控制電 路。快閃記憶體陣列包括記憶體單元的列和行,其中在特定列中的記憶體單元被耦合到源極線路(例如諸如共用源極線路)和選擇閘極(SG)線(例如諸如共用SG線路),並且其中在每個特定行中的記憶體單元被耦合到相應的位元線路。控制電路被配置為獨立於快閃記憶體陣列的電源電壓來調節選定SG線路的第一電壓和未選定位元線路的第二電壓兩者,並且基於記憶體裝置和/或快閃記憶體陣列的操作溫度的測量來調整第一電壓和第二電壓中的至少一者。在一個例示觀點中,在記憶體操作期間,第一記憶體單元被耦合到選定SG線路以編程第一記憶體單元,並且第二記憶體單元被耦合到未選定位元線路,其中第二記憶體單元在快閃記憶體陣列的同一列中相鄰/鄰近第一記憶體單元。在該觀點中,控制電路被配置成通過將第一電壓調節在0.9V至1.1V的範圍內並且將第二電壓調節在0.4V至1.2V的範圍內,以在記憶體操作期間抑制在第二記憶體單元處的程式干擾。在一個觀點中,控制電路被配置為操作第一電壓低於電源電壓,並且在另一觀點中,控制電路被配置為操作第二電壓高於電源電壓。在一個例示觀點中,控制電路被配置為在製造記憶體裝置時具有用於第一電壓和第二電壓的調整值,其中調整值可被配置成用於整個記憶體裝置或者單獨用於快閃記憶體陣列中的記憶體單元的每個區塊。在一個例示觀點中,快閃記憶體陣列的記憶體單元被製造為40nm技術節點,其中記憶體單元可以是分離閘極非揮發性記憶體單元或雙電晶體(2T)非揮發性記憶體單元。 To address these and other issues related to program interference, various embodiments of techniques for suppressing program interference in non-volatile memory units are described herein. In an exemplary embodiment, the memory device includes a flash memory array and a control circuit coupled thereto. A flash memory array includes columns and rows of memory cells, where the memory cells in a particular column are coupled to a source line (e.g., such as a shared source line) and a select gate (SG) line (e.g., such as a shared SG Lines), and where the memory cells in each particular line are coupled to the corresponding bit line. The control circuit is configured to regulate both the first voltage of the selected SG line and the second voltage of the unselected locator line independently of the power supply voltage of the flash memory array, and is based on the memory device and / or the flash memory array Measuring the operating temperature to adjust at least one of the first voltage and the second voltage. In an exemplary aspect, during memory operation, a first memory unit is coupled to a selected SG circuit to program a first memory unit, and a second memory unit is coupled to an unselected locator circuit, wherein the second memory The body unit is adjacent / adjacent to the first memory unit in the same column of the flash memory array. In this perspective, the control circuit is configured to suppress the first voltage during the memory operation by adjusting the first voltage within the range of 0.9V to 1.1V and the second voltage within the range of 0.4V to 1.2V. Program interference at two memory units. In one aspect, the control circuit is configured to operate the first voltage below the power supply voltage, and in another aspect, the control circuit is configured to operate the second voltage above the power supply voltage. In an exemplary aspect, the control circuit is configured to have adjustment values for the first voltage and the second voltage when the memory device is manufactured, wherein the adjustment values may be configured for the entire memory device or separately for the flash memory. Each block of a memory cell in a memory array. In an exemplary perspective, the memory cells of the flash memory array are manufactured as 40nm technology nodes, where the memory cells can be split gate non-volatile memory cells or dual-transistor (2T) non-volatile memory cells. .
在另一例示實施例中,一種用於抑制快閃記憶體陣列中的程式干擾的方法包括以下操作:對包括記憶體單元的列和行的快閃記憶體陣列中的第一記憶體單元進行編程,其中在特定列中的記憶體單元被耦合到 源極線路(例如諸如共用源極線路)以及到共用選擇閘極(SG)線路(例如諸如共用SG線路),並且其中在特定行中的記憶體單元被耦合到相應的特定位元線路;在對第一記憶體單元進行編程期間,獨立於快閃記憶體陣列的電源電壓來調節被耦合到第一記憶體單元的選定SG線路的第一電壓;在對第一記憶體單元進行編程期間,獨立於電源電壓來調節被耦合到快閃記憶體陣列的第二記憶體單元的未選定位元線路的第二電壓,其中第二記憶體單元在快閃記憶體陣列的同一列中相鄰/鄰近第一記憶體單元;以及基於快閃記憶體陣列的操作溫度的測量來調整第一電壓和第二電壓中的至少一個。在一個例示觀點中,調節第一電壓包括操作第一電壓低於電源電壓。在另一個例示觀點中,調節第二電壓包括操作第二電壓高於電源電壓。在一個例示性觀點,為在第一記憶體單元的編程期間抑制在第二記憶體單元處的程式干擾,上述方法包括將第一電壓調節在0.9V至1.1V的範圍內,並且將第二電壓調節在0.4V至1.2V的範圍內。在一個例示觀點面,在製造包括快閃記憶體陣列的非揮發性記憶體裝置時配置第一電壓和第二電壓的調整值,其中調整值被配置為用於整個非揮發性記憶體裝置或單獨用於快閃記憶體陣列中的記憶體單元的每個區塊。 In another exemplary embodiment, a method for suppressing program interference in a flash memory array includes the following operations: performing a first memory cell in a flash memory array including a column and a row of a memory cell Programming, where memory cells in a particular column are coupled to a source line (e.g., such as a shared source line) and to a shared selection gate (SG) line (e.g., such as a shared SG line), and where the The memory cell is coupled to the corresponding specific bit line; during programming of the first memory cell, the second voltage of the selected SG line coupled to the first memory cell is adjusted independently of the power supply voltage of the flash memory array. A voltage; during programming of the first memory cell, the second voltage of the unselected locator circuit coupled to the second memory cell of the flash memory array is adjusted independently of the power supply voltage, wherein the second memory The cells are adjacent / adjacent to the first memory cell in the same column of the flash memory array; and the first voltage is adjusted based on the measurement of the operating temperature of the flash memory array At least a second voltage. In an exemplary aspect, adjusting the first voltage includes operating the first voltage below a power supply voltage. In another illustrative aspect, adjusting the second voltage includes operating the second voltage above a power supply voltage. In an exemplary aspect, in order to suppress program interference at the second memory unit during programming of the first memory unit, the method includes adjusting the first voltage to a range of 0.9V to 1.1V, and adjusting the second voltage The voltage is regulated in the range of 0.4V to 1.2V. In an exemplary aspect, an adjustment value of the first voltage and the second voltage is configured when a non-volatile memory device including a flash memory array is manufactured, wherein the adjustment value is configured for the entire non-volatile memory device or Separate for each block of memory cells in the flash memory array.
在另一個例示實施例中,一種系統包括電源和予以耦合的快閃記憶體陣列。電源被配置為向快閃記憶體陣列提供電源電壓。快閃記憶體陣列包括記憶體單元的列和行,其中在特定列中的記憶體單元被耦合到源極線路(例如諸如共用源極線路)和選擇閘極(SG)線路(例如諸如共用SG線路),並且其中在特定行中的記憶體單元被耦合到相應的位元線路。快閃記憶體陣列進一步包括控制電路,其被配置為獨立於電源電壓來 調節選定SG線路的第一電壓和未選定位元線路的第二電壓兩者,並且基於快閃記憶體陣列的操作溫度的測量來調整第一電壓和第二電壓中的至少一個。在一個例示觀點點中,電源被耦合到包括快閃記憶體陣列的非揮發性記憶體裝置。在另一個例示觀點中,此系統包括被耦合到快閃記憶體陣列的處理裝置。在另一例示觀點中,電源,快閃記憶體陣列和處理裝置被設置在相同的半導體基板上,例如積體電路(IC)半導體裝置的基板上。 In another exemplary embodiment, a system includes a power source and a flash memory array coupled thereto. The power supply is configured to provide a power supply voltage to the flash memory array. A flash memory array includes columns and rows of memory cells, where the memory cells in a particular column are coupled to a source line (e.g., such as a shared source line) and a select gate (SG) line (e.g., such as a shared SG) Lines), and where the memory cells in a particular line are coupled to corresponding bit lines. The flash memory array further includes a control circuit configured to adjust both the first voltage of the selected SG line and the second voltage of the unselected locator line independently of the power supply voltage, and based on the operating temperature of the flash memory array Measurement to adjust at least one of the first voltage and the second voltage. In one exemplary aspect, a power source is coupled to a non-volatile memory device including a flash memory array. In another exemplary aspect, this system includes a processing device coupled to a flash memory array. In another illustrative aspect, a power source, a flash memory array, and a processing device are provided on the same semiconductor substrate, such as a substrate of an integrated circuit (IC) semiconductor device.
圖1A說明例示分離閘極非揮發性記憶體單元100的橫截面。分離閘極記憶體單元是通過使用電晶體裝置而形成的快閃記憶體單元,電晶體裝置具有經並排設置的選擇閘極和記憶體閘極的,經設置在選擇閘極側的汲極接面,以及經設置在記憶體閘極側的源極接面。在圖1A中,記憶體單元100被形成在諸如矽的基板102上。基板102通常是p型或p型阱,而摻雜源極區域106和摻雜汲極區域104是n型。(要注意的是在一些實施例中,基板也可以是n型,而源極和汲極區域也可以是p型。)源極區域106和汲極區域104分別形成分離閘極非揮發性記憶體單元100的源極和汲極。在各種實施例中,記憶體單元100可被製造為較小幾何結點,諸如40nm節點或28nm節點。 FIG. 1A illustrates a cross-section illustrating a separation gate non-volatile memory cell 100. The separated gate memory unit is a flash memory unit formed by using a transistor device. The transistor device has a selection gate and a memory gate arranged side by side, and is connected via a drain electrode provided on the selection gate side. And a source connection provided on the gate side of the memory. In FIG. 1A, a memory unit 100 is formed on a substrate 102 such as silicon. The substrate 102 is generally a p-type or p-type well, and the doped source region 106 and the doped drain region 104 are n-type. (It should be noted that in some embodiments, the substrate may also be n-type, and the source and drain regions may also be p-type.) The source region 106 and the drain region 104 form separate gate non-volatile memories, respectively. A source and a drain of the body unit 100. In various embodiments, the memory cell 100 may be manufactured as a smaller geometric node, such as a 40 nm node or a 28 nm node.
記憶體單元100包括具有兩個閘極,選擇閘極(SG)108和記憶體閘極(MG)110的電晶體。選擇閘極是選擇電晶體的閘極,其電壓控制分離閘極記憶體單元的電流流動。記憶體閘極是記憶體電晶體的閘極,其閾值電壓可通過變更在分離閘極記憶體單元中所俘獲的電荷量而改變。每個閘極可包括閘極導體,諸如通過沉積和蝕刻技術所形成的摻雜多晶矽(“poly”)層,以限定閘極結構。選擇閘極108被設置在介電層112上。 記憶體閘極110被設置在具有一個或多個介電層的電荷俘獲介電質114上。在一個實例中,電荷俘獲介電質114包括被夾設在兩個二氧化矽層之間的電荷俘獲矽氮化物層,以共同地形成三層堆疊並且通常稱為氧化物-氮化物-氧化物(“ONO”)堆疊。一些實施例可使用其它電荷俘獲介電質,其可包括富矽氮化物膜、或者是包括但不限於具有各種化學計量的矽,氧和氮的任何膜。垂直介電質116還被設置在選擇閘極108和記憶體閘極110之間,用於在兩個閘極之間的電性隔離(絕緣)。在一些實例中,垂直介電質116和電荷俘獲介電質114是相同的介電質,而在其它實例中,一個介電質被形成在另一介電質之前(例如,兩個介電質可具有不同的介電性質)。如此,垂直介電質116可包括或未必包括與電荷俘獲介電質114相同的膜結構。在業已界定閘極之後,通過使用例如離子植入技術植入摻雜劑來創建源極106和汲極104。 The memory unit 100 includes a transistor having two gates, a selection gate (SG) 108 and a memory gate (MG) 110. The selection gate is the gate of the selection transistor, and its voltage controls the current flow of the separate gate memory cell. The memory gate is the gate of the memory transistor, and its threshold voltage can be changed by changing the amount of charge trapped in the separate gate memory cell. Each gate may include a gate conductor, such as a doped polycrystalline silicon ("poly") layer formed by deposition and etching techniques to define the gate structure. A selection gate 108 is disposed on the dielectric layer 112. The memory gate 110 is disposed on a charge trapping dielectric 114 having one or more dielectric layers. In one example, the charge-trapping dielectric 114 includes a charge-trapping silicon nitride layer sandwiched between two silicon dioxide layers to collectively form a three-layer stack and is commonly referred to as an oxide-nitride-oxide Objects ("ONO"). Some embodiments may use other charge trapping dielectrics, which may include a silicon-rich nitride film, or any film including, but not limited to, silicon, oxygen, and nitrogen with various stoichiometry. The vertical dielectric 116 is also disposed between the selection gate 108 and the memory gate 110 for electrical isolation (insulation) between the two gates. In some examples, vertical dielectric 116 and charge-trapping dielectric 114 are the same dielectric, while in other examples, one dielectric is formed before the other dielectric (e.g., two dielectrics) May have different dielectric properties). As such, the vertical dielectric 116 may or may not include the same film structure as the charge trapping dielectric 114. After the gate has been defined, the source 106 and the drain 104 are created by implanting dopants using, for example, ion implantation techniques.
記憶體單元100上的例示“程式”操作可包括執行擦除操作而後隨寫入操作(例如,如果需要將“高”位元儲存在記憶體單元中作為編程的一部分)。因此,程式操作是改變非揮發性記憶體單元中的淨電荷量以增加其記憶體電晶體的閾值電壓VT的記憶體操作,其通常通過增加在單元的電荷俘獲層中所儲存的淨電荷量。擦除操作是改變非揮發性記憶體單元中的淨電荷量以降低其記憶體電晶體的閾值電壓VT的記憶體操作,通常通過減少在單元的電荷俘獲層中所儲存的淨電荷量。為在擦除操作中“擦除”可被儲存在記憶體單元100內的任何電荷並且將記憶體單元100的狀態返回到“低”位元,正電壓被施加到源極106而汲極104被浮置或處於一定偏壓,並且選擇閘極108和基板102通常接地。高的負電壓被施加到記憶體閘極 110。在記憶體閘極110和源極106之間的偏置條件通過帶間穿隧(band-to-band tunneling)產生電洞。所產生的電洞在記憶體閘極110下被強電場充分激勵,並且從通道區域103向上注入電荷俘獲介電質114。所注入的電洞有效地將記憶體單元100擦除到“低”位元狀態。如果需要將一位元儲存在記憶體單元100中,則在後續的寫入操作中,將正電壓施加到源極106,而將汲極104接地或處於一定的較低偏置,並且將基板102接地。低的正電壓被施加到選擇閘極108,而較高的正電壓被施加到記憶體閘極110。當電子在源極106和汲極104之間的通道區域103內被加速時,此些電子中的一些將獲得足夠能量以被向上注入並且被俘獲在電荷俘獲介電質114內。即使在去除各種供應電壓之後,被俘獲在電荷俘獲介電質114內的電荷仍在記憶體單元100內儲存“高”位元。 An example "program" operation on the memory unit 100 may include performing an erase operation followed by a write operation (eg, if "high" bits need to be stored in the memory unit as part of programming). Therefore, the program operation is a memory operation that changes the amount of net charge in a non-volatile memory cell to increase the threshold voltage V T of its memory transistor, which is usually performed by increasing the net charge stored in the charge trapping layer of the cell. the amount. An erase operation is a memory operation that changes the amount of net charge in a non-volatile memory cell to reduce the threshold voltage V T of its memory transistor, typically by reducing the amount of net charge stored in the charge-trapping layer of the cell. To "erase" any charge that can be stored in the memory cell 100 and return the state of the memory cell 100 to the "low" bit during the erase operation, a positive voltage is applied to the source 106 and the drain 104 Floating or at a certain bias, and the selection gate 108 and the substrate 102 are usually grounded. A high negative voltage is applied to the memory gate 110. A bias condition between the memory gate 110 and the source 106 generates a hole through band-to-band tunneling. The generated hole is fully excited by the strong electric field under the memory gate 110, and a charge trapping dielectric 114 is injected upward from the channel region 103. The injected holes effectively erase the memory cell 100 to a "low" bit state. If a bit needs to be stored in the memory cell 100, in a subsequent write operation, a positive voltage is applied to the source 106, and the drain 104 is grounded or at a certain lower bias, and the substrate is 102 Ground. A low positive voltage is applied to the selection gate 108 and a higher positive voltage is applied to the memory gate 110. When the electrons are accelerated in the channel region 103 between the source 106 and the drain 104, some of these electrons will get enough energy to be injected upward and trapped in the charge trapping dielectric 114. Even after removing various supply voltages, the charges trapped in the charge trapping dielectric 114 still store "high" bits in the memory cell 100.
為在讀取記憶體操作中“讀取”記憶體單元100的儲存位元,低電壓被施加到選擇閘極108,記憶體閘極110和汲極104中的每一個,而源極106和基板102通常接地。施加到記憶體閘極110的低電壓可被選擇為使得基本等距離地在儲存“高”位元時導通電晶體所需的閾值電壓與儲儲“低”位元時導通電晶體所需的閾值電壓之間,以便在這兩種狀態之間清楚地進行區分。因此,如果在讀取操作期間施加低電壓導致感測放大器檢測到在源極106與汲極104之間的通道區域103中的大量電流流動,則記憶體單元保持“低”位元。另或者,如果在讀取操作期間施加低電壓不會導致感測放大器檢測到在源極106與汲極104之間的通道區域103中的大量電流流動,則記憶體單元保持“高”位元。 To "read" the memory bits of the memory cell 100 during a read memory operation, a low voltage is applied to each of the select gate 108, the memory gate 110, and the drain 104, and the source 106 and The substrate 102 is usually grounded. The low voltage applied to the memory gate 110 may be selected such that the threshold voltage required to turn on the crystal when storing "high" bits is substantially equal to the threshold voltage required to turn on the crystal when storing "low" bits. Between threshold voltages to make a clear distinction between these two states. Therefore, if applying a low voltage during a read operation causes the sense amplifier to detect a large amount of current flowing in the channel region 103 between the source 106 and the drain 104, the memory cell remains "low" bits. Alternatively, if applying a low voltage during a read operation does not cause the sense amplifier to detect a large amount of current flowing in the channel region 103 between the source 106 and the drain 104, the memory cell remains "high" bits .
圖1B說明被形成在諸如矽之基板122上的例示性雙電晶體 (2T)非揮發性記憶體單元120的橫截面。基板122通常是p型或p型阱,而源極(或源極區域)126和汲極(或汲極區域)124是摻雜n型區域。(然而,要注意的是在一些實施例中,基板也可以是n型,而源極和汲極區域也可以是p型。)在各種實施例中,記憶體單元120可被製造為諸如40nm節點或28nm節點的較小幾何節點。 FIG. 1B illustrates a cross-section of an exemplary electric double crystal (2T) non-volatile memory cell 120 formed on a substrate 122 such as silicon. The substrate 122 is typically a p-type or p-type well, and the source (or source region) 126 and the drain (or drain region) 124 are doped n-type regions. (However, it should be noted that in some embodiments, the substrate may also be n-type, and the source and drain regions may also be p-type.) In various embodiments, the memory cell 120 may be manufactured such as 40 nm Nodes or smaller geometric nodes of 28nm nodes.
在記憶體單元120中,一個電晶體可以是具有記憶體閘極(MG)130的記憶體電晶體,而另一個電晶體可以是具有選擇閘極(SG)128的選擇(或通路)電晶體。記憶體單元120還可包括源極126,汲極124,以及在基板122上的記憶體閘極130和選擇閘極128之間的可選汲極區域136。具有選擇閘極128的通路電晶體可以是場效應電晶體(FET)(例如金屬氧化物半導體場效應電晶體或MOSFET),其具有選擇閘極介電層132並且被配置為開關以控制記憶體單元120的接觸節點處的電壓位準和/或電流位準(例如在通路電晶體和/或記憶體電晶體的源極和/或汲極處)。具有記憶體閘極130的記憶體電晶體可以是被配置成儲存二進制資訊位元的電晶體,例如通過改變在記憶體電晶體的電荷俘獲層134中所儲存的電荷資訊。 In the memory unit 120, one transistor may be a memory transistor having a memory gate (MG) 130, and the other transistor may be a selection (or path) transistor having a selection gate (SG) 128 . The memory unit 120 may further include a source 126, a drain 124, and an optional drain region 136 between the memory gate 130 and the selection gate 128 on the substrate 122. The pass transistor with the select gate 128 may be a field effect transistor (FET) (such as a metal oxide semiconductor field effect transistor or MOSFET), which has a select gate dielectric layer 132 and is configured as a switch to control the memory The voltage level and / or current level at the contact node of the cell 120 (eg, at the source and / or drain of the pass transistor and / or memory transistor). The memory transistor having the memory gate 130 may be a transistor configured to store binary information bits, for example, by changing the charge information stored in the charge trapping layer 134 of the memory transistor.
用於2T記憶體單元120的程式和讀取記憶體操作通過與圖1A的分離閘極記憶體單元100的類似方式來施加電壓並且偏置記憶體單元來執行。為在擦除操作中“擦除”可被儲存在記憶體單元120內的任何電荷並且將記憶體單元120的狀態返回到“低”位元,將正電壓施加到源極126,而使汲極124經浮置或處於一定偏壓,並且選擇閘極128和基板122通常接地。高的負電壓被施加到記憶體閘極130。在記憶體閘極130和源極126之間的偏置條件產生電洞,並且所產生的電洞被充分激發以從通道區域123b 向上注入到電荷俘獲介電質134中。所注入的電洞有效擦除記憶體單元120到“低”位元狀態。如果需要將位元儲存在記憶體單元120中,則在後續寫入操作中,將正電壓施加到源極126,而將汲極124接地或處於一定的較低偏置,並且將基板122接地。低的正電壓被施加到選擇閘極128,而較高的正電壓被施加到記憶體閘極130。當電子在源極126和汲極124之間的通道區域123a和123b內被加速時,此些電子中的一些將獲得足夠能量以被向上注入並且被俘獲在電荷俘獲介電質134內部。即使在各種供應電壓被移除之後,被俘獲在電荷俘獲介電質134內的電荷仍在記憶體單元120內儲存“高”位元。為在讀取記憶體操作中“讀取”記憶體單元120的儲存位元,低電壓被施加到選擇閘極128,記憶體閘極130和汲極124中的每一個,而源極126和基板102通常接地。如果在讀取操作期間施加低電壓導致感測放大器檢測到在源極126和汲極124之間的通道區域123a和123b中的大量電流流動,則記憶體單元保持“低”位元。另或者,如果在“讀取”操作期間施加低電壓不會導致感測放大器檢測到在源極126和汲極124之間的通道區域123a和123b中的大量電流流動,那麼記憶體單元保持“高“位元。 The program and read memory operation for the 2T memory cell 120 is performed by applying a voltage and biasing the memory cell in a similar manner to the split gate memory cell 100 of FIG. 1A. In order to "erase" any charge that can be stored in the memory cell 120 during the erase operation and return the state of the memory cell 120 to the "low" bit, a positive voltage is applied to the source electrode 126 to make the drain The pole 124 is floated or biased, and the selection gate 128 and the substrate 122 are usually grounded. A high negative voltage is applied to the memory gate 130. A bias condition between the memory gate 130 and the source electrode 126 generates a hole, and the generated hole is sufficiently excited to be injected upward from the channel region 123b into the charge trapping dielectric 134. The injected holes effectively erase the memory cell 120 to the "low" bit state. If the bits need to be stored in the memory unit 120, in a subsequent write operation, a positive voltage is applied to the source 126, and the drain 124 is grounded or at a certain lower bias, and the substrate 122 is grounded . A low positive voltage is applied to the selection gate 128 and a higher positive voltage is applied to the memory gate 130. When electrons are accelerated in the channel regions 123a and 123b between the source 126 and the drain 124, some of these electrons will get enough energy to be injected upward and trapped inside the charge trapping dielectric 134. Even after the various supply voltages are removed, the charges trapped in the charge trapping dielectric 134 still store the "high" bits in the memory cell 120. To "read" the storage bits of the memory cell 120 during a read memory operation, a low voltage is applied to each of the select gate 128, the memory gate 130, and the drain 124, and the source 126 and The substrate 102 is usually grounded. If applying a low voltage during a read operation causes the sense amplifier to detect a large amount of current flow in the channel regions 123a and 123b between the source 126 and the drain 124, the memory cell remains "low" bits. Alternatively, if the application of a low voltage during a "read" operation does not cause the sense amplifier to detect a large amount of current flowing in the channel regions 123a and 123b between the source 126 and the drain 124, the memory cell remains " High "bit.
計算裝置(例如,諸如膝上型電腦/筆記型電腦,平板電腦,智能手機等)可將數據,配置資訊和/或程式儲存在非揮發性記憶體(NVM)中,例如包括NAND和NOR的快閃記憶體,EEPROM和F-RAM。圖1C是說明例示性NVM系統145的方塊圖。在一些實施例中,NVM系統145可被實現為嵌入式晶片上子系統(例如包括諸如SRAM記憶體,微處理器和其它硬體組件之附加組件的快閃巨集),其位於被設置在積體電路(IC)裝置的基板的半導體基板上的微控制器單元(MCU)內。在一些實施例中 (例如如圖1C所例示),NVM系統145可包括經由位址匯流排152,數據匯流排154和控制匯流排156被耦合到NVM裝置160的處理裝置150。應該要理解到的是在圖1C中,NVM系統145出於說明目的已被簡化並且因此不打算作為完整敘述。具體來說,在圖1C中所例示各種硬體組件的細節(例如,處理裝置150,列解碼器164,源極線路驅動器166,行解碼器168,命令和控制電路170,感測放大器172等)不在本文中進行詳細敘述。還應該理解到的是NVM系統145可包括圖1的實施例中的不同的一些組件、全部組件、或不同/附加組件。因此,在圖1C中的NVM系統145應被認為是說明性而非限制性。 Computing devices (e.g., such as laptops / notebooks, tablets, smartphones, etc.) may store data, configuration information and / or programs in non-volatile memory (NVM), such as those including NAND and NOR Flash memory, EEPROM and F-RAM. FIG. 1C is a block diagram illustrating an exemplary NVM system 145. In some embodiments, the NVM system 145 may be implemented as an embedded on-chip subsystem (e.g., a flash macro including additional components such as SRAM memory, microprocessors, and other hardware components), which is located at A microcontroller unit (MCU) on a semiconductor substrate of a substrate of an integrated circuit (IC) device. In some embodiments (e.g., as illustrated in FIG. 1C), the NVM system 145 may include a processing device 150 coupled to the NVM device 160 via an address bus 152, a data bus 154, and a control bus 156. It should be understood that in FIG. 1C, the NVM system 145 has been simplified for illustrative purposes and is therefore not intended as a complete description. Specifically, details of various hardware components (e.g., processing device 150, column decoder 164, source line driver 166, row decoder 168, command and control circuit 170, sense amplifier 172, etc.) are illustrated in FIG. 1C. ) Will not be described in detail in this article. It should also be understood that the NVM system 145 may include some different components, all components, or different / additional components in the embodiment of FIG. 1. Therefore, the NVM system 145 in FIG. 1C should be considered illustrative and not restrictive.
電源158播耦合到NVM裝置160而予以提供電源電壓Vcc。在一些實施例中,電源電壓Vcc可以是大約1.8V±10%。電源158可以在NVM裝置160的外部和/或內部,並且由NVM裝置160用來產生電壓信號,例如高於由電源所提供的最高電壓的高電壓(HV)信號以及低於由電源所提供的最低電壓(例如,接地電壓)的低電壓(LV)信號。在一些實施例中,電源158可被配置成從處理裝置150和/或NVM裝置160接收控制信號和/或配置數據。 The power supply 158 is coupled to the NVM device 160 to provide a power supply voltage Vcc. In some embodiments, the power supply voltage Vcc may be about 1.8V ± 10%. The power source 158 may be external and / or internal to the NVM device 160 and used by the NVM device 160 to generate voltage signals, such as high voltage (HV) signals higher than the highest voltage provided by the power source and lower than Low voltage (LV) signal of the lowest voltage (eg, ground voltage). In some embodiments, the power source 158 may be configured to receive control signals and / or configuration data from the processing device 150 and / or the NVM device 160.
處理裝置150可以駐留在共用載體基板上,例如積體電路(IC)裸片基板,多晶片模塊基板等。或者,處理裝置150的組件可以是一個或多個單獨的積體電路和/或分立組件。在一個例示性實施例中,處理裝置150可以是來自加利福尼亞州聖何西的賽普拉斯半導體公司所開發的可編程晶片上系統(PSoC®)系列裝置中的裝置。另或者,處理裝置150可以是一個或多個其它處理裝置,例如微處理器或中央處理單元(“CPU”)、 微控制器(“MCU”)、控制器、專用處理器、數位信號處理器(“DSP”)、特殊應用積體電路(“ASIC”),現場可編程閘極陣列(“FPGA”)等。 The processing device 150 may reside on a common carrier substrate, such as an integrated circuit (IC) die substrate, a multi-wafer module substrate, and the like. Alternatively, the components of the processing device 150 may be one or more separate integrated circuits and / or discrete components. In an exemplary embodiment, processing device 150 may be a device in a Programmable System on a Chip (PSoC®) family of devices developed by Cypress Semiconductor Corporation of San Jose, California. Alternatively, the processing device 150 may be one or more other processing devices, such as a microprocessor or a central processing unit ("CPU"), a microcontroller ("MCU"), a controller, a dedicated processor, a digital signal processor ("DSP"), special application integrated circuits ("ASIC"), field programmable gate arrays ("FPGA"), etc.
NVM裝置160包含非揮發性記憶體陣列162,諸如快閃記憶體陣列。快閃記憶體陣列是按列和行所組構的一群快閃記憶體單元,所以每個記憶體單元可通過列和行解碼器電路按列和行位址進進行隨機存取。記憶體陣列162被組構為非揮發性記憶體單元的列和行,例如圖1A中的分離閘極記憶體單元100或圖1B中的2T記憶體單元120。在各種實施例中,記憶體陣列162可包含製造為較小幾何節點(諸如40nm節點或28nm節點)的記憶體單元。如圖1C所例示,記憶體陣列162可直接地或通過命令和控制電路170而經超過一個的匯流排,多條選擇線路和/或讀取線路以被耦合到列解碼器164。記憶體陣列162也經由多條位元線路(例如每一位元線路用於記憶體陣列的每一行)被耦合到行解碼器168。記憶體陣列162還被耦合到源極線路驅動器166,其被配置為控制被耦合到陣列中的記憶體單元的源極的源極線路(SL)。在一些實施例中,記憶體陣列的SL可以是被耦合到記憶體陣列162的獨立區塊、扇區或分頁的專用線路,並且源極線路驅動器166可被配置為按每個區塊、扇區或分頁以將相同的SL線路電壓施加到相應SL。在其它實施例中,源極線路可以是在記憶體陣列162中特定列的單元之間共享的共用源極線路(CSL),並且源極線路驅動器166可被配置為將相同的SL線路電壓施加到記憶體陣列的一個或更多SL的不同群組。這樣的CSL可被實施以減少每個記憶體單元的總體佔用面積,伴隨多條選擇線路,讀取線路和/或位元線路被耦合到陣列中的記憶體單元並且可被加以共享。記憶體陣列162可被耦合到感測放大器172(例如直接地 或經由行解碼器168),其被配置為從陣列中的記憶體單元讀取多位字組。 The NVM device 160 includes a non-volatile memory array 162, such as a flash memory array. A flash memory array is a group of flash memory cells organized in columns and rows, so each memory cell can be accessed randomly by column and row addresses through column and row decoder circuits. The memory array 162 is configured as columns and rows of non-volatile memory cells, such as the separated gate memory cell 100 in FIG. 1A or the 2T memory cell 120 in FIG. 1B. In various embodiments, the memory array 162 may include memory cells manufactured as smaller geometric nodes, such as a 40 nm node or a 28 nm node. As illustrated in FIG. 1C, the memory array 162 may be coupled to the column decoder 164 directly or through the command and control circuit 170 through more than one bus, multiple selection lines and / or read lines. The memory array 162 is also coupled to the row decoder 168 via a plurality of bit lines (eg, each bit line is used for each row of the memory array). The memory array 162 is also coupled to a source line driver 166 that is configured to control a source line (SL) that is coupled to a source of a memory cell in the array. In some embodiments, the SL of the memory array may be a dedicated line coupled to an independent block, sector, or page of the memory array 162, and the source line driver 166 may be configured to Zone or page to apply the same SL line voltage to the corresponding SL. In other embodiments, the source line may be a common source line (CSL) shared between cells in a particular column in the memory array 162, and the source line driver 166 may be configured to apply the same SL line voltage To different groups of one or more SLs of the memory array. Such a CSL can be implemented to reduce the overall footprint of each memory cell. With multiple selection lines, read lines and / or bit lines are coupled to the memory cells in the array and can be shared. The memory array 162 may be coupled to a sense amplifier 172 (e.g., directly or via a row decoder 168), which is configured to read multi-bit blocks from memory cells in the array.
NVM裝置160還包括命令和控制電路170,其包括電壓調節電路171和溫度感測和控制電路173。命令/控制電路170被配置為接收信號(例如來自處理裝置150),以發送控制和命令信號(例如到列解碼器164,源極線路驅動器166,行解碼器168,感測放大器172等),並且在各種記憶體操作期間控制被施加到記憶體陣列162的電壓信號。這樣的電壓信號可由電壓調節電路171產生或通過電壓調節電路171路由繞送。電壓調節電路171被配置為在編程,擦除,寫入和讀取記憶體操作和/或在記憶體陣列162上所執行的其它操作期間,向記憶體單元施加包括高電壓信號和低電壓信號的精確電壓。溫度感測/控制電路173被配置有一個或多個溫度感測器以感測NVM裝置160和/或記憶體陣列162的操作溫度。命令/控制電路170經配置以通過將第一電壓施加到被耦合到記憶體陣列162的特定列的記憶體單元的特定選擇閘極線路,而選擇此特定列進行程式操作。命令/控制電路170還被配置為控制行解碼器168以通過向特定行中的特定位元線路施加適當電壓來選擇特定列中的記憶體單元進行編程,並且將第二電壓施加到被耦合到特定行中相鄰/鄰近選定記憶體單元的記憶體單元的未選定位元線路。命令/控制電路170可進一步被配置為將適當電壓(例如通過源極線路驅動器166)施加到可被耦合到記憶體陣列162的特定列中的記憶體單元的一個或多個共用源極線路。 The NVM device 160 also includes a command and control circuit 170 including a voltage adjustment circuit 171 and a temperature sensing and control circuit 173. The command / control circuit 170 is configured to receive signals (e.g., from the processing device 150) to send control and command signals (e.g., to the column decoder 164, source line driver 166, row decoder 168, sense amplifier 172, etc.), And the voltage signals applied to the memory array 162 are controlled during various memory operations. Such a voltage signal may be generated by the voltage adjustment circuit 171 or routed through the voltage adjustment circuit 171. The voltage adjustment circuit 171 is configured to apply a memory cell including a high voltage signal and a low voltage signal during a program, erase, write, and read memory operation and / or other operations performed on the memory array 162 Precise voltage. The temperature sensing / control circuit 173 is configured with one or more temperature sensors to sense the operating temperature of the NVM device 160 and / or the memory array 162. The command / control circuit 170 is configured to select a particular column for program operation by applying a first voltage to a particular selection gate line of a memory cell coupled to a particular column of the memory array 162. The command / control circuit 170 is also configured to control the row decoder 168 to select a memory cell in a particular column for programming by applying an appropriate voltage to a particular bit line in a particular row, and to apply a second voltage to the coupled to An unselected locator line of memory cells adjacent / adjacent to a selected memory cell in a particular row. The command / control circuit 170 may be further configured to apply an appropriate voltage (eg, via the source line driver 166) to one or more common source lines of a memory cell that may be coupled to a particular column of the memory array 162.
根據在本文中所述的用於抑制程式干擾的技術,電壓調節電路171被配置有電荷泵,通路電晶體,邏輯閘以及其它硬體電路,以獨立於電源電壓Vcc來產生和調節在程式操作期間被用於操作記憶體陣列162 的精確電壓信號。溫度感測/控制電路173被配置有一個或多個二極體,邏輯閘和其它硬體電路以感測NVM裝置160(和/或記憶體陣列162)的操作溫度,並且向電壓調節電路171提供關於感測到的操作溫度的信號。在程式操作期間,命令/控制電路170(和/或其中的電路171和173)被配置為獨立於電源電壓Vcc來調節選定選擇閘極(SG)線路的電壓以及任何/全部未選定位元線路的電壓兩者,並且基於感測的操作溫度來調整這兩個電壓中的一個或兩個。在一些例示實施例中,在程式操作期間,命令/控制電路170被配置為調節並且施加在0.9V至1.1V的範圍內的電壓到一列記憶體單元的選擇閘(SG)線路,並且調節並且施加在0.4至1.2V範圍的電壓到記憶體陣列的位元線路(BL),而將1.2V的調節電壓施加到任何/全部未選定BL以抑制未選定記憶體單元的程式干擾。在一些實施例中,在程式操作期間,命令/控制電路170還被配置成基於感測到的NVM裝置和/或記憶體陣列的操作溫度來調整SG線路電壓和/或BL電壓。以此方式,根據在本文所述的技術,命令/控制電路170(和/或其中的電路171和173)在未選定記憶體單元上提供程式干擾的抑制。 According to the technique for suppressing program interference described in this article, the voltage adjustment circuit 171 is configured with a charge pump, a pass transistor, a logic gate, and other hardware circuits to generate and adjust the program operation independently of the power supply voltage Vcc. The period is used to manipulate the precise voltage signals of the memory array 162. The temperature sensing / control circuit 173 is configured with one or more diodes, logic gates, and other hardware circuits to sense the operating temperature of the NVM device 160 (and / or the memory array 162), and to the voltage regulating circuit 171. Provides a signal about the sensed operating temperature. During program operation, the command / control circuit 170 (and / or circuits 171 and 173 therein) is configured to adjust the voltage of the selected selection gate (SG) line and any / all unselected positioning element lines independently of the power supply voltage Vcc , And adjust one or both of the two voltages based on the sensed operating temperature. In some exemplary embodiments, during program operation, the command / control circuit 170 is configured to regulate and apply a voltage in the range of 0.9V to 1.1V to a selection gate (SG) line of a row of memory cells, and regulate and A voltage in the range of 0.4 to 1.2V is applied to the bit line (BL) of the memory array, and a regulated voltage of 1.2V is applied to any / all unselected BLs to suppress program interference of unselected memory cells. In some embodiments, during program operation, the command / control circuit 170 is further configured to adjust the SG line voltage and / or the BL voltage based on the sensed operating temperature of the NVM device and / or the memory array. In this manner, according to the techniques described herein, the command / control circuit 170 (and / or circuits 171 and 173 therein) provides suppression of program interference on unselected memory cells.
圖2說明根據例示實施例的快閃記憶體陣列200(例如諸如圖1C中的記憶體陣列162)的方塊圖。在圖2中,記憶體陣列200被組構為非揮發性記憶體單元的列和行,例如圖1A中的分離閘極記憶體單元100或圖1B中的2T記憶體單元120。然而,應該要認識到記憶體單元的術語“列”和“行”在本文中用於說明目的而非限制目的。例如在圖2的實施例中,記憶體單元列經過水平佈置,並且記憶體單元行經過垂直佈置。然而,在各種實施例中,“列”和“行”的取向可被顛倒、以相反方向使用、或以不同定向進 行佈置。因此,記憶體陣列200在本文中就列和行方面的敘述應該被認為是說明性而非限制性。 FIG. 2 illustrates a block diagram of a flash memory array 200 (eg, such as the memory array 162 in FIG. 1C) according to an exemplary embodiment. In FIG. 2, the memory array 200 is configured as columns and rows of non-volatile memory cells, such as the separated gate memory cell 100 in FIG. 1A or the 2T memory cell 120 in FIG. 1B. However, it should be recognized that the terms "column" and "row" of a memory unit are used herein for illustrative purposes and not for restrictive purposes. For example, in the embodiment of FIG. 2, the memory cell columns are horizontally arranged, and the memory cell rows are vertically arranged. However, in various embodiments, the "column" and "row" orientations may be reversed, used in opposite directions, or arranged in different orientations. Therefore, the description of the memory array 200 in terms of columns and rows herein should be considered as illustrative and not restrictive.
記憶體陣列200包含位元線路(BL)204,而每一位元線路被耦合到陣列的相對應行中的記憶體單元的汲極。記憶體陣列200還包括源極線路(SL)206。在一些實施例中,源極線路206可以是被耦合到記憶體陣列200的獨立區塊、扇區或分頁的專用線路。在其它實施例中,源極線路可以是在記憶體陣列200中特定列的單元之間共享的共用源極線路(CSL),例如每個特定源極線路被耦合到陣列的相應列中的記憶體單元的源極。記憶體陣列200還包括選擇閘極(SG)線路208和記憶體閘極(MG)線路210,其中每條SG線路和每條MG線路分別被耦合到陣列的相對應列中的記憶體單元的選擇閘極和記憶體閘極。BL 204,SL 206,SG線路208和MG線路210由金屬(和/或其它導電)層所形成,其彼此電性絕緣並且被佈置在半導體記憶體裝置的基板上。 The memory array 200 includes bit lines (BL) 204, and each bit line is coupled to a drain of a memory cell in a corresponding row of the array. The memory array 200 further includes a source line (SL) 206. In some embodiments, the source line 206 may be a dedicated line coupled to a separate block, sector, or page of the memory array 200. In other embodiments, the source line may be a common source line (CSL) shared between cells in a particular column in the memory array 200, for example, each particular source line is coupled to a memory in a corresponding column of the array Source of the body unit. The memory array 200 further includes a selection gate (SG) line 208 and a memory gate (MG) line 210, wherein each SG line and each MG line are respectively coupled to the memory cells in corresponding columns of the array. Select gate and memory gate. The BL 204, SL 206, SG line 208, and MG line 210 are formed of metal (and / or other conductive) layers, which are electrically insulated from each other and are disposed on a substrate of a semiconductor memory device.
如圖2所例示,記憶體陣列200包括非揮發性記憶體單元200A(單元“A”),200B(單元“B”),200C(單元“C”),200D(單元“D”),200E(單元“E”),200F(單元“F”)和其它單元(未用元件符號標記)。在各種實施例中,記憶體陣列200的記憶體單元可被製造為諸如40nm節點或28nm節點的較小幾何節點。NVM單元200A包括被電性耦合到位元線路204(1)的汲極,被電性耦合到源極線路206(1)的源極,被電性耦合到SG線路208(1)的選擇閘極,以及被電性耦合到MG線路210(1)的記憶體閘極。NVM單元200B包括被電性耦合到位元線路204(2)的汲極,被電性耦合到源極線路206(1)的源極,被電性耦合到SG線路208(1) 的選擇閘極,以及被電性耦合到MG線路210(1)的記憶體閘極。因此,NVM單元200B在同一列上相鄰NVM單元200A並且與其共享同一共用源極線路206(1),SG線路208(1)和MG線路210(1)。NVM單元200C包括被電性耦合到位元線路204(1)的汲極,被電性耦合到源極線路206(1)的源極,被電性耦合到SG線路208(2)的選擇閘極,以及被電性耦合到MG線路210(2)的記憶體閘極。NVM單元200C與NVM單元200A和200B共享相同的共用源極線路206(1)。NVM單元200D包括被電性耦合到位元線路204(2)的汲極,被電性耦合到源極線路206(1)的源極,被電性耦合到SG線路208(2)的選擇閘極,以及被電性耦合到MG線路210(2)的記憶體閘極。因此,NVM單元200D在同一列上相鄰NVM單元200C,並且與NVM單元200A,200B和200D共享相同的共用源極線路206(1)以及與NVM單元200C共享相同的SG線路208(2)和相同的MG線路210(2)。類似地,NVM單元200E包括被電性耦合到位元線路204(1)的汲極,被電性耦合到源極線路206(2)的源極,被電性耦合到SG線路208(3)的選擇閘極,以及被電性耦合到MG線路210(3)的記憶體閘極。NVM單元200F包括被電性耦合到位元線路204(2)的汲極,被電性耦合到源極線路206(2)的源極,被電性耦合到SG線路208(3)的選擇閘極,以及被電性耦合到MG線路210(3)的記憶體閘極。因此,NVM單元200F在同一列上相鄰NVM單元200E相鄰並且與其共享相同的共用源極線路206(2),SG線路208(3)和MG線路210(3)。 As illustrated in FIG. 2, the memory array 200 includes non-volatile memory cells 200A (cell “A”), 200B (cell “B”), 200C (cell “C”), 200D (cell “D”), and 200E. (Unit "E"), 200F (Unit "F") and other units (not marked with a component symbol). In various embodiments, the memory cells of the memory array 200 may be manufactured as smaller geometric nodes such as a 40 nm node or a 28 nm node. NVM unit 200A includes a drain electrode electrically coupled to bit line 204 (1), a source electrode electrically coupled to source line 206 (1), and a selection gate electrode electrically coupled to SG line 208 (1) And a memory gate electrically coupled to the MG line 210 (1). The NVM unit 200B includes a drain electrode electrically coupled to the bit line 204 (2), a source electrode electrically coupled to the source line 206 (1), and a selection gate electrically coupled to the SG line 208 (1) And a memory gate electrically coupled to the MG line 210 (1). Therefore, the NVM unit 200B is adjacent to the NVM unit 200A on the same column and shares the same common source line 206 (1), SG line 208 (1), and MG line 210 (1). The NVM unit 200C includes a drain electrode electrically coupled to the bit line 204 (1), a source electrode electrically coupled to the source line 206 (1), and a selection gate electrically coupled to the SG line 208 (2). And a memory gate electrically coupled to the MG line 210 (2). The NVM unit 200C and the NVM units 200A and 200B share the same common source line 206 (1). The NVM unit 200D includes a drain electrode electrically coupled to the bit line 204 (2), a source electrode electrically coupled to the source line 206 (1), and a selection gate electrode electrically coupled to the SG line 208 (2). And a memory gate electrically coupled to the MG line 210 (2). Therefore, the NVM unit 200D is adjacent to the NVM unit 200C on the same column and shares the same common source line 206 (1) with the NVM units 200A, 200B, and 200D and the same SG line 208 (2) and the NVM unit 200C. The same MG line 210 (2). Similarly, the NVM unit 200E includes a drain electrode that is electrically coupled to the bit line 204 (1), a source electrode that is electrically coupled to the source line 206 (2), and a source electrode that is electrically coupled to the SG line 208 (3). A gate is selected, and a memory gate electrically coupled to the MG line 210 (3). The NVM unit 200F includes a drain electrode electrically coupled to the bit line 204 (2), a source electrode electrically coupled to the source line 206 (2), and a selection gate electrode electrically coupled to the SG line 208 (3). And a memory gate electrically coupled to the MG line 210 (3). Therefore, the NVM unit 200F is adjacent to the NVM unit 200E on the same column and shares the same common source line 206 (2), SG line 208 (3), and MG line 210 (3).
在記憶體陣列200上的程式操作期間,根據在本文中所述的技術,被耦合到陣列的控制電路被配置成獨立於記憶體陣列200的電源電 壓以精確地調節選定選擇閘極(SG)線路的電壓和任何/全部未選定位元線路的電壓兩者,並且基於感測到的操作溫度來調整這兩個電壓中的一個或兩個。例如,在NVM單元200A上的程式操作期間,控制電路施加:(a)經調節的精確電壓(例如0.9V)到SG線路208(1),其低於電源電壓Vcc(例如1.1V);和(b)經調節的精確電壓到位元線路204(1)和204(2),其中被施加到NVM單元200A的位元線路204(1)的電壓(例如~0.4V)低於電源電壓,並且被施加到NVM單元200B的位元線路204(2)的電壓(例如1.2V)高於電源電壓Vcc。以這種方式,隨著被施加到記憶體陣列200,在本文中所述的技術在選定記憶體單元NVM 200A正被編程時抑制未選定記憶體單元NVM 200B上的程式干擾。 During program operation on the memory array 200, according to the techniques described herein, the control circuit coupled to the array is configured to be independent of the power supply voltage of the memory array 200 to precisely adjust the selected selection gate (SG) Both the voltage of the line and the voltage of any / all unselected locator lines, and one or both of these two voltages are adjusted based on the sensed operating temperature. For example, during program operation on the NVM unit 200A, the control circuit applies: (a) a regulated precise voltage (such as 0.9V) to the SG line 208 (1), which is lower than the power supply voltage Vcc (such as 1.1V); and (b) the adjusted precise voltage to bit lines 204 (1) and 204 (2), where the voltage (eg ~ 0.4V) of bit line 204 (1) applied to the NVM unit 200A is lower than the power supply voltage, and The voltage (for example, 1.2V) applied to the bit line 204 (2) of the NVM unit 200B is higher than the power supply voltage Vcc. In this manner, as applied to the memory array 200, the techniques described herein suppress program interference on the unselected memory cell NVM 200B while the selected memory cell NVM 200A is being programmed.
在一些實施例中,快閃記憶體陣列包括以列和行(例如諸如圖2中的記憶體陣列200)佈置的分離閘極或2T非揮發性記憶體單元。在這些實施例中,在同一列中的記憶體單元共享相同的選擇閘極(SG)線路和記憶體閘極(MG)線路,並且在同一行中的記憶體單元共享相同的位元線路(BL)。在程式操作期間,選定SG線路的電壓和未選定位元線路的電壓均由電壓調節電路來調節,並且基本上獨立於電源電壓Vcc。因此,在選定SG線路上的電壓和在未選定位元線路上的電壓都保持在適當固定值,並且不受電源電壓的變化(通常具有+/- 10%的變化)所影響。如此提供在選定記憶體單元上施加用以執行程式操作所需的電壓,而同時保持足以防止任何/全部未選定記憶體單元的程式干擾的適當偏置電壓。此外,由於電壓調節電路產生具有精確幅度的所施加電壓,因此在選定SG電壓與未選定BL電壓之間的較小幅度的偏置足以抑制在未選定記憶體單元上的程式干 擾,由此在快閃記憶體陣列的整個溫度操作範圍和電壓供應範圍內提供抑制這種程式干擾。 In some embodiments, the flash memory array includes discrete gates or 2T non-volatile memory cells arranged in columns and rows (such as, for example, the memory array 200 in FIG. 2). In these embodiments, memory cells in the same column share the same select gate (SG) line and memory gate (MG) line, and memory cells in the same row share the same bit line ( BL). During program operation, the voltage of the selected SG line and the voltage of the unselected positioning element line are adjusted by the voltage adjustment circuit, and are basically independent of the power supply voltage Vcc. Therefore, the voltage on the selected SG line and the voltage on the unselected locator line are both kept at a fixed value and are not affected by changes in the power supply voltage (typically with a +/- 10% change). This provides the voltage required to perform program operation on the selected memory cells while maintaining an appropriate bias voltage sufficient to prevent program interference from any / all unselected memory cells. In addition, because the voltage regulation circuit generates an applied voltage with a precise amplitude, a small offset between the selected SG voltage and the unselected BL voltage is sufficient to suppress program interference on the unselected memory cells, thereby The flash memory array provides suppression of such program interference over the entire temperature operating range and voltage supply range.
在一些實施例中,選定記憶體單元的選定SG線路電壓被調節在低於電源電壓Vcc的電壓位準的電壓位準。例如,電源電壓Vcc可在1.1V±10%左右,而選定SG線路電壓可被調節在0.9V左右。類似地,在一些實施例中,任何/所有未選定單元的未選定BL電壓被調節在高於電源電壓Vcc的電壓位準的電壓位準。例如,電源電壓Vcc可在1.1V±10%左右,而未選定BL電壓可被調節在1.2V左右。 In some embodiments, the selected SG line voltage of the selected memory cell is adjusted to a voltage level lower than the voltage level of the power supply voltage Vcc. For example, the power supply voltage Vcc can be about 1.1V ± 10%, and the selected SG line voltage can be adjusted at about 0.9V. Similarly, in some embodiments, the unselected BL voltage of any / all unselected cells is adjusted at a voltage level higher than the voltage level of the power supply voltage Vcc. For example, the power supply voltage Vcc can be around 1.1V ± 10%, while the unselected BL voltage can be adjusted around 1.2V.
圖4說明根據其中電源電壓Vcc=1.1V的例示性實施例,在程式操作期間所施加的經調節選擇閘極(SG)和位元線路(BL)電壓的表400。如圖4所例示,在程式操作期間,選定SG線路電壓和未選定BL電壓都被調節到與電源電壓不同的電壓-例如SG線路電壓被調節在0.9V(如404所示),而BL電壓被調節在~0.4V以用於選定記憶體單元(如402A所示)並且被調節在1.2V以用於未選定記憶體單元(如402B所示)。這種電壓調節和施加方案的好處在於未選定記憶體單元“B”的SG在其選擇閘極(SG)和其汲極(D)之間具有-0.3V偏壓。此偏置條件有助於在選定記憶體單元“A”的編程期間消除未選定記憶體單元“B”的任何次閾值洩漏,從而抑制對未選定單元“B”的程式干擾。而且,即使當電源電壓Vcc變化時,由於選定SG電壓和未選定BL電壓兩者都被精確的電壓調節電路調節,所以在未選定記憶體單元的選擇閘極(SG)和汲極(D)之間的-0.3V偏壓被予以保持。 FIG. 4 illustrates a table 400 of regulated select gate (SG) and bit line (BL) voltages applied during program operation according to an exemplary embodiment in which the power supply voltage Vcc = 1.1V. As illustrated in Figure 4, during the program operation, both the selected SG line voltage and the unselected BL voltage are adjusted to a voltage different from the power supply voltage-for example, the SG line voltage is adjusted at 0.9V (as shown in 404), and the BL voltage It is adjusted at ~ 0.4V for selected memory cells (as shown at 402A) and 1.2V for unselected memory cells (as shown at 402B). The benefit of this voltage regulation and application scheme is that the SG of the unselected memory cell "B" has a -0.3V bias between its selection gate (SG) and its drain (D). This bias condition helps to eliminate any sub-threshold leakage of the unselected memory cell "B" during programming of the selected memory cell "A", thereby suppressing program interference to the unselected cell "B". Moreover, even when the power supply voltage Vcc changes, since both the selected SG voltage and the unselected BL voltage are adjusted by the precise voltage adjustment circuit, the selection gate (SG) and the drain (D) of the unselected memory cell A -0.3V bias is maintained between them.
在一些實施例中,選定選擇閘極(SG)線路電壓可通過在 製造時所產生的調整值進行調整,其產生特別針對每個裸片(或IC晶片)或分別針對快閃記憶體陣列的每個記憶體區塊。以此方式,只要根據每個晶圓或每個裸片的選擇/通路電晶體的閾值電壓VT來精確地調整用於程式操作的選定SG電壓,即使在製造時總會存在製程變化而導致閾值電壓VT的變化,在本文所述技術仍提供可靠抑制未選定單元的程式干擾。例如,在具有高SG電晶體VT的裸片上,未選定單元(例如圖4中的單元“B”)的次閾值洩漏是低的,並且在本文所述的調整確保選定SG電壓保持足夠高以在選定單元上的程式操作期間導通選定單元(例如圖4中的單元“A”)的SG電晶體。而且,在具有高SG電晶體VT的此裸片上,未選定BL電壓不需要在非常高的電壓下被修整。另一方面,在具有低SG電晶體VT的裸片上,未選定單元(例如圖4中的單元“B”)的次閾值洩漏將是高的並且因此是主要關注,但是在本文所述的調整確保選定SG電壓將保持足夠低以在選定單元(例如圖4中的單元“A”)上的程式操作期間關閉未選定單元的SG電晶體。 In some embodiments, the selected selection gate (SG) line voltage can be adjusted by an adjustment value generated at the time of manufacture, which generates a specific voltage for each die (or IC chip) or separately for the flash memory array. Each memory block. In this way, as long as the selected SG voltage for program operation is precisely adjusted according to the threshold voltage V T of the selection / pass transistor of each wafer or each die, even if there is always a process change during manufacturing, The variation of the threshold voltage V T still provides reliable suppression of program interference of unselected cells. For example, on a die with a high SG transistor V T , the subthreshold leakage of unselected cells (such as cell "B" in Figure 4) is low, and the adjustments described herein ensure that the selected SG voltage remains sufficiently high The SG transistor is turned on during the program operation on the selected cell (for example, cell "A" in FIG. 4). Moreover, on this die with a high SG transistor V T , the unselected BL voltage does not need to be trimmed at a very high voltage. On the other hand, on a die with a low SG transistor V T , the sub-threshold leakage of unselected cells (such as cell "B" in Figure 4) will be high and therefore of primary concern, but as described herein The adjustment ensures that the selected SG voltage will remain low enough to turn off the SG transistors of the unselected cells during program operation on the selected cells (eg, cell "A" in Figure 4).
在一些實施例中,可基於非揮發性記憶體(NVM)裝置在其操作期間的溫度來自動調整選定選擇閘極(SG)線路電壓和未選定位元線路(BL)電壓。這可能是需要的原因在於SG電晶體的閾值電壓VT在較高操作溫度下變得較低。例如,當選定記憶體單元(例如圖4中的單元“A”)在高溫下進行編程時,為完全關斷未選定記憶體單元(例如圖4中的單元“B”)的SG電晶體,選定SG電壓需要較低。另一方面,當選定記憶體單元(例如圖4中的單元“A”)在低溫下進行編程時,為完全導通選定單元的SG電晶體(其在低溫下具有較高VT),選定SG電壓需要更高。在一些實 施例中,這種基於溫度的電壓調整可通過使用溫度感測和控制電路來實施。當這種電路感測到NVM裝置的操作溫度升高時,電路將適當的溫度指示信號發送到電壓調節電路,並且電壓調節電路將選定SG偏壓自動調節到較低電壓。當溫度感測和控制電路感測到NVM裝置的操作溫度降低時,電路將適當的溫度指示信號發送到電壓調節電路,並且電壓調節電路將選定SG偏壓自動調節到更高電壓。以這種方式,在本文所述的技術提供選定SG偏置電壓和未選定BL電壓,其在NVM裝置需要操作的整個溫度範圍上足以防止未選定記憶體單元的程式干擾。 In some embodiments, the selected selected gate (SG) line voltage and the unselected locator line (BL) voltage may be automatically adjusted based on the temperature of a non-volatile memory (NVM) device during its operation. This may be necessary because the threshold voltage V T of the SG transistor becomes lower at higher operating temperatures. For example, when a selected memory cell (such as cell "A" in FIG. 4) is programmed at a high temperature, to completely turn off the SG transistor of an unselected memory cell (such as cell "B" in FIG. 4), The selected SG voltage needs to be lower. On the other hand, when a selected memory cell (for example, cell "A" in FIG. 4) is programmed at a low temperature, in order to completely turn on the SG transistor of the selected cell (which has a higher V T at a low temperature), SG is selected The voltage needs to be higher. In some embodiments, such temperature-based voltage adjustment may be implemented using temperature sensing and control circuits. When this circuit senses that the operating temperature of the NVM device has increased, the circuit sends an appropriate temperature indication signal to the voltage adjustment circuit, and the voltage adjustment circuit automatically adjusts the selected SG bias voltage to a lower voltage. When the temperature sensing and control circuit senses a decrease in the operating temperature of the NVM device, the circuit sends an appropriate temperature indication signal to the voltage adjustment circuit, and the voltage adjustment circuit automatically adjusts the selected SG bias voltage to a higher voltage. In this way, the techniques described herein provide selected SG bias voltages and unselected BL voltages, which are sufficient to prevent program interference of unselected memory cells over the entire temperature range that the NVM device needs to operate.
圖5說明根據例示實施例的用於抑制非揮發性記憶體陣列中的程式干擾的方法的流程圖。圖5中的方法操作被敘述成通過非揮發性記憶體(NVM)裝置的控制電路(和/或其中的電路)來執行。然而,應當指出的是各種實施方式和實施例可使用各種並且可能不同的硬體組件來執行圖5中的方法操作。例如在各種實施例中,MCU可被配置有韌體指令,其在被執行時操作上導致圖5中方法執行在嵌入式NVM裝置上。在另一個實例中,在各種實施例中,NVM系統可包括被配置為執行圖5中的方法操作的單晶片或多晶片控制器。因此,由控制電路(和/或其中的電路)所執行圖5中的方法操作的後續敘述應該被認為是說明性而非限制性。 5 illustrates a flowchart of a method for suppressing program interference in a non-volatile memory array according to an exemplary embodiment. The method operation in FIG. 5 is described as being performed by a control circuit (and / or a circuit therein) of a non-volatile memory (NVM) device. It should be noted, however, that various implementations and embodiments may use various and possibly different hardware components to perform the method operations in FIG. 5. For example, in various embodiments, the MCU may be configured with firmware instructions that, when executed, cause the method in FIG. 5 to be executed on the embedded NVM device. In another example, in various embodiments, the NVM system may include a single-chip or multi-chip controller configured to perform the method operations in FIG. 5. Therefore, the subsequent description of the operation of the method in FIG. 5 performed by the control circuit (and / or the circuit therein) should be considered as illustrative and not restrictive.
在操作502中,NVM裝置的控制電路執行記憶體操作以對快閃記憶體陣列中的選定記憶體單元進行編程,快閃記憶體陣列向其記憶體單元提供共用源極線路和共用選擇閘極(SG)線路。在各種實施例中,快閃記憶體陣列可包括被製造為諸如40nm節點或28nm節點的較小幾何節點記憶體單元。 In operation 502, the control circuit of the NVM device performs a memory operation to program a selected memory cell in the flash memory array. The flash memory array provides a shared source line and a shared selection gate to the memory cell. (SG) line. In various embodiments, the flash memory array may include smaller geometric node memory cells that are manufactured such as a 40 nm node or a 28 nm node.
在操作504中,控制電路(或其中的電壓調節電路)獨立於NVM裝置的電源電壓來精確地調節選定SG線路的第一電壓,其中選定SG線路被耦合到選定記憶體單元。在程式操作期間,控制電路(或其中的電壓調節電路)向選定SG線路施加0.9V的調節電壓,此電壓低於電源電壓(例如1.1V)。 In operation 504, the control circuit (or a voltage adjustment circuit therein) accurately adjusts the first voltage of the selected SG line independently of the power supply voltage of the NVM device, wherein the selected SG line is coupled to the selected memory unit. During the program operation, the control circuit (or the voltage regulating circuit therein) applies a regulated voltage of 0.9V to the selected SG line, which voltage is lower than the power supply voltage (for example, 1.1V).
在操作506中,控制電路(或其中的電壓調節電路)獨立於NVM裝置的電源電壓來精確地調節未選定位元線路(BL)的第二電壓。未選定BL被耦合到在快閃記憶體陣列的同一列中相鄰選定記憶體單元的記憶體單元,並且因此與選定單元共享至少一個共用源極。例如,相鄰的記憶體單元可緊挨著選定記憶體單元、或者是可以是經定位以與選定單元相距一個或多個行的相鄰單元。在程式操作期間,控制電路(或其中的電壓調節電路)向未選定BL施加1.2V的調節電壓,此電壓高於電源電壓(例如1.1V)。 In operation 506, the control circuit (or a voltage adjustment circuit therein) accurately adjusts the second voltage of the unselected locating element line (BL) independently of the power supply voltage of the NVM device. Unselected BLs are coupled to memory cells adjacent to selected memory cells in the same column of the flash memory array, and therefore share at least one common source with the selected cells. For example, adjacent memory cells may be next to the selected memory cell or may be adjacent cells positioned one or more rows away from the selected cell. During program operation, the control circuit (or the voltage adjustment circuit therein) applies a 1.2V adjustment voltage to the unselected BL, which is higher than the power supply voltage (for example, 1.1V).
在操作508中,控制電路基於NVM裝置和/或其中的快閃記憶體陣列的操作溫度來自動調整第一電壓(被施加到選定SG線路)和第二電壓(被施加到未選定位元線路)中的一個或兩者。例如,在選定記憶體單元的程式操作期間,溫度感測電路可感測操作溫度並且可向控制電路(或其中的電壓調節電路)發送溫度指示信號。響應於溫度指示信號,控制電路(或其中的電壓調節電路)可自動調整選定SG電壓和/或未選定BL電壓。例如,當溫度指示信號指示操作溫度正在增加時,選定SG電壓可被自動調整到較低電壓,和/或未選定BL電壓可被自動調整到較高電壓。當溫度指示信號指示操作溫度正在下降時,選定SG電壓可被自動調整到較高 電壓,和/或未選定BL電壓可被自動調整到較低電壓。 In operation 508, the control circuit automatically adjusts the first voltage (applied to the selected SG line) and the second voltage (applied to the unselected locator element line) based on the operating temperature of the NVM device and / or the flash memory array therein. ) One or both. For example, during a program operation of a selected memory unit, the temperature sensing circuit may sense an operating temperature and may send a temperature indication signal to a control circuit (or a voltage regulating circuit therein). In response to the temperature indication signal, the control circuit (or a voltage adjustment circuit therein) may automatically adjust the selected SG voltage and / or the unselected BL voltage. For example, when the temperature indication signal indicates that the operating temperature is increasing, the selected SG voltage may be automatically adjusted to a lower voltage, and / or the unselected BL voltage may be automatically adjusted to a higher voltage. When the temperature indication signal indicates that the operating temperature is decreasing, the selected SG voltage may be automatically adjusted to a higher voltage, and / or the unselected BL voltage may be automatically adjusted to a lower voltage.
在各種實施例中,在本文所述用於抑制非揮發性記憶體(NVM)裝置中的程式干擾的技術提供用於獨立於NVM裝置的電源電壓以調節選定擇選擇閘極(SG)電壓和未選定位元線路(BL)電壓。這些經調節電壓可在操作期間基於所感測的NVM裝置的操作溫度來重新配置。例如在製造時,NVM裝置可被配置有用於經調節電壓的調整值,其中此些調整值可被配置為針對NVM裝置晶片整體,或分別針對NVM裝置的每個記憶體區塊。以這種方式,在本文所述技術可適應晶圓到晶圓,晶片到晶片和區塊到區塊的製程變化,並且仍然提供充分的程式干擾抑制。此外,在本文所述用於抑制程式干擾的技術使得40nm嵌入式快閃記憶體陣列能夠在高溫(例如高達150℃)下操作,而無需在位元線路(BL)偏置電路中使用任何高電壓裝置,從而保持快閃記憶體陣列的較小矽片段。 In various embodiments, the techniques described herein for suppressing programmatic interference in non-volatile memory (NVM) devices provide a power supply voltage independent of the NVM device to adjust the selected gate (SG) voltage and The locating element line (BL) voltage is not selected. These adjusted voltages can be reconfigured during operation based on the sensed operating temperature of the NVM device. For example, at the time of manufacture, the NVM device may be configured with adjustment values for the adjusted voltage, where such adjustment values may be configured for the entire NVM device chip, or for each memory block of the NVM device, respectively. In this way, the techniques described herein can accommodate wafer-to-wafer, wafer-to-wafer, and block-to-block process variations, while still providing adequate program interference suppression. In addition, the techniques described in this article for suppressing program interference enable 40nm embedded flash memory arrays to operate at high temperatures (e.g., up to 150 ° C) without using any high voltage in the bit line (BL) bias circuit. Voltage device to keep smaller silicon fragments of the flash memory array.
在本文所述用於抑制記憶體裝置中的程式干擾的技術的各種實施例可包括各種操作。這些操作可由硬體組件、韌體或前述組合來執行。如本文所使用,術語“耦合到”和“耦合於”意謂味直接耦合或通過一個或多個中間組件間接耦合。在本文所述經過各種匯流排所提供的任何信號可與其它信號進行分時多工,並且經過一個或多個共用匯流排予以提供。此外,在電路組件或區塊之間的互連可被顯示為匯流排或單一信號線路。每個匯流排可選擇為一個或多個單一信號線路,並且每個單一信號線路可選擇為匯流排。 Various embodiments of the techniques described herein for suppressing programmatic interference in a memory device may include various operations. These operations can be performed by hardware components, firmware, or a combination of the foregoing. As used herein, the terms "coupled to" and "coupled to" mean directly coupled or indirectly coupled through one or more intermediate components. Any signal provided through the various buses described herein can be time-multiplexed with other signals and provided via one or more shared buses. In addition, interconnections between circuit components or blocks may be shown as a bus or a single signal line. Each bus can be selected as one or more single signal lines, and each single signal line can be selected as a bus.
某些實施例可被實施為在例如揮發性記憶體和/或非揮發性記憶體的非臨時電腦可讀取媒體上所儲存的可執行韌體指令。這樣指令可 被用來對包括一個或多個通用或專用處理器(例如諸如中央處理單元或CPU)或其等同物(例如諸如處理核心、處理引擎、微控制器和類似元件)的一個或多個裝置進行編程,使得當由處理器或其等同物執行時,指令使裝置執行各種操作。非暫時電腦可讀取媒體可包括但不限於電磁儲存媒體(例如,軟碟、硬碟和類似元件),光儲存媒體(例如CD-ROM)、磁光儲存媒體、唯讀記憶體(ROM)、隨機存取記憶體(RAM)、可擦除可編程記憶體(例如EPROM和EEPROM)、快閃記憶體、或適合儲存資訊之另一現在已知或後來開發的媒體類型。 Certain embodiments may be implemented as executable firmware instructions stored on a non-transitory computer-readable medium such as volatile memory and / or non-volatile memory. Such instructions may be used to include one or more general or special purpose processors (e.g., such as a central processing unit or CPU) or their equivalents (e.g., such as a processing core, processing engine, microcontroller, and similar elements). Each device is programmed such that, when executed by a processor or equivalent, the instructions cause the device to perform various operations. Non-transitory computer-readable media may include, but is not limited to, electromagnetic storage media (e.g., floppy disks, hard disks, and similar components), optical storage media (e.g., CD-ROM), magneto-optical storage media, read-only memory (ROM) , Random access memory (RAM), erasable programmable memory (such as EPROM and EEPROM), flash memory, or another type of media now known or later developed suitable for storing information.
儘管在本文中的任何方法的操作可以特定順序顯示和敘述,但是可改變每個方法的操作順序而使得某些操作可以相反順序執行、或使得某些操作可至少部分地與其它操作同時執行。在其它實施例中,不同操作的指令或子操作可以是非連續和/或交替方式。 Although the operations of any method herein may be shown and described in a particular order, the order of operations of each method may be changed so that certain operations may be performed in the reverse order, or certain operations may be performed at least partially simultaneously with other operations. In other embodiments, instructions or sub-operations of different operations may be discontinuous and / or alternating.
在前述發明說明中,已經參考本發明的具體例示性實施例敘述本發明。然而,顯而易見的是可予以進行各種修改和改變,而不偏離如後附申請專利範圍中所闡述本發明更為廣泛的精神和範疇。因此,說明書和圖式被認為是說明性而非限制性。 In the foregoing description of the invention, the invention has been described with reference to specific exemplary embodiments of the invention. It will be apparent, however, that various modifications and changes may be made without departing from the broader spirit and scope of the invention as set forth in the scope of the appended patents. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.
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