TWI650637B - Inspection method for memory integrity, nonvolatile memory and electronic device - Google Patents
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Abstract
一種記憶體完整性的檢驗方法、非揮發性記憶體以及電子裝置。所述方法包括下列步驟。獲得非揮發性記憶體中至少一待檢驗記憶胞的閥值電壓。將讀取電壓以及所述閥值電壓進行比對來判斷所述至少一待檢驗記憶胞所屬的資料值。當確認所述至少一待檢驗記憶胞所屬的所述資料值後，依據所述資料值來設定預設電壓。將所述預設電壓與所述至少一待檢驗記憶胞的所述閥值電壓進行比對而獲得所述至少一待檢驗記憶胞的偏移資料值。以及，判斷所述至少一待檢驗記憶胞所屬的所述資料值以及所述偏移資料值是否相同，從而判定所述至少一待檢驗記憶胞的完整性是否有缺陷。A method for verifying memory integrity, non-volatile memory, and electronic devices. The method includes the following steps. Obtaining a threshold voltage of at least one memory cell to be tested in the non-volatile memory. And comparing the read voltage and the threshold voltage to determine a data value to which the at least one memory cell to be tested belongs. After confirming the data value to which the at least one memory cell to be tested belongs, the preset voltage is set according to the data value. And comparing the preset voltage with the threshold voltage of the at least one memory cell to be tested to obtain an offset data value of the at least one memory cell to be tested. And determining whether the data value of the at least one memory cell to be tested and the offset data value are the same, thereby determining whether the integrity of the at least one memory cell to be tested is defective.
Description
本發明是有關於一種記憶體的檢驗技術，且特別是有關於一種記憶體完整性的檢驗方法、非揮發性記憶體以及電子裝置。The present invention relates to a memory inspection technique, and more particularly to a memory integrity inspection method, a non-volatile memory, and an electronic device.
在不供電期間中仍可長時間儲存資料的非揮發性記憶體（如，快取記憶體）是諸多電子裝置中的必要組件之一。非揮發性記憶體的可靠度問題與其自身的資料保留（data retention）生命期限有關，換句話說，非揮發性記憶體可能因為諸多原因或潛在理由而導致縮減自身可保留資料的時間，或是在存取資料時受到傷害，因而發生非揮發性記憶體對資料存取的劣化。這些潛在理由例如是，進行資料循環（如，程式化／抹除）操作之後的壓力依賴漏流（Stress Induced Leakage Current（SILC））、程式化／抹除操作中的擾亂問題、裝置中的游離離子、出廠前並未發現的記憶體物理缺陷…等。Non-volatile memory (eg, cache memory) that can store data for extended periods of time during periods of no power supply is one of the essential components in many electronic devices. The reliability of non-volatile memory is related to its own data retention lifespan. In other words, non-volatile memory may reduce the time it takes to retain data for a number of reasons or potential reasons, or It is hurt when accessing data, and thus the degradation of data access by non-volatile memory occurs. These potential reasons are, for example, Stress Induced Leakage Current (SILC) after data cycling (eg, stylization/erasing) operations, disturbances in stylized/erase operations, and free in the device. Ion, memory physical defects not found before leaving the factory...etc.
在一般性消費型電子裝置來說，記憶體中的資料出錯僅導致部分資料錯誤或功能缺失，並可藉由許多方式進行補救。然而，若以自駕車或自動駕駛領域來說，部分資料的錯誤或系統延遲皆有可能導致系統當機，從而直接地關乎使用者的生命。為避免上述情況發生，在ISO 26262協定所規定的《道路車輛功能安全》國際標準中規定了汽車領域所使用的電子設備需要透過危害分析與風險評估（Hazard Analysis & Risk Assessment，HARA），以使產品的功能安全符合汽車安全完整性等級（ASIL）。因此，如何讓電子產品能夠診斷非揮發性記憶體的資料保留生命期限即將抵達，並在發現上述情況時能立刻處置，便是可作為技術研議的方向之一。In general consumer electronic devices, errors in the data in the memory only result in partial data errors or missing functions, and can be remedied in many ways. However, in the case of self-driving or autonomous driving, some data errors or system delays may cause the system to crash, which is directly related to the user's life. In order to avoid this, the international standards for road vehicle functional safety specified in the ISO 26262 Agreement stipulate that the electronic equipment used in the automotive field needs to pass the Hazard Analysis & Risk Assessment (HARA). The functional safety of the product complies with the Automotive Safety Integrity Level (ASIL). Therefore, how to make electronic products capable of diagnosing non-volatile memory data retention life is about to arrive, and can be disposed of immediately when the above conditions are discovered, which can be one of the directions of technical research.
本發明提供一種記憶體完整性的檢驗方法、非揮發性記憶體以及使用此非揮發性記憶體的電子裝置，可自行判斷非揮發性記憶體中的待檢測記憶胞是否完好或是已開始出現劣化可能有損壞風險的情況下，從而讓非揮發性記憶體以及電子裝置的功能安全能夠符合國際標準規定。The invention provides a method for checking the integrity of a memory, a non-volatile memory and an electronic device using the non-volatile memory, and can determine whether the memory cell to be detected in the non-volatile memory is intact or has begun to appear. Degradation may be at risk of damage, so that the functional safety of non-volatile memory and electronic devices can comply with international standards.
本揭露的記憶體完整性的檢驗方法包括下列步驟。獲得非揮發性記憶體中至少一待檢驗記憶胞的閥值電壓。將讀取電壓以及所述閥值電壓進行比對來判斷所述至少一待檢驗記憶胞所屬的資料值。當確認所述至少一待檢驗記憶胞所屬的所述資料值後，依據所述資料值來設定預設電壓。將所述預設電壓與所述至少一待檢驗記憶胞的所述閥值電壓進行比對而獲得所述至少一待檢驗記憶胞的偏移資料值。以及，判斷所述至少一待檢驗記憶胞所屬的所述資料值以及所述偏移資料值是否相同，從而判定所述至少一待檢驗記憶胞的完整性是否有缺陷。The method for verifying memory integrity of the present disclosure includes the following steps. Obtaining a threshold voltage of at least one memory cell to be tested in the non-volatile memory. And comparing the read voltage and the threshold voltage to determine a data value to which the at least one memory cell to be tested belongs. After confirming the data value to which the at least one memory cell to be tested belongs, the preset voltage is set according to the data value. And comparing the preset voltage with the threshold voltage of the at least one memory cell to be tested to obtain an offset data value of the at least one memory cell to be tested. And determining whether the data value of the at least one memory cell to be tested and the offset data value are the same, thereby determining whether the integrity of the at least one memory cell to be tested is defective.
本揭露的非揮發性記憶體包括記憶體陣列以及控制電路。記憶體陣列包括多個記憶胞，且控制電路耦接所述記憶體陣列。控制電路進行記憶體的資料完整性檢驗以獲得所述記憶胞中的至少一待檢驗記憶胞的閥值電壓，將讀取電壓以及所述閥值電壓進行比對來判斷所述至少一待檢驗記憶胞所屬的資料值。當確認所述至少一待檢驗記憶胞所屬的所述資料值後，控制電路依據所述資料值來設定預設電壓，將所述預設電壓與所述至少一待檢驗記憶胞的所述閥值電壓進行比對而獲得所述至少一待檢驗記憶胞的偏移資料值，判斷所述至少一待檢驗記憶胞所屬的所述資料值以及所述偏移資料值是否相同，從而判定所述至少一待檢驗記憶胞的完整性是否有缺陷。The non-volatile memory of the present disclosure includes a memory array and a control circuit. The memory array includes a plurality of memory cells, and a control circuit is coupled to the memory array. The control circuit performs a data integrity check of the memory to obtain a threshold voltage of at least one memory cell to be tested in the memory cell, and compares the read voltage and the threshold voltage to determine the at least one to be tested The data value to which the memory cell belongs. After confirming the data value to which the at least one memory cell to be tested belongs, the control circuit sets a preset voltage according to the data value, and the preset voltage and the valve of the at least one memory cell to be tested And determining, by comparing the value voltages, the offset data values of the at least one memory cell to be tested, determining whether the data value of the at least one memory cell to be tested and the offset data value are the same, thereby determining the At least one integrity of the memory cell to be tested is defective.
本揭露的電子裝置包括非揮發性記憶體以及控制器。非揮發性記憶體包括記憶體陣列以及狀態暫存器。控制器耦接所述非揮發性記憶體。控制器發送資料完整性診斷指令至所述非揮發性記憶體，對所述非揮發性記憶體發送第一資料讀取指令，以獲得所述狀態暫存器中的狀態資料，並依據所述狀態資料中的忙碌位元來判斷所述非揮發性記憶體是否完成所述資料完整性診斷指令。當所述資料完整性診斷指令已完成時，控制器對所述非揮發性記憶體發送第二資料讀取指令，以獲得所述狀態暫存器的所述狀態資料中的完整性驗證位元，並依據所述完整性驗證位元來判斷所述記憶體陣列中的多個記憶胞的完整性是否有缺陷。當非揮發性記憶體接收資料完整性診斷指令後，將讀取電壓以及所述閥值電壓進行比對來判斷所述至少一待檢驗記憶胞所屬的資料值。當確認所述至少一待檢驗記憶胞所屬的資料值後，非揮發性記憶體依據所述資料值來設定預設電壓，將所述預設電壓與所述至少一待檢驗記憶胞的所述閥值電壓進行比對而獲得所述至少一待檢驗記憶胞的偏移資料值，以及判斷所述至少一待檢驗記憶胞所屬的所述資料值以及所述偏移資料值是否相同，從而判定所述至少一待檢驗記憶胞的完整性是否有缺陷。The electronic device of the present disclosure includes a non-volatile memory and a controller. Non-volatile memory includes a memory array and a state register. The controller is coupled to the non-volatile memory. The controller sends a data integrity diagnostic command to the non-volatile memory, and sends a first data read command to the non-volatile memory to obtain status data in the status register, and according to the The busy bit in the status data determines whether the non-volatile memory completes the data integrity diagnostic instruction. When the data integrity diagnosis instruction has been completed, the controller sends a second data read instruction to the non-volatile memory to obtain an integrity verification bit in the status data of the status register. And determining, according to the integrity verification bit, whether the integrity of the plurality of memory cells in the memory array is defective. After the non-volatile memory receives the data integrity diagnosis command, the read voltage and the threshold voltage are compared to determine the data value to which the at least one memory cell to be tested belongs. After confirming the data value of the at least one memory cell to be tested, the non-volatile memory sets a preset voltage according to the data value, and the preset voltage and the at least one memory cell to be tested are And determining, by comparing the threshold voltages, the offset data values of the at least one memory cell to be tested, and determining whether the data value of the at least one memory cell to be tested and the offset data value are the same, thereby determining Whether the integrity of the at least one memory cell to be tested is defective.
基於上述，本發明實施例所述之記憶體完整性的檢驗方法、非揮發性記憶體以及使用此非揮發性記憶體的電子裝置可對非揮發性記憶體中的多個待檢測記憶胞依據資料值所設定的預設電壓來與待檢測記憶胞的閥值電壓進行比對，以實現記憶體的資料完整性檢驗，從而判斷此待檢測記憶胞是否完好或是處於即將損壞但仍可使用的情況（亦即，記憶體完整性有缺陷）。換句話說，為避免非揮發性記憶體損壞，本發明實施例的非揮發性記憶體可先行對各個記憶胞進行自檢其記憶體完整性是否良好，從而讓電子裝置能夠提前知曉非揮發性記憶體是否有機率損毀，致使電子裝置的功能安全能夠符合國際標準規定。Based on the above, the method for verifying the integrity of the memory, the non-volatile memory, and the electronic device using the non-volatile memory according to the embodiments of the present invention may be based on a plurality of memory cells to be detected in the non-volatile memory. The preset voltage set by the data value is compared with the threshold voltage of the memory cell to be detected, so as to implement the data integrity check of the memory, thereby determining whether the memory cell to be detected is intact or is about to be damaged but still usable. The situation (ie, memory integrity is flawed). In other words, in order to avoid non-volatile memory damage, the non-volatile memory of the embodiment of the present invention can perform self-test on each memory cell to check whether the memory integrity is good, so that the electronic device can know the non-volatile in advance. Whether the memory is damaged or not, so that the functional safety of the electronic device can comply with international standards.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1是依照本發明實施例的一種電子裝置100的功能方塊圖。電子裝置100包括控制器110以及非揮發性記憶體120。控制器110可以是中央處理單元（CPU）或是記憶體控制器。非揮發性記憶體120主要包括控制電路122以及記憶體陣列128。非揮發性記憶體120還可包括狀態暫存器124以及電壓產生器126。非揮發性記憶體120可以是快取記憶體，在此以串列式（SPI）NOR型快閃記憶體實現非揮發性記憶體120。本實施例的呈現方式可以是以電子裝置100為主體、或是以非揮發性記憶體120為主體來呈現。記憶體陣列128可包括多個記憶胞。1 is a functional block diagram of an electronic device 100 in accordance with an embodiment of the present invention. The electronic device 100 includes a controller 110 and a non-volatile memory 120. The controller 110 can be a central processing unit (CPU) or a memory controller. The non-volatile memory 120 mainly includes a control circuit 122 and a memory array 128. The non-volatile memory 120 can also include a state register 124 and a voltage generator 126. The non-volatile memory 120 can be a cache memory, where the non-volatile memory 120 is implemented in a tandem (SPI) NOR type flash memory. The presentation manner of this embodiment may be based on the electronic device 100 or the non-volatile memory 120 as a main body. Memory array 128 can include a plurality of memory cells.
為使電子裝置100以及非揮發性記憶體120能夠具備對於非揮發性記憶體120自身功能的危害分析與風險評估（HARA），本發明實施例的非揮發性記憶體120可通過進行記憶體的資料完整性檢驗來自行判斷記憶體陣列128中的待檢測記憶胞是否完好、或是已開始出現劣化可能有損壞風險的情況下（在此稱此情況為記憶體完整性有缺陷）。換句話說，為避免非揮發性記憶體120損壞，本發明實施例可先行對各個記憶胞進行自檢其記憶體完整性是否有缺陷，從而讓電子裝置100能夠提前知曉非揮發性記憶體120是否有損毀的風險，致使電子裝置100的功能安全能夠符合國際標準規定。In order to enable the electronic device 100 and the non-volatile memory 120 to have a hazard analysis and risk assessment (HARA) for the non-volatile memory 120's own functions, the non-volatile memory 120 of the embodiment of the present invention can pass through the memory. The data integrity check comes from the case where the memory cell to be detected in the memory array 128 is judged to be in good condition, or the risk of damage may be caused by deterioration (herein, the memory integrity is defective). In other words, in order to prevent the non-volatile memory 120 from being damaged, the embodiment of the present invention may perform a self-check on each memory cell to check whether the memory integrity is defective, so that the electronic device 100 can know the non-volatile memory 120 in advance. Whether there is a risk of damage, the functional safety of the electronic device 100 can comply with international standards.
圖2是依照本發明實施例說明預設電壓DM1/DM2、記憶胞的資料完整性區間DII1/DII2、失效電壓Ve1/Ve2、以及辨識區間EM的示意圖。圖2是以快取記憶體作為本實施例中圖1的非揮發性記憶體120的實作範例。快取記憶體的記憶胞數量（圖2中的縱軸）與記憶胞的閥值電壓（圖2中的橫軸）之間的關係可如圖2所示。當記憶胞的閥值電壓大於預設的讀取電壓Vread時，可認為記憶胞的資料值為邏輯”0”；當記憶胞的閥值電壓小於預設的讀取電壓Vread時，可認為記憶胞的資料值為邏輯”1”。一般而言，在正常使用下的快取記憶體（即，記憶體完整性無缺陷）中，記憶胞的閥值電壓在經過程式化／抹除操作後通常落入區域A1或區域A2。FIG. 2 is a schematic diagram illustrating a preset voltage DM1/DM2, a data integrity interval DII1/DII2 of a memory cell, a fail voltage Ve1/Ve2, and an identification interval EM according to an embodiment of the invention. FIG. 2 is a practical example of the non-volatile memory 120 of FIG. 1 in the present embodiment. The relationship between the number of memory cells of the cache memory (vertical axis in FIG. 2) and the threshold voltage of the memory cell (horizontal axis in FIG. 2) can be as shown in FIG. 2. When the threshold voltage of the memory cell is greater than the preset read voltage Vread, the data value of the memory cell can be considered as logic "0"; when the threshold voltage of the memory cell is less than the preset read voltage Vread, the memory can be regarded as memory The data value of the cell is a logic "1". In general, in a cache memory under normal use (ie, memory integrity is not defective), the threshold voltage of the memory cell typically falls into region A1 or region A2 after a stylization/erasing operation.
然而，在快取記憶體的實際運作中，記憶胞的閥值電壓常會隨資料循環的次數慢慢出現劣化的現象而往無法判斷記憶胞資料值的辨識區間EM移動。詳細而言，當記憶胞的閥值電壓出現劣化的現象而落入辨識區間EM中時，快取記憶體所屬的控制電路將可能無法識別記憶胞中所儲存的資料為邏輯”0”或是邏輯”1”，因而導致控制電路無法讀取記憶胞。其中，辨識區間EM位於邏輯”0”對應的失效電壓Ve1以及邏輯”1”對應的失效電壓Ve2之間。此時，快取記憶體將可能會發生資料讀取錯誤而直接使得電子裝置的功能缺失。換句話說，當記憶胞的閥值電壓落入辨識區間EM中時，快取記憶體便可能會直接損壞而無法進行其他操作。However, in the actual operation of the cache memory, the threshold voltage of the memory cell often degrades with the number of data cycles, and the recognition interval EM of the memory cell data value cannot be determined. In detail, when the threshold voltage of the memory cell is degraded and falls into the identification interval EM, the control circuit to which the cache memory belongs may not be able to recognize that the data stored in the memory cell is logic "0" or Logic "1", thus causing the control circuit to be unable to read the memory cells. The identification interval EM is located between the failure voltage Ve1 corresponding to the logic “0” and the failure voltage Ve2 corresponding to the logic “1”. At this time, the cache memory may have a data reading error and directly cause the function of the electronic device to be missing. In other words, when the threshold voltage of the memory cell falls within the identification interval EM, the cache memory may be directly damaged and cannot be operated.
因此本發明實施例希望可讓非揮發性記憶體120先行對各個記憶胞進行自檢以判斷其記憶體完整性是否有缺陷，進而提前防止當記憶胞的閥值電壓落入辨識區間EM中發生讀取錯誤才發現的狀況。如圖2所示，在區域A1到辨識區間EM之間具備區間DII1，且在區域A2到辨識區間EM之間具備區間DII2，若偵測到記憶胞的閥值電壓位於這兩個區間DII1及DII2時，可發現此記憶胞雖然可以正常使用（亦即，非揮發性記憶體可正常判斷此記憶胞的資料值），但此記憶胞已開始出現劣化的傾向，其被存取速度以及反應時間事實上已較正常記憶胞來說來的較慢，可能有損壞的風險（在此將其視為記憶體完整性有缺陷）。Therefore, the embodiment of the present invention hopes that the non-volatile memory 120 can perform self-test on each memory cell to determine whether the memory integrity is defective, thereby preventing the threshold voltage of the memory cell from falling into the identification interval EM in advance. The condition that was discovered only after reading the error. As shown in FIG. 2, a section DII1 is provided between the area A1 and the identification section EM, and a section DII2 is provided between the area A2 and the identification section EM, and the threshold voltage of the memory cell is detected in the two sections DII1 and In DII2, it can be found that although the memory cell can be used normally (that is, the non-volatile memory can judge the data value of the memory cell normally), the memory cell has begun to show a tendency to deteriorate, and its access speed and response. Time is actually slower than normal memory cells and may be at risk of damage (here considered to be a defect in memory integrity).
因此，本發明實施例的主要概念在於，對非揮發性記憶體120中的每個記憶胞進行記憶體的完整性檢驗已確認其閥值電壓是否仍落在區域A1及A2或已落入資料完整性區間DII1及區間DII2當中。若是有記憶胞落在資料完整性區間DII1或DII2當中時，表示非揮發性記憶體中的部分記憶胞可能有所劣化，因而可認定此非揮發性記憶體的資料完整性有缺陷。Therefore, the main concept of the embodiment of the present invention is that the memory integrity check of each memory cell in the non-volatile memory 120 has confirmed whether the threshold voltage still falls in the areas A1 and A2 or has fallen into the data. Integrity interval DII1 and interval DII2. If there is a memory cell falling in the data integrity interval DII1 or DII2, it means that some of the memory cells in the non-volatile memory may be degraded, so the data integrity of the non-volatile memory may be considered to be defective.
區間DII1位於邏輯”0”對應的預設電壓DM1以及邏輯”0”對應的失效電壓Ve1之間。區間DII2位於邏輯”1”對應的預設電壓DM2以及邏輯”1”對應的失效電壓Ve2之間。預設電壓DM1/DM2減去讀取電壓Vread的絕對值大於失效電壓Ve1/Ve2減去讀取電壓Vread的絕對值。資料完整性區間DII1及區間DII2與辨識區間EM互不重疊。The interval DII1 is located between the preset voltage DM1 corresponding to the logic “0” and the fail voltage Ve1 corresponding to the logic “0”. The interval DII2 is located between the preset voltage DM2 corresponding to the logic "1" and the failure voltage Ve2 corresponding to the logic "1". The absolute value of the preset voltage DM1/DM2 minus the read voltage Vread is greater than the absolute value of the fail voltage Ve1/Ve2 minus the read voltage Vread. The data integrity interval DII1 and the interval DII2 and the identification interval EM do not overlap each other.
圖3是依照本發明實施例的控制器110對非揮發性記憶體120進行記憶體完整性的檢驗方法的流程圖。圖3主要是以控制器110為指令發送者，讓非揮發性記憶體120進行資料完整性檢驗的操作流程。請同時參照圖1及圖3，於步驟S310中，控制器110發送資料完整性診斷指令至非揮發性記憶體120的控制電路122。於步驟S320中，控制器110對非揮發性記憶體120發送第一資料讀取指令。於步驟S330中，控制器110從非揮發性記憶體120獲得非揮發性記憶體120中的狀態暫存器124的狀態資料。詳細來說，每個狀態資料具備多個位元，每個位元可以分別表示此非揮發性記憶體的各個狀態。例如，本實施例的狀態資料具備位元S0至位元S15。位元S0表示為忙碌位元，位元S10表示為完整性驗證位元。本實施例中的第一資料讀取指令可讀取狀態資料中的位元S0至S7，而本實施例中的第二資料讀取指令則可讀取狀態資料中的位元S8至S15。非揮發性記憶體120的控制電路122在接收到第一資料讀取指令時，便通過狀態暫存器124以將具備忙碌位元的狀態資料（如，位元S0至位元S7）傳遞給控制器110。3 is a flow chart of a method for the controller 110 to verify the memory integrity of the non-volatile memory 120 in accordance with an embodiment of the present invention. FIG. 3 is mainly an operation flow in which the controller 110 is the sender of the instruction and the non-volatile memory 120 performs the data integrity check. Referring to FIG. 1 and FIG. 3 simultaneously, in step S310, the controller 110 sends a data integrity diagnostic command to the control circuit 122 of the non-volatile memory 120. In step S320, the controller 110 transmits a first data read command to the non-volatile memory 120. In step S330, the controller 110 obtains the status data of the status register 124 in the non-volatile memory 120 from the non-volatile memory 120. In detail, each state data has a plurality of bits, and each bit can represent each state of the non-volatile memory. For example, the status data of this embodiment has a bit S0 to a bit S15. Bit S0 is represented as a busy bit, and bit S10 is represented as an integrity verify bit. The first data read command in this embodiment can read the bits S0 to S7 in the status data, and the second data read command in this embodiment can read the bits S8 to S15 in the status data. When receiving the first data read command, the control circuit 122 of the non-volatile memory 120 passes the status register 124 to transfer the status data (eg, bit S0 to bit S7) having the busy bit to Controller 110.
於步驟S340中，控制器110依據狀態資料中的忙碌位元來判斷非揮發性記憶體120是否完成上述的資料完整性診斷指令。本實施例中，若非揮發性記憶體120正在執行相關操作時，忙碌位元將以邏輯”1”呈現；非揮發性記憶體120並未執行相關操作時，忙碌位元將以邏輯”0”呈現。當控制器110判斷忙碌位元為邏輯”1”時，表示非揮發性記憶體120並未完成資料完整性診斷指令，因此便回到步驟S320以及S330以繼續獲得非揮發性記憶體120的狀態資料，以持續地判斷非揮發性記憶體120的狀態是否仍然忙碌。當控制器110判斷忙碌位元為邏輯”0”時，表示非揮發性記憶體120已完成資料完整性診斷指令。因此，從步驟S340進入步驟S350，控制器110對非揮發性記憶體120發送第二資料讀取指令。非揮發性記憶體120的控制電路122在接收到第二資料讀取指令時，便從狀態暫存器124將具備完整性驗證位元的狀態資料（如，位元S8至位元S15）傳遞給控制器110。In step S340, the controller 110 determines whether the non-volatile memory 120 completes the above data integrity diagnosis instruction according to the busy bit in the status data. In this embodiment, if the non-volatile memory 120 is performing related operations, the busy bit will be presented with a logic "1"; when the non-volatile memory 120 does not perform the related operation, the busy bit will be logic "0". Presented. When the controller 110 determines that the busy bit is logic "1", it indicates that the non-volatile memory 120 has not completed the data integrity diagnosis instruction, and therefore returns to steps S320 and S330 to continue obtaining the state of the non-volatile memory 120. Data to continuously determine whether the state of the non-volatile memory 120 is still busy. When the controller 110 determines that the busy bit is logic "0", it indicates that the non-volatile memory 120 has completed the data integrity diagnostic instruction. Therefore, the process proceeds from step S340 to step S350, and the controller 110 transmits a second material reading instruction to the non-volatile memory 120. The control circuit 122 of the non-volatile memory 120 transmits the status data (eg, bit S8 to bit S15) having the integrity verification bit from the status register 124 upon receiving the second data read command. To the controller 110.
於步驟S360中，控制器110便依據狀態資料中的完整性驗證位元來判斷非揮發性記憶體120中記憶體陣列的多個記憶胞是否通過記憶體的資料完整性檢驗。本實施例中，當完整性驗證位元為邏輯”1”時，表示非揮發性記憶體120中的每個記憶胞的完整性皆沒有缺陷，從而使非揮發性記憶體120通過記憶體的資料完整性驗證。另一方面，當完整性驗證位元為邏輯”0”時，表示非揮發性記憶體120中有部分的記憶胞的完整性有缺陷，從而使非揮發性記憶體120沒有通過記憶體的資料完整性驗證。於步驟S370中，控制器110便會依據資料完整性驗證的結果來進行相應操作。例如，當非揮發性記憶體120的完整性有缺陷時，控制器110可控制非揮發性記憶體120以使其自行將有所缺陷的部分記憶胞直接不使用，僅使用正常運作的記憶胞；或是，控制器110在得知非揮發性記憶體並未通過記憶體的資料完整性驗證後，可藉由警示設備來讓電子裝置100的使用人員/維護人員判定是否需要更換非揮發性記憶體120。In step S360, the controller 110 determines whether the plurality of memory cells of the memory array in the non-volatile memory 120 pass the data integrity check of the memory according to the integrity verification bit in the state data. In this embodiment, when the integrity verification bit is logic "1", it means that the integrity of each memory cell in the non-volatile memory 120 is not defective, so that the non-volatile memory 120 passes through the memory. Data integrity verification. On the other hand, when the integrity verification bit is logic "0", it indicates that the integrity of a part of the memory cells in the non-volatile memory 120 is defective, so that the non-volatile memory 120 does not pass through the memory. Integrity verification. In step S370, the controller 110 performs corresponding operations according to the result of the data integrity verification. For example, when the integrity of the non-volatile memory 120 is defective, the controller 110 can control the non-volatile memory 120 so that it can directly use the defective memory cells without using the normal operating memory cells. Or, after the controller 110 knows that the non-volatile memory has not passed the data integrity verification of the memory, the user/maintenance person of the electronic device 100 can determine whether the non-volatile replacement needs to be replaced by the warning device. Memory 120.
圖4是依照本發明實施例的記憶體完整性的檢驗方法的流程圖。請同時參照圖1及圖4，於步驟S410中，非揮發性記憶體120中的控制電路122在接收到資料完整性診斷指令之後，便從非揮發性記憶體120的起始位址來啟動自動讀取功能，以獲得至少一待檢驗記憶胞的閥值電壓。本實施例圖4中的資料完整性診斷可針對記憶體陣列128中的每個記憶胞依序作為『待檢驗記憶胞』。於步驟S415中，控制電路122將狀態暫存器124中的忙碌位元設定為邏輯”1”，以讓控制器110知悉資料完整性的診斷正在執行。4 is a flow chart of a method of verifying memory integrity in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 4 simultaneously, in step S410, the control circuit 122 in the non-volatile memory 120 starts from the start address of the non-volatile memory 120 after receiving the data integrity diagnosis command. The automatic reading function is to obtain at least one threshold voltage of the memory cell to be tested. The data integrity diagnosis in FIG. 4 of the present embodiment can be sequentially referred to as "memory cell to be tested" for each memory cell in the memory array 128. In step S415, the control circuit 122 sets the busy bit in the status register 124 to a logic "1" to let the controller 110 know that the diagnosis of data integrity is being performed.
於步驟S420中，控制電路122從記憶體陣列128中讀取待檢測記憶胞的閥值電壓，利用讀取電壓（如圖2所示的電壓Vread）與待檢測記憶胞的閥值電壓進行比對（亦即，控制電路122利用讀取電壓對待檢測記憶胞進行正常讀取）來判斷待檢驗記憶胞所屬的資料值。所述資料值例如為邏輯”0”或是邏輯”1”。在步驟S420中的控制電路122還可依據硬體設計而栓鎖（latch）此資料值。讀取電壓Vread可由電壓產生器126所產生。於步驟S430中，控制電路122依據待檢測記憶胞的資料值來設定預設電壓。若待檢測記憶胞的資料值為邏輯”0”，則將預設電壓設定為圖2中的電壓DM1；若待檢測記憶胞的資料值為邏輯”1”，則將預設電壓設定為圖2中的電壓DM2。In step S420, the control circuit 122 reads the threshold voltage of the memory cell to be detected from the memory array 128, and compares the threshold voltage (such as the voltage Vread shown in FIG. 2) with the threshold voltage of the memory cell to be detected. The data value to which the memory cell to be tested belongs is determined (that is, the control circuit 122 performs normal reading of the memory cell to be detected by using the read voltage). The data value is, for example, a logical "0" or a logical "1". The control circuit 122 in step S420 can also latch this data value in accordance with the hardware design. The read voltage Vread can be generated by the voltage generator 126. In step S430, the control circuit 122 sets the preset voltage according to the data value of the memory cell to be detected. If the data value of the memory cell to be detected is logic "0", the preset voltage is set to the voltage DM1 in FIG. 2; if the data value of the memory cell to be detected is logic "1", the preset voltage is set as a map. The voltage in 2 is DM2.
於步驟S440中，控制電路122將步驟S430所設定的預設電壓與所述至少一待檢測記憶胞的閥值電壓進行比對（亦即，控制電路122利用所設定的預設電壓對待檢測記憶胞進行偏移讀取）而獲得待檢驗記憶胞的偏移資料值。具體而言，若設定的預設電壓為DM1，當待檢測記憶胞的閥值電壓大於預設電壓DM1時，可認為其偏移資料值為邏輯”0”；當待檢測記憶胞的閥值電壓小於預設電壓DM1時，可認為其偏移資料值為邏輯”1”。另一方面，若設定的預設電壓為DM2，當待檢測記憶胞的閥值電壓小於預設電壓DM2時，可認為其偏移資料值為邏輯”1”；當待檢測記憶胞的閥值電壓大於預設電壓DM2時，可認為其偏移資料值為邏輯”0”。In step S440, the control circuit 122 compares the preset voltage set in step S430 with the threshold voltage of the at least one memory cell to be detected (that is, the control circuit 122 uses the preset voltage to be set to detect the memory. The cell performs an offset reading to obtain an offset data value of the memory cell to be tested. Specifically, if the preset voltage is set to DM1, when the threshold voltage of the memory cell to be detected is greater than the preset voltage DM1, the offset data value may be regarded as logic “0”; when the threshold of the memory cell to be detected is detected When the voltage is less than the preset voltage DM1, the offset data value is considered to be logic "1". On the other hand, if the preset voltage is set to DM2, when the threshold voltage of the memory cell to be detected is less than the preset voltage DM2, the offset data value can be considered as logic "1"; when the threshold of the memory cell to be detected is detected When the voltage is greater than the preset voltage DM2, the offset data value can be considered as logic "0".
於步驟S450中，控制電路122判斷待檢驗記憶胞所屬的資料值以及步驟S440中的偏移資料值是否相同。當待檢驗記憶胞所屬的資料值以及偏移資料值相同時，表示待檢驗記憶胞的閥值電壓同時大於圖2中的失效電壓Ve1以及預設電壓DM1以位於區域A1中，或是待檢驗記憶胞的閥值電壓同時小於圖2中的失效電壓Ve2以及失效電壓DM2以位於區域A2中。也就是說，此待檢驗記憶胞正常運作，且待檢驗記憶胞的閥值電壓沒有位於圖2的資料完整性區間DII1或DII2中。因此，從步驟S450進入步驟S460，控制電路122判斷是否已對於位於記憶體陣列128中的所有記憶胞完成資料完整性檢驗。若沒有讓位於記憶體陣列128中的所有記憶胞皆完成資料完整性檢驗的話，則從步驟S460進入步驟S470，控制電路122調整非揮發性記憶體120的位址（例如，將位址加1），並回到步驟S420以重複進行步驟S420至步驟S460。若已讓位於記憶體陣列128中的所有記憶胞完成資料完整性檢驗的話，則從步驟S460進入步驟S480，控制電路122設定忙碌位元為邏輯”0”以表示非揮發性記憶體120並未忙碌，並設定資料完整性位元為邏輯”1”。邏輯”1”的資料完整性位元用以表示非揮發性記憶體120完成資料完整性檢驗且並無發現記憶胞具備資料完整性的缺陷。In step S450, the control circuit 122 determines whether the data value to which the memory cell to be tested belongs and whether the offset data value in step S440 is the same. When the data value and the offset data value of the memory cell to be tested are the same, it indicates that the threshold voltage of the memory cell to be tested is greater than the failing voltage Ve1 and the preset voltage DM1 in FIG. 2 to be located in the area A1, or to be tested. The threshold voltage of the memory cell is simultaneously smaller than the fail voltage Ve2 and the fail voltage DM2 in FIG. 2 to be located in the area A2. That is to say, the memory cell to be tested operates normally, and the threshold voltage of the memory cell to be tested is not located in the data integrity interval DII1 or DII2 of FIG. Therefore, from step S450 to step S460, the control circuit 122 determines whether the data integrity check has been completed for all of the memory cells located in the memory array 128. If all the memory cells in the memory array 128 are not subjected to the data integrity check, then the process proceeds from step S460 to step S470, and the control circuit 122 adjusts the address of the non-volatile memory 120 (for example, adding the address). 1), and returns to step S420 to repeat steps S420 to S460. If all the memory cells in the memory array 128 have been subjected to the data integrity check, then the process proceeds from step S460 to step S480, and the control circuit 122 sets the busy bit to logic "0" to indicate the non-volatile memory 120. Not busy, and set the data integrity bit to logic "1". The data integrity bit of logic "1" is used to indicate that the non-volatile memory 120 has completed the data integrity check and has not found that the memory cell has the defect of data integrity.
假設待檢驗記憶胞所屬的資料值為邏輯”0”時，若控制電路122判斷待檢驗記憶胞所屬的資料值（邏輯”0”）以及偏移資料值（邏輯”1”）不同的話，表示待檢驗記憶胞的閥值電壓大於圖2中的失效電壓Ve1但並未大於預設電壓DM1，使得待檢驗記憶胞的閥值電壓位於資料完整性區間DII1中。另一方面，假設待檢驗記憶胞所屬的資料值為邏輯”1”時，若控制電路122判斷待檢驗記憶胞所屬的資料值（邏輯”1”）以及偏移資料值（邏輯”0”）不同的話，表示待檢驗記憶胞的閥值電壓小於圖2中的失效電壓Ve2但並未小於預設電壓DM2，使得待檢驗記憶胞的閥值電壓位於資料完整性區間DII2中。如此一來，非揮發性記憶體120的資料完整性便有所缺陷，因此便從步驟S450進入步驟S490，控制電路122設定忙碌位元為邏輯”0”以表示非揮發性記憶體120並未忙碌，並設定資料完整性位元為邏輯”0”。邏輯”0”的資料完整性位元用以表示非揮發性記憶體120完成資料完整性檢驗且有發現部分的記憶胞具備資料完整性的缺陷。Assuming that the data value to be inspected by the memory cell is logic "0", if the control circuit 122 determines that the data value (logical "0") and the offset data value (logical "1") to which the memory cell to be tested belongs is different, The threshold voltage of the memory cell to be tested is greater than the fail voltage Ve1 in FIG. 2 but not greater than the preset voltage DM1, so that the threshold voltage of the memory cell to be tested is located in the data integrity interval DII1. On the other hand, if the data value to which the memory cell to be tested belongs is logical "1", if the control circuit 122 determines the data value (logical "1") and the offset data value (logical "0") to which the memory cell to be tested belongs. Differently, it indicates that the threshold voltage of the memory cell to be tested is smaller than the failure voltage Ve2 in FIG. 2 but not less than the preset voltage DM2, so that the threshold voltage of the memory cell to be tested is located in the data integrity interval DII2. As a result, the data integrity of the non-volatile memory 120 is defective. Therefore, the process proceeds from step S450 to step S490, and the control circuit 122 sets the busy bit to logic "0" to indicate that the non-volatile memory 120 is not Busy, and set the data integrity bit to logic "0". The data integrity bit of logic "0" is used to indicate that the non-volatile memory 120 has completed the data integrity check and that the memory cell of the found portion has the defect of data integrity.
圖4所示的流程圖是以單個待檢驗記憶胞（亦即，1個bit）為單位來進行步驟S420至步驟S460的資料完整性檢驗，應用本實施例者亦可以8個待檢驗記憶胞（亦即，1個byte）為單位來同時進行步驟S420至步驟S460的資料完整性檢驗，只要此8個待檢驗記憶胞皆為相同的資料值（邏輯”0”或邏輯”1”）即可實現。於部分實施例中，記憶體陣列終能被區分為多個區塊，應用本實施例者亦可以將整個區塊中的待檢驗記憶胞作為單位來同時進行步驟S420至步驟S460的資料完整性檢驗，只要此區塊中的待檢驗記憶胞的資料值皆為相同便可實現。The flowchart shown in FIG. 4 performs the data integrity check of steps S420 to S460 in units of a single memory cell to be tested (that is, 1 bit), and the memory cells to be tested can also be used in the embodiment. (that is, 1 byte) is a unit to perform the data integrity check of step S420 to step S460 at the same time, as long as the eight memory cells to be tested are all the same data value (logic "0" or logic "1") Can achieve. In some embodiments, the memory array can be divided into a plurality of blocks. The embodiment of the present embodiment can also perform the data integrity of steps S420 to S460 by using the memory cells to be tested in the entire block as a unit. The test can be realized as long as the data values of the memory cells to be tested in this block are the same.
圖5是依照本發明實施例的非揮發性記憶體120中的部分電路（包含電壓產生器128）的電路圖。本實施例透過圖5來說明如何設定/調整與記憶胞的閥值電壓相比較的參考電壓（如，圖2中的讀取電壓Vread、邏輯”0”對應的預設電壓DM1、以及邏輯”1”對應的預設電壓DM2）。應用本實施例者亦可透過其他電路來實現上述參考電壓的切換。圖5的電路中包括差動電壓感應器600。差動電壓感應器600主要包括參考電流源610、記憶胞電流源620、N型電晶體NM1及NM2、反相器INV1及INV2、P型電晶體PL0、差動放大器630以及電壓產生器640。電壓產生器640由多個P型電晶體PL1~PL3以及多個開關SW1~SW3構成。參考電流源610產生固定的參考電流。記憶胞電流源620耦接待檢測記憶胞以獲得待檢測記憶胞當中的閥值電壓。差動放大器630的非反相輸入端接收與待檢測記憶胞中的閥值電壓相關的偵測電壓Vsense。差動放大器630的反相輸入端則接參考電壓Vref。P型電晶體PL0的控制端接地（如，接收接地電壓Vss）。電壓產生器640可用以產生讀取電壓Vread以及與資料值（如，邏輯”0”以及邏輯”1”）對應的預設電壓DM1/DM2。FIG. 5 is a circuit diagram of a portion of circuitry (including voltage generator 128) in non-volatile memory 120 in accordance with an embodiment of the present invention. In this embodiment, how to set/adjust the reference voltage compared with the threshold voltage of the memory cell (for example, the read voltage Vread in FIG. 2, the preset voltage DM1 corresponding to the logic “0”, and the logic” is illustrated by FIG. 5 . 1" corresponds to the preset voltage DM2). The above reference voltage can also be switched by other circuits by applying the embodiment. The differential voltage inductor 600 is included in the circuit of FIG. The differential voltage sensor 600 mainly includes a reference current source 610, a memory cell current source 620, N-type transistors NM1 and NM2, inverters INV1 and INV2, a P-type transistor PL0, a differential amplifier 630, and a voltage generator 640. The voltage generator 640 is composed of a plurality of P-type transistors PL1 to PL3 and a plurality of switches SW1 to SW3. The reference current source 610 produces a fixed reference current. The memory cell current source 620 is coupled to receive the detection memory cell to obtain a threshold voltage among the memory cells to be detected. The non-inverting input of the differential amplifier 630 receives the detected voltage Vsense associated with the threshold voltage in the memory cell to be detected. The inverting input of the differential amplifier 630 is connected to the reference voltage Vref. The control terminal of the P-type transistor PL0 is grounded (eg, receives the ground voltage Vss). The voltage generator 640 can be used to generate the read voltage Vread and the preset voltages DM1/DM2 corresponding to the data values (eg, logic "0" and logic "1").
在本實施例中，當想要讓參考電壓Vref成為上述實施例圖2中的讀取電壓Vread時，可控制開關SW1與SW2讓P型電晶體PL1與PL2的控制端接地，且控制開關SW3讓P型電晶體PL3的控制端接收電源電壓Vdd，以使P型電晶體PL0與電壓產生器640之間的感測比率調整為2:1。如此一來，便可讓參考電壓Vref等於讀取電壓Vread，以對待檢驗記憶胞的閥值電壓進行正常讀取從而判斷其所屬的資料值。In the present embodiment, when the reference voltage Vref is to be the read voltage Vread in FIG. 2 of the above embodiment, the switches SW1 and SW2 can be controlled to ground the control terminals of the P-type transistors PL1 and PL2, and the switch SW3 is controlled. The control terminal of the P-type transistor PL3 is caused to receive the power supply voltage Vdd so that the sensing ratio between the P-type transistor PL0 and the voltage generator 640 is adjusted to 2:1. In this way, the reference voltage Vref is equal to the read voltage Vread, and the threshold voltage of the memory cell to be tested is normally read to determine the data value to which it belongs.
當待檢驗記憶胞所屬的資料值為邏輯”0”時，電路600便需要將參考電壓Vref設定為圖2的預設電壓DM1。本實施例可控制開關SW1~SW3讓P型電晶體PL1~PL3的控制端皆為接地，以使P型電晶體PL0與電壓產生器640之間的感測比率降至3:1。如此一來，便可讓參考電壓Vref等於預設電壓DM1，以對待檢驗記憶胞的閥值電壓進行邏輯”0”的偏移讀取從而判斷其所屬的的偏移資料值。當待檢驗記憶胞所屬的資料值為邏輯”1”時，電路600便需要將參考電壓Vref設定為圖2的預設電壓DM2。本實施例可控制開關SW1讓P型電晶體PL1的控制端為接地，控制開關SW2~SW3讓P型電晶體PL2~PL3的控制端接收電源電壓Vdd，以使P型電晶體PL0與電壓產生器640之間的感測比率調整為1:1。如此一來，便可讓參考電壓Vref等於預設電壓DM1，以對待檢驗記憶胞的閥值電壓進行邏輯”1”的偏移讀取從而判斷其所屬的的偏移資料值。When the data value to be verified by the memory cell belongs to logic "0", the circuit 600 needs to set the reference voltage Vref to the preset voltage DM1 of FIG. In this embodiment, the switches SW1 to SW3 can be controlled so that the control terminals of the P-type transistors PL1 to PL3 are both grounded, so that the sensing ratio between the P-type transistor PL0 and the voltage generator 640 is reduced to 3:1. In this way, the reference voltage Vref can be made equal to the preset voltage DM1, and the threshold value of the threshold voltage of the memory cell to be tested is logically “0” read to determine the offset data value to which it belongs. When the data value to be verified by the memory cell belongs to logic "1", the circuit 600 needs to set the reference voltage Vref to the preset voltage DM2 of FIG. In this embodiment, the switch SW1 can be controlled to ground the control terminal of the P-type transistor PL1, and the control switches SW2 to SW3 allow the control terminals of the P-type transistors PL2 to PL3 to receive the power supply voltage Vdd, so that the P-type transistor PL0 and the voltage are generated. The sensing ratio between the 640 is adjusted to 1:1. In this way, the reference voltage Vref is equal to the preset voltage DM1, and the threshold value of the threshold voltage of the memory cell to be tested is read by a logic "1" to determine the offset data value to which it belongs.
綜上所述，本發明實施例所述之記憶體完整性的檢驗方法、非揮發性記憶體以及使用此非揮發性記憶體的電子裝置可對非揮發性記憶體中的多個待檢測記憶胞的正常讀取所獲得的資料值與偏移讀取所獲得的偏移資料值進行比對，以實現記憶體的資料完整性檢驗，從而判斷此待檢測記憶胞是否完好或是已開始出現的劣化的傾向（亦即，記憶體完整性有缺陷）。換句話說，為避免非揮發性記憶體損壞，本發明實施例的非揮發性記憶體可先行對各個記憶胞進行自檢其記憶體完整性是否良好，從而讓電子裝置能夠提前知曉非揮發性記憶體是否有機率損毀，致使電子裝置的功能安全能夠符合國際標準規定。In summary, the method for verifying the integrity of the memory, the non-volatile memory, and the electronic device using the non-volatile memory according to the embodiments of the present invention can perform multiple memories to be detected in the non-volatile memory. The data value obtained by the normal reading of the cell is compared with the offset data value obtained by the offset reading to implement the data integrity check of the memory, thereby determining whether the memory cell to be detected is intact or has begun to appear. The tendency to deteriorate (ie, memory integrity is flawed). In other words, in order to avoid non-volatile memory damage, the non-volatile memory of the embodiment of the present invention can perform self-test on each memory cell to check whether the memory integrity is good, so that the electronic device can know the non-volatile in advance. Whether the memory is damaged or not, so that the functional safety of the electronic device can comply with international standards.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧電子裝置100‧‧‧Electronic devices
110‧‧‧控制器110‧‧‧ Controller
120‧‧‧非揮發性記憶體120‧‧‧Non-volatile memory
122‧‧‧控制電路122‧‧‧Control circuit
124‧‧‧狀態暫存器124‧‧‧Status register
126、640‧‧‧電壓產生器126, 640‧‧‧ voltage generator
128‧‧‧記憶體陣列128‧‧‧ memory array
600‧‧‧電路600‧‧‧ circuit
610‧‧‧參考電流源610‧‧‧Reference current source
620‧‧‧記憶胞電流源620‧‧‧Memory cell current source
630‧‧‧差動放大器630‧‧‧Differential Amplifier
A1、A2‧‧‧區域A1, A2‧‧‧ area
Vread‧‧‧讀取電壓Vread‧‧‧ reading voltage
DII1、DII2‧‧‧區間/資料完整性區間DII1, DII2‧‧‧Interval/data integrity interval
EM‧‧‧辨識區間EM‧‧‧ Identification interval
DM1、DM2‧‧‧電壓/預設電壓DM1, DM2‧‧‧ voltage / preset voltage
Ve1、Ve2‧‧‧電壓/失效電壓Ve1, Ve2‧‧‧ voltage/deactivation voltage
S310~S370、S410~S440、S410~S490‧‧‧步驟S310~S370, S410~S440, S410~S490‧‧‧ steps
NM1~NM2‧‧‧N型電晶體NM1~NM2‧‧‧N type transistor
INV1~INV2‧‧‧反相器INV1~INV2‧‧‧Inverter
PL0~PL3‧‧‧P型電晶體PL0~PL3‧‧‧P type transistor
SW1~SW3‧‧‧開關SW1~SW3‧‧‧ switch
Vsense‧‧‧偵測電壓Vsense‧‧‧Detection voltage
Vref‧‧‧參考電壓Vref‧‧‧reference voltage
Vss‧‧‧接地電壓Vss‧‧‧ Grounding voltage
Vdd‧‧‧電源電壓Vdd‧‧‧Power supply voltage
圖1是依照本發明實施例的一種電子裝置的功能方塊圖。 圖2是依照本發明實施例說明預設電壓、記憶胞的資料完整性區間、失效電壓、以及辨識區間的示意圖。 圖3是依照本發明實施例的控制器對非揮發性記憶體進行記憶體完整性的檢驗方法的流程圖。 圖4是依照本發明實施例的記憶體完整性的檢驗方法的詳細流程圖。 圖5是依照本發明實施例的非揮發性記憶體中的部分電路（包含電壓產生器）的電路圖。1 is a functional block diagram of an electronic device in accordance with an embodiment of the present invention. 2 is a schematic diagram illustrating a preset voltage, a data integrity interval of a memory cell, a fail voltage, and an identification interval, in accordance with an embodiment of the present invention. 3 is a flow chart of a method for verifying memory integrity of a non-volatile memory by a controller in accordance with an embodiment of the present invention. 4 is a detailed flow chart of a method of verifying memory integrity in accordance with an embodiment of the present invention. 5 is a circuit diagram of a portion of a circuit (including a voltage generator) in a non-volatile memory in accordance with an embodiment of the present invention.
Claims (10)
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Citations (6)
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| US20060155882A1 (en) * | 2003-06-05 | 2006-07-13 | Koninklijke Philips Electronics N.V. | Integrity control for data stored in a non-volatile memory |
| TW201001430A (en) * | 2008-06-03 | 2010-01-01 | Marvell World Trade Ltd | Statistical tracking for flash memory |
| TW201110128A (en) * | 2009-09-01 | 2011-03-16 | Elite Semiconductor Esmt | Method for conducting over-erase correction |
| US20110107161A1 (en) * | 2009-10-29 | 2011-05-05 | Freescale Semiconductor, Inc. | Threshold voltage techniques for detecting an imminent read failure in a memory array |
| US8179717B2 (en) * | 2009-09-29 | 2012-05-15 | Sandisk Technologies Inc. | Maintaining integrity of preloaded content in non-volatile memory during surface mounting |
| US9329921B2 (en) * | 2014-04-25 | 2016-05-03 | Freescale Semiconductor, Inc. | Imminent read failure detection using high/low read voltage levels |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060155882A1 (en) * | 2003-06-05 | 2006-07-13 | Koninklijke Philips Electronics N.V. | Integrity control for data stored in a non-volatile memory |
| TW201001430A (en) * | 2008-06-03 | 2010-01-01 | Marvell World Trade Ltd | Statistical tracking for flash memory |
| TW201110128A (en) * | 2009-09-01 | 2011-03-16 | Elite Semiconductor Esmt | Method for conducting over-erase correction |
| US8179717B2 (en) * | 2009-09-29 | 2012-05-15 | Sandisk Technologies Inc. | Maintaining integrity of preloaded content in non-volatile memory during surface mounting |
| US20110107161A1 (en) * | 2009-10-29 | 2011-05-05 | Freescale Semiconductor, Inc. | Threshold voltage techniques for detecting an imminent read failure in a memory array |
| US9329921B2 (en) * | 2014-04-25 | 2016-05-03 | Freescale Semiconductor, Inc. | Imminent read failure detection using high/low read voltage levels |
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