TWI649760B - Methods for accessing a storage unit of a flash memory and apparatuses using the same - Google Patents
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Abstract
本發明的實施例提出一種存取快閃記憶體中儲存單元的方法,由處理單元執行,包含下列步驟。透過處理單元存取介面接收到由電子裝置發出的讀取命令及讀取位址後,判斷關聯於讀取位址的值是否尚未穩定地儲存於儲存單元中。若是,指示記憶體存取控制器從動態隨機存取記憶體讀取請求的值,並且透過處理單元存取介面回覆給電子裝置。 Embodiments of the present invention provide a method of accessing a storage unit in a flash memory, executed by a processing unit, including the following steps. After receiving the read command and the read address sent by the electronic device through the processing unit access interface, it is determined whether the value associated with the read address has not been stably stored in the storage unit. If so, the memory access controller is instructed to read the requested value from the DRAM and reply to the electronic device through the processing unit access interface.
Description
本發明關連於一種快閃記憶體裝置,特別是一種存取快閃記憶體中儲存單元的方法以及使用該方法的裝置。 The present invention relates to a flash memory device, and more particularly to a method of accessing a memory unit in a flash memory and a device using the same.
快閃記憶體(flash memory)中的記憶單元(memory cells)可能於多次的存取後失效。此外,亦可能於生產過程中,會因為粉塵或是光罩問題,使得儲存單元中的一整列(column)的資料都無法正確存取。因此,本發明提出一種存取快閃記憶單元的方法以及使用該方法的裝置,用以保護快閃記憶體中儲存的資料。 Memory cells in flash memory may fail after multiple accesses. In addition, it is also possible that in the production process, a whole column of data in the storage unit cannot be correctly accessed due to dust or mask problems. Accordingly, the present invention is directed to a method of accessing a flash memory unit and apparatus for using the same to protect data stored in a flash memory.
本發明的實施例提出一種存取快閃記憶體中儲存單元的方法,由處理單元執行,包含下列步驟。透過處理單元存取介面接收到由電子裝置發出的讀取命令及讀取位址後,判斷關聯於讀取位址的值是否尚未穩定地儲存於儲存單元中。若是,指示記憶體存取控制器從態隨機存取記憶體讀取請求的值,並且透過處理單元存取介面回覆給電子裝置。 Embodiments of the present invention provide a method of accessing a storage unit in a flash memory, executed by a processing unit, including the following steps. After receiving the read command and the read address sent by the electronic device through the processing unit access interface, it is determined whether the value associated with the read address has not been stably stored in the storage unit. If so, the memory access controller is instructed to read the requested value from the random access memory and reply to the electronic device through the processing unit access interface.
本發明的實施例提出一種存取快閃記憶體中之儲存單元的裝置,至少包含儲存單元存取介面、處理單元存取介 面以及處理單元。處理單元耦接於儲存單元存取介面及處理單元存取介面。處理單元透過處理單元存取介面接收到由電子裝置發出的讀取命令及讀取位址後,判斷關聯於讀取位址的值是否尚未穩定地儲存於儲存單元中;以及,若是,指示記憶體存取控制器從動態隨機存取記憶體讀取請求的值,並且透過處理單元存取介面回覆給電子裝置。 An embodiment of the present invention provides an apparatus for accessing a storage unit in a flash memory, including at least a storage unit access interface and a processing unit access medium. Surface and processing unit. The processing unit is coupled to the storage unit access interface and the processing unit access interface. After receiving the read command and the read address sent by the electronic device through the processing unit access interface, the processing unit determines whether the value associated with the read address has not been stably stored in the storage unit; and, if so, indicates the memory The body access controller reads the requested value from the dynamic random access memory and replies to the electronic device through the processing unit access interface.
10‧‧‧儲存單元 10‧‧‧ storage unit
110‧‧‧記憶體單元陣列 110‧‧‧Memory cell array
120‧‧‧行解碼單元 120‧‧‧ line decoding unit
130‧‧‧列編碼單元 130‧‧‧ column coding unit
140‧‧‧位址單元 140‧‧‧ address unit
150‧‧‧資料緩存器 150‧‧‧ data buffer
20‧‧‧快閃記憶體的系統架構 20‧‧‧System Architecture of Flash Memory
200‧‧‧控制器 200‧‧‧ controller
210‧‧‧控制單元 210‧‧‧Control unit
230‧‧‧儲存單元存取介面 230‧‧‧storage unit access interface
250‧‧‧處理單元存取介面 250‧‧‧Processing unit access interface
300‧‧‧快閃儲存裝置 300‧‧‧Flash storage device
10[0][0]~10[j][i]‧‧‧儲存單元 10[ 0 ][ 0 ]~10[ j ][ i ]‧‧‧ storage unit
310[0][0]~310[j][i]‧‧‧電子訊號 310[ 0 ][ 0 ]~310[ j ][ i ]‧‧‧Electronic signal
230[0]~230[j]‧‧‧儲存單元存取介面 230[ 0 ]~230[ j ]‧‧‧storage unit access interface
410[0][0][0]~410[j][i][k]‧‧‧區段資料 410[ 0 ][ 0 ][ 0 ]~410[ j ][ i ][ k ]‧‧‧ Section data
510‧‧‧訊息 510‧‧‧Information
530‧‧‧水平錯誤修正碼 530‧‧‧ horizontal error correction code
510[0][0][0]~510[j][i][0]‧‧‧訊息 510[ 0 ][ 0 ][ 0 ]~510[ j ][ i ][ 0 ]‧‧‧Message
530[0][0][0]~530[j][i][0]‧‧‧水平錯誤修正碼 530[ 0 ][ 0 ][ 0 ]~530[ j ][ i ][ 0 ]‧‧‧Horizontal Error Correction Code
610‧‧‧處理單元 610‧‧‧Processing unit
620‧‧‧動態隨機存取記憶體 620‧‧‧ Dynamic Random Access Memory
621、623‧‧‧直接記憶體存取控制器 621, 623‧‧‧ Direct Memory Access Controller
630‧‧‧磁碟陣列編碼單元 630‧‧‧Disk array coding unit
640‧‧‧多工器 640‧‧‧Multiplexer
650‧‧‧緩存器 650‧‧‧ Cache
660‧‧‧仲裁單元 660‧‧‧ Arbitration Unit
S711~S751‧‧‧方法步驟 S711~S751‧‧‧ method steps
S811~S831‧‧‧方法步驟 S811~S831‧‧‧ method steps
910‧‧‧處理單元 910‧‧‧Processing unit
930‧‧‧磁碟陣列解碼單元 930‧‧‧Disk array decoding unit
950‧‧‧緩存器 950‧‧‧ Cache
960‧‧‧區段解碼單元 960‧‧‧section decoding unit
S1010~S1070‧‧‧方法步驟 S1010~S1070‧‧‧ method steps
S1110~S1170‧‧‧方法步驟 S1110~S1170‧‧‧ method steps
1210‧‧‧處理單元 1210‧‧‧Processing unit
1220、1230‧‧‧直接記憶體存取控制器 1220, 1230‧‧‧ Direct Memory Access Controller
1240‧‧‧動態隨機存取記憶體 1240‧‧‧ Dynamic Random Access Memory
1250‧‧‧緩存器 1250‧‧‧ Cache
1300‧‧‧三層式單元區塊 1300‧‧‧Three-tier unit block
PG0~PG191‧‧‧頁面 PG0~PG191‧‧‧ page
WL0~WL63‧‧‧字元線 WL0~WL63‧‧‧ character line
S1410~S1470‧‧‧方法步驟 S1410~S1470‧‧‧ method steps
S1510~S1550‧‧‧方法步驟 S1510~S1550‧‧‧ method steps
LSB‧‧‧最低位元 LSB‧‧‧ Lowest Bit
CSB‧‧‧中間位元 CSB‧‧‧Intermediate bit
MSB‧‧‧最高位元 MSB‧‧‧ highest bit
10[0][0]~10[3][3]‧‧‧儲存單元 10[ 0 ][ 0 ]~10[ 3 ][ 3 ]‧‧‧ Storage unit
CH0~CH3‧‧‧通道 CH0~CH3‧‧‧ channel
CE0~CE3‧‧‧連接至特定通道的儲存單元 CE0~CE3‧‧‧ connected to a specific channel storage unit
S2011~S2087‧‧‧方法步驟 S2011~S2087‧‧‧ method steps
2100‧‧‧字元線寫入順序查找表 2100‧‧‧ character line write order lookup table
第1圖係依據本發明實施例之快閃記憶體中的儲存單元示意圖。 1 is a schematic diagram of a storage unit in a flash memory according to an embodiment of the present invention.
第2圖係依據本發明實施例之快閃記憶體的系統架構示意圖。 2 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.
第3圖係依據本發明實施例之快閃記憶體的存取介面示意圖。 Figure 3 is a schematic diagram of an access interface of a flash memory in accordance with an embodiment of the present invention.
第4圖係依據本發明實施例的邏輯資料儲存示意圖。 Figure 4 is a schematic diagram of logical data storage in accordance with an embodiment of the present invention.
第5A圖係依據本發明實施例應用於每一區段的資料儲存示意圖。 Figure 5A is a schematic diagram of data storage applied to each segment in accordance with an embodiment of the present invention.
第5B圖係依據本發明實施例的二維錯誤修正碼示意圖。 Figure 5B is a schematic diagram of a two-dimensional error correction code in accordance with an embodiment of the present invention.
第6圖係依據本發明實施例之用以執行寫入作業的系統方塊圖。 Figure 6 is a block diagram of a system for performing a write job in accordance with an embodiment of the present invention.
第7A及7B圖係依據本發明實施例之執行於處理單元中之資料寫入方法流程圖。 7A and 7B are flowcharts of a method of writing data in a processing unit according to an embodiment of the present invention.
第8圖係依據本發明實施例之執行於儲存單元存取介面中之資料寫入方法流程圖。 Figure 8 is a flow chart of a method for writing data in a storage unit access interface in accordance with an embodiment of the present invention.
第9圖係依據本發明實施例之用以執行讀取作業的系統方塊圖。 Figure 9 is a block diagram of a system for performing a read job in accordance with an embodiment of the present invention.
第10圖係依據本發明實施例之執行於區段解碼單元中之資料讀取方法流程圖。 Figure 10 is a flow chart of a method of reading data in a segment decoding unit in accordance with an embodiment of the present invention.
第11圖係依據本發明實施例之執行於處理單元中之資料讀取方法流程圖。 Figure 11 is a flow chart of a method of reading data in a processing unit in accordance with an embodiment of the present invention.
第12圖係依據本發明實施例之用以執行寫入作業的系統方塊圖。 Figure 12 is a block diagram of a system for performing a write job in accordance with an embodiment of the present invention.
第13圖係依據本發明實施例之一個儲存單元中的三層式單元區塊的示意圖。 Figure 13 is a schematic illustration of a three-layer cell block in a storage unit in accordance with an embodiment of the present invention.
第14圖係依據本發明實施例之執行於處理單元中之寫入方法流程圖。 Figure 14 is a flow diagram of a method of writing performed in a processing unit in accordance with an embodiment of the present invention.
第15圖係依據本發明實施例之執行於處理單元中之寫入方法流程圖。 Figure 15 is a flow chart of a method of writing executed in a processing unit in accordance with an embodiment of the present invention.
第16A圖係依據本發明實施例之眾多單層式單元的臨界電壓分布示意圖。 Figure 16A is a schematic diagram showing the threshold voltage distribution of a plurality of single-layer cells in accordance with an embodiment of the present invention.
第16B圖係依據本發明實施例之眾多多層式單元的臨界電壓分布示意圖。 Figure 16B is a schematic diagram of the threshold voltage distribution of a plurality of multi-layer cells in accordance with an embodiment of the present invention.
第16C圖係依據本發明實施例之眾多三層式單元的臨界電壓分布示意圖。 Figure 16C is a schematic diagram showing the threshold voltage distribution of a plurality of three-layer cells in accordance with an embodiment of the present invention.
第17A至17C圖係顯示依據本發明實施例之經三次寫入操作後之一個字元線上的眾多三層式單元的臨界電壓分布示意圖。 17A to 17C are diagrams showing threshold voltage distributions of a plurality of three-layer cells on one word line after three write operations in accordance with an embodiment of the present invention.
第18A圖係依據本發明實施例之使用RS(48,45)垂直錯誤 修正碼之獨立磁碟冗餘陣列群組的資料擺放示意圖。 Figure 18A illustrates the use of RS (48, 45) vertical errors in accordance with an embodiment of the present invention. A schematic diagram of the data placement of the independent disk redundant array group of the correction code.
第18B圖係依據本發明實施例之使用RS(96,93)垂直錯誤修正碼之獨立磁碟冗餘陣列群組的資料擺放示意圖。 Figure 18B is a diagram showing the arrangement of data of a redundant array of independent disks using an RS (96, 93) vertical error correction code according to an embodiment of the present invention.
第19A至19B圖係依據本發明實施例之資料寫入時序圖。 19A to 19B are diagrams of data writing timings according to an embodiment of the present invention.
第20A至20D圖係依據本發明實施例之執行於處理單元中之寫入資料方法流程圖。 20A to 20D are flowcharts of a method of writing data executed in a processing unit according to an embodiment of the present invention.
第21圖係依據本發明實施例之字元線寫入順序示意圖。 Figure 21 is a diagram showing the sequence of writing of word lines in accordance with an embodiment of the present invention.
本發明實施例提出一種存取快閃記憶體中儲存單元的方法以及使用該方法的裝置,用以編碼即將儲存至儲存單元的資料,以及解碼從儲存單元中讀取的資料。第1圖係依據本發明實施例之快閃記憶體中的儲存單元示意圖。儲存單元10包含由MxN個記憶體單元(memory cells)組成的陣列(array)110,而每一個記憶體單元儲存至少一個位元(bit)的資訊。快閃記憶體可以是NOR型快閃記憶體(NOR flash memory)、NAND型快閃記憶體,或其他種類的快閃記憶體。為了正確存取資訊,行解碼單元120用以選擇記憶體單元陣列110中指定的行,而列編碼單元130用以選擇指定行中一定數量的位元組的資料作為輸出。位址單元140提供行資訊給行解碼器120,其中定義了選擇記憶體單元陣列110中的那些行。相似地,列解碼器130則根據位址單元140提供的列資訊,選擇記憶體單元陣列110的指定行中一定數量的列進行讀取或寫入操作。行可稱為為字元線(wordline),列可稱為位元線(bitline)。資料緩存器(data buffer)150可處存從記憶體單元陣列110讀取 出的資料,或欲寫入記憶體單元陣列110中的資料。記憶體單元可為單層式單元(single-level cells,SLCs)、多層式單元(multi-level cells,MLCs)或三層式單元(triple-level cells,TLCs)。 Embodiments of the present invention provide a method for accessing a storage unit in a flash memory and a device using the same for encoding data to be stored to a storage unit and decoding data read from the storage unit. 1 is a schematic diagram of a storage unit in a flash memory according to an embodiment of the present invention. The storage unit 10 includes an array 110 composed of MxN memory cells, and each memory unit stores information of at least one bit. The flash memory can be a NOR flash memory, a NAND flash memory, or other types of flash memory. In order to correctly access the information, the row decoding unit 120 is configured to select a row specified in the memory cell array 110, and the column encoding unit 130 is configured to select a data of a certain number of bytes in the specified row as an output. Address unit 140 provides row information to row decoder 120 in which those rows in select memory cell array 110 are defined. Similarly, column decoder 130 selects a certain number of columns in a specified row of memory cell array 110 for read or write operations based on the column information provided by address unit 140. A row can be called a wordline, and a column can be called a bitline. The data buffer 150 can store data read from the memory cell array 110 or data to be written into the memory cell array 110. The memory unit can be single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs).
一個單層式單元中可表示兩個狀態,其中之一係為於浮閘(floating gate)中擁有零電荷(zero charge)以及抹除後尚未寫入的狀態(通常定義為”1”的狀態),而另一則為於浮閘中擁有一些數量的負電荷(negative charge)的狀態(通常定義為”0”的狀態)。擁有負電荷的閘會讓此單元中之電晶體的臨界電壓(threshold voltage)增加,亦即是當施加此電壓至電晶體的控制閘(control gate)時可造成電晶體導通。一種可行的讀取儲存位元方式為檢查此單元中的臨界電壓。如果此臨界電壓處於較高的狀態,則位元值為”0”。如果此臨界電壓處於較低的狀態,則位元值為”1”。第16A圖係依據本發明實施例之眾多單層式單元的臨界電壓分布示意圖。因為快閃記憶體中的記憶體單元間的特性及操作結果並不會完全一致(例如,因為雜質濃度的微小變異或矽結構上的缺陷),雖然使用相同的寫入作業至所有的記憶體單元,卻不能讓所有的記憶體單元擁有完全一致的臨界電壓。因此,臨界電壓的分布如第16A所示。狀態”1”的單層式單元通常擁有負臨界電壓,使得大部分的單元擁有接近於左峰的中心電壓,而少部分的單元則擁有較高或較低於左峰中心電壓的臨界電壓。相似地,狀態”0”的單層式單元通常擁有正臨界電壓,使得大部分的單元擁有接近於右峰的中心電壓,而少部分的單元擁有較高或較低於右峰中心電壓的臨界電 壓。 A single-level cell can represent two states, one of which is a state in which there is a zero charge in the floating gate and a state that has not been written after erasing (usually defined as "1"). And the other is a state in which there is some amount of negative charge in the floating gate (usually defined as a state of "0"). A gate with a negative charge causes the threshold voltage of the transistor in the cell to increase, that is, when the voltage is applied to the control gate of the transistor, the transistor can be turned on. One possible way to read the storage bit is to check the threshold voltage in this cell. If the threshold voltage is in a higher state, the bit value is "0". If the threshold voltage is in a lower state, the bit value is "1". Figure 16A is a schematic diagram showing the threshold voltage distribution of a plurality of single-layer cells in accordance with an embodiment of the present invention. Because the characteristics and operation results between the memory cells in the flash memory are not completely consistent (for example, due to small variations in impurity concentration or defects in the structure), although the same write operation is used to all the memories. Units, but not all memory cells have a completely consistent threshold voltage. Therefore, the distribution of the threshold voltage is as shown in Fig. 16A. A single-layer cell of state "1" typically has a negative threshold voltage such that most of the cells have a center voltage close to the left peak, while a small number of cells have a threshold voltage that is higher or lower than the center voltage of the left peak. Similarly, a single-level cell of state "0" typically has a positive threshold voltage such that most of the cells have a center voltage close to the right peak, while a small number of cells have a higher or lower critical value of the right peak center voltage. Electricity Pressure.
雖然多層式單元從字面上表示為擁有多於二個電壓位準的狀態,亦即是,每個單元可表示多於一個位元的資訊,但目前大多的多層式單元只表示二個位元的資訊,從而提供如下所示的範例。單一個多層式單元使用四個不同狀態中之一者來儲存二個位元的資訊,其中的一個位元稱為最低位元(Least Significant Bit,LSB),另一個位元則稱為最高位元(Most Significant Bit,MSB)。由於一個記憶體單元的狀態係使用臨界電壓來表示,多層式單元的臨界電壓會有四個不同的有效區間。第16B圖係依據本發明實施例之眾多多層式單元的臨界電壓分布示意圖。預期的分布擁有四個峰,每一者相應於一個狀態。相似地,單一個三層式單元使用八個不同狀態中之一者來儲存三個位元的資訊,其中的一個位元稱為最低位元,另一個位元稱為中間位元(Center Significant Bit,CSB),而最後一個位元稱為最高位元。三層式單元的臨界電壓會有八個不同的有效區間。第16C圖係依據本發明實施例之眾多三層式單元的臨界電壓分布示意圖。預期的分布擁有八個峰,每一者相應於一個狀態。需注意的是,本發明也可應用在每個記憶體單元支援超過三個位元的快閃記憶體裝置中。 Although a multi-level cell is literally represented as having more than two voltage levels, that is, each cell can represent more than one bit of information, but currently most multi-level cells represent only two bits. Information to provide examples as shown below. A single multi-level cell uses one of four different states to store information for two bits, one of which is called the Least Significant Bit (LSB) and the other is called the highest bit. Most Significant Bit (MSB). Since the state of a memory cell is represented by a threshold voltage, the threshold voltage of the multi-layer cell has four different effective intervals. Figure 16B is a schematic diagram of the threshold voltage distribution of a plurality of multi-layer cells in accordance with an embodiment of the present invention. The expected distribution has four peaks, each corresponding to a state. Similarly, a single three-tier cell uses one of eight different states to store three bits of information, one of which is called the lowest bit and the other is called the middle bit (Center Significant) Bit, CSB), and the last bit is called the highest bit. The threshold voltage of a three-layer unit has eight different effective intervals. Figure 16C is a schematic diagram showing the threshold voltage distribution of a plurality of three-layer cells in accordance with an embodiment of the present invention. The expected distribution has eight peaks, each corresponding to a state. It should be noted that the present invention is also applicable to a flash memory device in which each memory unit supports more than three bits.
第2圖係依據本發明實施例之快閃記憶體的系統架構示意圖。快閃記憶體的系統架構20中包含控制器200,用以寫入資料到儲存單元10中的指定位址,以及從儲存單元10中的指定位址讀取資料。詳細來說,控制單元210透過儲存單元存取介面230寫入資料到儲存單元10中的指定位址,以及從儲 存單元10中的指定位址讀取資料。系統架構20使用數個電子訊號來協調控制器200與儲存單元10間的資料與命令傳遞,包含資料線(data line)、時脈訊號(clock signal)與控制訊號(control signal)。資料線可用以傳遞命令、位址、讀出及寫入的資料;控制訊號線可用以傳遞晶片致能(chip enable,CE)、位址提取致能(address latch enable,ALE)、命令提取致能(command latch enable,CLE)、寫入致能(write enable,WE)等控制訊號。儲存單元存取介面230可採用雙倍資料率(double data rate,DDR)通訊協定與儲存單元10溝通,例如,開放NAND快閃(open NAND flash interface,ONFI)、雙倍資料率開關(DDR toggle)或其他介面。控制單元210另可使用處理單元存取介面250透過指定通訊協定與其他電子裝置進行溝通,例如,通用序列匯流排(universal serial bus,USB)、先進技術附著(advanced technology attachment,ATA)、序列先進技術附著(serial advanced technology attachment,SATA)、快速周邊元件互聯(peripheral component interconnect express,PCI-E)或其他介面。 2 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention. The system architecture 20 of the flash memory includes a controller 200 for writing data to a specified address in the storage unit 10 and reading data from a specified address in the storage unit 10. In detail, the control unit 210 writes data to the specified address in the storage unit 10 through the storage unit access interface 230, and from the storage. The specified address in the memory unit 10 reads the data. The system architecture 20 uses a plurality of electronic signals to coordinate data and command transfer between the controller 200 and the storage unit 10, including a data line, a clock signal, and a control signal. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transmit chip enable (CE), address latch enable (ALE), command extraction Control signals such as command latch enable (CLE) and write enable (WE). The storage unit access interface 230 can communicate with the storage unit 10 by using a double data rate (DDR) protocol, for example, an open NAND flash interface (ONFI) and a double data rate switch (DDR toggle). ) or other interface. The control unit 210 can also use the processing unit access interface 250 to communicate with other electronic devices through a specified communication protocol, for example, a universal serial bus (USB), an advanced technology attachment (ATA), and an advanced sequence. Serial advanced technology attachment (SATA), peripheral component interconnect express (PCI-E) or other interface.
一個快閃儲存裝置(flash storage)可包含多個儲存單元10,每一個儲存單元實施於一個晶粒(die)上,具有各自獨立的介面與儲存單元存取介面230溝通。於存取大量資料時,這些存取儲存單元的操作(例如,讀取或寫入操作)可以被管線化(pipelined),提升存取效率。第3圖係依據本發明實施例之快閃記憶體的存取介面示意圖。快閃儲存裝置300可包含j+1個通道(channel),每一個通道包含i+1個儲存單元。換句話說,i+1個儲存單元分享同一個通道。例如,當快閃儲存裝置300包含8 個通道(j=7)且每一個通道包含8個儲存單元(i=7)時,快閃儲存裝置300一共擁有64個儲存單元10[0..j][0..i]。快閃記憶體的控制單元可使用快閃儲存裝置300所提供的電子訊號310[0..j][0..i]中之一者,將資料儲存至指定的儲存單元,以及/或從指定的儲存單元讀取資料。每個儲存單元擁有獨立的晶片致能(CE)控制訊號。換句話說,當欲對指定儲存單元存取介面(又可稱為通道)所連接的指定儲存單元進行資料存取時,需要致能相應的晶片致能控制訊號。熟習此技藝人士可在快閃儲存裝置300中使用任意數目的通道,而每一通道可包含任意數目的儲存單元,本發明並不因此而受限。 A flash storage device can include a plurality of storage units 10, each of which is implemented on a die having separate interfaces to communicate with the storage unit access interface 230. When accessing a large amount of data, the operations of these access storage units (for example, read or write operations) can be pipelined to improve access efficiency. Figure 3 is a schematic diagram of an access interface of a flash memory in accordance with an embodiment of the present invention. The flash storage device 300 can include j + 1 channels, each channel containing i + 1 storage units. In other words, i + 1 storage units share the same channel. For example, when the flash storage device 300 includes 8 channels ( j = 7 ) and each channel contains 8 storage units ( i = 7 ), the flash storage device 300 has a total of 64 storage units 10 [ 0..j ][ 0..i ]. The flash memory control unit may use one of the electronic signals 310[ 0..j ][ 0..i ] provided by the flash memory device 300 to store the data to a designated storage unit, and/or from The specified storage unit reads the data. Each storage unit has a separate wafer enable (CE) control signal. In other words, when data access is to be performed on a designated storage unit to which a specified storage unit access interface (also referred to as a channel) is connected, the corresponding wafer enable control signal needs to be enabled. Those skilled in the art can use any number of channels in the flash storage device 300, and each channel can include any number of storage units, and the invention is not so limited.
為了確保儲存訊息(message)的正確性,可加上儲存二維的錯誤修正碼(two-dimensional error correction code,ECC)來保護。第4圖係依據本發明實施例的邏輯資料儲存示意圖。(j+1)x(i+1)個儲存單元中可包含用以儲存錯誤修正碼的l個(例如,l=1、2或3個)儲存單元,其中所儲存的碼又可稱為垂直錯誤修正碼(vertical ECC)。每一個垂直錯誤修正碼係根據其他(j+1)x(i+1)-l個儲存單元中相應位址的值產生。垂直錯誤修正碼可以是單同位元修正碼(single parity correction,SPC)、RS碼(Reed-Solomon code)或其他可提供修正錯誤功能的碼。例如,當i=7,j=7且l=1時,儲存單元10[7][7]可儲存SPC(64,63)的錯誤修正碼。當i=7,j=7且l=2時,儲存單元10[7][6]及10[7][7]可儲存RS(64,62)的錯誤修正碼。當i=7,j=7且l=3時,儲存單元10[7][5]、10[7][6]及10[7][7]可儲存RS(64,61)的錯誤修正碼。垂直錯誤修正碼用來提供儲存單元層次的保護,亦即是,當其 中的一個儲存單元失效時,使用垂直錯誤修正碼以及其他儲存單元中所儲存正確的值可回復儲存於失效的儲存單元中的所有的值。其他不儲存垂直錯誤修正碼的儲存單元中,除了儲存訊息外,更儲存水平錯誤修正碼(horizontal ECC)。每一個儲存單元中的每條字元線可儲存k+1(例如k=31)個區段(sector)的資料。以上所述的k+1個區段又可統稱為一個頁面(page)。例如,針對指定一條字元線,儲存單元10[0][0]可儲存區段410[0][0][0]至區段410[0][0][k]的資料,儲存單元10[0][i]可儲存區段410[0][i][0]至區段410[0][i][k]的資料,儲存單元10[j][i]可儲存區段410[j][i][0]至區段410[j][i][k]的資料。區段410[0][0][0]至區段410[0][0][k]、區段410[0][i][0]至區段410[0][i][k]或410[j][i][0]至區段410[j][i][k]又可稱為一個晶片致能區段(CE sector)。第5A圖係依據本發明實施例應用於每一區段的資料儲存示意圖。區段410[0..j][0..i][0..k]中之任一者可包含訊息510與水平錯誤修正碼530。訊息長度是固定的,例如1K位元組(bytes)。水平錯誤修正碼530係根據訊息510中的值產生。水平錯誤修正碼可以是單同位元修正碼、RS碼或其他可提供修正錯誤功能的碼。水平錯誤修正碼係提供區段層次的保護,亦即是,當訊息中有可容許數量個值發生錯誤時,使用水平錯誤修正碼以及同一區段中所儲存其他正確的訊息值可還原這些錯誤的值。第5B圖係依據本發明實施例的二維錯誤修正碼示意圖。其中,每一個區段中包含了訊息及水平錯誤修正碼,例如,區段410[0][0][0]中包含了訊息510[0][0][0]以及用來修正訊息中的錯誤的水平錯誤修正碼530[0][0][0]。假設 l=1,亦即是僅使用一個儲存單元來儲存垂直錯誤修正碼。區塊510[j][i][0]儲存用以修正訊息510[0][0][0]至訊息510[j-1][i][0]中之錯誤位元的垂直修正碼,而區塊530[j][i][0]儲存用以修正水平錯誤修正碼530[0][0][0]至水平錯誤修正碼530[j-1][i][0]中之錯誤位元的垂直錯誤修正碼。當一個區塊中的錯誤位元太多或者是儲存單元發生硬體錯誤而造成水平錯誤修正碼無法還原此區塊中的訊息時,則可使用垂直錯誤修正碼加上其他區塊中正確的訊息來嘗試還原此區塊中的訊息。以上所述區塊加上用來保護區塊中的值的垂直錯誤修正碼可稱為一個獨立磁碟冗餘陣列群組(Redundant Array of Independent Disk,RAID group)。 In order to ensure the correctness of the stored message, it can be protected by storing a two-dimensional error correction code (ECC). Figure 4 is a schematic diagram of logical data storage in accordance with an embodiment of the present invention. (J + 1) x (i + 1) th storage units may be included for storing the l-th error correction code (e.g., l = 1, 2, or 3) a storage unit, a code stored therein may be called Vertical error correction code (vertical ECC). Each vertical error correction code is generated based on the values of the corresponding addresses in the other ( j + 1) x (i + 1) - 1 storage units. The vertical error correction code may be a single parity correction (SPC), an RS code (Reed-Solomon code) or other code that provides a correction error function. For example, when i = 7 , j = 7 and l = 1 , the storage unit 10[ 7 ][ 7 ] can store the error correction code of the SPC (64, 63). When i = 7 , j = 7 and l = 2 , the memory cells 10[ 7 ][ 6 ] and 10[ 7 ][ 7 ] can store the error correction code of RS(64,62). When i = 7 , j = 7 and l = 3 , the memory cells 10[ 7 ][ 5 ], 10[ 7 ][ 6 ] and 10[ 7 ][ 7 ] can store the error correction of RS (64,61) code. The vertical error correction code is used to provide protection of the storage unit level, that is, when one of the storage units fails, the vertical error correction code and the correct value stored in other storage units can be restored and stored in the failed storage unit. All the values. In other storage units that do not store the vertical error correction code, in addition to storing the message, a horizontal error correction code (horizontal ECC) is stored. Each word line in each storage unit can store k + 1 (eg, k = 31 ) sectors of data. The k + 1 segments described above can be collectively referred to as a page. For example, for a specified word line, the storage unit 10[ 0 ][ 0 ] can store data of the section 410[ 0 ][ 0 ][ 0 ] to the section 410[ 0 ][ 0 ][ k ], the storage unit 10[ 0 ][ i ] can store data of section 410[ 0 ][ i ][ 0 ] to section 410[ 0 ][ i ][ k ], storage unit 10[ j ][ i ] can store section 410[ j ][ i ][ 0 ] to the data of the section 410[ j ][ i ][ k ]. Section 410[ 0 ][ 0 ][ 0 ] to section 410[ 0 ][ 0 ][ k ], section 410[ 0 ][ i ][ 0 ] to section 410[ 0 ][ i ][ k ] or 410[ j ][ i ][ 0 ] to the section 410[ j ][ i ][ k ] may also be referred to as a CE sector. Figure 5A is a schematic diagram of data storage applied to each segment in accordance with an embodiment of the present invention. Any of the segments 410[ 0..j ][ 0..i ][ 0..k ] may include the message 510 and the horizontal error correction code 530. The length of the message is fixed, such as 1K bytes. The horizontal error correction code 530 is generated based on the value in the message 510. The horizontal error correction code can be a single parity correction code, an RS code, or other code that provides a correction error function. The horizontal error correction code provides segment level protection, that is, when there are errors in the number of allowable values in the message, the horizontal error correction code and other correct message values stored in the same segment can be used to restore these errors. Value. Figure 5B is a schematic diagram of a two-dimensional error correction code in accordance with an embodiment of the present invention. Each segment contains a message and a horizontal error correction code. For example, the segment 410[ 0 ][ 0 ][ 0 ] contains the message 510[ 0 ][ 0 ][ 0 ] and is used to correct the message. The wrong level of error correction code 530[ 0 ][ 0 ][ 0 ]. Assuming l =1, that is, only one storage unit is used to store the vertical error correction code. Block 510[ j ][ i ][ 0 ] stores a vertical correction code for correcting the error bit in the message 510[ 0 ][ 0 ][ 0 ] to the message 510[ j-1 ][ i ][ 0 ] And block 530[ j ][ i ][ 0 ] is stored to correct the horizontal error correction code 530[ 0 ][ 0 ][ 0 ] to the horizontal error correction code 530[ j-1 ][ i ][ 0 ] The vertical error correction code of the error bit. When there are too many error bits in a block or a hardware error occurs in the storage unit and the horizontal error correction code cannot restore the message in this block, the vertical error correction code can be used plus the correct one in other blocks. Message to try to restore the message in this block. The above-mentioned block plus a vertical error correction code for protecting the value in the block may be referred to as a Redundant Array of Independent Disk (RAID group).
第6圖係依據本發明實施例之用以執行寫入作業的系統方塊圖。處理單元610可使用多種方式實施,例如以專用硬體電路或通用硬體(例如,單一處理器、具平行處理能力的多處理器、圖形處理器或其他具運算能力的處理器),並且在執行程式碼或軟體時,提供之後所描述的功能。從其他電子裝置所接收之欲寫入至指定儲存單元的訊息,會由處理單元存取介面250透過直接記憶體存取(DMA,Direct Memory Access)控制器623儲存至動態隨機存取記憶體620。儲存單元10[0][0]至10[j][i]中之任一者可包含多個單層式單元。多工器640可預設為耦接動態隨機存取記憶體620以及緩存器650。當處理單元610偵測到動態隨機存取記憶體(DRAM-Dynamic Random Access Memory)620已儲存一定長度的訊息時,例如,32K位元組,指示直接記憶體存取控制器621將動態隨機存取記憶體620 中儲存的訊息經由多工器640儲存至緩存器650,並同時儲存至磁碟陣列編碼單元630中的緩存器(未顯示)。磁碟陣列編碼單元630可使用習知的錯誤修正碼編碼方法依據目前的儲存結果以及新接收到的訊息來產生垂直錯誤修正碼,例如SPC(64,63)、RS(64,62)、RS(64,61)的錯誤修正碼。處理單元610可包含兩個計數器(counter),一為訊息計數器用以數算已經輸出的訊息次數,另一為錯誤修正碼計數器用以數算已經輸出的垂直錯誤修正碼次數。當處理單元610中的訊息計數器數算到已輸出的訊息次數到達一個閥值時,控制多工器640用以將磁碟陣列編碼單元630耦接上緩存器650,並且指示磁碟陣列編碼單元630將編碼完成的垂直錯誤修正碼以一或多個批次輸出至緩存器650。當處理單元610中的錯誤修正碼計數器數算到已輸出的次數到達一個閥值時,控制多工器640用以將動態隨機存取記憶體620耦接上緩存器650,用以繼續後續的訊息儲存作業。例如,當使用RS(64,61)的錯誤修正碼時,處理單元610會在訊息計數器數算已輸出訊息的次數達到61次時,控制多工器640用以將磁碟陣列編碼單元630耦接上緩存器650,並將訊息計數器重設為0;接著,處理單元610會在錯誤修正碼計數器數算已輸出錯誤修正碼的次數達到3次時,控制多工器640用以將動態隨機存取記憶體620耦接上緩存器650,並將錯誤修正碼計數器重設為0。於每次控制動態隨機存取記憶體620或磁碟陣列編碼單元630的資料輸出後,處理單元610控制仲裁單元660讀取緩存器650中的區段或垂直錯誤修正碼的值並透過適當的儲存單元存取介面(例如,儲存單元存取介面230[0]至230[j]中之一者) 寫入讀取的值至相應的儲存單元(例如,儲存單元10[0][0]至10[j][i]中之一者)。仲裁單元660可拉起(activate)適當的儲存單元存取介面中相應儲存單元的晶片致能訊號,並且透過儲存單元存取介面中的資料線將讀取的值及寫入位址傳給相應的儲存單元。每一個儲存單元存取介面(例如,儲存單元存取介面230[0]至230[j])另包含水平錯誤修正碼電路,用以分批次地讀取緩存器650中的資料(可能為訊息或垂直錯誤修正碼),並據以產生水平錯誤修正碼。詳細而言,當儲存單元存取介面每次從緩存器650讀取指定長度的訊息後,例如1K位元組,依據讀取的訊息510產生水平錯誤修正碼530。儲存單元存取介面接著將訊息510以及產生的水平錯誤修正碼530寫入至指定的儲存單元中的指定位址。 Figure 6 is a block diagram of a system for performing a write job in accordance with an embodiment of the present invention. Processing unit 610 can be implemented in a variety of manners, such as with dedicated hardware circuitry or general purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, graphics processors, or other computing capable processors), and When the code or software is executed, the functions described later are provided. The information to be written from the other electronic device to the specified storage unit is stored by the processing unit access interface 250 through the direct memory access (DMA) controller 623 to the dynamic random access memory 620. . Any of the storage units 10[ 0 ][ 0 ] to 10[ j ][ i ] may include a plurality of single layer units. The multiplexer 640 can be preset to be coupled to the dynamic random access memory 620 and the buffer 650. When the processing unit 610 detects that the DRAM-Dynamic Random Access Memory 620 has stored a certain length of information, for example, a 32K byte indicates that the direct memory access controller 621 will dynamically store the random random access memory. The message stored in the memory 620 is stored in the buffer 650 via the multiplexer 640 and simultaneously stored in a buffer (not shown) in the disk array encoding unit 630. The disk array encoding unit 630 can generate a vertical error correction code based on the current stored result and the newly received message using a conventional error correction code encoding method, such as SPC (64, 63), RS (64, 62), RS. (64,61) error correction code. The processing unit 610 can include two counters, one is a message counter for counting the number of times the message has been output, and the other is an error correction code counter for counting the number of vertical error correction codes that have been output. When the number of message counters in the processing unit 610 counts to the threshold value of the outputted message, the control multiplexer 640 is configured to couple the disk array encoding unit 630 to the buffer 650 and indicate the disk array encoding unit. 630 outputs the encoded vertical error correction code to the buffer 650 in one or more batches. When the number of error correction code counters in the processing unit 610 is counted to reach a threshold, the control multiplexer 640 is configured to couple the dynamic random access memory 620 to the buffer 650 for continuing subsequent steps. Message storage job. For example, when the error correction code of RS (64, 61) is used, the processing unit 610 controls the multiplexer 640 to couple the disk array coding unit 630 when the number of times the message counter has outputted the message reaches 61 times. The buffer 650 is connected, and the message counter is reset to 0. Then, the processing unit 610 controls the multiplexer 640 to dynamically randomize when the error correction code counter counts the number of times the error correction code has been outputted to 3 times. The access memory 620 is coupled to the buffer 650 and resets the error correction code counter to zero. After each time controlling the data output of the DRAM 620 or the disk array encoding unit 630, the processing unit 610 controls the arbitration unit 660 to read the value of the sector or vertical error correction code in the buffer 650 and pass the appropriate The storage unit access interface (eg, one of the storage unit access interfaces 230[ 0 ] to 230[ j ]) writes the read value to the corresponding storage unit (eg, storage unit 10[ 0 ][ 0 ] To one of 10[ j ][ i ]). The arbitration unit 660 can activate the chip enable signal of the corresponding storage unit in the appropriate storage unit access interface, and transmit the read value and the write address to the corresponding data line in the storage unit access interface. Storage unit. Each storage unit access interface (eg, storage unit access interfaces 230[ 0 ] to 230[ j ]) further includes a horizontal error correction code circuit for reading the data in the buffer 650 in batches (probably A message or a vertical error correction code) and a horizontal error correction code is generated accordingly. In detail, the horizontal error correction code 530 is generated according to the read message 510 after the storage unit access interface reads a message of a specified length from the buffer 650 each time, for example, a 1K byte. The storage unit access interface then writes the message 510 and the generated horizontal error correction code 530 to the designated address in the designated storage unit.
第7A及7B圖係依據本發明實施例之執行於處理單元中之資料寫入方法流程圖。於一個獨立磁碟冗餘陣列群組的寫入作業中,處理單元610首先將訊息計數器以及錯誤修正碼計數器設為0(步驟S711),以及控制多工器640以耦接動態隨機存取記憶體620至緩存器650(步驟S713)。接著,反覆執行一個包含步驟S721至S731的迴圈直到一個獨立磁碟冗餘陣列群組中的訊息都寫入到指定的儲存單元中,例如,儲存單元10[0][0]至10[j][i-l]。詳細而言,處理單元610於偵測到動態隨機存取記憶體620已儲存指定長度的新訊息後,例如,32K位元組(步驟S721),指示直接記憶體存取控制器621將動態隨機存取記憶體620中儲存的訊息經由多工器640儲存至緩存器650,並同時儲存至磁碟陣列編碼單元630中的緩存器(未顯示)(步驟 S723)。接著,處理單元610控制仲裁單元660讀取緩存器650中的值並透過適當的儲存單元存取介面(例如,儲存單元存取介面230[0]至230[j]中之一者)寫入讀取的值至相應的儲存單元(例如,儲存單元10[0][0]至10[j][i]中之一者)(步驟S725)。處理單元610將訊息計數器加一後(步驟S727),判斷訊息計數器的值是否超過閥值,例如,(j+1)x(i+1)-l-1(步驟S731)。若是,則繼續執行步驟S733至S751,用以寫入獨立磁碟冗餘陣列群組中的垂直錯誤修正碼;否則,回到步驟S721,用以寫入獨立磁碟冗餘陣列群組中未完成的訊息。 7A and 7B are flowcharts of a method of writing data in a processing unit according to an embodiment of the present invention. In a write operation of a redundant array of independent disks, the processing unit 610 first sets the message counter and the error correction code counter to 0 (step S711), and controls the multiplexer 640 to couple the dynamic random access memory. The body 620 is to the buffer 650 (step S713). Then, a loop including steps S721 to S731 is repeatedly executed until the messages in a separate disk redundancy array group are written into the specified storage unit, for example, the storage unit 10[ 0 ][ 0 ] to 10[ j ][ il ]. In detail, the processing unit 610 detects that the dynamic random access memory 620 has stored a new message of a specified length, for example, a 32K byte (step S721), indicating that the direct memory access controller 621 will be dynamically random. The message stored in the access memory 620 is stored in the buffer 650 via the multiplexer 640 and simultaneously stored in a buffer (not shown) in the disk array encoding unit 630 (step S723). Next, the processing unit 610 controls the arbitration unit 660 to read the value in the buffer 650 and write it through an appropriate storage unit access interface (eg, one of the storage unit access interfaces 230[ 0 ] to 230[ j ]). The read value is to a corresponding storage unit (for example, one of the storage units 10[ 0 ][ 0 ] to 10[ j ][ i ]) (step S725). The processing unit 610 increments the message counter (step S727), and determines whether the value of the message counter exceeds a threshold, for example, ( j + 1) x(i + 1) - 1 - 1 (step S731). If yes, proceed to steps S733 to S751 to write the vertical error correction code in the independent disk redundancy array group; otherwise, return to step S721 to write to the independent disk redundancy array group. Completed message.
為寫入獨立磁碟冗餘陣列群組中的垂直錯誤修正碼,處理單元610控制多工器640以耦接磁碟陣列編碼單元630至緩存器650(步驟S733)。接著,反覆執行一個包含步驟S741至S751的迴圈直到獨立磁碟冗餘陣列群組中的垂直錯誤修正碼都寫入到指定的儲存單元中,例如,儲存單元10[j][i-l+1]至10[j][i]。詳而言之,處理單元610指示磁碟陣列編碼單元630將指定長度(例如,32K位元組)的垂直錯誤修正碼經由多工器640輸出至緩存器650(步驟S741)。接著,處理單元610控制仲裁單元660讀取緩存器650中的值並透過適當的儲存單元存取介面(例如,儲存單元存取介面230[j])寫入讀取的值至相應的儲存單元中的指定位址(例如,儲存單元10[j][i-l+1]至10[j][i]中之一者)(步驟S743)。處理單元610將錯誤修正碼計數器加一後(步驟S745),判斷錯誤修正碼計數器的值是否超過閥值,例如,l-1(步驟S751)。若是,則回到步驟S711繼續下一個獨立磁碟冗餘陣列群組的寫入作業;否則,回到步驟S741,用以寫入 獨立磁碟冗餘陣列群組中未完成的垂直錯誤修正碼。 To write the vertical error correction code in the independent disk redundancy array group, the processing unit 610 controls the multiplexer 640 to couple the disk array encoding unit 630 to the buffer 650 (step S733). Then, a loop including steps S741 to S751 is repeatedly executed until the vertical error correction code in the independent disk redundancy array group is written into the specified storage unit, for example, the storage unit 10[ j ][ il + 1 ] to 10[ j ][ i ]. In detail, the processing unit 610 instructs the disk array encoding unit 630 to output a vertical error correction code of a specified length (for example, 32K bytes) to the buffer 650 via the multiplexer 640 (step S741). Next, the processing unit 610 controls the arbitration unit 660 to read the value in the buffer 650 and write the read value to the corresponding storage unit through an appropriate storage unit access interface (eg, the storage unit access interface 230[ j ]). The specified address in (for example, one of the storage units 10[ j ][ il + 1 ] to 10[ j ][ i ]) (step S743). The processing unit 610 increments the error correction code counter (step S745), and determines whether the value of the error correction code counter exceeds a threshold, for example, l-1 (step S751). If yes, go back to step S711 to continue the write operation of the next independent disk redundancy array group; otherwise, return to step S741 to write the unfinished vertical error correction code in the independent disk redundancy array group. .
第8圖係依據本發明實施例之執行於儲存單元存取介面中之資料寫入方法流程圖。此方法可應用於儲存單元存取介面230[0]至230[j]中之一者。當儲存單元存取介面由仲裁單元660接收到將特定長度的訊息(例如,32K位元組的訊息)寫入儲存單元的指示後(步驟S811),反覆執行一個包含步驟S821至S831的資料寫入迴圈直到完成所有的寫入作業。詳細來說,針對每一回合的寫入作業,儲存單元存取介面從仲裁單元660取得指定長度的訊息(例如,1K位元組的訊息)(步驟S821),依據取得的訊息產生水平錯誤修正碼(步驟S823),以及將訊息及產生的水平錯誤修正碼寫入指定儲存單元中的指定字元線的下一個區段的位址(步驟S825)。於此須注意的是,於步驟S825中,若為第一回合的寫入作業,則將讀取的訊息及產生的水平錯誤修正碼寫入指定字元線的第一個區段的位址。接著,儲存單元存取介面判斷是否完成所有的寫入作業(步驟S831)。若是,則結束整個流程;否則,回到步驟S821用以進行下一回合的寫入作業。第19A圖係依據本發明實施例之資料寫入時序圖。儲存單元存取介面230[0]至230[3]分別以通道CH0至CH3表示,而連接至每個儲存單元存取介面的儲存單元分別以CE0至CE3表示。第19A圖係寫入一個頁面PG0的資料(包含訊息及水平錯誤修正碼,或者是垂直錯誤修正碼)至所有儲存單元10[0][0]至10[3][3]中的第一個字元線WL0的例子。仲裁單元660透過通道CH0至CH3依序將頁面PG0的資料傳送到每個通道所連接之第一個儲存單元CE0中的緩存器(未顯示),接著, 發送寫入命令給所有連接之儲存單元CE0,用以開始實際的寫入作業。當儲存單元CE0中之任一者接收到寫入命令後,隨即進入忙碌狀態(busy state)來將緩存器中的頁面PG0的資料寫入到字元線WL0中的單層式單元。當所有儲存單元CE0開始實際的資料寫入作業時,通道CH0至CH3處於可用狀態,使得仲裁單元660可利用通道CH0至CH3依序將頁面PG0的資料傳送到每個通道所連接之第二個儲存單元CE1中的緩存器(未顯示)。熟習此技藝人士可觀察到由於使用以上的獨立磁碟冗餘陣列群組之資料擺放方式,使得通道CH0至CH3具有較少的閒置時間,並得以有效利用來傳送資料至儲存單元。 Figure 8 is a flow chart of a method for writing data in a storage unit access interface in accordance with an embodiment of the present invention. This method can be applied to one of the storage unit access interfaces 230[ 0 ] to 230[ j ]. After the storage unit access interface receives the instruction to write a message of a specific length (for example, a message of 32K bytes) into the storage unit by the arbitration unit 660 (step S811), a data write including steps S821 to S831 is repeatedly executed. Enter the loop until all writes are completed. In detail, for each round of write operation, the storage unit access interface acquires a message of a specified length (for example, a 1K byte message) from the arbitration unit 660 (step S821), and generates a horizontal error correction based on the obtained message. The code (step S823), and writing the message and the generated horizontal error correction code to the address of the next sector of the designated word line in the designated storage unit (step S825). It should be noted that, in step S825, if it is the first round of the write job, the read message and the generated horizontal error correction code are written into the address of the first segment of the specified word line. . Next, the storage unit access interface determines whether or not all of the write jobs are completed (step S831). If so, the entire process is ended; otherwise, the process returns to step S821 for the next round of writing. Fig. 19A is a timing chart of data writing according to an embodiment of the present invention. The storage unit access interfaces 230[0] to 230[3] are represented by channels CH0 to CH3, respectively, and the storage units connected to each storage unit access interface are denoted by CE0 to CE3, respectively. Figure 19A is the first data in all storage units 10[ 0 ][ 0 ] to 10[ 3 ][ 3 ] written to a page PG0 (including message and horizontal error correction code, or vertical error correction code). An example of a word line WL0. The arbitration unit 660 sequentially transfers the data of the page PG0 to the buffer (not shown) in the first storage unit CE0 connected to each channel through the channels CH0 to CH3, and then sends a write command to all connected storage units. CE0, used to start the actual write job. When any of the storage units CE0 receives the write command, it then enters a busy state to write the data of the page PG0 in the buffer to the single-level cell in the word line WL0. When all the storage units CE0 start the actual data writing operation, the channels CH0 to CH3 are in an available state, so that the arbitration unit 660 can sequentially transmit the data of the page PG0 to the second connected to each channel by using the channels CH0 to CH3. A buffer (not shown) in the storage unit CE1. Those skilled in the art can observe that the channels CH0 to CH3 have less idle time due to the use of the above-described independent disk redundant array group data arrangement, and are effectively utilized to transfer data to the storage unit.
第9圖係依據本發明實施例之用以執行讀取作業的系統方塊圖。處理單元910可使用多種方式實施,例如以專用硬體電路或通用硬體(例如,單一處理器、具平行處理能力的多處理器、圖形處理器或其他具運算能力的處理器),並且在執行程式碼或軟體時,提供之後所描述的功能。儲存單元10[0][0]至10[j][i]中之任一者可包含多個單層式單元。儲存單元存取介面(230[0]至230[j]中之一者)讀取相應之儲存單元中一個區段的值後,會將讀取的內容傳到區段解碼單元960。區段解碼單元960首先利用其中的水平錯誤修正碼檢查其中的訊息是否有錯誤,若是,則嘗試使用其中的水平錯誤修正碼進行修正。當訊息內容正確或已經修正成功後,區段解碼單元960捨棄水平錯誤修正碼,將訊息內容儲存至緩存器950中,使得其他電子裝置可經由處理單元存取介面250讀取解碼後的訊息。當區段解碼單元960使用其中的水平錯誤修正碼還沒辦法修正訊息中 的錯誤時,會發訊息通知處理單元910,訊息中包含發生錯誤但無法復原的區段位址等資訊。接著,處理單元910會啟動垂直修正程序。於垂直修正程序中,處理單元910先取得此區段位址所屬的獨立磁碟冗餘陣列群組的資訊,並找出可用來復原此錯誤區段位址中的訊息的所有其他區段位址(包含儲存垂直錯誤修正碼的區段位址)。例如,請參考第5B圖,假設區段410[0][0][0]中的訊息510[0][0][0]包含了即使使用水平錯誤修正碼530[0][0][0]還無法修正的錯誤時,其他可用來嘗試進行修正的區段為410[0][1][0]至410[j][i][0]。接著,處理單元910指示區段解碼單元960垂直修正程序已啟動,決定相應於無法修正之區段的其他區段,並且指示儲存單元存取介面230[0]至230[j]讀取指定之其他區段的值。當垂直修正程序啟動時,區段解碼單元960會透過儲存單元存取介面230[0]至230[j]依序獲得指定區段的值,並在解碼完成後傳送給磁碟陣列解碼單元930。磁碟陣列解碼單元930可使用所有所需區段的資料(包含原始訊息以及垂直錯誤修正碼)來復原先前無法修正的錯誤,並將復原的結果傳送至緩存器950,使得其他電子裝置可經由處理單元存取介面250讀取修正後的訊息。須注意的是,第9圖的處理單元910與第6圖的處理單元610可為同一個處理單元,本發明並不因此受限。 Figure 9 is a block diagram of a system for performing a read job in accordance with an embodiment of the present invention. Processing unit 910 can be implemented in a variety of manners, such as with dedicated hardware circuitry or general purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, graphics processors, or other computing capable processors), and When the code or software is executed, the functions described later are provided. Any of the storage units 10[ 0 ][ 0 ] to 10[ j ][ i ] may include a plurality of single layer units. After the storage unit access interface (one of 230 [ 0 ] to 230 [ j ]) reads the value of one of the corresponding storage units, the read content is passed to the section decoding unit 960. The section decoding unit 960 first checks whether the message therein has an error using the horizontal error correction code therein, and if so, attempts to correct using the horizontal error correction code therein. After the content of the message is correct or has been successfully modified, the segment decoding unit 960 discards the horizontal error correction code and stores the message content in the buffer 950 so that other electronic devices can read the decoded message via the processing unit access interface 250. When the segment decoding unit 960 has not used the horizontal error correction code therein to correct the error in the message, the message processing unit 910 is sent to the message including the segment address and other information that the error occurred but cannot be restored. Next, processing unit 910 initiates a vertical correction procedure. In the vertical correction procedure, the processing unit 910 first obtains the information of the independent disk redundancy array group to which the segment address belongs, and finds all other segment addresses that can be used to recover the information in the error segment address (including The sector address where the vertical error correction code is stored). For example, please refer to FIG. 5B, assuming section 410 [0] [0] [0] 510 in the post [0] [0] [0] contains the error correction code even if the level of 530 [0] [0] [ 0 ] When the error cannot be corrected, the other sections that can be used to try to correct are 410[ 0 ][ 1 ][ 0 ] to 410[ j ][ i ][ 0 ]. Next, the processing unit 910 instructs the segment decoding unit 960 that the vertical correction procedure has been initiated, determines other segments corresponding to the segments that cannot be corrected, and instructs the storage unit access interfaces 230[ 0 ] to 230[ j ] to read the specified The value of the other sections. When the vertical correction program is started, the segment decoding unit 960 sequentially obtains the value of the specified segment through the storage unit access interfaces 230[ 0 ] to 230[ j ], and transmits the value to the disk array decoding unit 930 after the decoding is completed. . The disk array decoding unit 930 can use all the required segments of the data (including the original message and the vertical error correction code) to recover the previously uncorrectable error and transmit the restored result to the buffer 950 so that other electronic devices can be The processing unit access interface 250 reads the corrected message. It should be noted that the processing unit 910 of FIG. 9 and the processing unit 610 of FIG. 6 may be the same processing unit, and the present invention is not limited thereby.
第10圖係依據本發明實施例之執行於區段解碼單元中之資料讀取方法流程圖。區段解碼單元960從儲存單元存取介面230[0]至230[j]中之一者獲得一個區段的值後(步驟S1010),使用其中的水平錯誤修正碼檢查其中的訊息是否正確 (步驟S1020)。若正確(步驟S1020中"是”的路徑),則將原始的訊息儲存於緩存器950中(步驟S1070);否則(步驟S1020中"否”的路徑),嘗試使用其中的水平錯誤修正碼修正訊息中存在的錯誤(步驟S1030)。接著,區段解碼單元960決定是否修正成功(步驟S1040)。若成功(步驟S1040中"是”的路徑),則將修正後的訊息儲存於緩存器950中(步驟S1070);否則(步驟S1040中"否”的路徑),發訊息給處理單元910用以通知此區段的錯誤無法使用水平錯誤修正碼回復(步驟S1050)。 Figure 10 is a flow chart of a method of reading data in a segment decoding unit in accordance with an embodiment of the present invention. The section decoding unit 960 obtains the value of one section from one of the storage unit access interfaces 230[ 0 ] to 230[ j ] (step S1010), and checks whether the message is correct using the horizontal error correction code therein ( Step S1020). If it is correct ("YES" path in step S1020), the original message is stored in the buffer 950 (step S1070); otherwise (the path "NO" in step S1020), an attempt is made to correct the horizontal error correction code therein. There is an error in the message (step S1030). Next, the section decoding unit 960 decides whether or not the correction is successful (step S1040). If successful (the path of "Yes" in step S1040), the corrected message is stored in the buffer 950 (step S1070); otherwise (the path of "NO" in step S1040), the message is sent to the processing unit 910. The error notifying this section cannot be replied using the horizontal error correction code (step S1050).
第11圖係依據本發明實施例之執行於處理單元中之資料讀取方法流程圖。處理單元910從區段解碼單元接收指定區段無法使用水平錯誤修正碼回復的通知後(步驟S1110),決定屬於相同獨立磁碟冗餘陣列群組中的其他區段位址(步驟S1120)。例如,請參考第5B圖,當區段410[0][0][0]無法使用其中的水平錯誤修正碼510[0][0][0]回復時,處理單元910決定屬於相同獨立磁碟冗餘陣列群組中的其他區段為410[0][1][0]至410[j][i][0]。指示區段解碼單元960及磁碟陣列解碼單元930垂直修正程序已經啟動(步驟S1130)。當區段解碼單元960接收到指示後,會將由儲存單元存取介面230[0]至230[j]中之一者所讀取之指定的值解碼完成,並且輸出至磁碟陣列解碼單元930,而非儲存於緩存器950中。接著,處理單元910反覆地執行一個區段內容讀取的迴圈,用以指示儲存單元存取介面230[0]至230[j]讀取上述指定區段的內容。於迴圈中,處理單元910指示指定的儲存單元存取介面讀取下一個區段的內容(步驟S1140)。受指示的儲存單元存取介面會將讀取的結果傳送 至區段解碼單元960。區段解碼單元960解碼出其中的訊息後,傳送至磁碟陣列解碼單元930,而磁碟陣列解碼單元930則根據先前的解碼結果以及新接收到的訊息產生一個新的解碼結果。當處理單元910從受指示之儲存單元存取介面或區段解碼單元960接收到讀取完成的通知後(步驟S1150),決定是否完成屬於相同獨立磁碟冗餘陣列群組中所有其他區段的訊息讀取作業(步驟S1160)。若是(步驟S1160中"是”的路徑),則結束迴圈;否則(步驟S1160中"否”的路徑),指示指定的儲存單元存取介面繼續讀取下一個區段的內容(步驟S1140)。當迴圈結束時,處理單元910指示區段解碼單元960及磁碟陣列解碼單元930垂直修正程序已經結束(步驟S1170)。當區段解碼單元960接收到垂直修正程序已經結束的指示後,會將之後完成解碼的值儲存於緩存器950中,而非輸出至磁碟陣列解碼單元930。另一方面,當磁碟陣列解碼單元930接收到指示後,將目前的解碼結果儲存於緩存器950,作為指定區段的垂直回復結果。 Figure 11 is a flow chart of a method of reading data in a processing unit in accordance with an embodiment of the present invention. The processing unit 910, after receiving the notification that the specified segment cannot be replied with the horizontal error correction code from the segment decoding unit (step S1110), decides to belong to other segment addresses in the same independent disk redundancy array group (step S1120). For example, referring to FIG. 5B, when the segment 410[ 0 ][ 0 ][ 0 ] cannot be recovered using the horizontal error correction code 510[ 0 ][ 0 ][ 0 ], the processing unit 910 decides to belong to the same independent magnetic. The other segments in the disk redundancy array group are 410[ 0 ][ 1 ][ 0 ] to 410[ j ][ i ][ 0 ]. The segmentation decoding unit 960 and the disk array decoding unit 930 have been activated by the vertical correction program (step S1130). When the segment decoding unit 960 receives the indication, the specified value read by one of the storage unit access interfaces 230[ 0 ] to 230[ j ] is decoded and output to the disk array decoding unit 930. Instead of being stored in the buffer 950. Next, the processing unit 910 repeatedly performs a loop of the section content reading to instruct the storage unit access interfaces 230[ 0 ] to 230[ j ] to read the content of the specified section. In the loop, the processing unit 910 instructs the designated storage unit access interface to read the contents of the next section (step S1140). The indicated storage unit access interface transmits the read result to the section decoding unit 960. The segment decoding unit 960 decodes the message therein and transmits it to the disk array decoding unit 930, and the disk array decoding unit 930 generates a new decoding result based on the previous decoding result and the newly received message. When the processing unit 910 receives the notification of completion of reading from the indicated storage unit access interface or segment decoding unit 960 (step S1150), it is determined whether to complete all other segments belonging to the same independent disk redundancy array group. The message reading job (step S1160). If yes (the path of YES in step S1160), the loop is ended; otherwise (the path of "NO" in step S1160), the specified storage unit access interface continues to read the contents of the next section (step S1140) . When the loop ends, the processing unit 910 instructs the extent decoding unit 960 and the disk array decoding unit 930 that the vertical correction procedure has ended (step S1170). When the section decoding unit 960 receives the indication that the vertical correction procedure has ended, the value that is subsequently decoded is stored in the buffer 950 instead of being output to the disk array decoding unit 930. On the other hand, when the disk array decoding unit 930 receives the indication, the current decoding result is stored in the buffer 950 as a vertical reply result of the designated segment.
第12圖係依據本發明實施例之用以執行寫入作業的系統方塊圖。處理單元1210可使用多種方式實施,例如以專用硬體電路或通用硬體(例如,單一處理器、具平行處理能力的多處理器、圖形處理器或其他具運算能力的處理器),並且在執行程式碼或軟體時,提供之後所描述的功能。儲存單元10[0][0]至10[j][i]中之任一者可包含多個記憶單元,而每一個記憶單元可以三層式單元實施。處理單元1210可控制儲存單元存取介面230用以將儲存於緩存器1250中的值寫入至儲存單元10[0][0]至10[j][i]中之一者。針對每一個儲存單元,處理單元1210可逐 字元線(wordline)寫入值,其中,一個字元線上可儲存多頁(pages)的值。雖然以下以一個字元線包含三頁的值為例,但熟習此技藝人士亦可修改為於一個字元線上寫入更多或更少頁的值,本發明並不以此受限。一頁可包含8K、16K、32K或64K位元組(Bytes)的訊息。由於三層式單元會被鄰近字元線的寫入操作影響而使得原先儲存的電荷洩漏,或吸入更多的電荷,造成臨界電壓改變,所以,需要重複數次的寫入操作以避免因以上問題造成單元中代表的儲存值發生變化。以下說明的技術方案亦可稱為粗略至細緻(F&F,foggy and fine)的寫入方法。第17A至17C圖係顯示依據本發明實施例之經三次寫入操作後之一個字元線上的眾多三層式單元的臨界電壓分布示意圖。經過第一次寫入操作後,臨界電壓分布如第17A圖中的實線所示。從第17A圖中可觀察出經過第一次粗略的寫入作業後,臨界電壓分布無法產生具區別性的八個狀態。而接著,當鄰近的字元線進行寫入操作時,將影響此字元線上之三層式單元原先儲存的電荷,讓臨界電壓分布變得更糟。影響後的臨界電壓分布如第17A圖中的虛線所示。為了讓三層式單元中實際儲存的電荷數目更接近理想值,進行第二次寫入操作,而第二次寫入操作後的臨界電壓分布如第17B圖中的實線所示。從第17B圖中可觀察出經過第二次的寫入作業後,臨界電壓分布可以產出稍具區別性的八個狀態。但是,當受到鄰近字元線的後續寫入操作影響時,此臨界電壓分布中的八個狀態間又產生些許重疊。影響後的臨界電壓分布如第17B圖中的虛線所示。為了再次調整受到影響的結果,此字元線會再進行第三次的寫入作業,讓臨界 電壓分布中的八個狀態間可擁有較寬的間隔。經過第三次寫入作業後的臨界電壓分布請參考第17C圖。 Figure 12 is a block diagram of a system for performing a write job in accordance with an embodiment of the present invention. Processing unit 1210 can be implemented in a variety of manners, such as with dedicated hardware circuitry or general purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, graphics processors, or other computing capable processors), and When the code or software is executed, the functions described later are provided. Any of the storage units 10[ 0 ][ 0 ] to 10[ j ][ i ] may include a plurality of memory units, and each of the memory units may be implemented in a three-layer unit. The processing unit 1210 can control the storage unit access interface 230 to write the value stored in the buffer 1250 to one of the storage units 10[ 0 ][ 0 ] to 10[ j ][ i ]. For each storage unit, processing unit 1210 can write values word-by-word lines, where a number of pages can be stored on one word line. Although the following is an example in which one word line contains three pages, those skilled in the art can also modify the value of writing more or fewer pages on one word line, and the present invention is not limited thereto. A page can contain 8K, 16K, 32K or 64K Bytes. Since the three-layer cell is affected by the write operation of the adjacent word line, the original stored charge leaks, or more charges are drawn, causing the threshold voltage to change. Therefore, it is necessary to repeat the writing operation several times to avoid The problem caused the stored value represented in the unit to change. The technical solution described below can also be referred to as a F&F (foggy and fine) writing method. 17A to 17C are diagrams showing threshold voltage distributions of a plurality of three-layer cells on one word line after three write operations in accordance with an embodiment of the present invention. After the first write operation, the critical voltage distribution is shown by the solid line in Fig. 17A. It can be observed from Fig. 17A that after the first rough write operation, the critical voltage distribution cannot produce eight distinct states. Then, when a neighboring word line performs a write operation, it will affect the charge originally stored by the three-layer cell on the word line, making the threshold voltage distribution worse. The critical voltage distribution after the influence is shown by the broken line in Fig. 17A. In order to make the number of charges actually stored in the three-layer unit closer to the ideal value, the second write operation is performed, and the threshold voltage distribution after the second write operation is as shown by the solid line in FIG. 17B. It can be observed from Fig. 17B that after the second write operation, the critical voltage distribution can produce eight distinct states. However, when affected by subsequent write operations of adjacent word lines, a slight overlap occurs between the eight states in this threshold voltage distribution. The critical voltage distribution after the influence is shown by the broken line in Fig. 17B. In order to re-adjust the affected results, the word line will perform a third write operation, allowing for a wider gap between the eight states in the threshold voltage distribution. Please refer to Figure 17C for the threshold voltage distribution after the third write operation.
參考回第12圖,於此架構中,假設緩存器1250的容量可儲存三個頁面的值,因此需要動態隨機存取記憶體1240先暫存透過處理單元存取介面250從其他電子裝置傳來的九個頁面的值。處理單元1210可指示直接記憶體存取控制器(direct memory access,DMA controller)1220將處理單元存取介面250上的值儲存至動態隨機存取記憶體1240中的指定位址,而新接收之一個頁面的值會覆寫掉其中最早儲存之頁面的值。需注意的是,被覆寫掉之頁面的值已經經過三次寫入後穩定地被儲存於指定的儲存單元中。動態隨機存取記憶體1240可整合至包含元件230[0..j]、250、1210、1220、1230及1250的系統單晶片中(system on chip,SOC),或者是實施於獨立的晶片。於實際的寫入作業中,處理單元1210可指示直接記憶體存取控制器1230從動態隨機存取記憶體1240讀取三個頁面的值並儲存至緩存器1250中,接著透過儲存單元存取介面230[0]至230[j]中之一者,將緩存器1250中的值寫入指定儲存單元中的指定字元線上的三層式單元。第13圖係依據本發明實施例之一個儲存單元中的三層式單元區塊(TLC block)的示意圖。三層式單元區塊1300可包含總數為192個頁面的值,頁面標號為PG0至PG191。每個字元線上可儲存三個頁面的值,字元線標號為WL0至WL63。請參考第16C圖,每個字元線上之所有三層式單元中指示的最低位元,集合起來成為一個頁面的值。類似地,所有三層式單元中指示的中間位元以及最高位元,分別集合起來成為另二個 頁面的值。為了讓儲存的值能夠穩定,處理單元1210除了要將動態隨機存取記憶體1240中最近接收到的三個頁面的值寫入三層式單元區塊1300以外,還需要使用兩個批次從動態隨機存取記憶體1240讀取之前曾經寫入過的六個頁面的值至緩存器250,並使用指定的儲存單元存取介面寫入到指定儲存單元中的指定字元線上的三層式單元。例如,寫入頁面PG6至PG8至字元線WL2上的三層式單元後,處理單元1210更指示直接記憶體存取控制器1230從動態隨機存取記憶體1240讀取頁面PG0至PG2的值並儲存至緩存器250中,並使用儲存單元存取介面230將緩存器250中的值寫入字元線WL0上的記憶單元,接著,指示直接記憶體存取控制器1230從動態隨機存取記憶體1240讀取頁面PG3至PG5的值並儲存至緩存器250中,並使用儲存單元存取介面230將緩存器250中的值寫入字元線WL1上的記憶單元。第21圖係依據本發明實施例之字元線寫入順序示意圖。此針對單一儲存單元的寫入順序可記錄於查找表(lookup table)2100中,用以讓處理單元1210據以決定每次欲寫入的字元線或頁面。查找表中包含三欄,分別記錄每一個字元線WL0至WL63於第一次、第二次及第三次寫入間的順序。由於三層式單元中的值需要重複寫入數次後才會穩定,因此當處理單元1210透過處理單元存取介面250接收到其他電子裝置發出的資料讀取命令時,需要先判斷儲存單元中儲存的值是否已經穩定。若是,則透過指定的儲存單元存取介面230[0]至230[j]中之一者讀取指定儲存單元中之指定位址的值,並回覆給請求的電子裝置;若否,則從動態隨機存取記憶體1240中讀取欲儲存 至指定儲存單元中之指定位址的值,並回覆給請求的電子裝置。於此須注意的是,關於動態隨機存取記憶體1240所暫存的值將儲存於何儲存單元中之何位址的資訊可儲存於動態隨機存取記憶體1240或暫存器(register,未顯示)中,並且處理單元1210可透過此資訊來判斷其他電子裝置欲讀取的值是否已穩定地儲存於指定的儲存單元中。詳而言之,如果動態隨機存取記憶體1240或暫存器中儲存的資訊中指出動態隨機存取記憶體1240所暫存一部份的值將儲存於讀取位址,則代表欲讀取的值尚未穩定地儲存於儲存單元中。 Referring back to FIG. 12, in this architecture, it is assumed that the capacity of the buffer 1250 can store values of three pages. Therefore, the dynamic random access memory 1240 needs to be temporarily stored in the electronic device through the processing unit access interface 250. The value of the nine pages. The processing unit 1210 can instruct the direct memory access (DMA controller) 1220 to store the value on the processing unit access interface 250 to the specified address in the dynamic random access memory 1240, and receive the new address. The value of a page overwrites the value of the oldest stored page. It should be noted that the value of the page written by the overlay has been stably stored in the specified storage unit after three times of writing. The DRAM 1240 can be integrated into a system on chip (SOC) comprising components 230 [ 0..j ], 250, 1210, 1220, 1230, and 1250, or implemented in separate wafers. In the actual write operation, the processing unit 1210 may instruct the direct memory access controller 1230 to read the values of the three pages from the dynamic random access memory 1240 and store them in the buffer 1250, and then access through the storage unit. One of the interfaces 230[0] through 230[j] writes the value in the buffer 1250 to the three-level cell on the specified word line in the specified storage unit. Figure 13 is a schematic diagram of a three-layer cell block (TLC block) in a memory cell in accordance with an embodiment of the present invention. The three-level cell block 1300 may contain a total of 192 pages of values, with page numbers PG0 through PG191. The value of three pages can be stored on each character line, and the word line labels are WL0 to WL63. Referring to Figure 16C, the lowest bits indicated in all three-level cells on each character line are grouped together to become a page value. Similarly, the middle bits and the highest bits indicated in all three-tier units are grouped together to become the values of the other two pages. In order to stabilize the stored values, the processing unit 1210 needs to use two batches in addition to writing the values of the three most recently received pages in the DRAM 1240 to the three-level cell block 1300. The DRAM 1240 reads the values of the six pages that have been previously written to the buffer 250, and uses the specified storage unit access interface to write to the three-layered line on the specified word line in the specified storage unit. unit. For example, after writing the three-level cells on the pages PG6 to PG8 to the word line WL2, the processing unit 1210 instructs the direct memory access controller 1230 to read the values of the pages PG0 to PG2 from the dynamic random access memory 1240. And storing in the buffer 250, and using the storage unit access interface 230 to write the value in the buffer 250 to the memory unit on the word line WL0, and then instructing the direct memory access controller 1230 from the dynamic random access. The memory 1240 reads the values of the pages PG3 through PG5 and stores them in the buffer 250, and uses the storage unit access interface 230 to write the values in the buffer 250 to the memory cells on the word line WL1. Figure 21 is a diagram showing the sequence of writing of word lines in accordance with an embodiment of the present invention. This write order for a single storage unit can be recorded in a lookup table 2100 for the processing unit 1210 to determine the word line or page to be written each time. The lookup table contains three columns that record the order of each of the word lines WL0 to WL63 between the first, second, and third writes. Since the value in the three-layer unit needs to be repeated for several times, the processing unit 1210 needs to first determine the storage unit when receiving the data reading command from other electronic devices through the processing unit access interface 250. Whether the stored value has stabilized. If yes, the one of the specified storage unit access interfaces 230[ 0 ] to 230[ j ] reads the value of the specified address in the specified storage unit and replies to the requested electronic device; if not, then The DRAM 1240 reads the value of the specified address to be stored in the specified storage unit and replies to the requested electronic device. It should be noted that information about the address stored in the storage unit for the value temporarily stored in the DRAM 1240 can be stored in the DRAM 1240 or the register (register, Not shown, and the processing unit 1210 can use this information to determine whether the value to be read by other electronic devices has been stably stored in the specified storage unit. In detail, if the information stored in the DRAM 1240 or the scratchpad indicates that the temporarily stored value of the DRAM 1240 is stored in the read address, it means that it is to be read. The value taken has not been stored stably in the storage unit.
第14圖係依據本發明實施例之執行於處理單元中之寫入方法流程圖。當處理單元1210透過處理單元存取介面250接收到其他電子裝置發出的寫入命令及寫入位址後(步驟S1410),指示直接記憶體存取控制器1220將欲寫入的值由處理單元存取介面250搬至動態隨機存取記憶體1240(步驟S1420)。判斷是否已經接收完指定數目之頁面的值(步驟S1430),例如,第n至n+2頁的值,若是,進行實際的寫入作業(步驟S1440至步驟S1470);否則,繼續透過處理單元存取介面250接收尚未傳送完的值(步驟S1410至步驟S1420)。於實際的寫入作業中,處理單元1210指示直接記憶體存取控制器1230將最近暫存於動態隨機存取記憶體1240中指定數目之頁面的值儲存至緩存器1250(步驟S1440),指示儲存單元存取介面230將緩存器1250中的值寫入指定儲存單元中的指定字元線上的三層式單元(步驟S1450)。接著,為了讓先前已寫入的值避免受到這次寫入作業的影響,處理單元1210更使用二個的批次來指 示直接記憶體存取控制器1230將暫存於動態隨機存取記憶體1240中最近已寫入至儲存單元的六個頁面的值再次儲存至緩存器1250。詳而言之,處理單元1210指示直接記憶體存取控制器1230將暫存於動態隨機存取記憶體1240中之前第三至第一頁的值儲存至緩存器1250,例如,第n-3至n-1頁的值,並指示指定的儲存單元存取介面將緩存器1250中的值再次寫入指定儲存單元中之指定字元線上的三層式單元(步驟S1460),以及,處理單元1210指示直接記憶體存取控制器1230將暫存於動態隨機存取記憶體1240中之前第六至第四頁的值儲存至緩存器1250,例如,第n-6至n-4頁的值,並指示指定的儲存單元存取介面將緩存器1250中的值再次寫入指定儲存單元中之指定字元線上的三層式單元(步驟S1470)。 Figure 14 is a flow diagram of a method of writing performed in a processing unit in accordance with an embodiment of the present invention. After the processing unit 1210 receives the write command and the write address issued by the other electronic device through the processing unit access interface 250 (step S1410), the direct memory access controller 1220 instructs the value to be written by the processing unit. The access interface 250 is moved to the dynamic random access memory 1240 (step S1420). Determining whether the value of the specified number of pages has been received (step S1430), for example, the value of the nth to n + 2 pages, and if so, performing the actual write operation (step S1440 to step S1470); otherwise, continuing to pass through the processing unit The access interface 250 receives the value that has not been transmitted (step S1410 to step S1420). In the actual write operation, the processing unit 1210 instructs the direct memory access controller 1230 to store the value of the specified number of pages temporarily stored in the DRAM 1240 to the buffer 1250 (step S1440), indicating The storage unit access interface 230 writes the value in the buffer 1250 to the three-layer unit on the specified word line in the specified storage unit (step S1450). Next, in order to avoid the previously written value from being affected by the write operation, the processing unit 1210 further uses two batches to indicate that the direct memory access controller 1230 will be temporarily stored in the dynamic random access memory 1240. The values of the six pages that have been recently written to the storage unit are again stored in the buffer 1250. In detail, the processing unit 1210 instructs the direct memory access controller 1230 to store the values of the third to first pages before being temporarily stored in the dynamic random access memory 1240 to the buffer 1250, for example, the n-3. a value to page n-1 , and instructing the specified storage unit access interface to rewrite the value in the buffer 1250 to the three-layer unit on the specified word line in the specified storage unit (step S1460), and the processing unit 1210 instructs the direct memory access controller 1230 to store the values of the sixth to fourth pages previously stored in the DRAM 1240 to the buffer 1250, for example, the values of the n-6th to n-4th pages. And instructing the specified storage unit access interface to rewrite the value in the buffer 1250 to the three-layer unit on the designated word line in the specified storage unit (step S1470).
第15圖係依據本發明實施例之執行於處理單元中之寫入方法流程圖。當處理單元1210透過處理單元存取介面250接收到其他電子裝置發出的讀取命令及讀取位址後(步驟S1510),判斷欲讀取位址的值是否尚未穩定地儲存於儲存單元中(步驟S1520)。若是,指示直接記憶體存取控制器1220從動態隨機存取記憶體1240讀取請求的值並透過處理單元存取介面250回覆給請求的電子裝置(步驟S1530);否則,透過儲存單元存取介面從儲存單元讀出指定位址的值(步驟S1540),並且將讀出的值透過處理單元存取介面250回覆給請求的電子裝置(步驟S1550)。 Figure 15 is a flow chart of a method of writing executed in a processing unit in accordance with an embodiment of the present invention. After the processing unit 1210 receives the read command and the read address issued by the other electronic device through the processing unit access interface 250 (step S1510), it is determined whether the value of the address to be read has not been stably stored in the storage unit ( Step S1520). If so, the direct memory access controller 1220 is instructed to read the requested value from the dynamic random access memory 1240 and reply to the requested electronic device through the processing unit access interface 250 (step S1530); otherwise, access through the storage unit The interface reads the value of the specified address from the storage unit (step S1540), and replies the read value to the requesting electronic device through the processing unit access interface 250 (step S1550).
為了保護三層式單元中所儲存的資料(包含訊息及水平錯誤修正碼),可更儲存垂直錯誤修正碼而形成二維錯誤 修正碼的保護。為了提升寫入資料的效率,本發明實施例提出一種新的訊息以及錯誤修正碼的擺放方式。第18A圖係依據本發明實施例之使用RS(48,45)垂直錯誤修正碼之獨立磁碟冗餘陣列群組的資料擺放示意圖。假設i=3,j=3且每條字元線可儲存三個頁面的訊息及水平錯誤修正碼,或三個頁面的垂直錯誤修正碼。總共16個儲存單元10[0][0]至10[3][3]中的第一條字元線WL0中所儲存48個頁面,可以形成一個獨立磁碟冗餘陣列群組。其中,於儲存單元10[3][3]中的第一條字元線WL0(陰影部分)中儲存3個頁面的垂直錯誤修正碼。第18B圖係依據本發明實施例之使用RS(96,93)垂直錯誤修正碼之獨立磁碟冗餘陣列群組的資料擺放示意圖。總共16個儲存單元10[0][0]至10[3][3]中的第一及第二條字元線WL0及WL1中所儲存96個頁面,可以形成一個獨立磁碟冗餘陣列群組。其中,於儲存單元10[3][3]中的第二條字元線WL1(陰影部分)中儲存三個頁面的垂直錯誤修正碼。由於一個獨立磁碟冗餘陣列群組中的各頁面資料被分開擺放在不同的實體儲存單元中,可避免當其中的一個儲存單元發生不可回復的硬體錯誤時所造成資料不可回復的情形。此外,以上所述的擺放方式也可提升資料寫入的效率。請參考第6圖。處理單元610可指示仲裁單元660以事先定義的順序將資料寫入每個儲存單元中的第一條字元線。第19B圖係依據本發明實施例之資料寫入時序圖。儲存單元存取介面230[0]至230[3]分別以通道CH0至CH3表示,而連接至每個儲存單元存取介面的儲存單元分別以CE0至CE3表示。第19B圖係一個寫入三個頁面PG0、PG1及PG2的資料(包含訊息及水平錯誤修正碼,或者 是垂直錯誤修正碼)至所有儲存單元10[0][0]至10[3][3]中的第一個字元線WL0的例子。仲裁單元660透過通道CH0至CH3依序將三個頁面PG0、PG1及PG2的資料傳送到每個通道所連接之第一個儲存單元CE0中的緩存器(未顯示),接著,發送寫入命令給所有連接之儲存單元CE0,用以開始實際的寫入作業。當儲存單元CE0中之任一者接收到寫入命令後,隨即進入忙碌狀態(busy state)來將緩存器中三個頁面PG0、PG1及PG2的資料寫入到字元線WL0中的三層式單元。當所有儲存單元CE0開始實際的資料寫入作業時,通道CH0至CH3處於可用狀態,使得仲裁單元660可利用通道CH0至CH3依序將三個頁面PG0、PG1及PG2的資料傳送到每個通道所連接之第二個儲存單元CE1。熟習此技藝人士可觀察到由於使用以上的獨立磁碟冗餘陣列群組之資料擺放方式,使得通道CH0至CH3具有較少的閒置時間,並得以有效利用來傳送資料至儲存單元。 In order to protect the data stored in the three-layer unit (including the message and the horizontal error correction code), the vertical error correction code can be further stored to form a two-dimensional error correction code. In order to improve the efficiency of writing data, the embodiment of the present invention proposes a new message and a method for placing an error correction code. Figure 18A is a diagram showing the arrangement of data of a redundant array of independent disks using an RS (48, 45) vertical error correction code according to an embodiment of the present invention. Suppose i = 3 , j = 3 and each word line can store three pages of messages and horizontal error correction codes, or three pages of vertical error correction codes. A total of 48 pages stored in the first word line WL0 of the 16 storage units 10[ 0 ][ 0 ] to 10[ 3 ][ 3 ] may form an independent disk redundancy array group. Therein, three pages of vertical error correction codes are stored in the first word line WL0 (shaded portion) in the storage unit 10[3][3]. Figure 18B is a diagram showing the arrangement of data of a redundant array of independent disks using an RS (96, 93) vertical error correction code according to an embodiment of the present invention. A total of 96 pages stored in the first and second word lines WL0 and WL1 of the 16 storage units 10[ 0 ][ 0 ] to 10[ 3 ][ 3 ] can form a redundant array of independent disks. Group. Therein, three pages of vertical error correction codes are stored in the second word line WL1 (shaded portion) in the storage unit 10[3][3]. Since each page data in a redundant array of independent disks is separately placed in different physical storage units, it can avoid the situation that the data cannot be recovered when one of the storage units fails to recover. . In addition, the placement method described above can also improve the efficiency of data writing. Please refer to Figure 6. Processing unit 610 can instruct arbitration unit 660 to write material to the first word line in each storage unit in a predefined order. Fig. 19B is a timing chart of data writing according to an embodiment of the present invention. The storage unit access interfaces 230[0] to 230[3] are represented by channels CH0 to CH3, respectively, and the storage units connected to each storage unit access interface are denoted by CE0 to CE3, respectively. Figure 19B is a data (including message and horizontal error correction code, or vertical error correction code) written to three pages PG0, PG1 and PG2 to all storage units 10[ 0 ][ 0 ] to 10[ 3 ][ An example of the first word line WL0 in 3 ]. The arbitration unit 660 sequentially transfers the data of the three pages PG0, PG1, and PG2 to the buffer (not shown) in the first storage unit CE0 connected to each channel through the channels CH0 to CH3, and then sends a write command. All connected storage units CE0 are used to start the actual write operation. When any one of the storage units CE0 receives the write command, it then enters a busy state to write the data of the three pages PG0, PG1 and PG2 in the buffer to the third layer in the word line WL0. Unit. When all the storage units CE0 start the actual data writing operation, the channels CH0 to CH3 are in an available state, so that the arbitration unit 660 can sequentially transfer the data of the three pages PG0, PG1, and PG2 to each channel by using the channels CH0 to CH3. The second storage unit CE1 is connected. Those skilled in the art can observe that the channels CH0 to CH3 have less idle time due to the use of the above-described independent disk redundant array group data arrangement, and are effectively utilized to transfer data to the storage unit.
第6圖所示架構中的儲存單元10[0][0]至10[j][i]亦可以修改為包含多個三層式單元。第20A至20D圖係依據本發明實施例之執行於處理單元中之寫入資料方法流程圖。於一個獨立磁碟冗餘陣列群組的寫入作業中,處理單元610首先將訊息計數器以及錯誤修正碼計數器設為0(步驟S2011),以及控制多工器640以耦接動態隨機存取記憶體620至緩存器650(步驟S2013)。接著,反覆執行一個包含步驟S2021至S2087的迴圈直到一個獨立磁碟冗餘陣列群組中的訊息都寫入到指定的儲存單元中,例如,第18A圖所示之儲存單元10[0][0]至10[3][3]的字元線WL0,或者,第18B圖所示之儲存單元10[0][0]至10[3][3] 的字元線WL0及WL1。 The storage units 10[ 0 ][ 0 ] to 10[ j ][ i ] in the architecture shown in FIG. 6 can also be modified to include a plurality of three-layer units. 20A to 20D are flowcharts of a method of writing data executed in a processing unit according to an embodiment of the present invention. In a write operation of a redundant array of independent disks, the processing unit 610 first sets the message counter and the error correction code counter to 0 (step S2011), and controls the multiplexer 640 to couple the dynamic random access memory. The body 620 is to the buffer 650 (step S2013). Then, a loop including steps S2021 to S2087 is repeatedly executed until the message in the independent disk redundancy array group is written into the specified storage unit, for example, the storage unit 10[ 0 ] shown in FIG. 18A. [0] to 10 [3] [3] of the word lines WL0, or, as shown in FIG. 18B, the storage unit 10 [0] [0] to 10 [3] [3] of the word line WL0 and WL1.
步驟S2021至步驟S2031為寫入資料至所有儲存單元中之特定字元線的準備步驟。處理單元610使用變數q來決定此次寫入所使用的儲存單元存取介面為哪一個,以及使用變數p來決定寫入至此儲存單元存取介面中的第幾個儲存單元。為了讓儲存於三層式單元中的值能夠穩定,可以參考如第14圖所描述的字元線寫入方法,讓每個字元線都能夠反覆且交錯地寫入三次。於每一個字元線的第一個儲存單元寫入作業中,設變數p=0及q=0(步驟S2021)。針對儲存單元10[q][p],處理單元610決定欲寫入的字元線或頁面,例如,字元線WL0或頁面PG0至PG2(步驟S2023)。處理單元610可參考如第21圖所示的寫入順序以決定欲寫入的字元線或頁面。接著,選擇性地將訊息計數器維持為0或MAXixMAXjxn,以及將錯誤修正碼計數器設為0,其中常數MAXj代表儲存單元存取介面的總數,常數MAXi代表連結於每一個儲存單元存取介面的儲存單元總數,變數n則代表已經完成的字元線總數(步驟S2025)。以第18B圖所示之使用RS(96,93)錯誤修正碼之獨立磁碟冗餘陣列群組的資料擺放為例,當這次寫入作業關聯於字元線WL0時,則將訊息計數器維持為0。當這次寫入作業關聯於字元線WL1時,則將訊息計數器設為4x4x1=16。 Steps S2021 to S2031 are preparation steps of writing data to a specific word line in all the storage units. The processing unit 610 uses the variable q to determine which storage unit access interface is used for this write, and uses the variable p to determine the number of storage units written to the storage unit access interface. In order to stabilize the values stored in the three-layer cell, reference can be made to the word line write method as described in FIG. 14 so that each word line can be written three times repeatedly and in an interleaved manner. In the first memory cell write job of each word line, the variables p = 0 and q = 0 are set (step S2021). For the storage unit 10[ q ][ p ], the processing unit 610 decides the word line or page to be written, for example, the word line WL0 or the pages PG0 to PG2 (step S2023). The processing unit 610 can refer to the write sequence as shown in FIG. 21 to determine the word line or page to be written. Then, the message counter is selectively maintained at 0 or MAXixMAXjxn , and the error correction code counter is set to 0, wherein the constant MAXj represents the total number of storage unit access interfaces, and the constant MAXi represents the storage connected to each storage unit access interface. The total number of cells, the variable n , represents the total number of word lines that have been completed (step S2025). Taking the data placement of the independent disk redundancy array group using the RS (96, 93) error correction code shown in FIG. 18B as an example, when the write job is associated with the word line WL0, the message counter is used. Maintain at 0 . When this write job is associated with the word line WL1, the message counter is set to 4x4x1 = 16.
步驟S2031至S2035則用來寫入訊息及水平錯誤修正碼至指定的儲存單元10[q][p]。處理單元610指示直接記憶體存取控制器621將動態隨機存取記憶體620中儲存的三個頁面訊息經由多工器640儲存至緩存器650,並同時儲存至磁碟陣列 編碼單元630中的緩存器(未顯示)(步驟S2031)。接著,處理單元610控制仲裁單元660讀取緩存器650中的值並指示儲存單元存取介面230[q]寫入至儲存單元10[q][p](步驟S2033)。接著,處理單元610將訊息計數器加三(步驟S2035)。針對所有儲存單元的寫入時序可參考第19圖的說明。 Steps S2031 to S2035 are used to write the message and the horizontal error correction code to the specified storage unit 10[ q ][ p ]. The processing unit 610 instructs the direct memory access controller 621 to store the three page messages stored in the dynamic random access memory 620 to the buffer 650 via the multiplexer 640 and simultaneously store them in the disk array encoding unit 630. A buffer (not shown) (step S2031). Next, the processing unit 610 controls the arbitration unit 660 to read the value in the buffer 650 and instructs the storage unit access interface 230[ q ] to write to the storage unit 10[ q ][ p ] (step S2033). Next, the processing unit 610 adds three to the message counter (step S2035). For the write timing of all memory cells, refer to the description of Figure 19.
步驟S2041、S2081至S2087用以決定下一次寫入作業係針對哪一個儲存單元存取介面及儲存單元。當處理單元610判斷訊息計數器的值小於閥值後(步驟S2041中”否”的路徑),將變數q加一(步驟S2081)。以第18B圖所示之使用RS(96,93)錯誤修正碼之獨立磁碟冗餘陣列群組的資料擺放為例,訊息計數器的值小過閥值(如93)則代表一個獨立磁碟冗餘陣列群組中的訊息尚未全部寫完。接著,判斷變數q是否大於或等於常數MAXj(步驟S2083),若否,則此流程繼續進行至步驟S2031;若是,則將變數p加一並將變數q設為0(步驟S2085),並接著判斷變數p是否大於或等於常數MAXi(步驟S2087)。當變數p大於或等於常數MAXi時(步驟S2087中”是”的路徑),代表所有的儲存單元中的指定字元線已經寫入完成,流程繼續進行至步驟S2021,用以繼續下一個字元線的寫入作業。否則(步驟S2087中”否”的路徑),流程繼續進行至步驟S2031。 Steps S2041 and S2081 to S2087 are used to determine which storage unit access interface and storage unit the next write operation is for. When the processing unit 610 determines that the value of the message counter is less than the threshold (the path of NO in step S2041), the variable q is incremented by one (step S2081). Taking the data placement of the independent disk redundancy array group using the RS (96, 93) error correction code shown in Figure 18B as an example, the value of the message counter is smaller than the threshold (such as 93) to represent an independent magnetic field. The messages in the Dish Redundant Array group have not yet been written. Next, it is determined whether the variable q is greater than or equal to the constant MAXj (step S2083), and if not, the flow proceeds to step S2031; if so, the variable p is incremented by one and the variable q is set to 0 (step S2085), and then It is judged whether or not the variable p is greater than or equal to the constant MAXi (step S2087). When the variable p is greater than or equal to the constant MAXi (the path of YES in step S2087), the designated word line in all the storage units has been written, and the flow proceeds to step S2021 to continue the next character. Line write job. Otherwise (the path of "NO" in step S2087), the flow proceeds to step S2031.
由於垂直錯誤修正碼亦要被寫入三次才會穩定,本發明實施例提出一種程序,用以暫存第一次產生的垂直錯誤修正碼於動態隨機存取記憶體620中,並且於後續重新寫入時直接從動態隨機存取記憶體620中取得已經產生的垂直錯誤修正碼,而不需要重新計算。以第18B圖所示之使用RS(96,93)錯 誤修正碼之獨立磁碟冗餘陣列群組的資料擺放為例,另一種實施方式,當磁碟陣列編碼單元630要產生相應於儲存單元10[3][3]的字元線WL1的垂直錯誤修正碼時,可從動態隨機存取記憶體620重新載入欲儲存於16個儲存單元中之字元線WL0及WL1中的值來產生垂直錯誤修正碼,然而,這將耗費大量的時間。步驟S2051至S2079係用以寫入垂直錯誤修正碼至指定的儲存單元10[q][p]。當處理單元610判斷訊息計數器的值大於或等於閥值後(步驟S2041中”是”的路徑),將變數p加一(步驟S2051)。接著,判斷此獨立磁碟冗餘陣列群組的垂直錯誤修正碼是否已產生過(步驟S2053),是則讓儲存單元存取介面230[q]取得動態隨機存取記憶體620中暫存的先前計算結果,並寫入至儲存單元10[q][p](步驟S2061至S2068);否則,讓儲存單元存取介面230[q]取得磁碟陣列編碼單元630的編碼結果,並寫入至儲存單元10[q][p](步驟S2071至S2079)。 Since the vertical error correction code is also to be written three times to be stable, the embodiment of the present invention provides a program for temporarily storing the first generated vertical error correction code in the dynamic random access memory 620, and subsequently re- The vertical error correction code that has been generated is directly retrieved from the dynamic random access memory 620 at the time of writing without recalculation. For example, the data placement of the independent disk redundancy array group using the RS (96, 93) error correction code shown in FIG. 18B is taken as an example. In another embodiment, when the disk array coding unit 630 is to be generated corresponding to the storage. When the vertical error correction code of the word line WL1 of the cell 10[3][3] is reloaded from the dynamic random access memory 620 into the word lines WL0 and WL1 to be stored in the 16 memory cells. To generate a vertical error correction code, however, this will take a lot of time. Steps S2051 to S2079 are for writing a vertical error correction code to the specified storage unit 10[ q ][ p ]. When the processing unit 610 determines that the value of the message counter is greater than or equal to the threshold (the path of YES in step S2041), the variable p is incremented by one (step S2051). Then, it is determined whether the vertical error correction code of the independent disk redundancy array group has been generated (step S2053), and the storage unit access interface 230[ q ] is temporarily stored in the dynamic random access memory 620. The result is previously calculated and written to the storage unit 10[ q ][ p ] (steps S2061 to S2068); otherwise, the storage unit access interface 230[ q ] is taken to obtain the encoding result of the disk array encoding unit 630, and written To the storage unit 10[ q ][ p ] (steps S2071 to S2079).
如步驟S2071至S2079所示的迴圈會反覆執行直到所有由磁碟陣列編碼單元630所產生的垂直錯誤修正碼都寫入至指定的儲存單元中。詳細而言,處理單元610控制多工器640用以耦接磁碟陣列編碼單元630與緩存器650(步驟S2071),並指示磁碟陣列編碼單元630將三頁的垂直錯誤修正碼經由多工器640輸出至緩存器650,並且指示直接記憶體存取控制器621將磁碟陣列編碼單元630中之緩存器(未顯示)的計算結果儲存至動態隨機存取記憶體620中(步驟S2073)。接著,處理單元610控制仲裁單元660以讀取緩存器650中的值並指示儲存單元存取介面230[q]寫入至儲存單元10[q][p]中的指定字元線(步驟 S2075)。處理單元610將錯誤修正碼計數器加三後(步驟S2076),判斷錯誤修正碼計數器的值是否大於或等於閥值,例如,常數l(步驟S2077)。若是,則繼續進行步驟S2069;否則,將變數p加一後(步驟S2079),回到步驟S2073,用以寫入獨立磁碟冗餘陣列群組中未完成的垂直錯誤修正碼。 The loops as shown in steps S2071 to S2079 are repeatedly executed until all the vertical error correction codes generated by the disk array encoding unit 630 are written into the designated storage unit. In detail, the processing unit 610 controls the multiplexer 640 to couple the disk array encoding unit 630 and the buffer 650 (step S2071), and instructs the disk array encoding unit 630 to perform the three-page vertical error correction code via multiplexing. The 640 is output to the buffer 650, and instructs the direct memory access controller 621 to store the calculation result of the buffer (not shown) in the disk array encoding unit 630 into the dynamic random access memory 620 (step S2073). . Next, the processing unit 610 controls the arbitration unit 660 to read the value in the buffer 650 and instruct the storage unit access interface 230[ q ] to write to the specified word line in the storage unit 10[ q ][ p ] (step S2075) ). The processing unit 610 adds three to the error correction code counter (step S2076), and determines whether the value of the error correction code counter is greater than or equal to a threshold value, for example, a constant l (step S2077). If yes, proceed to step S2069; otherwise, after the variable p is incremented (step S2079), return to step S2073 for writing the unfinished vertical error correction code in the independent disk redundancy array group.
如步驟S2061至S2068所示的迴圈會反覆執行直到所有於動態隨機存取記憶體620所暫存的垂直錯誤修正碼都寫入至指定的儲存單元中。詳細而言,處理單元610指示直接記憶體存取控制器621將動態隨機存取記憶體620中暫存的三頁垂直錯誤修正碼經由多工器640儲存至緩存器650(步驟S2061)。接著,處理單元610控制仲裁單元660以指示儲存單元存取介面230[q]讀取緩存器650中的值並寫入至儲存單元10[q][p]中的指定字元線(步驟S2063)。處理單元610將錯誤修正碼計數器加三後(步驟S2065),判斷錯誤修正碼計數器的值是否大於或等於閥值,例如,l(步驟S2067)。若是,則繼續進行步驟S2069;否則,將變數p加一後(步驟S2068),回到步驟S2061,用以寫入獨立磁碟冗餘陣列群組中未完成的垂直錯誤修正碼。最後,處理器單元610判斷是否完成所有的寫入作業(步驟S2069),是則結束整個資料寫入處理;否則控制多工器640用以耦接動態隨機存取記憶體620與緩存器650後(步驟S2080),回到步驟S2021,用以繼續進行下一個獨立磁碟冗餘陣列群組的資料寫入作業。步驟S2033、S2063與S2075的技術細節可參考第8圖的說明。 The loops shown in steps S2061 to S2068 are repeatedly executed until all the vertical error correction codes temporarily stored in the DRAM 620 are written to the designated storage unit. In detail, the processing unit 610 instructs the direct memory access controller 621 to store the three-page vertical error correction code temporarily stored in the dynamic random access memory 620 to the buffer 650 via the multiplexer 640 (step S2061). Next, the processing unit 610 controls the arbitration unit 660 to instruct the storage unit access interface 230[ q ] to read the value in the buffer 650 and write to the specified word line in the storage unit 10[ q ][ p ] (step S2063) ). The processing unit 610 adds three to the error correction code counter (step S2065), and determines whether the value of the error correction code counter is greater than or equal to a threshold value, for example, l (step S2067). If yes, proceed to step S2069; otherwise, after the variable p is incremented (step S2068), return to step S2061 for writing the unfinished vertical error correction code in the independent disk redundancy array group. Finally, the processor unit 610 determines whether all the write operations are completed (step S2069), and then ends the entire data write process; otherwise, the control multiplexer 640 is coupled to the dynamic random access memory 620 and the buffer 650. (Step S2080), returning to step S2021, the data writing operation of the next independent disk redundancy array group is continued. The technical details of steps S2033, S2063 and S2075 can be referred to the description of FIG.
雖然第1至3圖、第6圖、第9圖及第12圖中包含了 以上描述的元件,但不排除在不違反發明的精神下,使用更多其他的附加元件,已達成更佳的技術效果。此外,雖然第7A至7B圖、第8圖、第10至11圖、第14至15圖以及第20A至20D圖的流程圖採用指定的順序來執行,但是在不違法發明精神的情況下,熟習此技藝人士可以在達到相同效果的前提下,修改這些步驟間的順序,所以,本發明並不侷限於僅使用如上所述的順序。此外,熟習此技藝人士亦可以將若干步驟整合為一個步驟,或者是除了這些步驟外,循序或平行地執行更多步驟,本發明亦不因此而侷限。 Although it is included in Figures 1 to 3, Figure 6, Figure 9, and Figure 12 The components described above, but do not exclude the use of more additional components without departing from the spirit of the invention, have achieved better technical results. Further, although the flowcharts of FIGS. 7A to 7B, 8 and 10 to 11, 14 to 15 and 20A to 20D are executed in a specified order, without the spirit of the invention, Those skilled in the art can modify the order among these steps while achieving the same effect, and therefore, the present invention is not limited to the use of only the order as described above. In addition, those skilled in the art may also integrate several steps into one step, or in addition to these steps, performing more steps sequentially or in parallel, and the present invention is not limited thereby.
雖然本發明使用以上實施例進行說明,但需要注意的是,這些描述並非用以限縮本發明。相反地,此發明涵蓋了熟習此技藝人士顯而易見的修改與相似設置。所以,申請權利要求範圍須以最寬廣的方式解釋來包含所有顯而易見的修改與相似設置。 Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements that are apparent to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest form to include all obvious modifications and similar arrangements.
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TW201603047A (en) | 2016-01-16 |
TW201508772A (en) | 2015-03-01 |
TW201508757A (en) | 2015-03-01 |
TWI515749B (en) | 2016-01-01 |
TW201724101A (en) | 2017-07-01 |
TW201508758A (en) | 2015-03-01 |
TWI553649B (en) | 2016-10-11 |
KR101677534B1 (en) | 2016-11-18 |
TWI530958B (en) | 2016-04-21 |
TW201724100A (en) | 2017-07-01 |
TW201508756A (en) | 2015-03-01 |
TWI588843B (en) | 2017-06-21 |
TWI552160B (en) | 2016-10-01 |
TWI553656B (en) | 2016-10-11 |
TWI646553B (en) | 2019-01-01 |
KR20150140621A (en) | 2015-12-16 |
TW201508774A (en) | 2015-03-01 |
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