TWI647744B - Method to grow thin epitaxial films at low temperature - Google Patents

Method to grow thin epitaxial films at low temperature Download PDF

Info

Publication number
TWI647744B
TWI647744B TW106117147A TW106117147A TWI647744B TW I647744 B TWI647744 B TW I647744B TW 106117147 A TW106117147 A TW 106117147A TW 106117147 A TW106117147 A TW 106117147A TW I647744 B TWI647744 B TW I647744B
Authority
TW
Taiwan
Prior art keywords
precursor gas
epitaxial film
seconds
facet
gas
Prior art date
Application number
TW106117147A
Other languages
Chinese (zh)
Other versions
TW201735117A (en
Inventor
督比阿布希雪克
仲華
王振宇
李學斌
黃奕樵
諸紹芳
Original Assignee
美商應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商應用材料股份有限公司 filed Critical 美商應用材料股份有限公司
Publication of TW201735117A publication Critical patent/TW201735117A/en
Application granted granted Critical
Publication of TWI647744B publication Critical patent/TWI647744B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02516—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

Abstract

本發明揭露的實施一般係關於磊晶薄膜上的矽材料的磊晶成長之方法。在一個實施中，該方法包括於半導體片（fin）上形成磊晶薄膜，其中磊晶薄膜包括具有第一刻面與第二刻面的頂表面，以及藉由在約375°C至約450°C的溫度與約5Torr至約20Torr的腔室壓力處將頂表面交替暴露於第一前驅物氣體與第二前驅物氣體而至少在磊晶薄膜的頂表面上形成磊晶層，第一前驅物氣體包含一或多個矽烷，第二前驅物氣體包含一或多個氯化矽烷。The practice disclosed herein is generally directed to a method of epitaxial growth of tantalum material on an epitaxial film. In one implementation, the method includes forming an epitaxial film on a semiconductor fin, wherein the epitaxial film comprises a top surface having a first facet and a second facet, and by at about 375 ° C to about 450 The top surface is alternately exposed to the first precursor gas and the second precursor gas at a temperature of ° C and a chamber pressure of about 5 Torr to about 20 Torr to form an epitaxial layer on at least the top surface of the epitaxial film, the first precursor The gas comprises one or more decanes and the second precursor gas comprises one or more decanes.

Description

在低溫下生長薄磊晶膜的方法Method for growing thin epitaxial film at low temperature

本發明揭露的實施一般係關於半導體製程與裝置的領域，更特定言之，係關於用於矽材料在磊晶薄膜上磊晶成長的方法。The presently disclosed embodiments are generally directed to the field of semiconductor processes and devices, and more particularly to methods for epitaxial growth of germanium materials on epitaxial films.

隨著對於下一代裝置的電路密度增加，互連件（如穿孔、溝槽、接觸件、閘極結構與其他特徵）的寬度以及於其間的介電材料減小至22nm或更小的尺寸，但是介電層的厚度保持實質不變，而有特徵的深寬比（aspect ratio）增加的結果。近來，互補式金屬氧化物半導體（CMOS）FinFET裝置已經廣泛地用於許多邏輯與其他應用中並整合入半導體裝置的各式不同類型。As the circuit density for next-generation devices increases, the width of interconnects (such as vias, trenches, contacts, gate structures, and other features) and the dielectric material therebetween are reduced to 22 nm or less. However, the thickness of the dielectric layer remains substantially unchanged, with the result that the characteristic aspect ratio increases. Recently, complementary metal oxide semiconductor (CMOS) FinFET devices have been widely used in many different types of logic and other applications and integrated into semiconductor devices.

FinFET裝置通常包括帶有高深寬比的半導體片（fin），其中用於電晶體的通道與源極/汲極區域於其上形成。利用通道與源極/汲極區域的增加之表面積的優勢而接著於片（fin）裝置的部分的側之上且沿著片裝置的部分的側形成閘極電極而產生更快、更可靠的且更好控制的半導體電晶體裝置。FinFETs的進一步優勢包括減少短通道效應以及提供更高的電流流動。FinFET devices typically include a semiconductor fin with a high aspect ratio in which the channel and source/drain regions for the transistor are formed. A faster, more reliable generation of gate electrodes over the side of the portion of the fin device and along the side of the portion of the sheet device, taking advantage of the increased surface area of the channel and source/drain regions And a better controlled semiconductor transistor device. Further advantages of FinFETs include reduced short channel effects and higher current flow.

為了改善電晶體效能，應力源（stressor）材料可填充源極/汲極區域，且該應力源材料可藉由磊晶而於源極/汲極區域中成長。磊晶薄膜由{111}平面刻面（facet）且沿著電晶體通道方向而具有金剛石形狀。隨著電晶體的縮減，對於形成FinFET的改善方法總是有所需求。To improve transistor performance, a stressor material can fill the source/drain regions, and the stressor material can be grown in the source/drain regions by epitaxy. The epitaxial film has a diamond shape from the {111} plane facet and along the transistor channel direction. As transistor shrinks, there is always a need for improved methods of forming FinFETs.

本發明揭露的實施一般係關於用於矽材料在磊晶薄膜上磊晶成長的方法。在一個實施中，該方法包括於半導體片上形成磊晶薄膜，該半導體片在該基板上形成，其中磊晶薄膜包含具有第一刻面與第二刻面的頂表面，以及藉由在約375°C至約450°C的溫度與約5 Torr至約20 Torr的腔室壓力處將頂表面交替暴露於第一前驅物氣體與第二前驅物氣體而至少在磊晶薄膜的頂表面上形成磊晶層，該第一前驅物氣體包含一或多個矽烷，該第二前驅物氣體包含一或多個氯化矽烷。The practice disclosed herein is generally directed to a method for epitaxial growth of germanium materials on epitaxial films. In one implementation, the method includes forming an epitaxial film on a semiconductor wafer, the semiconductor wafer being formed on the substrate, wherein the epitaxial film comprises a top surface having a first facet and a second facet, and by about 375 The top surface is alternately exposed to the first precursor gas and the second precursor gas at a temperature of from about °C to about 450 ° C and a chamber pressure of from about 5 Torr to about 20 Torr to form at least a top surface of the epitaxial film. An epitaxial layer, the first precursor gas comprising one or more decanes, the second precursor gas comprising one or more decanes.

在另一個實施中，該方法包括將半導體結構裝載入處理腔室中，其中半導體結構包含基板、於基板上形成的複數個半導體片以及設置於基板上的半導體片之間的介電材料，於複數個半導體片上形成磊晶薄膜，其中各磊晶薄膜包括具有第一刻面與第二刻面之頂表面，及藉由在小於約450°C的溫度與約5 Torr至約20 Torr的腔室壓力處將頂表面交替暴露於第一前驅物氣體與第二前驅物氣體而至少在磊晶薄膜的頂表面上形成矽層，該第一前驅物氣體包含一或多個矽烷，該第二前驅物氣體包含一或多個氯化矽烷。In another implementation, the method includes loading a semiconductor structure into a processing chamber, wherein the semiconductor structure includes a substrate, a plurality of semiconductor wafers formed on the substrate, and a dielectric material disposed between the semiconductor wafers on the substrate, Forming an epitaxial film on the plurality of semiconductor wafers, wherein each of the epitaxial films comprises a top surface having a first facet and a second facet, and by a temperature of less than about 450 ° C and from about 5 Torr to about 20 Torr The chamber pressure alternately exposes the top surface to the first precursor gas and the second precursor gas to form a germanium layer on at least the top surface of the epitaxial film, the first precursor gas comprising one or more germanes, the first The second precursor gas contains one or more decanes.

在又另一個實施中，該方法包括（a）於半導體片上形成磊晶薄膜，該半導體片於該基板上形成，其中各磊晶薄膜包括具有第一刻面與第二刻面之頂表面，（b）在約450°C溫度與約5 Torr至約20 Torr的腔室壓力處將磊晶薄膜暴露於第一前驅物氣體，該第一前驅物氣體包含矽烷（SiH4 ）或乙矽烷（Si2 H6 ），（c）在（b）步驟之後，用脈衝輸送第一前驅物氣體一第一周期時間，（d）在（c）步驟之後，將淨化氣體引入處理腔室中，（e）在（d）步驟之後，在小於約450°C的溫度與約5 Torr至約20 Torr的腔室壓力處將磊晶薄膜暴露於第二前驅物氣體，該第二前驅物氣體包含氯化矽烷，（f）在（e）步驟之後，用脈衝輸送第一前驅物氣體一第二周期時間，以及（g）在（f）步驟之後，將淨化氣體引入處理腔室中。在各式示範例中，該方法進一步包括重複（b）至（g）步驟約10個循環或300個循環直至所需的矽層厚度成長於磊晶薄膜的頂表面上。In still another implementation, the method includes (a) forming an epitaxial film on the semiconductor wafer, the semiconductor wafer being formed on the substrate, wherein each of the epitaxial films includes a top surface having a first facet and a second facet, (b) exposing the epitaxial film to a first precursor gas at a temperature of about 450 ° C and a chamber pressure of from about 5 Torr to about 20 Torr, the first precursor gas comprising decane (SiH 4 ) or acetane ( Si 2 H 6 ), (c) after the step (b), pulsing the first precursor gas for a first cycle time, (d) after the step (c), introducing the purge gas into the processing chamber, e) after the step (d), exposing the epitaxial film to a second precursor gas at a temperature of less than about 450 ° C and a chamber pressure of from about 5 Torr to about 20 Torr, the second precursor gas comprising chlorine The decane, (f) after the step (e), pulsing the first precursor gas for a second cycle time, and (g) after the step (f), introducing the purge gas into the processing chamber. In various exemplary embodiments, the method further comprises repeating steps (b) through (g) for about 10 cycles or 300 cycles until the desired thickness of the tantalum layer grows on the top surface of the epitaxial film.

圖1係根據本發明揭露實施的用於製造半導體結構之示範方法的流程圖。圖2A至2C繪示在根據圖1的流程圖的製造某些階段期間簡化的半導體結構之截面圖。本發明所屬領域具有通常知識者將進一步了解用於形成半導體裝置與相關結構的全部處理過程未繪示於圖式中或於此發明中描述。反之，為求簡單清楚，只繪示與描述了對於本發明揭露獨特或對於了解本發明揭露必要之用於形成半導體裝置與相關結構的某些處理過程。此外，雖然各式步驟繪示於圖式中及描述於本說明書中，但是沒有表示此等步驟的順序或中間步驟存在與否有所限制。除非明確指示，否則所繪示與描述的步驟僅用作解釋用途依序繪示與描述，如果沒完全實施的話，不排除個別的步驟實際上以同時或重疊的方式至少部分地施行之可能性。1 is a flow diagram of an exemplary method for fabricating a semiconductor structure in accordance with an embodiment of the present disclosure. 2A through 2C are cross-sectional views of a simplified semiconductor structure during certain stages of fabrication in accordance with the flow chart of FIG. 1. It will be apparent to those skilled in the art that the entire process for forming a semiconductor device and related structures is not shown in the drawings or described in the present invention. Conversely, for the sake of brevity and clarity, only certain processes for forming semiconductor devices and related structures that are unique to the present disclosure or necessary for understanding the present disclosure are shown and described. In addition, although various steps are illustrated in the drawings and described in the specification, there is no limitation in the presence or absence of the order or intermediate steps of the steps. Unless otherwise indicated, the illustrated and described steps are only shown and described for purposes of explanation only, and, if not fully implemented, the possibility that the individual steps are actually at least partially performed in a simultaneous or overlapping manner is not excluded. .

方法100在方塊102藉由將半導體結構200裝載入處理腔室而開始。半導體結構200包括基板202、複數個半導體片203（只顯示了兩個）以及設置於基板202上的半導體片203之間的介電材料206，如圖2A所示。處理腔室可係ALE（原子層磊晶）或ALD（原子層沈積）、CVD（化學氣相沈積）或電漿輔助處理技術領域中習知的任何適合的沈積處理腔室。The method 100 begins at block 102 by loading a semiconductor structure 200 into a processing chamber. The semiconductor structure 200 includes a substrate 202, a plurality of semiconductor wafers 203 (only two are shown), and a dielectric material 206 disposed between the semiconductor wafers 203 on the substrate 202, as shown in FIG. 2A. The processing chamber can be any suitable deposition processing chamber as is known in the art of ALE (atomic layer epitaxy) or ALD (atomic layer deposition), CVD (chemical vapor deposition) or plasma assisted processing.

本說明書所用術語「基板」意欲廣泛涵蓋可以在處理腔室中處理的任何物件。例如，基板202可係能夠具有材料沈積於其上的任何基板，如矽基板，例如矽（摻雜的或未摻雜的）、晶狀矽（如Si ＜100＞或Si ＜111＞）、氧化矽、應變矽、摻雜或未摻雜的多晶矽或類似物，鍺、III-V族化合物的基板，矽鍺（SiGe）基板，碳化矽鍺（SiGeC）基板，氧化矽鍺（SiGeO）基板，氮氧化矽鍺（SiGeON）基板，碳化矽（SiC）基板，碳氮化矽（SiCN）基板，碳氧化矽（SiCO），磊晶基板，矽上絕緣體（SOI）基板，碳摻雜氧化物，氮化矽，如液晶顯示器（LCD）的顯示基板，電漿顯示器，電致發光（EL）燈顯示器，太陽能陣列，太陽能板，發光二極管（LED）基板，圖案化或非圖案化的半導體晶圓，玻璃，藍寶石，或任何其它材料，例如金屬、金屬合金和其它導電材料。基板202可係平坦基板或圖案化基板。圖案化基板係包括在基板的處理表面中或上形成的電子特徵之基板。基板202可包括多個層或包括如部分製造的裝置（如電晶體、快閃記憶體裝置及其類似物）。The term "substrate" as used in this specification is intended to broadly encompass any item that can be processed in a processing chamber. For example, substrate 202 can be any substrate having a material deposited thereon, such as a germanium substrate, such as germanium (doped or undoped), crystalline germanium (eg, Si <100> or Si <111>), Cerium oxide, strained germanium, doped or undoped polysilicon or the like, substrate of germanium, III-V compound, germanium (SiGe) substrate, germanium carbide (SiGeC) substrate, germanium oxide (SiGeO) substrate , SiGeON substrate, SiC substrate, SiCN substrate, SiO2, epitaxial substrate, SOI substrate, carbon doped oxide , tantalum nitride, display substrate such as liquid crystal display (LCD), plasma display, electroluminescent (EL) lamp display, solar array, solar panel, light emitting diode (LED) substrate, patterned or unpatterned semiconductor crystal Round, glass, sapphire, or any other material such as metals, metal alloys, and other conductive materials. The substrate 202 can be a flat substrate or a patterned substrate. The patterned substrate is a substrate comprising electronic features formed in or on the processing surface of the substrate. Substrate 202 can include multiple layers or include devices such as partially fabricated devices such as transistors, flash memory devices, and the like.

在一個實施中，基板202係單晶體矽，如P摻雜矽。半導體片203可包括與基板202相同或不同的材料。在所示實施中，半導體片203與基板202由相同材料形成。介電材料206可形成隔離區域，如淺溝槽隔離（STI）區域，且可包括SiO、SiN、SiCN或任何適合的介電材料。In one implementation, the substrate 202 is a single crystal germanium, such as a P-doped germanium. The semiconductor wafer 203 may include the same or a different material than the substrate 202. In the illustrated implementation, the semiconductor wafer 203 and the substrate 202 are formed of the same material. Dielectric material 206 can form isolation regions, such as shallow trench isolation (STI) regions, and can include SiO, SiN, SiCN, or any suitable dielectric material.

半導體片203可實施在用於較後面階段中的FinFET電晶體的形成通道中。各半導體片203可包括第一部分204與第二部分205，第一部分204具有與介電材料206的表面209共面的表面207，第二部分205自第一部分204向上突出。第二部分205可作為源極或汲極區域的功能。因此，半導體結構200的頂表面包括一或多個半導體區域（即半導體片203的第一部分204與（或）第二部分205）以及一或多個介電區域（即介電材料206）。The semiconductor wafer 203 can be implemented in a formation channel for a FinFET transistor in a later stage. Each semiconductor wafer 203 can include a first portion 204 having a surface 207 that is coplanar with the surface 209 of the dielectric material 206 and a second portion 205 that protrudes upwardly from the first portion 204. The second portion 205 can function as a source or drain region. Thus, the top surface of semiconductor structure 200 includes one or more semiconductor regions (ie, first portion 204 and/or second portion 205 of semiconductor wafer 203) and one or more dielectric regions (ie, dielectric material 206).

在方塊104，磊晶應力源薄膜214、215於第二部分205（即源極/汲極區域）上的各半導體片203上成長以改善電晶體效能。磊晶應力源薄膜214、215可係源極或汲極區域的部份。磊晶應力源薄膜214、215可密封或覆蓋半導體片203的第二部分205所暴露的表面，如圖2A所示。或者，半導體片203的第二部分205可被移除且磊晶應力源薄膜214、215可於半導體片203的第一部分204上形成。At block 104, epitaxial stressor films 214, 215 are grown on respective semiconductor wafers 203 on second portion 205 (i.e., source/drain regions) to improve transistor performance. The epitaxial stressor films 214, 215 can be part of the source or drain regions. The epitaxial stressor films 214, 215 may seal or cover the exposed surface of the second portion 205 of the semiconductor wafer 203, as shown in Figure 2A. Alternatively, the second portion 205 of the semiconductor wafer 203 can be removed and the epitaxial stressor films 214, 215 can be formed on the first portion 204 of the semiconductor wafer 203.

磊晶應力源薄膜214、215可包括Si:P、SiGe、SiGe:B、Si:CP或其他適合的半導體材料。在一個實施中，磊晶應力源薄膜214、215包括SiGe材料。在某些應用中，其中需要高濃度的鍺，例如用於導電節點先進7nm及更進一步中使用的pMOS源極與汲極材料，在矽中的鍺之濃度可係在約30%之上，如約45%或更多，如約70%至約100%。The epitaxial stressor films 214, 215 may comprise Si:P, SiGe, SiGe:B, Si:CP or other suitable semiconductor materials. In one implementation, the epitaxial stressor films 214, 215 comprise a SiGe material. In some applications, where high concentrations of germanium are required, such as pMOS source and drain materials for advanced 7 nm and further use in conductive nodes, the concentration of germanium in germanium can be above about 30%. For example, about 45% or more, such as about 70% to about 100%.

磊晶應力源薄膜214、215可使用選擇性沈積處理形成，而使得磊晶應力源薄膜214、215於半導體片203上成長而不是在介電材料206上成長。生成的磊晶應力源薄膜214可具有單晶體結構。可藉由將蝕刻劑與前驅物氣體共同流入沈積腔室而達成選擇性沈積處理。蝕刻劑的示範例可係HCl、Cl2 或任何適合的鹵素氣體。前驅物氣體可包括任何適合的含矽氣體，如矽烷、乙矽烷、有機矽烷或鹵化矽烷，以及任何合適的含鍺氣體，如鍺烷。The epitaxial stressor films 214, 215 can be formed using a selective deposition process such that the epitaxial stressor films 214, 215 grow on the semiconductor wafer 203 rather than growing over the dielectric material 206. The resulting epitaxial stressor film 214 may have a single crystal structure. The selective deposition process can be achieved by flowing the etchant together with the precursor gas into the deposition chamber. An example of an etchant can be HCl, Cl 2 or any suitable halogen gas. The precursor gas can include any suitable helium-containing gas, such as decane, ethane, organodecane or decane, and any suitable helium-containing gas, such as decane.

磊晶應力源薄膜214、215可於半導體片203上磊晶成長，且由於在不同表面平面上的不同成長速率，刻面經形成以導致當沿著電晶體通道方向（該通道沿著半導體片203的頂與相對側壁延伸）觀察刻面時，磊晶應力源薄膜214、215具有金剛石形狀。磊晶應力源薄膜214、215由{111}平面刻面、固定在頂角落與側壁角落處。例如，磊晶應力源薄膜214可包括複數個刻面216、218、220、222（為求清楚，半導體片203中只有一個標示於圖2A中）。刻面216、218可接觸半導體片203。刻面216與刻面220可互相接觸，且角（corner）224可在接觸點處形成。刻面218與刻面222可互相接觸，且角226可在接觸點處形成。刻面220與刻面222可互相接觸，且角228可在接觸點處形成。The epitaxial stressor films 214, 215 can be epitaxially grown on the semiconductor wafer 203, and due to different growth rates on different surface planes, the facets are formed to result in a direction along the transistor channel (the channel along the semiconductor wafer) The top of the 203 and the opposite sidewalls extend. When the facets are viewed, the epitaxial stressor films 214, 215 have a diamond shape. The epitaxial stressor films 214, 215 are faceted by the {111} plane, fixed at the top corners and the corners of the sidewalls. For example, the epitaxial stressor film 214 can include a plurality of facets 216, 218, 220, 222 (for clarity, only one of the semiconductor wafers 203 is labeled in FIG. 2A). The facets 216, 218 can contact the semiconductor wafer 203. Facet 216 and facet 220 may be in contact with each other, and corner 224 may be formed at the point of contact. Facet 218 and facet 222 may be in contact with each other, and corner 226 may be formed at the point of contact. Facet 220 and facet 222 may be in contact with each other, and corner 228 may be formed at the point of contact.

在方塊106，磊晶應力源薄膜214、215的部分可選擇性地在側向維度上移除。具體言之，磊晶應力源薄膜214的相對側上的部分經移除以增加半導體片上的磊晶應力源薄膜214與鄰近半導體片上成長的磊晶應力源薄膜215之間的距離。接觸點處的角228的部分可選擇性地被移除，如圖2B所示。隨著電晶體縮減，片間距（fin pitch，兩鄰近片之間的距離）變得更小。因此，源極/汲極上成長的磊晶應力源薄膜可以被碰觸（touched）或合併（merged）。一旦合併產生，（電晶體通道上的應變上的）應力源的效應減小且缺陷容易在合併區域的連接點處形成，其對半導體結構的效能以及電晶體效能有負面影響。由於鄰近磊晶薄膜之間的距離增加，而防止磊晶應力源薄膜214與鄰近應力源薄膜215互相碰觸或合併。可藉由蝕刻、研磨或其他適合的移除處理而達成磊晶應力源薄膜的部分之選擇性移除。蝕刻處理可在用於沈積的相同腔室中實施，或在分開但整合的腔室中實施。At block 106, portions of the epitaxial stressor films 214, 215 are selectively removable in the lateral dimension. In particular, portions of the opposite sides of the epitaxial stressor film 214 are removed to increase the distance between the epitaxial stressor film 214 on the semiconductor wafer and the epitaxial stressor film 215 grown on adjacent semiconductor wafers. Portions of the corners 228 at the point of contact are selectively removed, as shown in Figure 2B. As the transistor shrinks, the fin pitch (distance between two adjacent patches) becomes smaller. Therefore, the epitaxial stressor film grown on the source/drain can be touched or merged. Once merged, the effect of the stressor (on strain on the transistor channel) is reduced and defects are easily formed at the junctions of the merged regions, which have a negative impact on the performance of the semiconductor structure and on transistor efficacy. The epitaxial stressor film 214 and the adjacent stressor film 215 are prevented from touching or combining with each other due to an increase in the distance between adjacent epitaxial films. Selective removal of portions of the epitaxial stressor film can be achieved by etching, grinding, or other suitable removal process. The etching process can be performed in the same chamber used for deposition, or in a separate but integrated chamber.

在方塊108，矽帽層217、219一致地於磊晶應力源薄膜214、215上分別形成以鈍化磊晶應力源薄膜214、215，使得後續的層（如閘極介電，如二氧化矽、摻雜碳的矽氧化物、矽鍺氧化物、或高k介電材料）可以輕易地於半導體片203的部分上形成。矽帽層可在應力源薄膜214、215的至少頂表面（即刻面220、222）上形成。矽帽層217、219可藉由化學氣相沈積（CVD）處理、原子層磊晶（ALE）或原子層沈積（ALD）處理而成長。在一個實施中，矽帽層217、219由ALE處理形成。ALE係一種周期性沈積處理，其施用化學吸附（chemisorption）技術以將前驅物分子依順序周期傳送於加熱的基板表面上。在各式實施中，磊晶應力源薄膜214、215依序暴露於第一前驅物氣體、淨化氣體、第二前驅物氣體與淨化氣體。第一與第二前驅物氣體反應以形成化學化合物而形成薄膜於磊晶應力源薄膜214、215的表面上。重複此周期以一層一層的方式成長矽帽層217、219直到所需的厚度達到。在一個實施中，其中下面的SiGe磊晶應力源薄膜214、215係約3-6nm厚度，矽帽層217、219可具有約1nm至約5nm的厚度，例如約2nm至約3nm。矽帽層的沈積可於相同腔室中實施以用於沈積磊晶應力源薄膜214、215，或是在分開但整合的腔室中實施。At block 108, the cap layers 217, 219 are uniformly formed on the epitaxial stressor films 214, 215, respectively, to passivate the epitaxial stressor films 214, 215 such that the subsequent layers (eg, gate dielectrics, such as cerium oxide) A carbon-doped tantalum oxide, tantalum oxide, or high-k dielectric material can be easily formed on a portion of the semiconductor wafer 203. A cap layer may be formed on at least the top surface (i.e., facets 220, 222) of the stressor films 214, 215. The cap layers 217, 219 can be grown by chemical vapor deposition (CVD) processing, atomic layer epitaxy (ALE) or atomic layer deposition (ALD) processing. In one implementation, the cap layers 217, 219 are formed by ALE processing. ALE is a periodic deposition process that applies a chemisorption technique to deliver precursor molecules sequentially onto a heated substrate surface. In various implementations, the epitaxial stressor films 214, 215 are sequentially exposed to the first precursor gas, the purge gas, the second precursor gas, and the purge gas. The first and second precursor gases react to form a chemical compound to form a film on the surface of the epitaxial stressor films 214, 215. This cycle is repeated to grow the cap layers 217, 219 layer by layer until the desired thickness is reached. In one implementation, wherein the underlying SiGe epitaxial stressor films 214, 215 are about 3-6 nm thick, the cap layers 217, 219 can have a thickness of from about 1 nm to about 5 nm, such as from about 2 nm to about 3 nm. The deposition of the cap layer can be performed in the same chamber for depositing the epitaxial stressor films 214, 215, or in separate but integrated chambers.

在各式實施中，第一前驅物氣體與第二前驅物氣體可係含矽氣體。適合的含矽氣體可包括矽烷、鹵化矽烷或有機矽烷中的一或多個。矽烷可包括矽烷（SiH4 ）與帶有經驗方程式Six H(2x+2) 的更高階的矽烷（higher silanes），如乙矽烷（Si2 H6 ）、丙矽烷（Si3 H8 ）與四矽烷（Si4 H10 ），或其他更高階的矽烷，如聚氯矽烷。鹵化矽烷可包括帶有經驗方程式的化合物 X’ y Six H(2x+2-y) ，其中X’ = F, Cl, Br 或I，如六氯二矽烷（Si2 Cl6 ）、四氯矽烷（SiCl4 ）、二氯矽烷（Cl2 SiH2 ）與三氯矽烷（Cl3 SiH）。有機矽烷可包括帶有經驗方程式Ry Six H(2x+2-y) 的化合物，其中R = 甲基、乙基、丙基或丁基，如甲基矽烷（(CH3 )SiH3 ）、二甲基矽烷（CH3 )2 SiH2 ）、乙基矽烷（CH3 CH2 )SiH3 ）、甲基二矽烷（CH3)Si2H5）、二甲基二矽烷（(CH3)2Si2H4）與六甲基二矽烷（(CH3 )6 Si2 ）。合適的含鍺氣體可包括但不局限於鍺烷（GeH4 ）、二鍺烷（Ge2 H6 ）、三鍺烷（Ge3 H8 ）或以上其中兩個或更多之組合。在某些實施中，四乙氧基矽烷（TEOS）亦可用作第一或第二前驅物氣體。In various implementations, the first precursor gas and the second precursor gas may be helium containing gases. Suitable helium-containing gases can include one or more of decane, decane or organodecane. The decane may include decane (SiH 4 ) and higher silanes with the empirical equation Si x H (2x+2 ), such as ethane (Si 2 H 6 ), propane (Si 3 H 8 ) and Tetra-decane (Si 4 H 10 ), or other higher order decane, such as polychlorin. The halogenated decane may comprise a compound X ' y Si x H (2x+2-y) with an empirical equation, wherein X ' = F, Cl, Br or I, such as hexachlorodioxane (Si 2 Cl 6 ), tetrachloro Decane (SiCl 4 ), dichlorodecane (Cl 2 SiH 2 ) and trichlorodecane (Cl 3 SiH). The organodecane may comprise a compound having the empirical equation R y Si x H (2x+2-y) , wherein R = methyl, ethyl, propyl or butyl, such as methyl decane ((CH 3 )SiH 3 ) , dimethyl decane (CH 3 ) 2 SiH 2 ), ethyl decane (CH 3 CH 2 )SiH 3 ), methyl dioxane (CH 3 ) Si 2 H 5 ), dimethyl dioxane ((CH 3 ) 2 Si 2 H 4 ) and Methyldioxane ((CH 3 ) 6 Si 2 ). Suitable ruthenium containing gases may include, but are not limited to, decane (GeH 4 ), dioxane (Ge 2 H 6 ), trioxane (Ge 3 H 8 ), or a combination of two or more thereof. In certain embodiments, tetraethoxy decane (TEOS) can also be used as the first or second precursor gas.

在一個示範的實施中，第一前驅物氣體係矽基前驅物氣體，如矽烷（SiH4 ）與帶有經驗方程式Six H(2x+2) 的更高階的矽烷如乙矽烷（Si2 H6 ）、丙矽烷（Si3 H8 ）或四矽烷（Si4 H10 ）。如需要的話，第一前驅物氣體可包括本發明所述的矽基前驅物氣體中的一或多個。第二前驅物氣體係鹵化矽烷，例如氯化矽烷，如一氯矽烷（SiH3 Cl, MCS）、二氯矽烷（Si2 H2 Cl2 , DCS）、三氯矽烷（SiHCl3 , TCS）、六氯二矽烷（Si2 Cl6 , HCDS）、八氯三矽烷（Si3 Cl8 , OCTS）或四氯化矽（STC）。如需要的話，第二前驅物氣體可包括本發明所述的鹵化矽烷中的一或多個。合適的淨化氣體可包括氦、氬、氮、氫、形成氣體或以上各者之組合。In an exemplary implementation, the first precursor gas system sulfhydryl precursor gas, such as decane (SiH 4 ), and a higher order decane such as ethane (Si 2 H) with the empirical equation Si x H (2x+2) 6 ), propane (Si 3 H 8 ) or tetradecane (Si 4 H 10 ). If desired, the first precursor gas can include one or more of the sulfhydryl precursor gases of the present invention. a second precursor gas system, a halogenated decane, such as a decane chloride such as monochloromethane (SiH 3 Cl, MCS), dichlorosilane (Si 2 H 2 Cl 2 , DCS), trichlorodecane (SiHCl 3 , TCS), six Chlorodioxane (Si 2 Cl 6 , HCDS), octachlorotrioxane (Si 3 Cl 8 , OCTS) or ruthenium tetrachloride (STC). If desired, the second precursor gas can include one or more of the halogenated decanes described herein. Suitable purge gases can include helium, argon, nitrogen, hydrogen, forming gases, or a combination of the above.

在使用ALE處理的一個示範例中，第一前驅物氣體係乙矽烷而第二前驅物氣體係HCDS。ALE處理在約350°C至約550°C的溫度範圍（如375°C至約450°C，如約425°C）以及約1 Torr至約40 Torr（如約5 Torr至約20 Torr，例如約10 Torr）腔室壓力處實施。在下方磊晶應力源薄膜214、215於矽中具有高濃度Ge（如30%或以上，如40%或以上）的情況下，使用較低沈積溫度（如約425°C或更低，如350°C至約375°C）可係有優勢的，以避免磊晶應力源薄膜的變形。In one example using ALE processing, the first precursor gas system is decane and the second precursor gas system is HCDS. The ALE treatment is at a temperature ranging from about 350 ° C to about 550 ° C (eg, 375 ° C to about 450 ° C, such as about 425 ° C) and from about 1 Torr to about 40 Torr (eg, from about 5 Torr to about 20 Torr, For example, about 10 Torr) is performed at the chamber pressure. In the case where the lower epitaxial stressor films 214, 215 have a high concentration of Ge (e.g., 30% or more, such as 40% or more) in the crucible, a lower deposition temperature (e.g., about 425 ° C or lower, such as 350 ° C to about 375 ° C) can be advantageous to avoid deformation of the epitaxial stressor film.

在操作中，磊晶應力源薄膜214、215暴露於使用乙矽烷的第一前驅物氣體。第一前驅物氣體以約5 sccm至約35 sccm範圍的流動速率被引入處理腔室中，如約10 sccm至約25 sccm，例如約20 sccm。接著用脈衝輸送（pulse）第一前驅物氣體約5秒至約25秒，如約15秒。下一步，淨化氣體以約5 sccm至約25 sccm範圍的流動速率被引入處理腔室中，如約10 sccm至約20 sccm，例如約15 sccm。下一步，磊晶應力源薄膜214、215暴露於使用HCDS的第二前驅物氣體。第二前驅物氣體以約250 sccm至約550 sccm範圍的流動速率被引入處理腔室中，如約350 sccm至約450 sccm，例如約400 sccm。第二前驅物氣體稀釋於氮氣或氫氣載體氣體中，氮氣或氫氣載體氣體以約1 SLM至約30 SLM的流動速率流動入處理腔室中，如約3 SLM。接著用脈衝輸送（pulse）第二前驅物氣體約5秒至約25秒，如約15秒。之後，淨化氣體以約5 sccm至約25 sccm範圍的流動速率被引入處理腔室中，如約10 sccm至約20 sccm，例如約15 sccm。藉由上述處理狀況交替乙矽烷與HCDS而將矽帽層一致地（conformally）且均勻地成長於磊晶應力源薄膜上。加入六氯二矽烷（Si2 Cl6 , HCDS）而在表面處將-H配位基（ligand）換成Cl終端（termination）並在其上形成額外的矽層。此處理過程以約0.1Å/周期的成長速率重複約300個周期以達到所需的厚度。In operation, the epitaxial stressor films 214, 215 are exposed to a first precursor gas using acetane. The first precursor gas is introduced into the processing chamber at a flow rate ranging from about 5 sccm to about 35 sccm, such as from about 10 sccm to about 25 sccm, such as about 20 sccm. The first precursor gas is then pulsed for about 5 seconds to about 25 seconds, such as about 15 seconds. Next, the purge gas is introduced into the processing chamber at a flow rate ranging from about 5 sccm to about 25 sccm, such as from about 10 sccm to about 20 sccm, such as about 15 sccm. Next, the epitaxial stressor films 214, 215 are exposed to a second precursor gas using HCDS. The second precursor gas is introduced into the processing chamber at a flow rate ranging from about 250 sccm to about 550 sccm, such as from about 350 sccm to about 450 sccm, such as about 400 sccm. The second precursor gas is diluted in a nitrogen or hydrogen carrier gas, and the nitrogen or hydrogen carrier gas flows into the processing chamber at a flow rate of from about 1 SLM to about 30 SLM, such as about 3 SLM. The second precursor gas is then pulsed for about 5 seconds to about 25 seconds, such as about 15 seconds. Thereafter, the purge gas is introduced into the processing chamber at a flow rate ranging from about 5 sccm to about 25 sccm, such as from about 10 sccm to about 20 sccm, such as about 15 sccm. The ruthenium cap layer was uniformly and uniformly grown on the epitaxial stressor film by alternating acetane and HCDS by the above treatment conditions. Hexachlorodioxane (Si 2 Cl 6 , HCDS) was added to replace the -H ligand at the surface with a Cl termination and form an additional layer of ruthenium thereon. This process is repeated for about 300 cycles at a growth rate of about 0.1 Å/cycle to achieve the desired thickness.

在使用ALE處理的另一個示範例中，第一前驅物氣體仍係乙矽烷而第二前驅物氣體仍係HCDS。然而，調整為較長的脈衝時間（pulse time）。在此示範例中，ALE處理在約350°C至約550°C的溫度範圍（如約375°C至約450°C，例如約425°C）以及約1 Torr至約40 Torr（如約5 Torr至約20 Torr，例如約10 Torr）的腔室壓力處實施。在下方磊晶應力源薄膜214、215於矽中具有高濃度Ge（如30%或以上，如40%或以上）的情況下，使用較低沈積溫度（如約425°C或更低，如350°C至約375°C）可係有優勢的，以避免磊晶應力源薄膜的變形。In another example of processing using ALE, the first precursor gas is still ethane oxide and the second precursor gas is still HCDS. However, it is adjusted to a longer pulse time. In this example, the ALE treatment is in a temperature range of from about 350 ° C to about 550 ° C (eg, from about 375 ° C to about 450 ° C, such as about 425 ° C) and from about 1 Torr to about 40 Torr (eg, about It is carried out at a chamber pressure of 5 Torr to about 20 Torr, for example about 10 Torr. In the case where the lower epitaxial stressor films 214, 215 have a high concentration of Ge (e.g., 30% or more, such as 40% or more) in the crucible, a lower deposition temperature (e.g., about 425 ° C or lower, such as 350 ° C to about 375 ° C) can be advantageous to avoid deformation of the epitaxial stressor film.

在操作中，磊晶應力源薄膜214、215暴露於使用乙矽烷的第一前驅物氣體。第一前驅物氣體以約5 sccm至約35 sccm範圍的流動速率被引入處理腔室中，如約10 sccm至約25 sccm，例如約20 sccm。接著用脈衝輸送（pulse）第一前驅物氣體約350秒至約550秒，如約450秒。下一步，淨化氣體以約5 sccm至約25 sccm範圍的流動速率被引入處理腔室中，如約10 sccm至約20 sccm，例如約15 sccm。下一步，磊晶應力源薄膜214、215暴露於使用HCDS的第二前驅物氣體。第二前驅物氣體以約250 sccm至約550 sccm範圍的流動速率被引入處理腔室中，如約350 sccm至約450 sccm，例如約400 sccm。第二前驅物氣體稀釋於氮氣或氫氣載體氣體中，氮氣或氫氣載體氣體以約1 SLM至約30 SLM的流動速率流動入處理腔室中，如約3 SLM。接著用脈衝輸送（pulse）第二前驅物氣體約350秒至約550秒，如約450秒。之後，淨化氣體以約5 sccm至約25 sccm範圍的流動速率被引入處理腔室中，如約10 sccm至約20 sccm，例如約15 sccm。藉由上述處理狀況交替乙矽烷與HCDS而將一單層的矽一致地（conformally）且均勻地成長於磊晶應力源薄膜上。此處理過程以約0.1Å/周期的成長速率重複約10個周期以達到所需的厚度。In operation, the epitaxial stressor films 214, 215 are exposed to a first precursor gas using acetane. The first precursor gas is introduced into the processing chamber at a flow rate ranging from about 5 sccm to about 35 sccm, such as from about 10 sccm to about 25 sccm, such as about 20 sccm. The first precursor gas is then pulsed for about 350 seconds to about 550 seconds, such as about 450 seconds. Next, the purge gas is introduced into the processing chamber at a flow rate ranging from about 5 sccm to about 25 sccm, such as from about 10 sccm to about 20 sccm, such as about 15 sccm. Next, the epitaxial stressor films 214, 215 are exposed to a second precursor gas using HCDS. The second precursor gas is introduced into the processing chamber at a flow rate ranging from about 250 sccm to about 550 sccm, such as from about 350 sccm to about 450 sccm, such as about 400 sccm. The second precursor gas is diluted in a nitrogen or hydrogen carrier gas, and the nitrogen or hydrogen carrier gas flows into the processing chamber at a flow rate of from about 1 SLM to about 30 SLM, such as about 3 SLM. The second precursor gas is then pulsed for about 350 seconds to about 550 seconds, such as about 450 seconds. Thereafter, the purge gas is introduced into the processing chamber at a flow rate ranging from about 5 sccm to about 25 sccm, such as from about 10 sccm to about 20 sccm, such as about 15 sccm. A single layer of ruthenium is conformally and uniformly grown on the epitaxial stressor film by alternating acetane with HCDS by the above treatment conditions. This process is repeated for about 10 cycles at a growth rate of about 0.1 Å/cycle to achieve the desired thickness.

在使用ALE處理的又另一個示範例中，第一前驅物氣體係矽烷而第二前驅物氣體係HCDS。因為矽烷在半導體片203的側壁上顯示有較少的側向薄膜成長，所以觀察到矽烷在某些應用中是有優勢的。在此示範例中，ALE處理在約350°C至約550°C的溫度範圍（如375°C至約450°C，例如約425°C）以及約1 Torr至約40 Torr（如約5 Torr至約20 Torr，例如約10 Torr）的腔室壓力處實施。在下方磊晶應力源薄膜214、215於矽中具有高濃度Ge（如30%或以上，如40%或以上）的情況下，使用較低沈積溫度（如約425°C或更低，如350°C至約375°C）可係有優勢的，以避免磊晶應力源薄膜的變形。In yet another example of the use of ALE processing, the first precursor gas system decane and the second precursor gas system HCDS. Since decane shows less lateral film growth on the sidewalls of the semiconductor wafer 203, it has been observed that decane is advantageous in certain applications. In this example, the ALE is processed at a temperature ranging from about 350 ° C to about 550 ° C (eg, 375 ° C to about 450 ° C, such as about 425 ° C) and from about 1 Torr to about 40 Torr (eg, about 5 It is carried out at a chamber pressure of Torr to about 20 Torr, for example about 10 Torr. In the case where the lower epitaxial stressor films 214, 215 have a high concentration of Ge (e.g., 30% or more, such as 40% or more) in the crucible, a lower deposition temperature (e.g., about 425 ° C or lower, such as 350 ° C to about 375 ° C) can be advantageous to avoid deformation of the epitaxial stressor film.

在操作中，磊晶應力源薄膜214、215暴露於使用矽烷的第一前驅物氣體。第一前驅物氣體以約25 sccm至約55 sccm範圍的流動速率被引入處理腔室中，如約30 sccm至約45 sccm，例如約40 sccm。接著用脈衝輸送（pulse）第一前驅物氣體約650秒至約1200秒，如約900秒。下一步，淨化氣體以約5 sccm至約25 sccm範圍的流動速率被引入處理腔室中，如約10 sccm至約20 sccm，例如約15 sccm。下一步，磊晶應力源薄膜214、215暴露於使用HCDS的第二前驅物氣體。第二前驅物氣體以約250 sccm至約550 sccm範圍的流動速率被引入處理腔室中，如約350 sccm至約450 sccm，例如約400 sccm。第二前驅物氣體稀釋於氮氣或氫氣載體氣體中，氮氣或氫氣載體氣體以約1 SLM至約30 SLM的流動速率流動入處理腔室中，如約3 SLM。接著用脈衝輸送（pulse）第二前驅物氣體約350秒至約550秒，如約450秒。之後，淨化氣體以約5 sccm至約25 sccm範圍的流動速率被引入處理腔室中，如約10 sccm至約20 sccm，例如約15 sccm。藉由上述處理狀況交替矽烷與HCDS而將一單層的矽一致地且均勻地成長於磊晶應力源薄膜上。此處理過程以約0.1Å/周期的成長速率重複約10個周期以達到所需的厚度。In operation, the epitaxial stressor films 214, 215 are exposed to a first precursor gas using decane. The first precursor gas is introduced into the processing chamber at a flow rate ranging from about 25 sccm to about 55 sccm, such as from about 30 sccm to about 45 sccm, such as about 40 sccm. The first precursor gas is then pulsed for about 650 seconds to about 1200 seconds, such as about 900 seconds. Next, the purge gas is introduced into the processing chamber at a flow rate ranging from about 5 sccm to about 25 sccm, such as from about 10 sccm to about 20 sccm, such as about 15 sccm. Next, the epitaxial stressor films 214, 215 are exposed to a second precursor gas using HCDS. The second precursor gas is introduced into the processing chamber at a flow rate ranging from about 250 sccm to about 550 sccm, such as from about 350 sccm to about 450 sccm, such as about 400 sccm. The second precursor gas is diluted in a nitrogen or hydrogen carrier gas, and the nitrogen or hydrogen carrier gas flows into the processing chamber at a flow rate of from about 1 SLM to about 30 SLM, such as about 3 SLM. The second precursor gas is then pulsed for about 350 seconds to about 550 seconds, such as about 450 seconds. Thereafter, the purge gas is introduced into the processing chamber at a flow rate ranging from about 5 sccm to about 25 sccm, such as from about 10 sccm to about 20 sccm, such as about 15 sccm. A single layer of germanium is uniformly and uniformly grown on the epitaxial stressor film by alternating the decane and the HCDS by the above treatment conditions. This process is repeated for about 10 cycles at a growth rate of about 0.1 Å/cycle to achieve the desired thickness.

在矽帽層217、219以所需的厚度成長於磊晶應力源薄膜214、215上後，閘極介電層（未圖示）可於矽帽層217、219上形成。閘極電極接著於半導體片203的部分上且沿著半導體片203的部分側形成以形成FinFET的一般結構。After the cap layers 217, 219 are grown on the epitaxial stressor films 214, 215 with a desired thickness, a gate dielectric layer (not shown) can be formed over the cap layers 217, 219. The gate electrode is then formed on a portion of the semiconductor wafer 203 and along a portion side of the semiconductor wafer 203 to form a general structure of the FinFET.

本發明揭露的實施中所述之概念亦適用於其他磊晶材料。某些示範例可包括Si:CP、純Ge、GeSn、GeP、GeB或GeSnB等，其可用於邏輯與記憶體應用。在此等情況中，可能的矽前驅物可包括如上所述的鹵化矽化合物與選擇性的含矽化合物，而可能的鍺前驅物可包括如上所述的鹵化鍺化合物與選擇性的含鍺化合物。例如，如果矽鍺用作為帽層，可藉由將磊晶應力源薄膜交替暴露於第一前驅物氣體與第二前驅物氣體而達到矽鍺的磊晶成長，第一前驅物氣體包括本發明揭露中所述的含矽氣體中的一或多個，第二前驅物氣體包括鹵化鍺氣體（如氯化鍺烷氣體、含鍺氣體或含矽氣體）中的一或多個。淨化氣體與任何所需的摻雜氣體可依以上相對於矽帽層所述的方式引入處理腔室中。在一個示範實施中，第一前驅物氣體可係矽烷或乙矽烷，而第二前驅物氣體可係氯化鍺烷氣體，如四氯化鍺（GeCl4 ）、二氯鍺烷（GeH2 Cl2 ）或鍺烷（GeH4 ）。The concepts described in the practice of the present disclosure are also applicable to other epitaxial materials. Some examples may include Si: CP, pure Ge, GeSn, GeP, GeB, or GeSnB, etc., which may be used in logic and memory applications. In such cases, possible ruthenium precursors may include ruthenium halide compounds and selective ruthenium containing compounds as described above, while possible ruthenium precursors may include ruthenium halide compounds and selective ruthenium containing compounds as described above. . For example, if used as a cap layer, the epitaxial growth of germanium can be achieved by alternately exposing the epitaxial stressor film to the first precursor gas and the second precursor gas, the first precursor gas including the present invention One or more of the helium-containing gases described in the disclosure, the second precursor gas comprising one or more of a hafnium halide gas such as a decane gas, a helium-containing gas or a helium-containing gas. The purge gas and any desired dopant gases can be introduced into the process chamber as described above with respect to the ruthenium cap layer. In an exemplary implementation, the first precursor gas may be decane or ethane oxide, and the second precursor gas may be a decane gas such as ruthenium tetrachloride (GeCl 4 ) or chloroform (GeH 2 Cl). 2 ) or decane (GeH 4 ).

本發明揭露的好處包括藉由使用第一前驅物氣體與第二前驅物氣體的原子層磊晶（ALE）而於SiGe磊晶應力源層上直接成長薄矽帽層，第一前驅物氣體包括矽烷，第二前驅物氣體包括氯化矽烷。已經觀察到藉由交替矽烷或乙矽烷與HCDS可以在較低成長溫度達到矽帽層於包含SiGe的磊晶應力源薄膜上的成長。具體言之，因為藉由使用自我限制一層一層的方式（self-limiting layer-by-layer fashion）的ALE處理成長矽帽層，所以矽帽層可以均勻且一致地成長於磊晶應力源薄膜而不失介電質（如矽氧化物與矽氮化物）成長的選擇性。使用矽烷與氯化矽烷的矽磊晶成長鈍化應力源薄膜而允許後續閘極介電質有更好的成長，而使得用於FinFET的磊晶材料有更好的整合與表面形狀控制（surface morphology）。The benefits disclosed by the present invention include directly growing a thin cap layer on the SiGe epitaxial stressor layer by using atomic layer epitaxy (ALE) of the first precursor gas and the second precursor gas, the first precursor gas including The decane, the second precursor gas includes decane chloride. It has been observed that the growth of the ruthenium cap layer on the epitaxial stressor film comprising SiGe can be achieved at lower growth temperatures by alternating decane or ethane oxide with HCDS. Specifically, since the 矽 cap layer is grown by the ALE process using a self-limiting layer-by-layer fashion, the enamel cap layer can be uniformly and uniformly grown on the epitaxial stressor film. The selectivity of the growth of dielectrics such as niobium oxide and tantalum nitride is not lost. The ruthenium epitaxial growth of decane and decane is used to passivate the stressor film to allow better growth of the subsequent gate dielectric, which results in better integration and surface shape control of the epitaxial material for FinFET. ).

雖然前面所述係針對本發明揭露的實施，但在不背離本發明基本範圍下，可設計本發明揭露的其他與進一步的實施例，而本發明範圍由以下申請專利範圍所界定。While the foregoing is directed to the embodiments of the present invention, the invention and the scope of the invention are defined by the scope of the following claims.

100‧‧‧方法100‧‧‧ method

102‧‧‧方塊102‧‧‧ squares

104‧‧‧方塊104‧‧‧ square

106‧‧‧方塊106‧‧‧ squares

108‧‧‧方塊108‧‧‧ square

200‧‧‧半導體結構200‧‧‧Semiconductor structure

202‧‧‧基板202‧‧‧Substrate

203‧‧‧半導體片203‧‧‧Semiconductor film

204‧‧‧第一部分204‧‧‧Part 1

205‧‧‧第二部分205‧‧‧Part II

206‧‧‧介電材料206‧‧‧Dielectric materials

207‧‧‧表面207‧‧‧ surface

209‧‧‧表面209‧‧‧ surface

214‧‧‧磊晶應力源薄膜214‧‧‧ epitaxial stressor film

215‧‧‧磊晶應力源薄膜215‧‧‧ epitaxial stressor film

216‧‧‧刻面216‧‧ ‧ facets

217‧‧‧矽帽層217‧‧‧矽Cap

218‧‧‧刻面218‧‧・facet

219‧‧‧矽帽層219‧‧‧矽Cap

220‧‧‧刻面220‧‧ ‧ facets

222‧‧‧刻面222‧‧ ‧ facets

224‧‧‧角224‧‧‧ corner

226‧‧‧角226‧‧‧ corner

228‧‧‧角228‧‧‧ corner

本發明揭露之特徵已簡要概述於前，並在以下有更詳盡之討論，可以藉由參考附圖中繪示之本發明實施以作參考。然而，值得注意的是，附圖只繪示了本發明揭露的典型實施，而由於本發明可允許其他等效之實施例，附圖並不會視為本發明範圍之限制。The features of the present invention have been briefly described in the foregoing, and are discussed in more detail below by reference to the accompanying drawings. It is to be understood, however, that the appended claims

圖1係根據本發明揭露的用於製造半導體結構之示範方法的流程圖。1 is a flow chart of an exemplary method for fabricating a semiconductor structure in accordance with the present disclosure.

圖2A至2C繪示在根據圖1的流程圖的製造某些階段期間簡化的半導體結構之截面圖。2A through 2C are cross-sectional views of a simplified semiconductor structure during certain stages of fabrication in accordance with the flow chart of FIG. 1.

為便於理解，在可能的情況下，使用相同的數字編號代表圖示中相同的元件。可以明白，一個實施例中的元件與特徵可有利地用於其它實施例中而無需贅述。For the sake of understanding, the same reference numerals will be used to refer to the same elements in the drawings. It will be appreciated that the elements and features of one embodiment may be advantageously utilized in other embodiments without further recitation.

國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無Domestic deposit information (please note according to the order of the depository, date, number)

國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無Foreign deposit information (please note in the order of country, organization, date, number)

(請換頁單獨記載) 無(Please change the page separately) No

Claims (20)

一種在一處理腔室中處理一基板的方法，包括以下步驟： 於一半導體片上形成一磊晶薄膜，該半導體片在該基板上形成，其中該磊晶薄膜包含具有一第一刻面與一第二刻面的一頂表面，該第一刻面具有一暴露的{111}平面及該第二刻面具有一暴露的{111}平面；及藉由在約425°C或小於425°C的一溫度與約5 Torr至約20 Torr的一腔室壓力下將該頂表面交替暴露於一第一前驅物氣體與一第二前驅物氣體而至少在該磊晶薄膜的該頂表面上形成一共形保護層，該第一前驅物氣體包含一或多個矽烷，該第二前驅物氣體包含一或多個鹵化矽烷。A method for processing a substrate in a processing chamber, comprising the steps of: forming an epitaxial film on a semiconductor wafer, the semiconductor wafer being formed on the substrate, wherein the epitaxial film comprises a first facet and a a top surface of the second facet, the first mask having an exposed {111} plane and the second mask having an exposed {111} plane; and by at about 425 ° C or less than 425 ° C Exposing the top surface to a first precursor gas and a second precursor gas alternately at least on the top surface of the epitaxial film at a temperature of from about 5 Torr to about 20 Torr. A conformal protective layer, the first precursor gas comprising one or more decanes, the second precursor gas comprising one or more halogenated decanes. 如請求項1所述之方法，其中該第一前驅物氣體包括矽烷（SiH4 ）、乙矽烷（Si2 H6 ）、丙矽烷（Si3 H8 ）、四矽烷（Si4 H10 ）、四乙氧基矽烷（TEOS）或以上各者之任何組合。The method of claim 1, wherein the first precursor gas comprises decane (SiH 4 ), acetane (Si 2 H 6 ), propane (Si 3 H 8 ), tetraoxane (Si 4 H 10 ), Tetraethoxydecane (TEOS) or any combination of the above. 如請求項2所述之方法，其中該第二前驅物氣體包括一氯矽烷（SiH3 Cl）、二氯矽烷（Si2 H2 Cl2 ）、三氯矽烷（SiHCl3 ）、六氯二矽烷（Si2 Cl6 ）、八氯三矽烷（Si3 Cl8 ）、四氯化矽（STC）或以上各者之任何組合。The method of claim 2, wherein the second precursor gas comprises monochlorosilane (SiH 3 Cl), dichlorodecane (Si 2 H 2 Cl 2 ), trichlorodecane (SiHCl 3 ), hexachlorodioxane. (Si 2 Cl 6 ), octachlorotrioxane (Si 3 Cl 8 ), ruthenium tetrachloride (STC), or any combination of the above. 如請求項1所述之方法，其中該淨化氣體包括氦、氬、氮、氫、形成氣體或以上各者之組合。The method of claim 1, wherein the purge gas comprises helium, argon, nitrogen, hydrogen, forming gas, or a combination thereof. 如請求項1所述之方法，其中該磊晶薄膜為具有於矽中約30%或以上的Ge濃度之矽鍺（SiGe）。The method of claim 1, wherein the epitaxial film is germanium (SiGe) having a Ge concentration of about 30% or more in germanium. 如請求項3所述之方法，其中該第一前驅物氣體是乙矽烷及該第二前驅物是六氯二矽烷（Si2 Cl6 ）。The method of claim 3, wherein the first precursor gas is ethane oxide and the second precursor is hexachlorodioxane (Si 2 Cl 6 ). 如請求項3所述之方法，其中該第一前驅物氣體是矽烷（SiH4 ）及該第二前驅物是六氯二矽烷（Si2 Cl6 ）。The method of claim 3, wherein the first precursor gas is decane (SiH 4 ) and the second precursor is hexachlorodioxane (Si 2 Cl 6 ). 如請求項1所述之方法，進一步包括以下步驟： 將一淨化氣體引入該第一前驅物氣體的流動與該第二前驅物氣體的流動之間的該處理腔室中。The method of claim 1, further comprising the step of: introducing a purge gas into the processing chamber between the flow of the first precursor gas and the flow of the second precursor gas. 如請求項7所述之方法，進一步包括以下步驟： 在流動該淨化氣體之前，用脈衝輸送（pulse）該第一前驅物氣體的流動約5秒至約25秒。The method of claim 7, further comprising the step of: pulsing the flow of the first precursor gas for about 5 seconds to about 25 seconds before flowing the purge gas. 如請求項7所述之方法，進一步包括以下步驟： 在流動該淨化氣體之前，用脈衝輸送該第一前驅物氣體的流動約350秒至約550秒。The method of claim 7, further comprising the step of: pulsing the flow of the first precursor gas for about 350 seconds to about 550 seconds prior to flowing the purge gas. 如請求項1所述之方法，其中該第一刻面的一端與該第二刻面的一端彼此接觸。The method of claim 1, wherein one end of the first facet and one end of the second facet are in contact with each other. 如請求項11所述之方法，進一步包括以下步驟： 至少在該磊晶薄膜的該頂表面上形成該共形保護層之前，在一側向尺度上移除該第一刻面的一部分與該第二刻面的一部分。The method of claim 11, further comprising the steps of: removing a portion of the first facet on a side dimension and at least before forming the conformal protective layer on the top surface of the epitaxial film Part of the second facet. 如請求項1所述之方法，其中該磊晶薄膜與該共形保護層形成在相同的處理腔室中。The method of claim 1, wherein the epitaxial film and the conformal protective layer are formed in the same processing chamber. 如請求項1所述之方法，進一步包括以下步驟： 至少在該磊晶薄膜的該頂表面上形成該共形保護層之後，在該共形保護層的一部分上方形成一閘極電極。The method of claim 1, further comprising the step of: forming a gate electrode over a portion of the conformal protective layer after forming the conformal protective layer on the top surface of the epitaxial film. 如請求項1所述之方法，其中該磊晶薄膜是純鍺（Ge）。The method of claim 1, wherein the epitaxial film is pure germanium (Ge). 如請求項1所述之方法，其中該磊晶薄膜是摻雜磷的碳化矽（Si:CP）。The method of claim 1, wherein the epitaxial film is phosphorus-doped lanthanum carbide (Si:CP). 如請求項1所述之方法，其中該磊晶薄膜是摻雜磷的矽（Si:P）。The method of claim 1, wherein the epitaxial film is doped with phosphorus (Si:P). 如請求項1所述之方法，其中該磊晶薄膜是摻雜硼的矽鍺（SiGe:B）。The method of claim 1, wherein the epitaxial film is boron-doped germanium (SiGe:B). 一種在一處理腔室中處理一基板的方法，包括以下步驟： 於一半導體片上形成一磊晶薄膜，該半導體片於該基板上形成，其中該磊晶薄膜包含具有一第一刻面與一第二刻面之一頂表面，該第一刻面具有暴露的{111}平面及該第二刻面具有暴露的{111}平面； 在約425°C或小於425°C的一溫度下將該磊晶薄膜暴露於一第一前驅物氣體，該第一前驅物氣體包含矽烷（SiH4 ）或乙矽烷（Si2 H6 ）； 用脈衝輸送該第一前驅物氣體一第一周期時間； 將一淨化氣體引入該處理腔室中； 在小於約425°C或更小的一溫度下將該磊晶薄膜暴露於一第二前驅物氣體，該第二前驅物氣體包含氯化矽烷； 用脈衝輸送該第二前驅物氣體一第二周期時間；及 將該淨化氣體引入該處理腔室中。A method for processing a substrate in a processing chamber, comprising the steps of: forming an epitaxial film on a semiconductor wafer, the semiconductor wafer being formed on the substrate, wherein the epitaxial film comprises a first facet and a a top surface of the second facet having an exposed {111} plane and the second facet having an exposed {111} plane; at a temperature of about 425 ° C or less than 425 ° C The epitaxial film is exposed to a first precursor gas, the first precursor gas comprising decane (SiH 4 ) or oxirane (Si 2 H 6 ); the first precursor gas is pulsed for a first cycle time; Introducing a purge gas into the processing chamber; exposing the epitaxial film to a second precursor gas at a temperature of less than about 425 ° C or less, the second precursor gas comprising decane chloride; Pulse the second precursor gas for a second cycle time; and introducing the purge gas into the processing chamber. 如請求項19所述之方法，其中該第一周期時間係約5秒至約25秒或約350秒至約550秒，及該第二周期時間係約5秒至約25秒或約350秒至約550秒。The method of claim 19, wherein the first cycle time is from about 5 seconds to about 25 seconds or from about 350 seconds to about 550 seconds, and the second cycle time is from about 5 seconds to about 25 seconds or about 350 seconds. It takes about 550 seconds.
TW106117147A 2014-10-30 2015-10-30 Method to grow thin epitaxial films at low temperature TWI647744B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462072937P 2014-10-30 2014-10-30
US62/072,937 2014-10-30

Publications (2)

Publication Number Publication Date
TW201735117A TW201735117A (en) 2017-10-01
TWI647744B true TWI647744B (en) 2019-01-11

Family

ID=55853460

Family Applications (2)

Application Number Title Priority Date Filing Date
TW104135804A TWI613705B (en) 2014-10-30 2015-10-30 Method to grow thin epitaxial films at low temperature
TW106117147A TWI647744B (en) 2014-10-30 2015-10-30 Method to grow thin epitaxial films at low temperature

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW104135804A TWI613705B (en) 2014-10-30 2015-10-30 Method to grow thin epitaxial films at low temperature

Country Status (6)

Country Link
US (2) US9530638B2 (en)
KR (2) KR20170070281A (en)
CN (2) CN107112213B (en)
SG (1) SG11201703228XA (en)
TW (2) TWI613705B (en)
WO (1) WO2016069180A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI739332B (en) * 2019-03-08 2021-09-11 美商應用材料股份有限公司 Methods for low temperature silicide formation

Families Citing this family (205)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
US20160376700A1 (en) 2013-02-01 2016-12-29 Asm Ip Holding B.V. System for treatment of deposition reactor
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
KR102310076B1 (en) * 2015-04-23 2021-10-08 삼성전자주식회사 Semiconductor devices having a source/drain ofasymmetrical shape
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
WO2017196490A1 (en) * 2016-05-09 2017-11-16 Applied Materials, Inc. Method of selective etching on epitaxial film on source/drain area of transistor
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US9773870B1 (en) * 2016-06-28 2017-09-26 International Business Machines Corporation Strained semiconductor device
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
KR101960763B1 (en) * 2016-11-03 2019-03-21 주식회사 유진테크 Method for manufacturing an epitaxial layer in low temperature
KR102546317B1 (en) 2016-11-15 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Gas supply unit and substrate processing apparatus including the same
US10515951B2 (en) * 2016-11-29 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
TWI812984B (en) * 2016-12-12 2023-08-21 美商應用材料股份有限公司 Method of forming strained channel layer
KR20180068582A (en) 2016-12-14 2018-06-22 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
EP3339244A1 (en) * 2016-12-21 2018-06-27 IMEC vzw Source and drain contacts in fin- or nanowire- based semiconductor devices.
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
CN109119331B (en) * 2017-06-23 2021-02-02 上海新昇半导体科技有限公司 Semiconductor device, manufacturing method thereof and electronic device
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
KR102414182B1 (en) 2017-06-29 2022-06-28 삼성전자주식회사 Semiconductor device
KR20190009245A (en) 2017-07-18 2019-01-28 에이에스엠 아이피 홀딩 비.브이. Methods for forming a semiconductor device structure and related semiconductor device structures
US11374112B2 (en) 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
JP7288432B2 (en) * 2017-09-03 2023-06-07 アプライド マテリアルズ インコーポレイテッド Conformal halogen doping of 3D structures using conformal dopant film deposition
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
KR102597978B1 (en) 2017-11-27 2023-11-06 에이에스엠 아이피 홀딩 비.브이. Storage device for storing wafer cassettes for use with batch furnaces
CN111344522B (en) 2017-11-27 2022-04-12 阿斯莫Ip控股公司 Including clean mini-environment device
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
TW202325889A (en) 2018-01-19 2023-07-01 荷蘭商Ａｓｍ 智慧財產控股公司 Deposition method
CN111630203A (en) 2018-01-19 2020-09-04 Asm Ip私人控股有限公司 Method for depositing gap filling layer by plasma auxiliary deposition
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
EP3737779A1 (en) 2018-02-14 2020-11-18 ASM IP Holding B.V. A method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
KR102636427B1 (en) 2018-02-20 2024-02-13 에이에스엠 아이피 홀딩 비.브이. Substrate processing method and apparatus
US10975470B2 (en) 2018-02-23 2021-04-13 Asm Ip Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US11629406B2 (en) 2018-03-09 2023-04-18 Asm Ip Holding B.V. Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
KR102646467B1 (en) 2018-03-27 2024-03-11 에이에스엠 아이피 홀딩 비.브이. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
US11230766B2 (en) 2018-03-29 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
TW202344708A (en) 2018-05-08 2023-11-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
KR102596988B1 (en) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate and a device manufactured by the same
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
US11270899B2 (en) 2018-06-04 2022-03-08 Asm Ip Holding B.V. Wafer handling chamber with moisture reduction
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
KR102568797B1 (en) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing system
WO2020003000A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US11492703B2 (en) 2018-06-27 2022-11-08 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
EP3830860A4 (en) 2018-07-30 2022-04-20 Applied Materials, Inc. Method of selective silicon germanium epitaxy at low temperatures
US10679995B2 (en) * 2018-07-31 2020-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
KR20200030162A (en) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. Method for deposition of a thin film
CN110970344A (en) 2018-10-01 2020-04-07 Asm Ip控股有限公司 Substrate holding apparatus, system including the same, and method of using the same
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR102592699B1 (en) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same
US11230474B2 (en) 2018-10-11 2022-01-25 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Process for producing isomer enriched higher silanes
US11401166B2 (en) 2018-10-11 2022-08-02 L'Air Liaquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Process for producing isomer enriched higher silanes
US10752507B2 (en) 2018-10-11 2020-08-25 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Process for producing liquid polysilanes and isomer enriched higher silanes
US11097953B2 (en) 2018-10-11 2021-08-24 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Process for producing liquid polysilanes and isomer enriched higher silanes
KR102546322B1 (en) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
KR102605121B1 (en) 2018-10-19 2023-11-23 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
KR20200051105A (en) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and substrate processing apparatus including the same
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
KR102636428B1 (en) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. A method for cleaning a substrate processing apparatus
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
JP2020096183A (en) 2018-12-14 2020-06-18 エーエスエム・アイピー・ホールディング・ベー・フェー Method of forming device structure using selective deposition of gallium nitride, and system for the same
TWI819180B (en) 2019-01-17 2023-10-21 荷蘭商Ａｓｍ 智慧財產控股公司 Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
KR20200091543A (en) 2019-01-22 2020-07-31 에이에스엠 아이피 홀딩 비.브이. Semiconductor processing device
TW202044325A (en) 2019-02-20 2020-12-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of filling a recess formed within a surface of a substrate, semiconductor structure formed according to the method, and semiconductor processing apparatus
TW202104632A (en) 2019-02-20 2021-02-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
KR20200102357A (en) 2019-02-20 2020-08-31 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for plug fill deposition in 3-d nand applications
KR102626263B1 (en) 2019-02-20 2024-01-16 에이에스엠 아이피 홀딩 비.브이. Cyclical deposition method including treatment step and apparatus for same
TW202100794A (en) 2019-02-22 2021-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing apparatus and method for processing substrate
KR20200108248A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. STRUCTURE INCLUDING SiOCN LAYER AND METHOD OF FORMING SAME
KR20200108242A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer
JP2020167398A (en) 2019-03-28 2020-10-08 エーエスエム・アイピー・ホールディング・ベー・フェー Door opener and substrate processing apparatus provided therewith
JP7203670B2 (en) * 2019-04-01 2023-01-13 東京エレクトロン株式会社 Film forming method and film forming apparatus
KR20200116855A (en) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. Method of manufacturing semiconductor device
KR20200123380A (en) 2019-04-19 2020-10-29 에이에스엠 아이피 홀딩 비.브이. Layer forming method and apparatus
KR20200125453A (en) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. Gas-phase reactor system and method of using same
KR20200130118A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Method for Reforming Amorphous Carbon Polymer Film
KR20200130121A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Chemical source vessel with dip tube
KR20200130652A (en) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. Method of depositing material onto a surface and structure formed according to the method
JP2020188255A (en) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー．ブイ． Wafer boat handling device, vertical batch furnace, and method
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
KR20200141003A (en) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. Gas-phase reactor system including a gas detector
KR20200143254A (en) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method
US11948796B2 (en) 2019-06-12 2024-04-02 Applied Materials, Inc. Selective methods for fabricating devices and structures
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
CN114270476A (en) * 2019-06-24 2022-04-01 朗姆研究公司 Selective carbon deposition
KR20210005515A (en) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. Temperature control assembly for substrate processing apparatus and method of using same
JP2021015791A (en) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー．ブイ． Plasma device and substrate processing method using coaxial waveguide
CN112216646A (en) 2019-07-10 2021-01-12 Asm Ip私人控股有限公司 Substrate supporting assembly and substrate processing device comprising same
KR20210010307A (en) 2019-07-16 2021-01-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210010816A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Radical assist ignition plasma system and method
KR20210010820A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Methods of forming silicon germanium structures
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
CN112242296A (en) 2019-07-19 2021-01-19 Asm Ip私人控股有限公司 Method of forming topologically controlled amorphous carbon polymer films
CN114072544A (en) * 2019-07-26 2022-02-18 应用材料公司 Anisotropic epitaxial growth
CN112309843A (en) 2019-07-29 2021-02-02 Asm Ip私人控股有限公司 Selective deposition method for achieving high dopant doping
CN112309899A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112309900A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
KR20210018759A (en) 2019-08-05 2021-02-18 에이에스엠 아이피 홀딩 비.브이. Liquid level sensor for a chemical source vessel
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
JP2021031769A (en) 2019-08-21 2021-03-01 エーエスエム アイピー ホールディング ビー．ブイ． Production apparatus of mixed gas of film deposition raw material and film deposition apparatus
KR20210024423A (en) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for forming a structure with a hole
USD949319S1 (en) 2019-08-22 2022-04-19 Asm Ip Holding B.V. Exhaust duct
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
USD940837S1 (en) 2019-08-22 2022-01-11 Asm Ip Holding B.V. Electrode
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
KR20210024420A (en) 2019-08-23 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane
KR20210029090A (en) 2019-09-04 2021-03-15 에이에스엠 아이피 홀딩 비.브이. Methods for selective deposition using a sacrificial capping layer
KR20210029663A (en) 2019-09-05 2021-03-16 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210035449A (en) 2019-09-24 2021-04-01 삼성전자주식회사 A semiconductor device and method of manufacturing the same
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
CN112593212B (en) 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process
TW202129060A (en) 2019-10-08 2021-08-01 荷蘭商Ａｓｍ Ｉｐ控股公司 Substrate processing device, and substrate processing method
KR20210043460A (en) 2019-10-10 2021-04-21 에이에스엠 아이피 홀딩 비.브이. Method of forming a photoresist underlayer and structure including same
KR20210045930A (en) 2019-10-16 2021-04-27 에이에스엠 아이피 홀딩 비.브이. Method of Topology-Selective Film Formation of Silicon Oxide
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
KR20210047808A (en) 2019-10-21 2021-04-30 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for selectively etching films
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
KR20210054983A (en) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. Structures with doped semiconductor layers and methods and systems for forming same
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
KR20210062561A (en) 2019-11-20 2021-05-31 에이에스엠 아이피 홀딩 비.브이. Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure
CN112951697A (en) 2019-11-26 2021-06-11 Asm Ip私人控股有限公司 Substrate processing apparatus
KR20210065848A (en) 2019-11-26 2021-06-04 에이에스엠 아이피 홀딩 비.브이. Methods for selectivley forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
CN112885692A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112885693A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
JP2021090042A (en) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー．ブイ． Substrate processing apparatus and substrate processing method
KR20210070898A (en) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
TW202125596A (en) 2019-12-17 2021-07-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming vanadium nitride layer and structure including the vanadium nitride layer
KR20210080214A (en) 2019-12-19 2021-06-30 에이에스엠 아이피 홀딩 비.브이. Methods for filling a gap feature on a substrate and related semiconductor structures
JP2021109175A (en) 2020-01-06 2021-08-02 エーエスエム・アイピー・ホールディング・ベー・フェー Gas supply assembly, components thereof, and reactor system including the same
KR20210095050A (en) 2020-01-20 2021-07-30 에이에스엠 아이피 홀딩 비.브이. Method of forming thin film and method of modifying surface of thin film
TW202130846A (en) 2020-02-03 2021-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of forming structures including a vanadium or indium layer
TW202146882A (en) 2020-02-04 2021-12-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of verifying an article, apparatus for verifying an article, and system for verifying a reaction chamber
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
US11781243B2 (en) 2020-02-17 2023-10-10 Asm Ip Holding B.V. Method for depositing low temperature phosphorous-doped silicon
US11876356B2 (en) 2020-03-11 2024-01-16 Asm Ip Holding B.V. Lockout tagout assembly and system and method of using same
KR20210116240A (en) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. Substrate handling device with adjustable joints
KR20210117157A (en) 2020-03-12 2021-09-28 에이에스엠 아이피 홀딩 비.브이. Method for Fabricating Layer Structure Having Target Topological Profile
US11677013B2 (en) 2020-03-30 2023-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain epitaxial layers for transistors
KR20210124042A (en) 2020-04-02 2021-10-14 에이에스엠 아이피 홀딩 비.브이. Thin film forming method
TW202146689A (en) 2020-04-03 2021-12-16 荷蘭商Ａｓｍ Ｉｐ控股公司 Method for forming barrier layer and method for manufacturing semiconductor device
TW202145344A (en) 2020-04-08 2021-12-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Apparatus and methods for selectively etching silcon oxide films
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
KR20210132600A (en) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
US11898243B2 (en) 2020-04-24 2024-02-13 Asm Ip Holding B.V. Method of forming vanadium nitride-containing layer
KR20210132605A (en) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. Vertical batch furnace assembly comprising a cooling gas supply
KR20210134226A (en) 2020-04-29 2021-11-09 에이에스엠 아이피 홀딩 비.브이. Solid source precursor vessel
KR20210134869A (en) 2020-05-01 2021-11-11 에이에스엠 아이피 홀딩 비.브이. Fast FOUP swapping with a FOUP handler
KR20210141379A (en) 2020-05-13 2021-11-23 에이에스엠 아이피 홀딩 비.브이. Laser alignment fixture for a reactor system
KR20210143653A (en) 2020-05-19 2021-11-29 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210145078A (en) 2020-05-21 2021-12-01 에이에스엠 아이피 홀딩 비.브이. Structures including multiple carbon layers and methods of forming and using same
TW202201602A (en) 2020-05-29 2022-01-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing device
TW202218133A (en) 2020-06-24 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for forming a layer provided with silicon
TW202217953A (en) 2020-06-30 2022-05-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Substrate processing method
TW202219628A (en) 2020-07-17 2022-05-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Structures and methods for use in photolithography
TW202204662A (en) 2020-07-20 2022-02-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method and system for depositing molybdenum layers
KR20220027026A (en) 2020-08-26 2022-03-07 에이에스엠 아이피 홀딩 비.브이. Method and system for forming metal silicon oxide and metal silicon oxynitride
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
TW202229613A (en) 2020-10-14 2022-08-01 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method of depositing material on stepped structure
KR20220053482A (en) 2020-10-22 2022-04-29 에이에스엠 아이피 홀딩 비.브이. Method of depositing vanadium metal, structure, device and a deposition assembly
TW202223136A (en) 2020-10-28 2022-06-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Method for forming layer on substrate, and semiconductor processing system
TW202235675A (en) 2020-11-30 2022-09-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Injector, and substrate processing apparatus
US11946137B2 (en) 2020-12-16 2024-04-02 Asm Ip Holding B.V. Runout and wobble measurement fixtures
TW202231903A (en) 2020-12-22 2022-08-16 荷蘭商Ａｓｍ Ｉｐ私人控股有限公司 Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate
USD1023959S1 (en) 2021-05-11 2024-04-23 Asm Ip Holding B.V. Electrode for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140084369A1 (en) * 2009-12-21 2014-03-27 Anand S. Murthy Semiconductor device having doped epitaxial region and its methods of fabrication

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176109B2 (en) * 2001-03-23 2007-02-13 Micron Technology, Inc. Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
JP4369359B2 (en) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 Semiconductor device
US8030108B1 (en) 2008-06-30 2011-10-04 Stc.Unm Epitaxial growth of in-plane nanowires and nanowire devices
US8263451B2 (en) 2010-02-26 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxy profile engineering for FinFETs
US8659032B2 (en) * 2012-01-31 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
JP5815443B2 (en) * 2012-03-19 2015-11-17 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing method, and substrate processing apparatus
US8497177B1 (en) * 2012-10-04 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US20140120678A1 (en) * 2012-10-29 2014-05-01 Matheson Tri-Gas Methods for Selective and Conformal Epitaxy of Highly Doped Si-containing Materials for Three Dimensional Structures
US9142633B2 (en) * 2012-12-13 2015-09-22 GlobalFoundries, Inc. Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
US9812556B2 (en) * 2012-12-28 2017-11-07 Renesas Electronics Corporation Semiconductor device and method of manufacturing the semiconductor device
US20150170916A1 (en) * 2013-12-17 2015-06-18 United Microelectronics Corp. Semiconductor process for manufacturing epitaxial structures

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140084369A1 (en) * 2009-12-21 2014-03-27 Anand S. Murthy Semiconductor device having doped epitaxial region and its methods of fabrication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI739332B (en) * 2019-03-08 2021-09-11 美商應用材料股份有限公司 Methods for low temperature silicide formation

Also Published As

Publication number Publication date
KR20170061724A (en) 2017-06-05
TW201628065A (en) 2016-08-01
CN107112213B (en) 2021-04-16
US20160126093A1 (en) 2016-05-05
TWI613705B (en) 2018-02-01
KR101850666B1 (en) 2018-04-19
SG11201703228XA (en) 2017-05-30
US9929055B2 (en) 2018-03-27
CN107112213A (en) 2017-08-29
US9530638B2 (en) 2016-12-27
KR20170070281A (en) 2017-06-21
WO2016069180A1 (en) 2016-05-06
CN107546108A (en) 2018-01-05
TW201735117A (en) 2017-10-01
US20170178962A1 (en) 2017-06-22

Similar Documents

Publication Publication Date Title
TWI647744B (en) Method to grow thin epitaxial films at low temperature
KR102113114B1 (en) N-doped selective epitaxial growth is used to form a non-visible source drain extension in the NMOS finpet
TWI430335B (en) Methods of selectively depositing an epitaxial layer
TWI677906B (en) Method of selective epitaxy
US10205002B2 (en) Method of epitaxial growth shape control for CMOS applications
TW201608643A (en) Method of forming field effect transistor and integrated circuit structure
TW201411700A (en) Processes and structures for dopant profile control in epitaxial trench fill
US10727064B2 (en) Post UV cure for gapfill improvement
CN104752504B (en) Semiconductor device structure and its manufacturing method
KR102321839B1 (en) Selective etching method for epitaxial films on source/drain regions of transistors
TWI623022B (en) Method of semiconductor device fabrication
CN107430994B (en) Method for increasing growth rate of selective epitaxial growth
TWI768245B (en) Methods and apparatus for silicon-germanium pre-clean
KR102659317B1 (en) Apparatus and methods for manufacturing semiconductor structures using a protective barrier layer
TWI738207B (en) Methods and apparatus for metal silicide deposition
JP2012104735A (en) Semiconductor device and manufacturing method thereof
JP7288432B2 (en) Conformal halogen doping of 3D structures using conformal dopant film deposition
TWI748021B (en) Method of forming strained channel layer
TW202218133A (en) Method for forming a layer provided with silicon
US20240145241A1 (en) Surface modifiers for enhanced epitaxial nucleation and wetting
TW202318664A (en) Anisotropic sige:b epitaxial film growth for gate all around transistor