TWI642119B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
- Publication number
- TWI642119B TWI642119B TW104126411A TW104126411A TWI642119B TW I642119 B TWI642119 B TW I642119B TW 104126411 A TW104126411 A TW 104126411A TW 104126411 A TW104126411 A TW 104126411A TW I642119 B TWI642119 B TW I642119B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- region
- exclusion
- wire
- protective layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
提供第一基板附著至第二基板之方法及裝置。在一些實施方式中,第一基板具有保護層,如焊罩(solder mask),其圍繞第二基板所附著之晶粒附著區域(die attach area)。排除區域(keep-out region)(例如第二基板與保護層間之區域)為一個區域圍繞未形成或移除保護層之第二基板。排除區域的尺寸大小使第二基板與保護層間存在足夠的間隔,以放置底部填膠(underfill)於第一基板與第二基板之間,同時降低或避免空隙,且同時允許排除區域中之導線藉由底部填膠而覆蓋。 A method and apparatus for attaching a first substrate to a second substrate are provided. In some embodiments, the first substrate has a protective layer, such as a solder mask, surrounding a die attach area to which the second substrate is attached. A keep-out region (eg, a region between the second substrate and the protective layer) is a region surrounding the second substrate on which the protective layer is not formed or removed. The size of the exclusion region is such that there is sufficient spacing between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or avoiding voids, and at the same time allowing the wires in the exclusion region to be excluded Covered by bottom filling.
Description
本發明是關於一種半導體裝置及其形成方法,特別是有關於一種凸塊導線直連晶片封裝裝置及其形成方法。 BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device and a method of forming the same, and more particularly to a bump-on-line wafer package device and a method of forming the same.
積體電路或晶片係由大量的主動及被動元件如電晶體及電容器所組成。這些元件最初彼此隔離,之後會互連形成積體電路。連接器結構更進一步形成以用於積體電路,其可包含結合墊(bond pads)或金屬凸塊形成於電路之表面上。電性連接(electrical connection)係經由結合墊或金屬凸塊以產生,其可連接晶片至封裝基板或其他晶粒。一般而言,利用打線接合(wire bonding,WB)或覆晶(flip chip,FC)封裝技術,可將晶片組裝成一個封裝如接腳柵格陣列(pin grid array,PGA),或球狀柵格陣列(ball grid array,BGA)。 Integrated circuits or wafers consist of a large number of active and passive components such as transistors and capacitors. These components are initially isolated from each other and then interconnected to form an integrated circuit. The connector structure is further formed for use in an integrated circuit that may include bond pads or metal bumps formed on the surface of the circuit. Electrical connections are made via bond pads or metal bumps that connect the wafer to the package substrate or other die. In general, wafer bonding can be assembled into a package such as a pin grid array (PGA) or a ball grid using wire bonding (WB) or flip chip (FC) packaging techniques. Ball grid array (BGA).
覆晶(flip-chip,FC)封裝技術利用凸塊導線直連(bump-on-trace,BOT)結構可連接晶片至封裝基板,其中經由金屬凸塊之連接,可連接晶片至封裝基板或晶粒之金屬導線(traces)。BOT結構提供的低成本可替代微電子封裝產業。然而,隨著基板結構變薄,BOT結構之可靠性問題上升。 A flip-chip (FC) package technology utilizes a bump-on-trace (BOT) structure to connect a wafer to a package substrate, wherein the connection to the package substrate or crystal is via a metal bump connection Metal traces of particles. The low cost provided by the BOT structure can replace the microelectronic packaging industry. However, as the substrate structure becomes thinner, the reliability problem of the BOT structure rises.
當利用BOT結構時,用於晶片之凸塊藉由回焊製程被焊接至封裝基板上之導線上。當凸塊接合至基板並自回焊狀態冷卻至室 溫時,熱膨脹係數(coefficient of thermal expansion,CTE)不匹配導致的熱力(thermal force)會使基板收縮(shrinkage)並導致相對的扭轉於每個凸塊上。一旦應力等級(stress level)上升超過基板與導線間之黏著標準,會產生導線剝離缺陷(trace peeling failure)。 When the BOT structure is utilized, the bumps for the wafer are soldered to the wires on the package substrate by a reflow process. When the bump is bonded to the substrate and cooled to the chamber from the reflow state At warmer temperatures, the thermal force caused by the coefficient of thermal expansion (CTE) mismatch causes the substrate to shrinkage and cause relative torsion on each bump. Once the stress level rises above the adhesion standard between the substrate and the wire, a trace peeling failure occurs.
在一實施方式中,提供一種半導體裝置。所述裝置包含第一基板具有導線形成於其上。第一基板具有晶粒附著區域,排除區域圍繞於該晶粒附著區域之周圍,及一周圍區域圍繞於該排除區域之周圍。第一基板具有保護層上覆周圍區域中之導線。第二基板電性耦接至第一基板於晶粒附著區域中;以及底部填膠夾設於第一基板與第二基板之間,底部填膠在位於排除區域中之導線的上方延伸;其中排除區域的面積佔第二基板的面積約5%至約18%。 In an embodiment, a semiconductor device is provided. The device includes a first substrate having a wire formed thereon. The first substrate has a die attaching region, the exclusion region surrounds the periphery of the die attach region, and a surrounding region surrounds the periphery of the exclusion region. The first substrate has a wire overlying the surrounding area of the protective layer. The second substrate is electrically coupled to the first substrate in the die attach region; and the bottom filler is sandwiched between the first substrate and the second substrate, and the bottom filler extends over the wires in the exclusion region; The area of the exclusion zone accounts for about 5% to about 18% of the area of the second substrate.
在另一實施方式中,提供一種半導體裝置。所述裝置包含第一基板具有晶粒附著區域、周圍區域及排除區域夾設於晶粒附著區域與周圍區域之間,其中保護層覆蓋周圍區域中之導線,且其中保護層不會延伸進入晶粒附著區域與排除區域。第二基板電性耦接至第一基板,使第二基板位於第一基板之晶粒附著區域的上方。晶粒附著區域相當於第一基板位於第二基板正下方之區域,而排除區域自保護層之邊界延伸至晶粒附著區域之邊界。排除區域的面積佔該第二基板的面積約5%至約18%。 In another embodiment, a semiconductor device is provided. The device includes a first substrate having a die attach region, a surrounding region and a exclusion region interposed between the die attach region and the surrounding region, wherein the protective layer covers the wires in the surrounding region, and wherein the protective layer does not extend into the crystal Grain attachment area and exclusion area. The second substrate is electrically coupled to the first substrate such that the second substrate is located above the die attach region of the first substrate. The die attach region corresponds to a region where the first substrate is directly under the second substrate, and the exclusion region extends from the boundary of the protective layer to the boundary of the die attach region. The area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate.
在又一實施方式,提供一種形成半導體裝置之方法,所述方法包含提供第一基板,第一基板具有導線形成於其上,並形成保護層於第一基板之一部分的上方。將第二基板附著至第一基板。排除 區域在保護層之邊界與第二基板之周圍間延伸,其中排除區域的面積佔第二基板的面積約5%至約18%。 In still another embodiment, a method of forming a semiconductor device is provided, the method comprising providing a first substrate having a wire formed thereon and forming a protective layer over a portion of the first substrate. The second substrate is attached to the first substrate. exclude The region extends between the boundary of the protective layer and the periphery of the second substrate, wherein the area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate.
201‧‧‧晶片 201‧‧‧ wafer
202‧‧‧銅柱凸塊或支柱(Cu pillar bump or post)、銅柱、支柱 202‧‧‧Cullar bump or post, copper pillar, pillar
203‧‧‧焊球、焊凸塊 203‧‧‧ solder balls, solder bumps
204‧‧‧導線(trace) 204‧‧‧Wire (trace)
205‧‧‧封裝體(encapsulation body) 205‧‧‧Encapsulation body
206‧‧‧基板 206‧‧‧Substrate
207‧‧‧球 207‧‧‧ ball
210‧‧‧焊罩溝槽 210‧‧‧welding groove
211‧‧‧焊罩、焊罩層 211‧‧‧welding cover, welding cover
220‧‧‧步驟 220‧‧‧Steps
221‧‧‧步驟 221‧‧‧Steps
223‧‧‧步驟 223‧‧ steps
227‧‧‧步驟 227‧‧‧Steps
231‧‧‧步驟 231‧‧‧Steps
233‧‧‧步驟 233‧‧ steps
235‧‧‧步驟 235‧‧ steps
301‧‧‧區域 301‧‧‧Area
311‧‧‧焊罩溝槽 311‧‧‧welding groove
2021‧‧‧支柱或互連 2021‧‧‧ Pillars or interconnections
2022‧‧‧支柱或互連 2022‧‧‧ pillars or interconnections
402‧‧‧第一基板 402‧‧‧First substrate
404‧‧‧導線 404‧‧‧Wire
404a‧‧‧導線之末端 404a‧‧‧End of wire
406‧‧‧保護層 406‧‧‧Protective layer
408‧‧‧晶粒附著區域 408‧‧‧ die attach area
520‧‧‧第二基板 520‧‧‧second substrate
522‧‧‧電性連接器 522‧‧‧Electrical connector
522a‧‧‧導電柱 522a‧‧‧conductive column
522b‧‧‧焊接材料 522b‧‧‧Welding materials
524‧‧‧排除區域(keep-out-region,KOR) 524‧‧‧Keep-out-region (KOR)
650‧‧‧底部填膠 650‧‧‧Bottom filling
702‧‧‧步驟 702‧‧‧Steps
704‧‧‧步驟 704‧‧‧Steps
706‧‧‧步驟 706‧‧‧Steps
708‧‧‧步驟 708‧‧ steps
B-B‧‧‧剖線 B-B‧‧‧ cut line
L1‧‧‧長度 L 1 ‧‧‧ length
W1‧‧‧寬度 W 1 ‧‧‧Width
D1‧‧‧排除距離(keep-out distance,KOD) D1‧‧‧Keep-out distance (KOD)
本發明內容的實施方式可從下面的詳細描述並結合參閱附圖得到最佳的理解。要強調的是,按照在業界的標準實務做法,各種特徵不一定是按比例繪製。事實上,為了清楚的討論各種特徵的尺寸可任意放大或縮小。 The embodiments of the present invention can be best understood from the following detailed description and appended claims. It is emphasized that, in accordance with standard practice practices in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of discussion.
第1圖繪示出晶片在凸塊導線直連(bump-on-trace,BOT)結構上以形成覆晶(flip-chip,FC)封裝之一實施方式。 Figure 1 illustrates one embodiment of a wafer on a bump-on-trace (BOT) structure to form a flip-chip (FC) package.
第2a-c圖繪示出焊罩溝槽(solder mask trench)用於BOT結構中以形成FC封裝之方法及裝置之一實施方式。 2a-c illustrate one embodiment of a method and apparatus for a solder mask trench for use in a BOT structure to form an FC package.
第3圖繪示出在BOT結構中所使用之複數個焊罩溝槽內,複數個凸塊連接至導線之俯視圖。 Figure 3 illustrates a top view of a plurality of bumps connected to the wires in a plurality of solder mask trenches used in the BOT structure.
第4a-6b圖係根據一些實施方式繪示出中間製程步驟之各種平面及剖面圖。 4a-6b illustrate various planes and cross-sectional views of an intermediate process step in accordance with some embodiments.
第7圖係根據一些實施方式之製造方法流程圖。 Figure 7 is a flow diagram of a method of fabrication in accordance with some embodiments.
應該理解到,以下揭露的內容提供多種不同的實施方式或實例,用於實現本發明內容的不同特徵。元件和配置的具體實例描述如下以簡化本發明內容。當然,這些僅僅是例子而沒有進行限制的目的。舉例而言,下面某一第一特徵形成在一第二特徵之上的描述可包括的實施方式為第 一和第二特徵直接接觸形成,也可包括其他特徵介於第一與第二特徵之間,使得第一和第二特徵可以不直接接觸。除此之外,本發明內容於各個實例中可能用到重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施方式及/或所述結構之間的關係。 It should be understood that the following disclosure provides various embodiments or examples for implementing different features of the present invention. Specific examples of components and configurations are described below to simplify the present invention. Of course, these are just examples and are not intended to be limiting. For example, a description in which one of the following first features is formed on a second feature may include an embodiment The first and second features are formed in direct contact, and other features may be included between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may use repeated reference symbols and/or words in the various examples. These repeated symbols or words are not intended to limit the relationship between the various embodiments and/or the structures.
另外,空間相對用語,如「下」、「低」、「上」等,是用以方便描述一元件或特徵與其他元件或特徵在圖式中的相對關係。這些空間相對用語旨在包含除了圖式中所示之方位以外,裝置在使用或操作時的不同方位。裝置可被另外定位(例如旋轉90度或其他方位),而本文所使用的空間相對敘述亦可相對應地進行解釋。 In addition, spatial relative terms, such as "lower", "lower", "upper", etc., are used to describe the relative relationship of an element or feature to other elements or features in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device can be otherwise positioned (e.g., rotated 90 degrees or other orientation), and the spatially relative descriptions used herein can also be interpreted accordingly.
接下來的介紹將揭露焊罩溝槽用於BOT結構中以形成半導體封裝之方法及裝置。焊罩層(solder mask layer)形成於導線上與基板上。形成稱為焊罩溝槽的焊罩層之開口,以暴露基板上之導線。晶片連接至焊罩溝槽中所暴露出之導線。隨著焊罩溝槽的形成,暴露在溝槽中之導線可具有較好的抓力,其可降低半導體封裝導線剝離缺陷(trace peeling failure)。 The following description will disclose a method and apparatus for a solder mask trench for use in a BOT structure to form a semiconductor package. A solder mask layer is formed on the wires and on the substrate. An opening is formed into the solder mask layer called the solder mask trench to expose the wires on the substrate. The wafer is connected to the exposed conductors in the solder mask trench. As the shroud trench is formed, the wires exposed in the trench can have better grip, which can reduce semiconductor package wire peeling failure.
第1圖依據一實施方式繪示出晶片201在凸塊導線直連(bump-on-trace,BOT)結構上以形成覆晶(flip-chip,FC)封裝之示意圖。基板206可具有複數個子層。第1圖所示基板206之兩個子層僅用於說明之目的並非限制。位於基板206下方之複數個球207可形成球狀柵格陣列(ball grid array,BGA)。晶片201藉由複數個互連(interconnect)連接至基板206,其中每一個互連包含銅柱凸塊或支柱(Cu pillar bump or post)202及焊球203。焊球203放置導線204上,而所述導線204形成於基 板206上。焊罩211形成於基板206之表面覆蓋導線。形成稱為焊罩溝槽的焊罩之開口,以暴露導線204。晶片201和基板206之間的空間可填入化合物,形成封裝體(encapsulation body)205。 1 is a schematic diagram showing a wafer 201 on a bump-on-trace (BOT) structure to form a flip-chip (FC) package, according to an embodiment. Substrate 206 can have a plurality of sub-layers. The two sub-layers of substrate 206 shown in Figure 1 are for illustrative purposes only and are not limiting. A plurality of balls 207 located below the substrate 206 may form a ball grid array (BGA). The wafer 201 is connected to the substrate 206 by a plurality of interconnects, each of which includes a copper pillar bump or post 202 and solder balls 203. Solder balls 203 are placed on wires 204, and wires 204 are formed on the base On board 206. The solder mask 211 is formed on the surface of the substrate 206 to cover the wires. An opening of a solder mask called a solder mask trench is formed to expose the wire 204. The space between the wafer 201 and the substrate 206 can be filled with a compound to form an encapsulation body 205.
第2a圖係根據一實施方式繪示出基板206上單一個焊罩溝槽210,其可為第1圖中暴露出導線且連接至晶片201之任一溝槽。導線204形成於基板206之表面上。焊罩層211可形成於導線上覆蓋導線與基板206之表面。溝槽可在焊罩層211中形成開口,以形成焊罩溝槽210暴露出導線204。溝槽具有足夠大的開口,使互連如焊球203可直接落在開口中之導線上。舉例而言,焊罩溝槽具有大约焊凸塊直徑之尺寸。導線204可藉由互連之方式連接至晶片201。互連可包含焊凸塊203與支柱(post)如銅柱202,其中焊球203直接被放置於導線204上,且被焊罩溝槽圍繞。第2a圖中所示之結構僅用於說明之目的並非限制。可構想另外的實施方式。 2a is a single solder mask trench 210 on substrate 206, which may be one of the trenches exposed in FIG. 1 and connected to wafer 201, in accordance with an embodiment. A wire 204 is formed on the surface of the substrate 206. The solder mask layer 211 may be formed on the wire to cover the surface of the wire and the substrate 206. The trench may form an opening in the solder mask layer 211 to form the solder mask trench 210 exposing the wire 204. The trench has a sufficiently large opening such that the interconnect, such as solder ball 203, can land directly on the wire in the opening. For example, the shroud trench has a size that is approximately the diameter of the solder bump. Wires 204 can be connected to wafer 201 by interconnection. The interconnect may include solder bumps 203 and posts such as copper pillars 202, wherein solder balls 203 are placed directly on conductors 204 and surrounded by solder mask trenches. The structure shown in Figure 2a is for illustrative purposes only and is not limiting. Additional embodiments are contemplated.
第2b圖繪示出支柱(post)202於導線204上之俯視圖,其被焊罩211圍繞。晶片201與基板206並未顯示於第2b圖中。 Figure 2b depicts a top view of post 202 on wire 204, which is surrounded by solder mask 211. The wafer 201 and the substrate 206 are not shown in FIG. 2b.
第2c圖繪示出第2a圖中所示之實施方式的示例式製造過程。第2c圖中所示之製程的詳細內容闡明如下。 Figure 2c depicts an exemplary manufacturing process of the embodiment shown in Figure 2a. The details of the process shown in Figure 2c are set forth below.
製程開始於步驟220,提供基板如第2a圖中之基板206。基板206可提供封裝具有機械性支撐,與允許外部元件進入封裝內裝置之界面。基板206可包含矽塊材(bulk silicon)基板、摻雜或非摻雜基板、或絕緣體上覆矽(silicon-on-insulator,SOI)基板之主動層。其他基板可包含多層基板、梯度基板(gradient substrate)、或混合式方向基板(hybrid orientation substrate)。基板206可進一步為層疊式基板(laminate substrate),其係由高分子材料(polymer material)之多個薄層之堆疊而形 成,而高分子材料如雙馬來醯亞胺三氮雜苯樹脂(bismaleimide triazine),或其他類似物。 The process begins in step 220 by providing a substrate such as substrate 206 in Figure 2a. The substrate 206 can provide a mechanical support for the package and an interface that allows external components to enter the device within the package. The substrate 206 may comprise a bulk silicon substrate, a doped or undoped substrate, or an active layer of a silicon-on-insulator (SOI) substrate. Other substrates may include a multilayer substrate, a gradient substrate, or a hybrid orientation substrate. The substrate 206 may further be a laminate substrate formed by stacking a plurality of thin layers of a polymer material. And a polymer material such as bismaleimide triazine, or the like.
導線204可位於基板206之表面上。導線204可用於擴張晶粒之佔用面積(footprint)。導線之寬度或直徑可大約與球(或凸塊)之直徑相同,或可高達二至四倍的窄於球(或凸塊)之直徑。舉例而言,導線204可具有介於约10微米(μm)與40微米(μm)間之線寬,及介於約30微米(μm)與70微米(μm)間之導線間距P。導線可具有窄、寬或錐狀。導線之末端相較於導線之主體可為不同之形狀。導線主體可為實質上不變之厚度。導線之末端與導線之主體形成為一體,其與放置櫬墊於導線上不同。導線可具有較球(或凸塊)直徑長的長度。另一方面,連接襯墊可具有與球或凸塊直徑相似之長度或寬度。 Wires 204 can be located on the surface of substrate 206. Wire 204 can be used to expand the footprint of the die. The width or diameter of the wire may be approximately the same as the diameter of the ball (or bump), or may be as narrow as two to four times the diameter of the ball (or bump). For example, wire 204 can have a line width between about 10 micrometers (μm) and 40 micrometers (μm), and a wire spacing P between about 30 micrometers (μm) and 70 micrometers (μm). The wires can be narrow, wide or tapered. The ends of the wires may be of different shapes than the bodies of the wires. The wire body can be of substantially constant thickness. The end of the wire is formed integrally with the body of the wire, which is different from placing the pad on the wire. The wire may have a length that is longer than the diameter of the ball (or bump). Alternatively, the attachment pad can have a length or width that is similar to the diameter of the ball or bump.
可有多個導線於基板上,每個導線電性絕緣於另一個導線,且兩個導線間之空間可介於10微米與40微米之間。 There may be multiple wires on the substrate, each wire being electrically insulated from the other wire, and the space between the two wires may be between 10 microns and 40 microns.
舉例而言,導線204可包含導電材料如鋁(Al)、銅(Cu)、金(Au)、其合金、其他材料、或其組合及/或其多層。替代地,導線204可包含其他材料。在一些實施方式中,介電層可覆蓋導線204之一些部分。導線204可被塗佈於導線204上之金屬拋光層(metal finish)所覆蓋,而金屬拋光層例如有機膜層或如鎳(Ni)/鈀(Pd)/金(Au)之混合材料層。 For example, the wire 204 can comprise a conductive material such as aluminum (Al), copper (Cu), gold (Au), alloys thereof, other materials, or combinations thereof, and/or multilayers thereof. Alternatively, wire 204 can comprise other materials. In some embodiments, the dielectric layer can cover portions of the wire 204. The wire 204 may be covered by a metal finish coated on the wire 204, such as an organic film layer or a mixed material layer such as nickel (Ni) / palladium (Pd) / gold (Au).
導線204與基板僅藉由介於其二者間之界面附著連接,其可能未具有足夠的抓力,因而在導線204與基板206間無法形成強大的連結。 The wire 204 and the substrate are attached by only the interface therebetween, which may not have sufficient grip force, and thus a strong bond cannot be formed between the wire 204 and the substrate 206.
在步驟221,焊罩層如第2a圖中所示之焊罩層211,其可形成於基板206之表面上覆蓋導線204與基板之表面。焊罩層211可執行數個功能,包含提供基板上導線間之電性絕緣抗性(electrical insulation resistance)、化學及腐蝕抗性或保護、機械式(刮、磨)保護、焊表面上之邊界、導線上額外的抓力以及改善介電可靠度。焊罩層提供導線204與基板206間額外的抓力,因為焊罩、導線、基板形成一個三明治結構(sandwich structure),其中焊罩與基板”夾”住導線。 In step 221, the solder mask layer is as shown in FIG. 2a, which can be formed on the surface of the substrate 206 to cover the surface of the wire 204 and the substrate. The solder mask layer 211 can perform several functions, including providing electrical insulation resistance between the wires on the substrate (electrical insulation) Resistance), chemical and corrosion resistance or protection, mechanical (scraping, grinding) protection, boundary on the solder surface, additional grip on the wire, and improved dielectric reliability. The shroud layer provides additional grip between the wire 204 and the substrate 206 because the shroud, wire, and substrate form a sandwich structure in which the shroud and the substrate "snap" the wire.
焊罩層211可形成於單一步驟,藉由網印(screening)基板表面上之濕式膜,而後藉由烤箱烘烤(oven baking)固化所述濕式膜。焊罩層211之厚度可為約30至40微米(通常約為35微米)。焊罩層可包含高分子材料。 The solder mask layer 211 can be formed in a single step by screening a wet film on the surface of the substrate and then curing the wet film by oven baking. The thickness of the solder mask layer 211 can be from about 30 to 40 microns (typically about 35 microns). The solder mask layer may comprise a polymer material.
在步驟223,溝槽可在焊罩層211中形成開口,以形成焊罩溝槽210暴露出導線204,如第2a圖中所示。溝槽具有足夠大的開口,使互連如焊球203可直接落在開口中之導線上。較寬的開口抓住焊球可增加焊球與導線間之連接強度。因而開口的尺寸為有彈性的,且可隨著連接至導線所使用的焊球尺寸而改變。藉由濕式膜而形成之焊罩層211,可依據一圖案進行網印以形成焊罩溝槽210。舉例而言,具有焊罩溝槽之焊罩層可先被放置於滾筒上以印刷於基板上。替代地,感光材料可用於圖案化焊罩溝槽以固化膜。可形成焊罩溝槽210暴露出導線204,以與之後將安裝在基板上之晶粒更進一步地形成適當的電性連接。 At step 223, the trench may form an opening in the solder mask layer 211 to form the solder mask trench 210 exposing the trace 204, as shown in FIG. 2a. The trench has a sufficiently large opening such that the interconnect, such as solder ball 203, can land directly on the wire in the opening. The wider opening of the solder ball can increase the strength of the connection between the solder ball and the wire. Thus the size of the opening is resilient and can vary with the size of the solder balls used to connect to the wires. The solder mask layer 211 formed by the wet film can be screen printed according to a pattern to form the solder mask trench 210. For example, a solder mask layer having a solder mask trench can be placed on the roller to be printed on the substrate. Alternatively, a photosensitive material can be used to pattern the solder mask trench to cure the film. The shroud trench 210 can be formed to expose the wire 204 to further form an appropriate electrical connection with the die that will later be mounted on the substrate.
可施加焊接熔劑(solder flux)(未顯示)至導線。熔劑(flux)主要用來幫助焊料之流動,使焊球203與在基板上之導線具有良好的接觸。此可被施加於任一變化的方法,包含刷(brushing)或噴(spraying)。熔劑通常具有酸性成分,其自焊表面移除氧化障壁,以及附著品質,其幫助於組裝製程期間,避免晶片在基板上移動。 A solder flux (not shown) can be applied to the wire. Flux is primarily used to aid in the flow of solder, allowing solder balls 203 to have good contact with the wires on the substrate. This can be applied to any changing method, including brushing or spraying. Fluxes typically have an acidic component that removes the oxidative barrier from the solder surface and adhesion quality that helps prevent wafer movement on the substrate during the assembly process.
在步驟227,如第2a圖中所示,藉由晶片之互連方式, 晶片201可連接至導線204。如第2a圖中所示,所述互連可包含焊凸塊203及如銅柱202之支柱。溝槽具有足夠大的開口,使焊球203可直接落在開口中之導線上。 In step 227, as shown in FIG. 2a, by way of interconnecting the wafers, Wafer 201 can be connected to wire 204. As shown in FIG. 2a, the interconnects can include solder bumps 203 and pillars such as copper pillars 202. The trench has a sufficiently large opening so that the solder ball 203 can land directly on the wire in the opening.
晶片201之焊凸塊203可放置於藉由焊罩溝槽所暴露出之導線204上。焊凸塊203可包含如錫(tin)之材料,或其他合適之材料如銀(silver)、無鉛錫(lead-free tin)、銅(copper)、其組合或其他類似材料。在一實施方式中,其焊凸塊203為錫焊凸塊(tin solder bump),焊凸塊203的形成,可經由如蒸鍍(evaporation)、電鍍(electroplating)、印刷(printing)、焊料轉移(solder transfer)或植球(ball placement)所形成最初的錫層至約15微米的厚度,而後進行回焊以將材料定型為所欲之凸塊形狀。任何製造焊凸塊203的合適方法可被替代地利用。 The solder bumps 203 of the wafer 201 can be placed on the wires 204 exposed by the solder mask trenches. Solder bumps 203 may comprise materials such as tin, or other suitable materials such as silver, lead-free tin, copper, combinations thereof, or the like. In one embodiment, the solder bumps 203 are tin solder bumps, and the solder bumps 203 are formed by, for example, evaporation, electroplating, printing, solder transfer. The original tin layer formed by ball transfer or ball placement is to a thickness of about 15 microns and then reflowed to shape the material into the desired bump shape. Any suitable method of making the solder bumps 203 can be used instead.
晶片如第2a圖中所示之晶片201藉由焊凸塊203與支柱202可連接至導線204。支柱202可形成於晶片201上。支柱202可為銅柱或其他熔點高於300℃之金屬。可對準晶片201,使支柱202放置至焊凸塊203上。晶片可為記憶晶片或任何其他功能之晶片。 The wafer 201 as shown in FIG. 2a can be connected to the wire 204 by solder bumps 203 and pillars 202. The pillars 202 may be formed on the wafer 201. The struts 202 can be copper posts or other metals having a melting point above 300 °C. The wafer 201 can be aligned such that the posts 202 are placed onto the solder bumps 203. The wafer can be a memory chip or any other functional wafer.
支柱202與焊凸塊203共同形成晶片之互連,支柱202與焊凸塊203可形成為複數種適當的形狀,以避開附近的元件、控制晶片201與導線204間之連接面積或其他合適的理由。所述互連之形狀可為圓形、八邊形、矩形、細長的六邊形、橢圓形、菱形,其中細長的六邊形具有位於其相對端之兩個梯形。 The pillars 202 and the solder bumps 203 together form an interconnection of the wafers. The pillars 202 and the solder bumps 203 may be formed in a plurality of suitable shapes to avoid nearby components, control the connection area between the wafer 201 and the wires 204, or other suitable Reasons. The shape of the interconnect may be circular, octagonal, rectangular, elongated hexagonal, elliptical, diamond shaped, wherein the elongated hexagon has two trapezoids at opposite ends thereof.
在步驟231,執行回流製程。如第2a圖中所示,在晶片201結合至導線後,可施加熱至晶片201與基板206,導致焊球203回焊且形成晶片201與基板206間之電性連接。對於一實施方式,所述熱溫度可至約220℃。 At step 231, a reflow process is performed. As shown in FIG. 2a, after the wafer 201 is bonded to the wire, heat can be applied to the wafer 201 and the substrate 206, causing the solder balls 203 to be reflowed and forming an electrical connection between the wafer 201 and the substrate 206. For an embodiment, the thermal temperature can be up to about 220 °C.
在步驟233,底部填膠材料,通常為熱固型環氧樹脂(thermo-set epoxy),可分配其進入晶片201與基板206間之間隔。可沿著晶片之一邊緣施加熱固型環氧樹脂之珠粒(bead),其中環氧樹脂係藉由毛細管作用(capillary action)在晶片之下方拉伸,直至其完全填充於晶片與基板間之間隔。重要的是,所屬底部填膠材料在間隔中均勻分散。 At step 233, the underfill material, typically a thermo-set epoxy, can be dispensed into the space between wafer 201 and substrate 206. A bead of a thermosetting epoxy resin may be applied along one edge of the wafer, wherein the epoxy resin is stretched under the wafer by a capillary action until it is completely filled between the wafer and the substrate The interval. It is important that the underlying filler material is evenly dispersed throughout the space.
環氧樹脂之單獨珠粒(separate bead)亦可被分散且結合圍繞於晶片201之外圍。之後,藉由將基板與晶片加熱至適當之固化溫度,固化底部填膠與外圍結合之環氧樹脂,以形成一封裝體,如第1圖中所示之封裝體205。封裝體205已填充了晶片201與基板206間之間隔。在這種方式中,當所述製程結束時,所述製程產生機械性以及電性結合半導體晶片組裝。 A separate bead of epoxy resin may also be dispersed and bonded around the periphery of the wafer 201. Thereafter, the underfill and the peripherally bonded epoxy are cured by heating the substrate and the wafer to a suitable curing temperature to form a package such as the package 205 shown in FIG. The package 205 has been filled with a gap between the wafer 201 and the substrate 206. In this manner, the process produces a mechanical and electrical combination of semiconductor wafer assembly when the process is complete.
第3圖繪示出藉由BOT結構所形成半導體封裝之基板的俯視圖。基板之表面除了區域301外可藉由焊罩覆蓋。焊罩亦可覆蓋其他形狀基板之表面。複數個焊罩溝槽311可形成於焊罩層上。焊罩溝槽圍繞基板之中心區域並形成複數個焊罩溝槽環。焊罩溝槽之形狀係依據基板上之導線的輪廓(contour),有其他形狀可替代所形成之焊罩環。有三個所述之焊罩溝槽環形成於第3圖中,亦可有其他數量之焊罩溝槽環形成。可放置複數個支柱或互連如2021與2022於焊罩溝槽內所暴露出之導線上。兩個支柱或兩個互連間之間距可小於約140微米。 FIG. 3 is a plan view showing a substrate of a semiconductor package formed by a BOT structure. The surface of the substrate can be covered by a solder mask in addition to the region 301. The solder mask can also cover the surface of other shaped substrates. A plurality of solder mask trenches 311 may be formed on the solder mask layer. The shroud trench surrounds a central region of the substrate and forms a plurality of shroud trench rings. The shape of the shroud trench is based on the contour of the wire on the substrate, and other shapes may be substituted for the formed shroud ring. Three of the described shroud groove rings are formed in Figure 3, and other numbers of shroud groove rings may be formed. A plurality of struts or interconnects such as 2021 and 2022 can be placed over the wires exposed in the shroud trenches. The distance between the two pillars or the two interconnects can be less than about 140 microns.
在其他實施方式中,焊罩自晶粒附著區域(die-attach area)移除,如晶粒或其他基板可附著之區域,及排除區域(keep-out region)(例如緊密圍繞於晶粒附著區域之區域)。更詳細說明如下,將移除焊罩材料,以使晶粒正下方區域及緊密圍繞區域被移除。焊罩材料 被移除之面積尺寸大於晶粒之尺寸。確定焊罩材料被移除之面積尺寸,使晶粒邊緣與焊罩邊緣間之側面區域,允許經由完全填充晶粒與下方基板間之區域的方式施加底部填膠材料,不留下暴露出之導線。 In other embodiments, the solder mask is removed from a die-attach area, such as a region where the die or other substrate can be attached, and a keep-out region (eg, closely surrounding the die attach) Area of the area). As described in more detail below, the shroud material will be removed such that the area directly under the die and the tight surrounding area are removed. Welding cover material The size of the removed area is larger than the size of the die. Determining the size of the area in which the shroud material is removed, such that the side regions between the edge of the die and the edge of the shroud allow the underfill material to be applied by completely filling the area between the die and the underlying substrate, leaving no exposure wire.
舉例而言,在一些情況中,晶粒邊緣與焊罩邊緣間之側面區域太小,底部填膠材料可能無法完全填充晶粒與下方基板間之區域,允許一或多個空隙形成於晶粒與下方基板之間。在其他情況中,晶粒邊緣與焊罩邊緣間之側面區域太大,導線可能仍被暴露出。已發現藉由控制晶粒邊緣與焊罩邊緣之距離寬度,及/或控制晶粒邊緣與焊罩邊緣間之區域面積和晶粒面積之比值,底部填膠可完全填充晶粒與下方基板間之區域並覆蓋導線,因而對於晶粒與下方基板間之電性連接提供保護,亦對於下方基板上之導線提供保護。 For example, in some cases, the side area between the edge of the die and the edge of the shroud is too small, and the underfill material may not completely fill the area between the die and the underlying substrate, allowing one or more voids to be formed in the die. Between the substrate and the lower substrate. In other cases, the side areas between the edge of the die and the edge of the weld bead are too large and the wire may still be exposed. It has been found that by controlling the distance between the edge of the die and the edge of the bead, and/or controlling the ratio of the area of the die to the area of the die and the area of the die, the underfill can completely fill the die and the underlying substrate. The area covers the wires, thereby providing protection for the electrical connection between the die and the underlying substrate, as well as for the wires on the underlying substrate.
值得注意的是,在此關於晶粒附著至基板的討論係用於說明目的,以解釋多個實施方式之特徵。在其他實施方式中,晶粒可為另一基板,如封裝(package)、封裝基板(packaging substrate)、中介基板(interposer)、晶粒(die)、印刷電路板(printed circuit board)或其他類似物。 It is noted that the discussion herein regarding the attachment of the die to the substrate is for illustrative purposes to explain the features of various embodiments. In other embodiments, the die may be another substrate, such as a package, a packaging substrate, an interposer, a die, a printed circuit board, or the like. Things.
第4a-6b圖係根據一些實施方式繪示出形成製程之各種中間階段,其中”A”圖為平面圖,而”B”圖為沿著對應”A”圖之B-B線的剖面圖。首先參照第4a、4b圖,其繪示出第一基板402之平面圖以及沿著第4a圖中B-B線之剖面圖。第一基板402可為,例如積體電路晶粒、封裝基板、晶圓(wafer)、印刷電路板、中介基板或其他類似物。在一些實施方式中,使用BOT配置。舉例而言,第4a、4b圖繪示出導線404。一般來說,導線404發送電性訊號至想要的位置及/或用於擴張晶粒之佔用面積。導線404之寬度或直徑可大約與球(或凸塊)之直徑相同,或 高達二至三倍的窄於球(或凸塊)之直徑。舉例而言,導線404可具有介於約10微米與40微米間之線寬,以及介於30微米與70微米間之導線間距P。導線可具有窄、寬或錐狀。在一些實施方式中,導線之末端404a相較於導線之主體可為不同之形狀,或導線主體可為實質上不變之厚度。導線之末端404a與導線之主體形成為一體,其與放置櫬墊於導線上不同。導線可具有實質上較球(或凸塊)直徑長的長度。另一方面,連接襯墊可具有與球或凸塊直徑相似之長度或寬度。 4a-6b illustrate various intermediate stages of forming a process in accordance with some embodiments, wherein the "A" diagram is a plan view and the "B" diagram is a cross-sectional view along line B-B of the corresponding "A" diagram. Referring first to Figures 4a and 4b, a plan view of the first substrate 402 and a cross-sectional view taken along line B-B of Figure 4a are shown. The first substrate 402 can be, for example, an integrated circuit die, a package substrate, a wafer, a printed circuit board, an interposer, or the like. In some embodiments, a BOT configuration is used. For example, the wires 404 are depicted in Figures 4a, 4b. In general, wire 404 sends an electrical signal to a desired location and/or an area used to expand the die. The width or diameter of the wire 404 can be approximately the same as the diameter of the ball (or bump), or Up to two to three times narrower than the diameter of the ball (or bump). For example, wire 404 can have a line width between about 10 microns and 40 microns, and a wire pitch P between 30 microns and 70 microns. The wires can be narrow, wide or tapered. In some embodiments, the ends 404a of the wires can be of different shapes than the body of the wires, or the body of the wires can be of substantially constant thickness. The end 404a of the wire is formed integrally with the body of the wire, which is different from placing the pad on the wire. The wire can have a length that is substantially longer than the diameter of the ball (or bump). Alternatively, the attachment pad can have a length or width that is similar to the diameter of the ball or bump.
在一些實施方式中,舉例而言,導線404可包含導電材料如鋁(Al)、銅(Cu)、金(Au)、其合金、其他材料、或其組合及/或其多層。替代地,導線404可包含其他材料。導線404可被塗佈於導線404上之金屬拋光層所覆蓋,而金屬拋光層例如有機膜層或如鎳(Ni)/鈀(Pd)/金(Au)之混合材料層。在一些實施方式中,鄰近導線間之間距可介於約10微米與40微米間。 In some embodiments, for example, wire 404 can comprise a conductive material such as aluminum (Al), copper (Cu), gold (Au), alloys thereof, other materials, or combinations thereof, and/or multilayers thereof. Alternatively, wire 404 can comprise other materials. The wire 404 can be covered by a metal polishing layer coated on the wire 404, such as an organic film layer or a mixed material layer such as nickel (Ni) / palladium (Pd) / gold (Au). In some embodiments, the distance between adjacent wires can be between about 10 microns and 40 microns.
第4a、4b圖更進一步繪示出保護層406。一般而言,保護層406提供保護,使其免受環境汙染物、基板上電路導線間之電性絕緣抗性、化學及腐蝕抗性或保護、機械式(刮、磨)保護、焊表面上之邊界、導線及/或基板上額外的抓力以及改善介電可靠度。在一些實施方式中,舉例而言,保護層406為高分子或其他介電材料。在一些實施方式中,舉例而言,保護層406為高分子,而其係藉由網印或旋轉塗佈、圖案化與之後的固化所形成。 The protective layer 406 is further illustrated in Figures 4a, 4b. In general, the protective layer 406 provides protection from environmental contaminants, electrical insulation resistance between circuit leads on the substrate, chemical and corrosion resistance or protection, mechanical (scraping, grinding) protection, on the solder surface. Additional grip on the boundaries, wires and/or substrate and improved dielectric reliability. In some embodiments, for example, the protective layer 406 is a polymeric or other dielectric material. In some embodiments, for example, the protective layer 406 is a polymer that is formed by screen printing or spin coating, patterning, and subsequent curing.
保護層406覆蓋導線404之部分,例如第一基板402之周圍區域中之導線的部分。舉例而言,第4a圖繪示出一實施方式,保護層406形成圍繞於晶粒附著區域408(如第4a圖中所示之虛線輪廓)且與其分離。更詳細說明如下,晶粒附著區域408表示將被放置的另一基板 上之一區域。保護層406將保護導線404免於外部環境汙染物,且其尺寸可允許底部填膠完全填充晶粒與第一基板402間之區域同時亦覆蓋暴露出之導線404。保護層406之厚度可為约30微米至約40微米,如約35微米。 The protective layer 406 covers portions of the wires 404, such as portions of the wires in the surrounding area of the first substrate 402. For example, Figure 4a depicts an embodiment in which the protective layer 406 is formed around and separated from the die attach region 408 (as shown by the dashed outline shown in Figure 4a). As described in more detail below, the die attach region 408 represents another substrate to be placed One of the areas above. The protective layer 406 protects the protective conductor 404 from external environmental contaminants and is sized to allow the underfill to completely fill the area between the die and the first substrate 402 while also covering the exposed wires 404. The protective layer 406 can have a thickness of from about 30 microns to about 40 microns, such as about 35 microns.
現在參照第5a、5b圖,其顯示出第4a、4b圖之第一基板402在第二基板520已附著至第一基板402後之一些實施方式。舉例而言,第二基板520可為晶粒、基板、晶圓、封裝基板、印刷電路板或其他類似物。第二基板520藉由電性連接器(connector)522電性耦接至第一基板。在一些實施方式中,電性連接器522包含導電柱522a(例如銅柱)與焊接材料552b彼此耦接,然而亦可使用其他電性連接器。 Referring now to Figures 5a, 5b, there are shown some embodiments of the first substrate 402 of Figures 4a, 4b after the second substrate 520 has been attached to the first substrate 402. For example, the second substrate 520 can be a die, a substrate, a wafer, a package substrate, a printed circuit board, or the like. The second substrate 520 is electrically coupled to the first substrate by an electrical connector 522. In some embodiments, the electrical connector 522 includes conductive posts 522a (eg, copper posts) and solder material 552b coupled to each other, although other electrical connectors may be used.
在一些實施方式中,第一基板402為積體電路晶粒,而第二基板520為晶圓,其中結合基板於覆晶型晶片尺寸封裝(flip-chip chip-scale package,FCCSP)中。之後單片化晶圓以形成個別封裝(separate package)。然而,亦可使用其他配置。 In some embodiments, the first substrate 402 is an integrated circuit die, and the second substrate 520 is a wafer, wherein the bonding substrate is in a flip-chip chip-scale package (FCCSP). The wafers are then singulated to form a separate package. However, other configurations are also possible.
如第5a、5b圖所示,排除區域(keep-out-region,KOR)524位於第二基板520與保護層406間且延伸圍繞第二基板520。在一些實施方式中,排除區域524包含藉由排除距離(keep-out distance,KOD)D1將保護層406內緣與第二基板520邊緣間隔開之一區域。在一些實施方式中,排除區域524之面積為第二基板520之面積的約5%至約18%。舉例而言,第二基板520之面積為寬度W1乘以長度L1,排除區域524之面積與第二基板520之面積的比值(例如寬度W1乘以長度L1)係介於約1:20至約9:50。此外,在一些實施方式中,排除距離D1大於或等於420微米。 As shown in FIGS. 5a and 5b, a keep-out-region (KOR) 524 is located between the second substrate 520 and the protective layer 406 and extends around the second substrate 520. In some embodiments, the exclusion region 524 includes a region that separates the inner edge of the protective layer 406 from the edge of the second substrate 520 by a keep-out distance (KOD) D 1 . In some embodiments, the area of the exclusion zone 524 is from about 5% to about 18% of the area of the second substrate 520. For example, the area of the second substrate 520 is multiplied by the width W 1 of length L 1, the area ratio of the area of the second region 524 of the substrate 520 (e.g., length multiplied by width W 1 of L 1) between about 1 negative line : 20 to about 9:50. Further, in some embodiments, the exclusion distance D 1 is greater than or equal to 420 microns.
已發現利用這些指標(排除區域524之面積與第二基板 520之面積的比值以及排除距離之最小尺寸),保護層406邊緣與第二基板間所提供之足夠的距離可允許之後施加底部填膠材料,使底部填膠材料將為實質上無空隙(void-free)且覆蓋排除區域524中所暴露出之導線。如上所述,較小的距離可能造成第一基板402與第二基板520間較差的填充能力,因而造成空隙,而較大的距離可能導致暴露出排除區域524中之導線。維持上述之排除距離與排除區域524解決這些問題,避免或降低第一基板402與第二基板520間空隙的發生,且提供排除區域524中暴露出之導線較好的覆蓋率。 It has been found that the use of these indicators (excluding the area of the area 524 and the second substrate The ratio of the area of 520 and the minimum dimension of the exclusion distance), the sufficient distance provided between the edge of the protective layer 406 and the second substrate allows the underfill material to be applied afterwards so that the underfill material will be substantially void free (void -free) and covering the exposed wires in the exclusion area 524. As noted above, a smaller distance may result in a poorer fill capability between the first substrate 402 and the second substrate 520, thereby creating voids, while larger distances may result in exposure of the wires in the exclusion region 524. Maintaining the exclusion distance and exclusion region 524 described above solves these problems, avoids or reduces the occurrence of voids between the first substrate 402 and the second substrate 520, and provides better coverage of the exposed wires in the exclusion region 524.
第6a、6b圖係根據一些實施方式繪示出第一基板402與第二基板520,其具有底部填膠650插設於其二者間。在一些實施方式中,底部填膠650包含高分子、熱固型環氧樹脂或其他類似物,其分配進入第二基板520與保護層406間之間隔,例如排除區域524。舉例而言,在一些實施方式中,底部填膠材料為具有二氧化矽填充材料之高分子化合物。可沿著晶片之一邊緣施加底部填膠650之珠粒,其中底部填膠650係藉由毛細管作用在晶片之下方拉伸,直至其完全填充於第一基板402與第二基板520間之間隔。 6a, 6b illustrate a first substrate 402 and a second substrate 520 having a bottom fill 650 interposed therebetween, in accordance with some embodiments. In some embodiments, the underfill 650 comprises a polymer, a thermoset epoxy or the like that is dispensed into the space between the second substrate 520 and the protective layer 406, such as the exclusion region 524. For example, in some embodiments, the underfill material is a high molecular compound having a ceria filler material. The beads of the underfill 650 can be applied along one edge of the wafer, wherein the underfill 650 is stretched under the wafer by capillary action until it is completely filled between the first substrate 402 and the second substrate 520. .
第7圖係根據一些實施方式繪示出製造過程之流程圖。所述製程起始於步驟702,其中提供第一基板,使第一基板包含晶粒附著區域、排除區域及周圍區域,其中保護層保護周圍區域中之導線,如參照上述第4a、4b圖。在步驟704,提供第二基板,而在步驟706中第二基板附著至第一基板,如參照上述第5a、5b圖。第一基板附著至第二基板之方式,係提供第一基板與保護層最接近一邊緣間之排除區域與排除距離。在步驟708,底部填膠放置於第一基板與第二基板間。當提供保護予排除區域內之導線時,維持上述之排除區域與排除距 離,可讓之後放置之底部填膠具有很少的空隙或不具有空隙。 Figure 7 is a flow chart illustrating a manufacturing process in accordance with some embodiments. The process begins in step 702, in which a first substrate is provided such that the first substrate includes a die attach region, a exclusion region, and a surrounding region, wherein the protective layer protects the wires in the surrounding region, as described with reference to Figures 4a, 4b above. In step 704, a second substrate is provided, and in step 706 the second substrate is attached to the first substrate, as described with reference to Figures 5a, 5b above. The manner in which the first substrate is attached to the second substrate is to provide an exclusion region and an exclusion distance between the first substrate and the protective layer closest to an edge. At step 708, the underfill is placed between the first substrate and the second substrate. Maintaining the above exclusion and exclusion distances when providing protection to the wires in the exclusion zone This allows the underfill to be placed with little or no voids.
在一實施方式中,提供一種半導體裝置。所述裝置包含第一基板具有導線形成於其上。第一基板具有晶粒附著區域,排除區域圍繞於該晶粒附著區域之周圍,及一周圍區域圍繞於該排除區域之周圍。第一基板具有保護層上覆周圍區域中之導線。第二基板電性耦接至第一基板於晶粒附著區域中;以及底部填膠夾設於第一基板與第二基板之間,底部填膠在位於排除區域中之導線的上方延伸;其中排除區域的面積佔第二基板的面積約5%至約18%。 In an embodiment, a semiconductor device is provided. The device includes a first substrate having a wire formed thereon. The first substrate has a die attaching region, the exclusion region surrounds the periphery of the die attach region, and a surrounding region surrounds the periphery of the exclusion region. The first substrate has a wire overlying the surrounding area of the protective layer. The second substrate is electrically coupled to the first substrate in the die attach region; and the bottom filler is sandwiched between the first substrate and the second substrate, and the bottom filler extends over the wires in the exclusion region; The area of the exclusion zone accounts for about 5% to about 18% of the area of the second substrate.
在另一實施方式中,提供一種半導體裝置。所述裝置包含第一基板具有晶粒附著區域、周圍區域及排除區域夾設於晶粒附著區域與周圍區域之間,其中保護層覆蓋周圍區域中之導線,且其中保護層不會延伸進入晶粒附著區域與排除區域。第二基板電性耦接至第一基板,使第二基板位於第一基板之晶粒附著區域的上方。晶粒附著區域相當於第一基板位於第二基板正下方之區域,而排除區域自保護層之邊界延伸至晶粒附著區域之邊界。排除區域的面積佔該第二基板的面積約5%至約18%。 In another embodiment, a semiconductor device is provided. The device includes a first substrate having a die attach region, a surrounding region and a exclusion region interposed between the die attach region and the surrounding region, wherein the protective layer covers the wires in the surrounding region, and wherein the protective layer does not extend into the crystal Grain attachment area and exclusion area. The second substrate is electrically coupled to the first substrate such that the second substrate is located above the die attach region of the first substrate. The die attach region corresponds to a region where the first substrate is directly under the second substrate, and the exclusion region extends from the boundary of the protective layer to the boundary of the die attach region. The area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate.
在又一實施方式,提供一種形成半導體裝置之方法,所述方法包含提供第一基板,第一基板具有導線形成於其上,並形成保護層於第一基板之一部分的上方。將第二基板附著至第一基板。排除區域在保護層之邊界與第二基板之周圍間延伸,其中排除區域的面積佔第二基板的面積約5%至約18%。 In still another embodiment, a method of forming a semiconductor device is provided, the method comprising providing a first substrate having a wire formed thereon and forming a protective layer over a portion of the first substrate. The second substrate is attached to the first substrate. The exclusion region extends between the boundary of the protective layer and the periphery of the second substrate, wherein the area of the exclusion region accounts for about 5% to about 18% of the area of the second substrate.
前面已概述了數個實施方式的特徵。本技術領域中具有通常知識者應當理解,其可以使用本發明內容作為用於實現相同目的及/或實現本文中所介紹的實施方式中相同的優點設計或修改其他過 程和結構之基礎。本技術領域中具有通常知識者也應該認識到,此類等效構造不脫離本發明內容中所揭露的精神和範圍,並且可以對其進行各種改變,替代和變更,而不脫離本發明內容之精神和範圍。 The features of several embodiments have been outlined above. It should be understood by those of ordinary skill in the art that the present invention can be used to implement the same objectives and/or achieve the same advantages in the embodiments described herein. The basis of the process and structure. It is also to be understood by those skilled in the art that such equivalents are not to be Spirit and scope.
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/459,047 US9165796B2 (en) | 2012-04-18 | 2014-08-13 | Methods and apparatus for bump-on-trace chip packaging |
US14/459,047 | 2014-08-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201611134A TW201611134A (en) | 2016-03-16 |
TWI642119B true TWI642119B (en) | 2018-11-21 |
Family
ID=55449253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW104126411A TWI642119B (en) | 2014-08-13 | 2015-08-13 | Semiconductor device and method of forming the same |
Country Status (3)
Country | Link |
---|---|
KR (2) | KR20160020347A (en) |
CN (1) | CN105762087B (en) |
TW (1) | TWI642119B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10276382B2 (en) | 2016-08-11 | 2019-04-30 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages and stacked package assemblies including high density interconnections |
CN112635335B (en) * | 2020-12-11 | 2021-11-02 | 广东佛智芯微电子技术研究有限公司 | Chip packaging method and chip packaging structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5647123A (en) * | 1995-10-16 | 1997-07-15 | Motorola, Inc. | Method for improving distribution of underfill between a flip chip die and a circuit board |
US20070096336A1 (en) * | 2005-11-02 | 2007-05-03 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and substrate structure thereof |
TW201430970A (en) * | 2012-12-27 | 2014-08-01 | Renesas Electronics Corp | Method of manufacturing semiconductor device and semiconductor device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI245402B (en) | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
US7057284B2 (en) * | 2004-08-12 | 2006-06-06 | Texas Instruments Incorporated | Fine pitch low-cost flip chip substrate |
US8604624B2 (en) | 2008-03-19 | 2013-12-10 | Stats Chippac Ltd. | Flip chip interconnection system having solder position control mechanism |
US20100007015A1 (en) * | 2008-07-11 | 2010-01-14 | Bernardo Gallegos | Integrated circuit device with improved underfill coverage |
US9355962B2 (en) * | 2009-06-12 | 2016-05-31 | Stats Chippac Ltd. | Integrated circuit package stacking system with redistribution and method of manufacture thereof |
US8089148B1 (en) * | 2009-08-11 | 2012-01-03 | Amkor Technology, Inc. | Circuit board and semiconductor device having the same |
US20130277828A1 (en) * | 2012-04-18 | 2013-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for bump-on-trace Chip Packaging |
-
2014
- 2014-12-19 CN CN201410800491.8A patent/CN105762087B/en active Active
-
2015
- 2015-07-08 KR KR1020150097255A patent/KR20160020347A/en active Application Filing
- 2015-08-13 TW TW104126411A patent/TWI642119B/en active
-
2017
- 2017-05-22 KR KR1020170062994A patent/KR101887306B1/en active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5647123A (en) * | 1995-10-16 | 1997-07-15 | Motorola, Inc. | Method for improving distribution of underfill between a flip chip die and a circuit board |
US20070096336A1 (en) * | 2005-11-02 | 2007-05-03 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and substrate structure thereof |
TW201430970A (en) * | 2012-12-27 | 2014-08-01 | Renesas Electronics Corp | Method of manufacturing semiconductor device and semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR20170060612A (en) | 2017-06-01 |
KR101887306B1 (en) | 2018-08-09 |
TW201611134A (en) | 2016-03-16 |
CN105762087B (en) | 2019-01-11 |
KR20160020347A (en) | 2016-02-23 |
CN105762087A (en) | 2016-07-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11612057B2 (en) | Opening in the pad for bonding integrated passive device in InFO package | |
US9583367B2 (en) | Methods and apparatus for bump-on-trace chip packaging | |
US11837587B2 (en) | Package structure and manufacturing method thereof | |
TWI529886B (en) | Packages, methods of packaging a device and package on package devices | |
US20170301637A1 (en) | Contact Pad For Semiconductor Device | |
TWI567900B (en) | Semiconductor device and package assembly | |
US11004812B2 (en) | Package structure and method of forming the same | |
US7863740B2 (en) | Semiconductor device having conductive bumps, metallic layers, covering layers and fabrication method thereof | |
US9299606B2 (en) | Fabricating pillar solder bump | |
JPH11233687A (en) | Semiconductor device having sub-chip scale package structure and manufacture thereof | |
US9171814B2 (en) | Method of manufacturing semiconductor device and semiconductor device | |
US20130277828A1 (en) | Methods and Apparatus for bump-on-trace Chip Packaging | |
US9379076B2 (en) | Semiconductor device and manufacturing method thereof | |
TWI642119B (en) | Semiconductor device and method of forming the same | |
US7344971B2 (en) | Manufacturing method of semiconductor device | |
WO2018198544A1 (en) | Method for manufacturing semiconductor device, and semiconductor device | |
TWI839093B (en) | Manufacturing method of electronic structure | |
TWI843675B (en) | Electronic package and electronic structure thereof | |
US11810847B2 (en) | Package structure and method of fabricating the same | |
US20240063130A1 (en) | Package structure and fabricating method thereof | |
US20230063270A1 (en) | Semiconductor die package with ring structure and method for forming the same | |
CN109390307B (en) | Semiconductor device and method for manufacturing the same | |
CN118412327A (en) | Electronic package, electronic structure and manufacturing method thereof |