TWI642116B - A method of manufacturing a semiconductor device - Google Patents
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Abstract
製作半導體元件的方法包含以下操作：提供一基材；形成圖案化遮罩層於基材上，圖案化遮罩層具有第一開口，第一開口暴露出基材的一部分；移除暴露的基材部分，以在基材中形成凹槽，凹槽具有底部和側壁；經由第一開口在凹槽的底部和側壁摻雜第一n型摻雜劑，以形成電洞阻隔層包圍凹槽的底部和側壁；以及形成p型磊晶層於凹槽中。 The method of fabricating a semiconductor device includes the steps of: providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer having a first opening, the first opening exposing a portion of the substrate; removing the exposed substrate a portion for forming a recess in the substrate, the recess having a bottom and a sidewall; wherein the first n-type dopant is doped at the bottom and sidewall of the recess via the first opening to form a hole barrier surrounding the recess a bottom and a sidewall; and forming a p-type epitaxial layer in the recess.
Description
本發明係關於一種半導體元件的製作方法，更詳細係關於功率半導體元件的製作方法。 The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a power semiconductor device.
由於絕緣柵雙極電晶體(insulated gate bipolar transistor,IGBT)具有高頻率、大電流等優良特性，因此被廣泛地應用於交通工具、家電、電力工程、航空、軍事等領域。近年來絕緣柵雙極電晶體各種新製程、新技術不斷的出現，使絕緣柵雙極電晶體的性能更加完善和優良。 Insulated gate bipolar transistors (IGBTs) are widely used in transportation, home appliances, power engineering, aviation, military, etc. because of their high frequency and high current. In recent years, various new processes and new technologies for insulated gate bipolar transistors have emerged, making the performance of insulated gate bipolar transistors more perfect and excellent.
但是，由於目前的製程方法皆是使用摻雜製程，需要計算n型摻雜劑及p型摻雜劑在不同溫度環境下的擴散速率，才能製作出預期的n型摻雜厚度及p型摻雜厚度。因為需要精準控制n型摻雜劑及p型摻雜劑的擴散厚度，製程的難度提高。因此，亟需改進並簡化製程，以提高生產效率與良率。 However, since the current process methods use a doping process, it is necessary to calculate the diffusion rate of the n-type dopant and the p-type dopant under different temperature environments to produce the desired n-type doping thickness and p-type doping. Mixed thickness. Because of the need to precisely control the diffusion thickness of the n-type dopant and the p-type dopant, the difficulty of the process is improved. Therefore, there is an urgent need to improve and simplify the process to increase production efficiency and yield.
本揭露之一態樣，係提供一種製作半導體元件的方法，其包含提供基材；形成圖案化遮罩層於基材上，圖案化遮罩層具有第一開口，此第一開口暴露出基材的一部分；移除暴露的基材部分，以在基材中形成凹槽，此凹槽具有底部和側壁；經由第一開口在凹槽的底部和側壁摻雜第一n型摻雜劑，以形成電洞阻隔層，此電洞阻隔層包圍凹槽的底部和側壁；以及形成p型磊晶層於凹槽中。 In one aspect of the disclosure, a method of fabricating a semiconductor device includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer having a first opening, the first opening exposing a substrate a portion of the material; removing the exposed portion of the substrate to form a recess in the substrate, the recess having a bottom and a sidewall; and doping the first n-type dopant at the bottom and sidewall of the recess via the first opening, To form a hole barrier layer, the hole barrier layer surrounds the bottom and sidewalls of the groove; and a p-type epitaxial layer is formed in the groove.
根據本揭露一或多個實施方式，基材包含p型摻雜層、n型緩衝層及n型漂移層，其中n型緩衝層位於p型摻雜層與n型漂移層之間。 According to one or more embodiments of the present disclosure, the substrate includes a p-type doped layer, an n-type buffer layer, and an n-type drift layer, wherein the n-type buffer layer is between the p-type doped layer and the n-type drift layer.
根據本揭露一或多個實施方式，其中電洞阻隔層的摻雜濃度為約1×1015至約5×1019cm-3。 According to one or more embodiments of the present disclosure, the doping concentration of the hole barrier layer is from about 1×10 15 to about 5×10 19 cm −3 .
根據本揭露一或多個實施方式，經由第一開口在凹槽的底部和側壁摻雜第一n型摻雜劑包含使用離子植入或電漿離子浸潤。 In accordance with one or more embodiments of the present disclosure, doping the first n-type dopant at the bottom and sidewalls of the trench via the first opening comprises using ion implantation or plasma ion infiltration.
根據本揭露一或多個實施方式，在形成p型磊晶層於凹槽中之後，電洞阻隔層的厚度小於或等於3μm。 According to one or more embodiments of the present disclosure, after forming the p-type epitaxial layer in the recess, the thickness of the hole barrier layer is less than or equal to 3 μm.
根據本揭露一或多個實施方式，其中凹槽具有深度為約1μm至約10μm。 In accordance with one or more embodiments of the present disclosure, the grooves have a depth of from about 1 [mu]m to about 10 [mu]m.
根據本揭露一或多個實施方式，在形成p型磊晶層於凹槽中之後，更包含平坦化p型磊晶層，其中平坦化p型磊晶層包含移除p型磊晶層的一部分以及圖案化遮罩層，而露出基材的表面、電洞阻隔層的表面及p型磊晶層的表面；形成閘極氧化層，此閘極氧化層覆蓋基材的表面、電 洞阻隔層的表面及p型磊晶層的表面；形成圖案化閘極層於閘極氧化層上，其中圖案化閘極層具有第二開口，此第二開口位於p型磊晶層上；經由第二開口在p型磊晶層中摻雜第二n型摻雜劑，而形成複數個n型源極區；形成層間介電層覆蓋圖案化閘極層；在形成層間介電層之後，在p型磊晶層形成p型摻雜區，且p型摻雜區位於這些n型源極區之間；以及形成電極層於p型摻雜區及層間介電層上，並與p型摻雜區接觸。 According to one or more embodiments of the present disclosure, after the p-type epitaxial layer is formed in the recess, the planarization of the p-type epitaxial layer is further included, wherein the planarizing the p-type epitaxial layer comprises removing the p-type epitaxial layer. Part and patterning the mask layer to expose the surface of the substrate, the surface of the hole barrier layer, and the surface of the p-type epitaxial layer; forming a gate oxide layer covering the surface of the substrate and being electrically a surface of the hole barrier layer and a surface of the p-type epitaxial layer; forming a patterned gate layer on the gate oxide layer, wherein the patterned gate layer has a second opening, the second opening is located on the p-type epitaxial layer; Doping a second n-type dopant in the p-type epitaxial layer via the second opening to form a plurality of n-type source regions; forming an interlayer dielectric layer covering the patterned gate layer; after forming the interlayer dielectric layer Forming a p-type doped region in the p-type epitaxial layer, and the p-type doped region is located between the n-type source regions; and forming an electrode layer on the p-type doped region and the interlayer dielectric layer, and Type doped regions are in contact.
根據本揭露一或多個實施方式，平坦化p型磊晶層包含使用化學機械研磨製程移除p型磊晶層的一部分；移除圖案化遮罩層，而暴露出基材；形成犧牲氧化層覆蓋p型磊晶層及基材；以及移除犧牲氧化層。 According to one or more embodiments of the present disclosure, planarizing the p-type epitaxial layer includes removing a portion of the p-type epitaxial layer using a chemical mechanical polishing process; removing the patterned mask layer to expose the substrate; forming sacrificial oxide The layer covers the p-type epitaxial layer and the substrate; and the sacrificial oxide layer is removed.
根據本揭露一或多個實施方式，在形成p型磊晶層於凹槽中之後，更包含移除遮罩層；形成犧牲氧化層覆蓋基材及p型磊晶層；在形成犧牲氧化層之後，形成複數個n型源極區於p型磊晶層中，這些n型源極區與犧牲氧化層接觸；在p型磊晶層形成p型摻雜區，且p型摻雜區位於這些n型源極區之間；在形成p型摻雜區之後，移除犧牲氧化層，而暴露出基材、電洞阻隔層、p型磊晶層中的這些n型源極區及p型摻雜區；形成閘極氧化層覆蓋基材、電洞阻隔層及p型磊晶層中的這些n型源極區及p型摻雜區；形成圖案化閘極層於閘極氧化層上，其中圖案化閘極層具有第二開口，此第二開口位於p型摻雜區及這些n型源極區上方。 According to one or more embodiments of the present disclosure, after forming the p-type epitaxial layer in the recess, the method further includes removing the mask layer; forming a sacrificial oxide layer covering the substrate and the p-type epitaxial layer; forming a sacrificial oxide layer Thereafter, a plurality of n-type source regions are formed in the p-type epitaxial layer, the n-type source regions are in contact with the sacrificial oxide layer; a p-type doped region is formed in the p-type epitaxial layer, and the p-type doped region is located Between these n-type source regions; after forming the p-type doping region, the sacrificial oxide layer is removed, and the n-type source regions in the substrate, the hole barrier layer, and the p-type epitaxial layer are exposed and p a doped region; forming a gate oxide layer covering the substrate, the hole barrier layer, and the n-type source region and the p-type doped region in the p-type epitaxial layer; forming a patterned gate layer on the gate oxide layer The patterned gate layer has a second opening, and the second opening is located above the p-type doping region and the n-type source regions.
根據本揭露一或多個實施方式，製作半導體元 件的方法更包含形成層間介電層覆蓋圖案化閘極層；以及形成電極層於p型摻雜區及層間介電層上，並與p型摻雜區接觸。 Making a semiconductor element according to one or more embodiments of the present disclosure The method further includes forming an interlayer dielectric layer over the patterned gate layer; and forming an electrode layer on the p-type doped region and the interlayer dielectric layer and contacting the p-type doped region.
根據本揭露一或多個實施方式，在形成層間介電層覆蓋閘極層之後，暴露一部分的n型源極區。 According to one or more embodiments of the present disclosure, after forming the interlayer dielectric layer to cover the gate layer, a portion of the n-type source region is exposed.
100‧‧‧基材 100‧‧‧Substrate
110‧‧‧p型摻雜層 110‧‧‧p-type doped layer
120‧‧‧n型緩衝層 120‧‧‧n type buffer layer
130‧‧‧n型漂移層 130‧‧‧n type drift layer
140‧‧‧圖案化遮罩層 140‧‧‧ patterned mask layer
150‧‧‧第一開口 150‧‧‧first opening
160‧‧‧凹槽 160‧‧‧ Groove
162‧‧‧底部 162‧‧‧ bottom
164‧‧‧側壁 164‧‧‧ side wall
170‧‧‧電洞阻隔層 170‧‧‧ hole barrier
180‧‧‧p型磊晶層 180‧‧‧p type epitaxial layer
210、310‧‧‧犧牲氧化層 210, 310‧‧‧ Sacrificial oxide layer
220、320‧‧‧閘極氧化層 220, 320‧‧‧ gate oxide layer
230、330‧‧‧圖案化閘極層 230, 330‧‧‧ patterned gate layer
240、340‧‧‧第二開口 240, 340‧‧‧ second opening
250、260、350、360‧‧‧n型源極區 250, 260, 350, 360‧‧‧n type source regions
270、370‧‧‧p型摻雜區 270, 370‧‧‧p-type doped region
280、380‧‧‧層間介電層 280, 380‧‧ ‧ interlayer dielectric layer
290、390‧‧‧電極層 290, 390‧‧‧ electrode layer
300‧‧‧閘極結構 300‧‧‧ gate structure
為讓本揭露之上述和其他目的、特徵、優點與實施方式能更明顯易懂，所附圖式之詳細說明如下：第1圖繪示根據本揭露的某些實施例，製作半導體元件的製程中的一個階段的半導體元件的剖面圖；第2圖繪示根據本揭露的某些實施例，製作半導體元件的製程中的一個階段的半導體元件的剖面圖；第3圖繪示根據本揭露的某些實施例，製作半導體元件的製程中的一個階段的半導體元件的剖面圖；第4圖繪示根據本揭露的某些實施例，製作半導體元件的製程中的一個階段的半導體元件的剖面圖；第5圖繪示根據本揭露的某些實施例，製作半導體元件的製程中的一個階段的半導體元件的剖面圖；第6圖繪示根據本揭露的某些實施例，製作半導體元件的製程中的一個階段的半導體元件的剖面圖；第7A-7E圖繪示根據本揭露的某些實施例，製作半導體元件的製程中的各個階段的半導體元件的剖面圖； 第8A-8E圖繪示根據本揭露的某些實施例，製作半導體元件的製程中的各個階段的半導體元件的剖面圖。 The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. Detailed description of the drawings is as follows: FIG. 1 illustrates a process for fabricating a semiconductor device in accordance with certain embodiments of the present disclosure. FIG. 2 is a cross-sectional view of a semiconductor element in a process of fabricating a semiconductor device in accordance with some embodiments of the present disclosure; and FIG. 3 is a cross-sectional view of the semiconductor device in accordance with the present disclosure. Some embodiments, a cross-sectional view of a semiconductor element in a stage in a process of fabricating a semiconductor device; and FIG. 4 is a cross-sectional view of a semiconductor device in a stage in a process of fabricating a semiconductor device in accordance with certain embodiments of the present disclosure. 5 is a cross-sectional view of a semiconductor device in a stage in a process of fabricating a semiconductor device in accordance with some embodiments of the present disclosure; and FIG. 6 illustrates a process of fabricating a semiconductor device in accordance with certain embodiments of the present disclosure. A cross-sectional view of a semiconductor component in one stage; and FIGS. 7A-7E illustrate a process of fabricating a semiconductor device in accordance with certain embodiments of the present disclosure A cross-sectional view of a semiconductor element stages; 8A-8E are cross-sectional views of semiconductor components at various stages in the fabrication of semiconductor devices in accordance with certain embodiments of the present disclosure.
以下揭露提供許多不同實施例，或示例，以建置所提供之標的物的不同特徵。以下敘述之成份和排列方式的特定示例是為了簡化本公開。這些當然僅是做為示例，其目的不在構成限制。舉例而言，元件的尺寸不被揭露之範圍或數值所限制，但可以取決於元件之製程條件與/或所需的特性。此外，第一特徵形成在第二特徵之上或上方的描述包含第一特徵和第二特徵有直接接觸的實施例，也包含有其他特徵形成在第一特徵和第二特徵之間，以致第一特徵和第二特徵沒有直接接觸的實施例。為了簡單與清晰起見，不同特徵可以任意地繪示成不同大小。 The following disclosure provides many different embodiments, or examples, to construct different features of the subject matter provided. Specific examples of the components and arrangements described below are intended to simplify the disclosure. These are of course only examples and their purpose is not to be construed as limiting. For example, the dimensions of the components are not limited by the scope or value disclosed, but may depend on the process conditions and/or desired characteristics of the components. Furthermore, the description in which the first feature is formed on or over the second feature includes an embodiment in which the first feature and the second feature are in direct contact, and other features are included between the first feature and the second feature, such that An embodiment in which a feature and a second feature are not in direct contact. For simplicity and clarity, different features may be arbitrarily drawn to different sizes.
再者，空間相對性用語，例如「下方(beneath)」、「在…之下(below)」、「低於(lower)」、「在…之上(above)」、「高於(upper)」等，是為了易於描述圖式中所繪示的元素或特徵和其他元素或特徵的關係。空間相對性用語除了圖式中所描繪的方向外，還包含元件在使用或操作時的不同方向。儀器可以其他方式定向(旋轉90度或在其他方向)，而本文所用的空間相對性描述也可以如此解讀。 Furthermore, spatially relative terms such as "beneath", "below", "lower", "above", "upper" And the like, for ease of description of the relationship between the elements or features and other elements or features illustrated in the drawings. Spatially relative terms, in addition to the directions depicted in the figures, also encompass different orientations of the components in use or operation. The instrument can be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative description used herein can be interpreted as such.
第1-8F圖繪示根據本發明各種實施例之半導體元件在不同製程階段的剖面示意圖。首先，請參照第1 圖，提供基材100。在一些實施例中，基材100包含p型摻雜層110、n型緩衝層120及n型漂移層130。基材100的材料可以包含矽(silicon)、碳化矽(silicon carbide)或其他合適的材料。 1-8F are schematic cross-sectional views showing semiconductor elements in different process stages in accordance with various embodiments of the present invention. First, please refer to the first The figure provides a substrate 100. In some embodiments, the substrate 100 includes a p-type doped layer 110, an n-type buffer layer 120, and an n-type drift layer 130. The material of the substrate 100 may comprise silicon, silicon carbide or other suitable materials.
之後，在基材100上形成圖案化遮罩層140。圖案化遮罩層140具有第一開口150，第一開口150暴露一部分的基材100。在某些實施例中，圖案化遮罩層140係形成於n型漂移層130上。在某些實施例中，圖案化遮罩層140的材料可以包含二氧化矽、其他氧化物或其他合適的材料。 Thereafter, a patterned mask layer 140 is formed on the substrate 100. The patterned mask layer 140 has a first opening 150 that exposes a portion of the substrate 100. In some embodiments, the patterned mask layer 140 is formed on the n-type drift layer 130. In some embodiments, the material of the patterned mask layer 140 can comprise ceria, other oxides, or other suitable materials.
請參照第2圖，移除基材100的暴露部分，以形成凹槽160於基材100中。凹槽160具有底部162以及側壁164。在某些實施例中，可以使用合適的製程移除基材100的暴露部分，舉例來說，乾蝕刻或濕蝕刻。在某些實施例中，基材100包含矽的情況下，凹槽160的深度係約1μm至約10μm。在某些實施例中，基材100包含碳化矽的情況下，凹槽160的深度係約1μm至約3μm。值得注意的是，在某些實施例中，圖案化遮罩層140係作為移除基材100的暴露部分的蝕刻製程中的遮罩。 Referring to FIG. 2, the exposed portion of the substrate 100 is removed to form the recess 160 in the substrate 100. The groove 160 has a bottom 162 and a side wall 164. In some embodiments, the exposed portion of substrate 100 can be removed using a suitable process, such as dry etching or wet etching. In certain embodiments, where the substrate 100 comprises tantalum, the depth of the grooves 160 is from about 1 [mu]m to about 10 [mu]m. In certain embodiments, where the substrate 100 comprises tantalum carbide, the depth of the grooves 160 is from about 1 [mu]m to about 3 [mu]m. Notably, in some embodiments, the patterned mask layer 140 acts as a mask in an etch process that removes exposed portions of the substrate 100.
接著請參照第3圖，經由第一開口150在凹槽160的底部162及側壁164摻雜第一n型摻雜劑，以形成電洞阻隔層170。在某些實施例中，電洞阻隔層170包圍凹槽160的底部162及側壁164。在某些實施例中，第一n型摻雜劑可以包含氮(Nitrogen)或磷(phosphorus)或砷(arsenic)。在某些實施例中，摻雜第一n型摻雜劑可以包含使用離子植入 (ionic implantation)或電漿離子浸潤(plasma ion implant immersion)。在一些實施例中，第一n型摻雜劑的摻雜濃度為約1×1015cm-3至約5×1019cm-3。 Next, referring to FIG. 3, the first n-type dopant is doped at the bottom 162 and the sidewall 164 of the recess 160 via the first opening 150 to form the hole barrier layer 170. In some embodiments, the hole barrier layer 170 surrounds the bottom 162 and sidewalls 164 of the recess 160. In certain embodiments, the first n-type dopant can comprise nitrogen (Nitrogen) or phosphorous or arsenic. In some embodiments, doping the first n-type dopant can comprise using an ionic implantation or a plasma ion implant immersion. In some embodiments, the first n-type dopant has a doping concentration of from about 1 x 10 15 cm -3 to about 5 x 10 19 cm -3 .
接著請參照第4圖，形成p型磊晶層180於凹槽160中。在某些實施例中，形成p型磊晶層180可以使用適當的製程達成，例如選擇性磊晶成長(selective epitaxial growth)。由於在氧化物上較難形成磊晶，故可以利用圖案化遮罩層140，使得p型磊晶層180形成於凹槽160中。值得注意的是，由於形成p型磊晶層180的製程需要在高溫的環境下執行，此高溫的環境可以使電洞阻隔層170的第一n型摻雜劑擴散，使得電洞阻隔層170的厚度增厚。利用形成p型磊晶層180的環境使電洞阻隔層170的厚度增加，可以簡化製程，而不需再另外執行加溫製程使電洞阻隔層170的第一n型摻雜劑擴散。在某些實施例中，在形成p型磊晶層180之後，電洞阻隔層170的厚度可以為小於或等於3μm。在某些基材100包含矽的實施例中，電洞阻隔層170的厚度可以為約0.5μm至約3μm。在某些基材100包含碳化矽的實施例中，電洞阻隔層170的厚度可以為小於或等於0.5μm。 Next, referring to FIG. 4, a p-type epitaxial layer 180 is formed in the recess 160. In some embodiments, forming the p-type epitaxial layer 180 can be accomplished using a suitable process, such as selective epitaxial growth. Since epitaxy is more difficult to form on the oxide, the patterned mask layer 140 can be utilized such that the p-type epitaxial layer 180 is formed in the recess 160. It should be noted that since the process of forming the p-type epitaxial layer 180 needs to be performed in a high temperature environment, the high temperature environment can diffuse the first n-type dopant of the hole barrier layer 170, so that the hole barrier layer 170 The thickness is thickened. By increasing the thickness of the hole barrier layer 170 by the environment in which the p-type epitaxial layer 180 is formed, the process can be simplified without additionally performing a warming process to diffuse the first n-type dopant of the hole barrier layer 170. In some embodiments, after forming the p-type epitaxial layer 180, the thickness of the hole blocking layer 170 may be less than or equal to 3 μm. In some embodiments in which the substrate 100 comprises tantalum, the hole barrier layer 170 can have a thickness of from about 0.5 [mu]m to about 3 [mu]m. In some embodiments in which the substrate 100 comprises tantalum carbide, the thickness of the hole barrier layer 170 may be less than or equal to 0.5 μm.
請參照第5圖，在形成p型磊晶層180後，執行化學機械研磨製程(chemical-mechanical polishing,CMP)，以平坦化p型磊晶層180。值得注意的是，在某些實施例中，在以化學機械研磨製程平坦化p型磊晶層180後，由於化學機械研磨製程本身的限制的關係，靠近圖案化遮罩層140的p型磊晶層180的部分尚具有不平整的表面。 Referring to FIG. 5, after the p-type epitaxial layer 180 is formed, a chemical-mechanical polishing (CMP) is performed to planarize the p-type epitaxial layer 180. It should be noted that in some embodiments, after planarizing the p-type epitaxial layer 180 by a chemical mechanical polishing process, the p-type Lei near the patterned mask layer 140 is limited by the chemical mechanical polishing process itself. The portion of the layer 180 still has an uneven surface.
接著請參照第6圖，移除圖案化遮罩層140，以暴露基材100的表面、電洞阻隔層170的表面及p型磊晶層180的表面。在某些實施例中，進行此步驟後，p型磊晶層180的兩側尚具有不平整的表面。本發明實施方式亦提供一種平坦化方法，可以平坦化p型磊晶層180的兩側的不平整表面，請見以下第7A-7B圖及第8A-8C圖所描述之製程。在某些實施例中，移除圖案化遮罩層140可以用合適的方法達成，可例如乾蝕刻製程或濕蝕刻製程。 Next, referring to FIG. 6, the patterned mask layer 140 is removed to expose the surface of the substrate 100, the surface of the hole barrier layer 170, and the surface of the p-type epitaxial layer 180. In some embodiments, after this step, the p-type epitaxial layer 180 has an uneven surface on both sides. Embodiments of the present invention also provide a planarization method for planarizing uneven surfaces on both sides of the p-type epitaxial layer 180, as described in the following FIGS. 7A-7B and 8A-8C. In some embodiments, removing the patterned mask layer 140 can be accomplished in a suitable manner, such as a dry etch process or a wet etch process.
根據本發明某些實施例，第7A-7E圖所示的製程可適用於基材100包含矽的半導體元件，並在執行第6圖所示的製程後，執行第7A-7E圖所示之製程。在第7A圖中，形成犧牲氧化層210於基材100上。值得注意的是，犧牲氧化層210係共形形成於基材100上，也就是說，原本在第6圖中p型磊晶層180的兩側的不平整表面被氧化。另外，由於係在高溫的環境下形成犧牲氧化層210，此高溫的環境亦可以使p型磊晶層180的p型摻雜劑擴散至基材100中，使得p型磊晶層180的厚度增加。利用形成犧牲氧化層210的環境使p型磊晶層180的厚度增加，可以減少製程的步驟，而不需再另外執行加溫製程使p型磊晶層180的p型摻雜劑擴散。在某些實施例中，犧牲氧化層210的材料可為矽氧化物，例如二氧化矽(SiO2)。 According to some embodiments of the present invention, the process illustrated in FIGS. 7A-7E can be applied to a semiconductor device including a germanium substrate 100, and after performing the process illustrated in FIG. 6, performing the processes shown in FIGS. 7A-7E Process. In FIG. 7A, a sacrificial oxide layer 210 is formed on the substrate 100. It is to be noted that the sacrificial oxide layer 210 is conformally formed on the substrate 100, that is, the uneven surface on both sides of the p-type epitaxial layer 180 originally in FIG. 6 is oxidized. In addition, since the sacrificial oxide layer 210 is formed in a high temperature environment, the high temperature environment can also diffuse the p-type dopant of the p-type epitaxial layer 180 into the substrate 100 such that the thickness of the p-type epitaxial layer 180 increase. By increasing the thickness of the p-type epitaxial layer 180 by the environment in which the sacrificial oxide layer 210 is formed, the process of the process can be reduced without additionally performing a warming process to diffuse the p-type dopant of the p-type epitaxial layer 180. In some embodiments, the material of the sacrificial oxide layer 210 can be a tantalum oxide such as hafnium oxide (SiO 2 ).
請參考第7B圖，移除犧牲氧化層210，使p型磊晶層180的表面平整，並暴露出基材100、電洞阻隔層170及p型磊晶層180。值得注意的是，在移除犧牲氧化層210 之後，p型磊晶層180上的不平整表面亦被移除。更進一步說明，在某些實施例中，p型磊晶層180的表面與基材100的表面共平面。 Referring to FIG. 7B, the sacrificial oxide layer 210 is removed to planarize the surface of the p-type epitaxial layer 180, and the substrate 100, the hole barrier layer 170, and the p-type epitaxial layer 180 are exposed. It is worth noting that the sacrificial oxide layer 210 is removed. Thereafter, the uneven surface on the p-type epitaxial layer 180 is also removed. Still further, in some embodiments, the surface of the p-type epitaxial layer 180 is coplanar with the surface of the substrate 100.
請參考第7C圖，形成閘極氧化層220於基材100、電洞阻隔層170及p型磊晶層180上，其中閘極氧化層220覆蓋基材100的表面、電洞阻隔層170的表面及p型磊晶層180的表面。在某些實施例中，閘極氧化層220的材料可為矽氧化物，例如二氧化矽(SiO2)。在某些實施例中，閘極氧化層220可以使用熱氧化製程或沉積製程形成。 Referring to FIG. 7C, a gate oxide layer 220 is formed on the substrate 100, the hole barrier layer 170, and the p-type epitaxial layer 180, wherein the gate oxide layer 220 covers the surface of the substrate 100 and the hole barrier layer 170. The surface and the surface of the p-type epitaxial layer 180. In some embodiments, the material of the gate oxide layer 220 can be a tantalum oxide such as hafnium oxide (SiO 2 ). In some embodiments, the gate oxide layer 220 can be formed using a thermal oxidation process or a deposition process.
請參考第7D圖，形成圖案化閘極層230於閘極氧化層220上。圖案化閘極層230具有第二開口240，第二開口240位於p型磊晶層180上方。然後，經由第二開口240在p型磊晶層180中摻雜第二n型摻雜劑，以形成n型源極區250及n型源極區260於p型磊晶層180中。在某些實施例中，形成n型源極區250及n型源極區260係先摻雜第二n型摻雜劑於p型磊晶層180中，再進行退火製程，以使第二n型摻雜劑擴散。在某些實施例中，第二開口240的兩邊緣各自對準n型源極區250及n型源極區260。在某些實施例中，n型源極區250及n型源極區260皆與閘極氧化層220接觸。在某些實施例中，圖案化閘極層230的材料可例如為多晶矽。在一些實施例中，可以藉由先形成閘極層(未繪示)覆蓋閘極氧化層220，再執行蝕刻製程以移除部分的閘極層，形成第二開口240，而形成圖案化閘極層230。在某些實施例中，形成第二開口240可以使用乾蝕刻或濕蝕刻達成。在某 些實施例中，第二n型摻雜劑可以包含磷(phosphorum)或砷(arsenic)。 Referring to FIG. 7D, a patterned gate layer 230 is formed on the gate oxide layer 220. The patterned gate layer 230 has a second opening 240 above the p-type epitaxial layer 180. Then, a second n-type dopant is doped in the p-type epitaxial layer 180 via the second opening 240 to form an n-type source region 250 and an n-type source region 260 in the p-type epitaxial layer 180. In some embodiments, the n-type source region 250 and the n-type source region 260 are formed by first doping a second n-type dopant into the p-type epitaxial layer 180, and then performing an annealing process to make the second The n-type dopant diffuses. In some embodiments, both edges of the second opening 240 are aligned with the n-type source region 250 and the n-type source region 260, respectively. In some embodiments, both the n-type source region 250 and the n-type source region 260 are in contact with the gate oxide layer 220. In some embodiments, the material of the patterned gate layer 230 can be, for example, a polysilicon. In some embodiments, the gate oxide layer 220 may be formed by first forming a gate layer (not shown), and then an etching process may be performed to remove a portion of the gate layer to form a second opening 240 to form a patterned gate. Polar layer 230. In some embodiments, forming the second opening 240 can be accomplished using dry etching or wet etching. In a certain In some embodiments, the second n-type dopant may comprise phosphorum or arsenic.
請參考第7E圖，形成層間介電層280覆蓋圖案化閘極層230，其中層間介電層280亦覆蓋部分的閘極氧化層220。在一實施例中，先毯覆式地沉積一層介電層(未繪示)，然後再進行微影蝕刻製程而形成層間介電層280。值得注意的是，在進行蝕刻製程時，亦會將一部分的閘極氧化層220移除，而暴露出一部分的n型源極區250、一部分的n型源極區260及一部分的p型磊晶層180。更進一步說明，層間介電層280的邊緣與閘極氧化層220的邊緣對齊。 Referring to FIG. 7E, an interlayer dielectric layer 280 is formed to cover the patterned gate layer 230, wherein the interlayer dielectric layer 280 also covers a portion of the gate oxide layer 220. In one embodiment, a dielectric layer (not shown) is first blanket deposited, and then a photolithography process is performed to form an interlayer dielectric layer 280. It is worth noting that during the etching process, a portion of the gate oxide layer 220 is also removed, and a portion of the n-type source region 250, a portion of the n-type source region 260, and a portion of the p-type Lei are exposed. Crystal layer 180. Still further, the edges of the interlayer dielectric layer 280 are aligned with the edges of the gate oxide layer 220.
在形成層間介電層280之後，在p型磊晶層180中形成p型摻雜區270，其中p型摻雜區270位於n型源極區250及n型源極區260之間。在某些實施例中，形成p型摻雜區270係先在p型磊晶層180中摻雜p型摻雜劑，再進行退火製程。在層間介電層280形成之後再進行p型磊晶層180的退火製程，有助於層間介電層280的平坦化及平滑化。在某些實施例中，p型摻雜區270係使用離子植入製程而形成。 After the interlayer dielectric layer 280 is formed, a p-type doped region 270 is formed in the p-type epitaxial layer 180, wherein the p-type doped region 270 is located between the n-type source region 250 and the n-type source region 260. In some embodiments, the p-type doped region 270 is formed by first doping a p-type dopant into the p-type epitaxial layer 180 and then performing an annealing process. After the interlayer dielectric layer 280 is formed, the annealing process of the p-type epitaxial layer 180 is performed to facilitate planarization and smoothing of the interlayer dielectric layer 280. In some embodiments, the p-doped region 270 is formed using an ion implantation process.
然後，如第7E圖所示，在層間介電層280及p型摻雜區270上形成電極層290，其中電極層290與p型摻雜區270接觸。更進一步說明，電極層290亦與一部分的n型源極區250和一部分的n型源極區260接觸。在一些實施例中，電極層290的材料為金屬。 Then, as shown in FIG. 7E, an electrode layer 290 is formed on the interlayer dielectric layer 280 and the p-type doping region 270, wherein the electrode layer 290 is in contact with the p-type doping region 270. Still further, the electrode layer 290 is also in contact with a portion of the n-type source region 250 and a portion of the n-type source region 260. In some embodiments, the material of electrode layer 290 is a metal.
根據本發明某些實施例，第8A-8E圖所示的製程可適用於基材100包含碳化矽的半導體元件。在某些實施 例中，在執行第6圖所示的製程後，執行第8A-8E圖所示之製程。請參見第8A圖，形成犧牲氧化層310於基材100上。犧牲氧化層310係共形形成於基材100上，也就是說，原本在第6圖中p型磊晶層180的兩側的不平整表面被氧化。由於係在高溫的環境下形成犧牲氧化層310，在高溫的環境中，可以使p型磊晶層180的p型摻雜劑擴散至基材100中，使得p型磊晶層180的厚度增加。利用形成犧牲氧化層310的高溫環境使p型摻雜劑擴散，以使p型磊晶層180的厚度增加，可以減少製程的步驟，而不需再另外執行加溫製程，例如退火。在某些實施例中，犧牲氧化層310的材料可為矽氧化物，例如二氧化矽(SiO2)。值得注意的是，在基材包含碳化矽的實施例中，犧牲氧化層的厚度比基材包含矽的實施例的犧牲氧化層的厚度薄。 According to some embodiments of the present invention, the process illustrated in FIGS. 8A-8E can be applied to a semiconductor device in which the substrate 100 comprises tantalum carbide. In some embodiments, after the process illustrated in FIG. 6 is performed, the process illustrated in FIGS. 8A-8E is performed. Referring to FIG. 8A, a sacrificial oxide layer 310 is formed on the substrate 100. The sacrificial oxide layer 310 is conformally formed on the substrate 100, that is, the uneven surface on both sides of the p-type epitaxial layer 180 originally in FIG. 6 is oxidized. Since the sacrificial oxide layer 310 is formed in a high-temperature environment, the p-type dopant of the p-type epitaxial layer 180 can be diffused into the substrate 100 in a high-temperature environment, so that the thickness of the p-type epitaxial layer 180 is increased. . By diffusing the p-type dopant by the high temperature environment in which the sacrificial oxide layer 310 is formed, the thickness of the p-type epitaxial layer 180 is increased, and the process of the process can be reduced without additionally performing a heating process such as annealing. In some embodiments, the material of the sacrificial oxide layer 310 can be a tantalum oxide such as hafnium oxide (SiO 2 ). Notably, in embodiments where the substrate comprises tantalum carbide, the thickness of the sacrificial oxide layer is less than the thickness of the sacrificial oxide layer of the embodiment in which the substrate comprises tantalum.
請參考第8B圖，在p型磊晶層180中形成n型源極區350及n型源極區360。在某些實施例中，n型源極區350及n型源極區360與犧牲氧化層310接觸。在第8B圖中，亦在p型磊晶層180中形成p型摻雜區370。在某些實施例中，p型摻雜區370配置於n型源極區350及n型源極區360之間。在某些實施例中，p型摻雜區370與犧牲氧化層310接觸。在某些實施例中，p型摻雜區270係使用離子植入製程而形成。由於在基材100包含碳化矽的半導體元件中，在高溫下的表面性質不穩定，需要較為精準地控制製程溫度及時間。若製程中有多次的溫度變化，會增加製程的難度，因此可在摻雜第二n型摻雜劑及p型摻雜劑之後，再一併執行退 火製程，以降低製程難度。 Referring to FIG. 8B, an n-type source region 350 and an n-type source region 360 are formed in the p-type epitaxial layer 180. In some embodiments, the n-type source region 350 and the n-type source region 360 are in contact with the sacrificial oxide layer 310. In FIG. 8B, a p-type doping region 370 is also formed in the p-type epitaxial layer 180. In some embodiments, p-doped region 370 is disposed between n-type source region 350 and n-type source region 360. In some embodiments, p-type doped region 370 is in contact with sacrificial oxide layer 310. In some embodiments, the p-doped region 270 is formed using an ion implantation process. Since the surface property at a high temperature is unstable in the semiconductor element in which the substrate 100 contains tantalum carbide, it is necessary to control the process temperature and time more accurately. If there are multiple temperature changes in the process, it will increase the difficulty of the process, so it can be performed after doping the second n-type dopant and the p-type dopant. Fire process to reduce the difficulty of the process.
請參考第8C圖，移除犧牲氧化層310，以暴露基材100、電洞阻隔層170、p型磊晶層180、n型源極區350、n型源極區360及p型摻雜區370。在移除犧牲氧化層310之後，p型磊晶層180上的不平整表面亦被移除，以使p型磊晶層180表面平整。 Referring to FIG. 8C, the sacrificial oxide layer 310 is removed to expose the substrate 100, the hole barrier layer 170, the p-type epitaxial layer 180, the n-type source region 350, the n-type source region 360, and the p-type doping. Area 370. After the sacrificial oxide layer 310 is removed, the uneven surface on the p-type epitaxial layer 180 is also removed to planarize the surface of the p-type epitaxial layer 180.
請參考第8D圖，形成閘極氧化層320覆蓋基材100、電洞阻隔層170及p型磊晶層180中的n型源極區350、n型源極區360及p型摻雜區370。在某些實施例中，閘極氧化層320可以使用熱氧化製程或沉積製程形成。在某些實施例中，閘極氧化層320的材料可為矽氧化物，例如二氧化矽(SiO2)。 Referring to FIG. 8D, the gate oxide layer 320 is formed to cover the n-type source region 350, the n-type source region 360, and the p-type doping region in the substrate 100, the hole barrier layer 170, and the p-type epitaxial layer 180. 370. In some embodiments, the gate oxide layer 320 can be formed using a thermal oxidation process or a deposition process. In some embodiments, the material of the gate oxide layer 320 can be a tantalum oxide such as hafnium oxide (SiO 2 ).
如第8D圖所示，在形成閘極氧化層320之後，形成圖案化閘極層330於閘極氧化層320上。圖案化閘極層330具有第二開口340，第二開口340位於p型磊晶層180上方。更詳細說明，第二開口340位於n型源極區350、n型源極區360及p型摻雜區370上方。值得注意的是，在某些實施例中，第二開口340的兩邊緣各自分別對準n型源極區350及n型源極區360。在某些實施例中，n型源極區350、n型源極區360及p型摻雜區370皆與閘極氧化層320接觸。在某些實施例中，圖案化閘極層330的材料可例如為多晶矽。在一些實施例中，可以藉由先形成閘極層(未繪示)覆蓋閘極氧化層320，再執行蝕刻製程以移除部分的閘極層，形成第二開口240，而形成圖案化閘極層230。在某些實施例中，形 成第二開口240可以使用乾蝕刻或濕蝕刻達成。 As shown in FIG. 8D, after the gate oxide layer 320 is formed, a patterned gate layer 330 is formed on the gate oxide layer 320. The patterned gate layer 330 has a second opening 340 that is above the p-type epitaxial layer 180. In more detail, the second opening 340 is located above the n-type source region 350, the n-type source region 360, and the p-type doping region 370. It should be noted that in some embodiments, the two edges of the second opening 340 are respectively aligned with the n-type source region 350 and the n-type source region 360, respectively. In some embodiments, n-type source region 350, n-type source region 360, and p-type doped region 370 are all in contact with gate oxide layer 320. In some embodiments, the material of the patterned gate layer 330 can be, for example, a polysilicon. In some embodiments, the gate oxide layer 320 may be formed by first forming a gate layer (not shown), and then an etching process may be performed to remove a portion of the gate layer to form a second opening 240 to form a patterned gate. Polar layer 230. In some embodiments, the shape The second opening 240 can be achieved using dry etching or wet etching.
請參考第8E圖，形成層間介電層380覆蓋圖案化閘極層330，其中層間介電層380亦覆蓋部分的閘極氧化層320。在一實施例中，先毯覆式地沉積一層介電層(未繪示)，然後再進行微影蝕刻製程而形成層間介電層380。值得注意的是，在進行蝕刻製程時，亦會將一部分的閘極氧化層320移除，而暴露出一部分的n型源極區350、一部分的n型源極區360以及p型摻雜區370。更進一步說明，層間介電層380的邊緣與閘極氧化層320的邊緣對齊。 Referring to FIG. 8E, an interlayer dielectric layer 380 is formed to cover the patterned gate layer 330, wherein the interlayer dielectric layer 380 also covers a portion of the gate oxide layer 320. In one embodiment, a dielectric layer (not shown) is first blanket deposited, and then a photolithography process is performed to form an interlayer dielectric layer 380. It is worth noting that during the etching process, a portion of the gate oxide layer 320 is also removed, and a portion of the n-type source region 350, a portion of the n-type source region 360, and the p-type doped region are exposed. 370. Still further, the edges of the interlayer dielectric layer 380 are aligned with the edges of the gate oxide layer 320.
在形成層間介電層380之後，形成電極層390於層間介電層380及p型摻雜區370上，其中電極層390與p型摻雜區370接觸。更進一步說明，電極層390亦與一部分的n型源極區350和一部分的n型源極區360接觸。在一些實施例中，電極層390的材料為金屬。 After the interlayer dielectric layer 380 is formed, the electrode layer 390 is formed on the interlayer dielectric layer 380 and the p-type doping region 370, wherein the electrode layer 390 is in contact with the p-type doping region 370. Still further, electrode layer 390 is also in contact with a portion of n-type source region 350 and a portion of n-type source region 360. In some embodiments, the material of electrode layer 390 is a metal.
請繼續參考第8E圖，本發明實施方式亦提供一種半導體元件結構，此半導體元件結構包含基材100、p型磊晶層180、電洞阻隔層170以及閘極結構300。p型磊晶層180嵌設基材100中。電洞阻隔層170位於基材100中，並包圍p型磊晶層180。在某些實施例中，p型磊晶層180包含n型源極區350、n型源極區360及p型摻雜區370，其中p型摻雜區370位於n型源極區350及n型源極區360之間。閘極結構300位於基材100及p型磊晶層180上。在某些實施例中，閘極結構300包含圖案化閘極層330及閘極氧化層320，其中圖案化閘極層330配置於閘極氧化層320上。在某些實施 例中，一部分的n型源極區350及一部分的n型源極區360與閘極氧化層320接觸。在一些實施例中，基材100包含p型摻雜層110、n型緩衝層120及n型漂移層130，其中n型緩衝層120位於p型摻雜層110及n型漂移層130之間。 Referring to FIG. 8E , an embodiment of the present invention also provides a semiconductor device structure including a substrate 100 , a p-type epitaxial layer 180 , a hole barrier layer 170 , and a gate structure 300 . The p-type epitaxial layer 180 is embedded in the substrate 100. The hole barrier layer 170 is located in the substrate 100 and surrounds the p-type epitaxial layer 180. In some embodiments, the p-type epitaxial layer 180 includes an n-type source region 350, an n-type source region 360, and a p-type doping region 370, wherein the p-type doping region 370 is located in the n-type source region 350 and Between the n-type source regions 360. The gate structure 300 is located on the substrate 100 and the p-type epitaxial layer 180. In some embodiments, the gate structure 300 includes a patterned gate layer 330 and a gate oxide layer 320, wherein the patterned gate layer 330 is disposed on the gate oxide layer 320. In some implementations In the example, a portion of the n-type source region 350 and a portion of the n-type source region 360 are in contact with the gate oxide layer 320. In some embodiments, the substrate 100 includes a p-type doped layer 110 , an n-type buffer layer 120 , and an n-type drift layer 130 , wherein the n-type buffer layer 120 is between the p-type doped layer 110 and the n-type drift layer 130 . .
在一些實施例中，此半導體元件結構更包含層間介電層380及電極層390。層間介電層380覆蓋圖案化閘極層330。在一些實施例中，層間介電層380亦覆蓋一部分的閘極氧化層320。在一些實施例中，電極層390與p型摻雜區370接觸。 In some embodiments, the semiconductor device structure further includes an interlayer dielectric layer 380 and an electrode layer 390. An interlayer dielectric layer 380 covers the patterned gate layer 330. In some embodiments, the interlayer dielectric layer 380 also covers a portion of the gate oxide layer 320. In some embodiments, electrode layer 390 is in contact with p-type doped region 370.
本發明實施方式提供的製作方法以及結構，可以適用於各種半導體元件，例如功率半導體元件。更詳細的說明，本發明實施方式提供的製作方法以及結構可以適用於絕緣柵雙極電晶體(insulated gate bipolar transistor,IGBT)。另外，本發明實施方式提供之製程亦可以使用於包含矽或碳化矽的基材的半導體元件，但不限於此。 The fabrication method and structure provided by the embodiments of the present invention can be applied to various semiconductor elements, such as power semiconductor elements. In more detail, the fabrication method and structure provided by the embodiments of the present invention can be applied to an insulated gate bipolar transistor (IGBT). In addition, the process provided by the embodiment of the present invention may also be used for a semiconductor element including a substrate of tantalum or tantalum carbide, but is not limited thereto.
本發明實施方式已經詳細地描述某些實施方式，但其他的實施方式也是可能的。因此，所附請求項的精神和範疇不應限於本文所描述的實施方式。 Certain embodiments have been described in detail in the embodiments of the invention, but other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
雖然本發明實施方式已以實施方式揭露如上，然其並非用以限定本揭露內容，任何熟習此技術者，在不脫離本揭露內容之精神與範圍內，當可作各種更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。 The embodiments of the present invention have been disclosed in the above embodiments, and are not intended to limit the disclosure. Anyone skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection disclosed is subject to the definition of the scope of the patent application.
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