TWI639847B - Integrated circuit chip and inspection method thereof - Google Patents
Integrated circuit chip and inspection method thereof Download PDFInfo
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- G05B23/00—Testing or monitoring of control systems or parts thereof
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- G—PHYSICS
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Abstract
積體電路晶片及其檢查方法。積體電路晶片的目標電路產生目標信號。積體電路晶片的轉態偵測電路於初始化期間偵測目標信號的轉態，以產生轉態偵測結果。依據轉態偵測結果判斷目標電路的初始化是否正常。Integrated circuit wafer and inspection method thereof. The target circuit of the integrated circuit chip generates a target signal. The transition detection circuit of the integrated circuit chip detects the transition of the target signal during initialization to generate a transition detection result. Determine whether the initialization of the target circuit is normal according to the transition detection result.
Description
本發明是有關於一種晶片，且特別是有關於一種積體電路晶片及其檢查方法。The present invention relates to a wafer, and more particularly, to an integrated circuit wafer and an inspection method thereof.
積體電路晶片內含有多個電路模組。這些電路模組彼此協同工作。當這些電路模組任何一者的初始化失敗時，往往會讓積體電路晶片的功能失效。舉例來說，當積體電路晶片內部的電壓調整器（voltage regulator）壞掉而無法供應電源電壓給其他電路模組時，這些電路模組將無法正常運作。當積體電路晶片的功能失效時，為了找出問題的癥結點，一般需要昂貴的測試機台利用探針去擷取在積體電路晶片內的目標電路的目標信號（例如電壓調整器所輸出的電源電壓），以便監視目標電路的初始化是否正常。The integrated circuit chip contains a plurality of circuit modules. These circuit modules work in conjunction with each other. When the initialization of any of these circuit modules fails, the function of the integrated circuit chip is often invalidated. For example, when the voltage regulator inside the integrated circuit chip is broken and cannot supply power to other circuit modules, these circuit modules will not operate normally. When the function of the integrated circuit chip fails, in order to find the crux of the problem, an expensive test machine is generally required to use a probe to capture the target signal of the target circuit in the integrated circuit chip (such as the output of a voltage regulator) Power supply voltage) to monitor the initialization of the target circuit.
本發明提供一種積體電路晶片及其檢查方法，以便自我監視目標信號的轉態。The invention provides an integrated circuit chip and an inspection method thereof, in order to self-monitor a transition state of a target signal.
本發明的實施例提供一種積體電路晶片的檢查方法。所述檢查方法包括：由積體電路晶片的目標電路產生目標信號；由積體電路晶片的轉態（slew）偵測電路於初始化期間偵測目標信號的轉態，以產生轉態偵測結果；以及依據轉態偵測結果判斷目標電路的初始化是否正常。An embodiment of the present invention provides a method for inspecting an integrated circuit wafer. The inspection method includes: generating a target signal by a target circuit of an integrated circuit chip; and detecting a transition of the target signal by a slew detection circuit of the integrated circuit chip during initialization to generate a transition detection result ; And judging whether the initialization of the target circuit is normal according to the transition detection result.
在本發明的一實施例中，上述的檢查方法更包括：由積體電路晶片的準位偵測電路偵測目標信號的準位，以產生準位偵測結果。In an embodiment of the present invention, the above-mentioned inspection method further includes: detecting a level of the target signal by a level detection circuit of the integrated circuit chip to generate a level detection result.
在本發明的一實施例中，上述的檢查方法更包括：當目標信號的準位於第一期間未達額定準位，且目標信號的轉態速率（slew rate）不為0時，由目標電路加大目標信號的轉態速率，以使目標信號的準位於額定期間內達到額定準位。In an embodiment of the present invention, the above-mentioned inspection method further includes: when the target signal quasi is located in the first period and does not reach the rated level, and the slew rate of the target signal is not 0, the target circuit Increase the transition rate of the target signal so that the target signal's accuracy is within the rated period to reach the rated level.
在本發明的一實施例中，上述的檢查方法更包括：將轉態偵測結果記錄於積體電路晶片內的第一狀態暫存器（register）；以及將準位偵測結果記錄於積體電路晶片內的第二狀態暫存器。In an embodiment of the present invention, the above-mentioned inspection method further includes: recording a transition detection result in a first state register in the integrated circuit chip; and recording a level detection result in the product. The second state register in the body circuit chip.
在本發明的一實施例中，上述的判斷目標電路的初始化是否正常之步驟包括：當目標信號的準位於額定期間內達額定準位時，判定目標電路的初始化為正常；當目標信號的準位於額定期間內未達額定準位，且目標信號的轉態速率不為0時，判定目標電路的初始化為正常；以及當目標信號的準位於額定期間內未達額定準位，且目標信號的轉態速率幾乎為0時，判定目標電路的初始化為失敗。In an embodiment of the present invention, the step of judging whether the initialization of the target circuit is normal includes: determining that the initialization of the target circuit is normal when the target signal reaches the rated level within the rated period; If the target signal does not reach the rated level during the rated period and the target signal's transition rate is not 0, the initialization of the target circuit is determined to be normal; When the transition rate is almost zero, it is determined that the initialization of the target circuit has failed.
本發明的實施例提供一種積體電路晶片。所述積體電路晶片包括目標電路以及轉態偵測電路。目標電路用以產生目標信號。轉態偵測電路耦接至目標電路。轉態偵測電路用以偵測於初始化期間目標信號的轉態，以產生轉態偵測結果。An embodiment of the present invention provides an integrated circuit wafer. The integrated circuit chip includes a target circuit and a transition detection circuit. The target circuit is used to generate a target signal. The transition detection circuit is coupled to the target circuit. The transition detection circuit is used to detect a transition of a target signal during initialization to generate a transition detection result.
在本發明的一實施例中，上述的積體電路晶片更包括準位偵測電路。準位偵測電路耦接至目標電路。準位偵測電路用以偵測目標信號的準位，以產生準位偵測結果。In an embodiment of the present invention, the integrated circuit chip further includes a level detection circuit. The level detection circuit is coupled to the target circuit. The level detection circuit is used to detect the level of the target signal to generate a level detection result.
在本發明的一實施例中，當上述的目標信號的準位於第一期間未達額定準位，且目標信號的轉態速率不為0時，目標電路加大目標信號的轉態速率，以使目標信號的準位於額定期間內達到額定準位。In an embodiment of the present invention, when the above-mentioned target signal is in the first period and the rated level is not reached and the target signal transition rate is not 0, the target circuit increases the target signal transition rate to Make the target signal reach the rated level within the rated period.
在本發明的一實施例中，上述的轉態偵測結果被記錄於積體電路晶片內的第一狀態暫存器，而準位偵測結果被記錄於該積體電路晶片內的第二狀態暫存器。In an embodiment of the present invention, the above-mentioned transition detection result is recorded in a first state register in the integrated circuit chip, and the level detection result is recorded in a second state register in the integrated circuit chip. Status register.
在本發明的一實施例中，上述的目標電路包括電源供應電路、回授電路與電壓比較電路，而上述的轉態偵測電路包括濾波器。電源供應電路提供電源電壓作為目標信號。回授電路耦接至電源供應電路以接收電源電壓，並且回授電路提供回授電壓。電壓比較電路耦接至回授電路以接收回授電壓。電壓比較電路比較回授電壓與參考電壓，以產生比較結果給電源供應電路的回授控制端。濾波器耦接至電壓比較電路，以接收比較結果。濾波器對比較結果進行濾波，以獲得轉態偵測結果。In an embodiment of the present invention, the target circuit includes a power supply circuit, a feedback circuit, and a voltage comparison circuit, and the transition detection circuit includes a filter. The power supply circuit provides a power supply voltage as a target signal. The feedback circuit is coupled to the power supply circuit to receive the power supply voltage, and the feedback circuit provides a feedback voltage. The voltage comparison circuit is coupled to the feedback circuit to receive the feedback voltage. The voltage comparison circuit compares the feedback voltage with a reference voltage to generate a comparison result to the feedback control terminal of the power supply circuit. The filter is coupled to the voltage comparison circuit to receive the comparison result. The filter filters the comparison result to obtain a transition detection result.
基於上述，本發明諸實施例所述積體電路晶片被配置了轉態偵測電路。於初始化期間，轉態偵測電路可以偵測目標電路的目標信號的轉態，以產生轉態偵測結果。也就是說，積體電路晶片可以自我監視目標信號的轉態。依據轉態偵測結果，目標電路的初始化是否正常可以被判斷，而不需要昂貴的測試機台。Based on the above, the integrated circuit chip according to the embodiments of the present invention is configured with a transition detection circuit. During the initialization period, the transition detection circuit can detect the transition of the target signal of the target circuit to generate a transition detection result. In other words, the integrated circuit chip can monitor the transition of the target signal by itself. According to the transition detection result, whether the initialization of the target circuit is normal can be judged without the need for expensive test equipment.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.
在本案說明書全文(包括申請專利範圍)中所使用的「耦接（或連接）」一詞可指任何直接或間接的連接手段。舉例而言，若文中描述第一裝置耦接（或連接）於第二裝置，則應該被解釋成該第一裝置可以直接連接於該第二裝置，或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似部分。不同實施例中使用相同標號或使用相同用語的元件/構件/步驟可以相互參照相關說明。The term "coupling (or connection)" used throughout the specification of this case (including the scope of patent application) can refer to any direct or indirect means of connection. For example, if the first device is described as being coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected through another device or some This connection means is indirectly connected to the second device. In addition, wherever possible, the same reference numbers are used in the drawings and embodiments to represent the same or similar parts. Elements / components / steps using the same reference numerals or using the same terms in different embodiments may refer to related descriptions.
圖1繪示一種積體電路晶片100的電路方塊（circuit block）示意圖。積體電路晶片100包括目標電路110以及電壓偵測電路120。為方便說明，在此假設目標電路110為電源供應電路，因此目標電路110具有電壓調整器（voltage regulator）111、回授電路112與電壓比較電路113。電壓調整器111使用輸入電壓Vin來提供電源電壓Vout。依照電壓調整器111的回授控制端的比較結果CPR1，電壓調整器111可以對應調整電源電壓Vout的準位。電壓調整器111可以是習知的電壓調整器或是其他電源供應電路/元件。電源電壓Vout可以供電給積體電路晶片100的其他電路/元件。FIG. 1 is a schematic diagram of a circuit block of an integrated circuit chip 100. The integrated circuit chip 100 includes a target circuit 110 and a voltage detection circuit 120. For convenience of description, the target circuit 110 is assumed to be a power supply circuit, so the target circuit 110 has a voltage regulator 111, a feedback circuit 112, and a voltage comparison circuit 113. The voltage regulator 111 uses the input voltage Vin to provide the power supply voltage Vout. According to the comparison result CPR1 of the feedback control terminal of the voltage regulator 111, the voltage regulator 111 can correspondingly adjust the level of the power supply voltage Vout. The voltage regulator 111 may be a conventional voltage regulator or other power supply circuits / components. The power supply voltage Vout can supply power to other circuits / components of the integrated circuit chip 100.
回授電路112耦接至電壓調整器111，以接收電源電壓Vout，並且提供回授電壓VFB1給電壓比較電路113。電壓比較電路113的第一輸入端耦接至回授電路112，以接收回授電壓VFB1。電壓比較電路113的第二輸入端接收參考電壓VREF1。電壓比較電路113可以比較回授電壓VFB1與參考電壓VREF1，以產生比較結果CPR1給電壓調整器111的回授控制端。電壓比較電路113可以是習知的電壓比較器或是其他準位比較電路/元件。The feedback circuit 112 is coupled to the voltage regulator 111 to receive the power supply voltage Vout, and provides the feedback voltage VFB1 to the voltage comparison circuit 113. The first input terminal of the voltage comparison circuit 113 is coupled to the feedback circuit 112 to receive the feedback voltage VFB1. The second input terminal of the voltage comparison circuit 113 receives the reference voltage VREF1. The voltage comparison circuit 113 may compare the feedback voltage VFB1 with the reference voltage VREF1 to generate a comparison result CPR1 to the feedback control terminal of the voltage regulator 111. The voltage comparison circuit 113 may be a conventional voltage comparator or other level comparison circuits / components.
圖2繪示一種檢查方法的流程示意圖。請參照圖1與圖2。於步驟S210中，目標電路110被啟動（例如，開始供應輸入電壓Vin給電壓調整器111）。在目標電路110被啟動後，目標電路110會進行初始化，以便讓目標電路110進入正常操作模式。理想上，在初始化期間中，目標電路110可以將電源電壓Vout從0伏特拉至額定電壓準位。FIG. 2 is a schematic flowchart of an inspection method. Please refer to FIG. 1 and FIG. 2. In step S210, the target circuit 110 is activated (for example, the supply of the input voltage Vin to the voltage regulator 111 is started). After the target circuit 110 is started, the target circuit 110 is initialized so that the target circuit 110 enters a normal operation mode. Ideally, during the initialization period, the target circuit 110 can set the power supply voltage Vout from 0 volts to a rated voltage level.
於步驟S220中，電壓偵測電路120可以偵測電源電壓Vout的準位。電壓偵測電路120可以是習知的電壓準位偵測器或是其他準位偵測電路/元件。當步驟S220判斷目標信號的準位（電源電壓Vout的電壓準位）已經達到額定準位時，步驟S230會被執行。於步驟S230中，電壓偵測電路120可以輸出準位偵測結果LOK，以表示「準位OK」。依照設計需求，準位偵測結果LOK可以有不同的處理方式。在一些實施例中，準位偵測結果LOK可以被傳送至焊墊（未繪示）或接腳（未繪示），以便將準位偵測結果LOK提供給較便宜的外部測試治具（例如電壓表、示波器、電腦等，未繪示）。在另一些實施例中，準位偵測結果LOK可以被記錄在積體電路晶片100內的狀態暫存器（register，未繪示）中。依照應用需求，此狀態暫存器（未繪示）的內容可以供應給外部分析平台（例如電腦，未繪示），以及/或是此狀態暫存器（未繪示）的內容可以供應給在積體電路晶片100內的控制電路（未繪示）。In step S220, the voltage detection circuit 120 can detect the level of the power supply voltage Vout. The voltage detection circuit 120 may be a conventional voltage level detector or other level detection circuits / components. When it is determined in step S220 that the level of the target signal (the voltage level of the power supply voltage Vout) has reached the rated level, step S230 is performed. In step S230, the voltage detection circuit 120 may output a level detection result LOK to indicate "level OK". According to the design requirements, the level detection result LOK can be processed in different ways. In some embodiments, the level detection result LOK may be transmitted to a pad (not shown) or a pin (not shown) in order to provide the level detection result LOK to a cheaper external test fixture ( (Such as voltmeter, oscilloscope, computer, etc., not shown). In other embodiments, the level detection result LOK may be recorded in a state register (not shown) in the integrated circuit chip 100. According to application requirements, the contents of this state register (not shown) can be supplied to an external analysis platform (such as a computer, not shown), and / or the contents of this state register (not shown) can be supplied to A control circuit (not shown) in the integrated circuit chip 100.
當步驟S220判斷目標信號的準位（電源電壓Vout的電壓準位）尚未達到額定準位時，步驟S240會被執行。步驟S240可以判定進行初始化的時間是否逾時。若步驟S240判斷尚未逾時，則步驟S220會被再一次執行。若步驟S240判斷已經逾時而目標信號的準位（電源電壓Vout的電壓準位）仍然還沒達到額定準位，則目標電路110的初始化可以被判定為失敗（步驟S250）。When it is determined in step S220 that the level of the target signal (the voltage level of the power supply voltage Vout) has not reached the rated level, step S240 is performed. Step S240 may determine whether the time for initialization has expired. If it is determined in step S240 that the timeout has not expired, step S220 will be executed again. If it is determined in step S240 that the timeout has elapsed and the level of the target signal (the voltage level of the power supply voltage Vout) has not yet reached the rated level, the initialization of the target circuit 110 may be determined as a failure (step S250).
然而，在不同產品的應用環境中，同一個目標電路110所輸出的電源電壓Vout可能有不同的轉態速率（slew rate）。例如，當目標電路110的負載電路為輕負載時，電源電壓Vout從0伏特被拉至額定電壓準位的速率是比較快的，因此可以在額定時間中及時地將電源電壓Vout拉至額定電壓準位，進而目標電路110的初始化被判定為成功（判定目標電路110是良好的）。當目標電路110的負載電路為重負載時，電源電壓Vout從0伏特被拉至額定電壓準位的速率是比較慢的，因此在額定時間中電源電壓Vout可能來不及拉至額定電壓準位，進而目標電路110的初始化被判定為失敗（誤判定目標電路110是壞的）。若有足夠時間，目標電路110仍然可以將電源電壓Vout拉至額定電壓準位。因此，藉由電壓準位的偵測來判定目標電路110是否良好，有可能會造成誤判。However, in the application environment of different products, the power supply voltage Vout output by the same target circuit 110 may have different slew rates. For example, when the load circuit of the target circuit 110 is a light load, the rate at which the power supply voltage Vout is pulled from 0 volts to the rated voltage level is relatively fast, so the power supply voltage Vout can be pulled to the rated voltage in time within the rated time Level, and further, the initialization of the target circuit 110 is determined to be successful (the target circuit 110 is determined to be good). When the load circuit of the target circuit 110 is a heavy load, the rate at which the power supply voltage Vout is pulled from 0 volts to the rated voltage level is relatively slow. Therefore, during the rated time, the power supply voltage Vout may be too late to reach the rated voltage level, and thus The initialization of the circuit 110 is determined to have failed (the target circuit 110 is erroneously determined to be bad). If there is enough time, the target circuit 110 can still pull the power supply voltage Vout to the rated voltage level. Therefore, judging whether the target circuit 110 is good by detecting the voltage level may cause misjudgment.
圖3是依照本發明的一實施例所繪示的一種積體電路晶片300的電路方塊示意圖。積體電路晶片300包括目標電路310以及轉態偵測（slew detection）電路320。目標電路310可以產生目標信號301。依照設計需求，目標電路310可以是積體電路晶片300的任何電路模組。舉例來說，目標電路310可以是電源供應電路，而目標信號301可以是電源電壓。於圖3所示實施例中，準位偵測（level detection）電路330還可以依照設計需求而選擇性地被配置於積體電路晶片300中。FIG. 3 is a schematic circuit block diagram of an integrated circuit chip 300 according to an embodiment of the present invention. The integrated circuit chip 300 includes a target circuit 310 and a slew detection circuit 320. The target circuit 310 may generate a target signal 301. According to design requirements, the target circuit 310 may be any circuit module of the integrated circuit chip 300. For example, the target circuit 310 may be a power supply circuit, and the target signal 301 may be a power supply voltage. In the embodiment shown in FIG. 3, the level detection circuit 330 may be selectively configured in the integrated circuit chip 300 according to design requirements.
圖4是依照本發明的一實施例所繪示的一種積體電路晶片的檢查方法的流程示意圖。請參照圖3與圖4。於步驟S410中，目標電路310被啟動（例如，開始供應電源電壓給目標電路310）。在目標電路310被啟動後，目標電路310會進行初始化，以便讓目標電路310進入正常操作模式。目標電路310可以產生目標信號310。理想上，在初始化期間中，目標電路310可以將目標信號301的準位拉至額定準位。FIG. 4 is a schematic flowchart of an inspection method of an integrated circuit wafer according to an embodiment of the present invention. Please refer to FIG. 3 and FIG. 4. In step S410, the target circuit 310 is activated (for example, the supply of the power supply voltage to the target circuit 310 is started). After the target circuit 310 is started, the target circuit 310 is initialized so that the target circuit 310 enters a normal operation mode. The target circuit 310 may generate a target signal 310. Ideally, during the initialization period, the target circuit 310 can pull the level of the target signal 301 to a rated level.
轉態偵測電路320耦接至目標電路310。轉態偵測電路320可以偵測於初始化期間目標信號301的轉態（slew），以產生轉態偵測結果302（步驟S420）。準位偵測電路330耦接至目標電路310。準位偵測電路330可以偵測目標信號301的準位（步驟S430），例如偵測目標信號301的電壓準位、電流準位及/或其他物理量的準位。依據目標信號301的準位，準位偵測電路330可以產生準位偵測結果303。依照設計需求，準位偵測電路330可以是習知的電壓準位偵測器或是其他準位偵測電路/元件。在一些實施例中，圖3所示準位偵測電路330與準位偵測結果303可以參照圖1所示電壓偵測電路120與準位偵測結果LOK的相關說明來類推。The transition detection circuit 320 is coupled to the target circuit 310. The transition detection circuit 320 may detect a transition of the target signal 301 during the initialization period to generate a transition detection result 302 (step S420). The level detection circuit 330 is coupled to the target circuit 310. The level detection circuit 330 can detect the level of the target signal 301 (step S430), for example, detect the level of the voltage, current, and / or other physical quantities of the target signal 301. According to the level of the target signal 301, the level detection circuit 330 can generate a level detection result 303. According to design requirements, the level detection circuit 330 may be a conventional voltage level detector or other level detection circuits / components. In some embodiments, the level detection circuit 330 and the level detection result 303 shown in FIG. 3 can be deduced by referring to the description of the voltage detection circuit 120 and the level detection result LOK shown in FIG. 1.
依照設計需求，轉態偵測結果302與準位偵測結果303可以有不同的處理方式。在一些實施例中，轉態偵測結果302與準位偵測結果303可以分別被傳送至不同焊墊（未繪示）或不同接腳（未繪示），以便將轉態偵測結果302與準位偵測結果303提供給較便宜的外部測試治具（例如電壓表、示波器、電腦等，未繪示）。在另一些實施例中，轉態偵測結果302與準位偵測結果303可以分別被記錄在積體電路晶片100內的第一狀態暫存器（未繪示）與第二狀態暫存器（未繪示）中。依照應用需求，這些狀態暫存器（未繪示）的內容可以供應給外部分析平台（例如電腦，未繪示），以及/或是這些狀態暫存器（未繪示）的內容可以供應給在積體電路晶片100內的控制電路（未繪示）。According to design requirements, the transition detection result 302 and the level detection result 303 can be processed in different ways. In some embodiments, the transition detection result 302 and the level detection result 303 may be transmitted to different pads (not shown) or different pins (not shown), respectively, so as to transfer the transition detection result 302. The level detection result 303 is provided to a cheaper external test fixture (such as a voltmeter, oscilloscope, computer, etc., not shown). In other embodiments, the transition detection result 302 and the level detection result 303 may be recorded in a first state register (not shown) and a second state register in the integrated circuit chip 100, respectively. (Not shown). According to application requirements, the contents of these state registers (not shown) can be supplied to external analysis platforms (such as computers, not shown), and / or the contents of these state registers (not shown) can be supplied to A control circuit (not shown) in the integrated circuit chip 100.
在步驟S440中，相關的檢查電路（未繪示，例如外部測試治具、外部分析平台或是內部控制電路）可以依據轉態偵測結果302與/或準位偵測結果303來判斷目標電路310的初始化是否正常。在一些實施例中，圖4所示步驟S440可以參照圖2所示步驟S220、S230、S240與S250的相關說明來類推。In step S440, the relevant inspection circuit (not shown, such as an external test fixture, an external analysis platform, or an internal control circuit) may determine the target circuit according to the transition detection result 302 and / or the level detection result 303. Whether the initialization of 310 is normal. In some embodiments, step S440 shown in FIG. 4 can be deduced by referring to the related description of steps S220, S230, S240, and S250 shown in FIG. 2.
圖5繪示了在一些實施例中，圖3所示電路的信號波形示意圖。於時間點t51，目標電路310被啟動，因此目標電路310在初始化期間Pini中可以將目標信號301的準位拉至額定準位。轉態偵測電路320可以在初始化期間Pini中偵測目標信號301的轉態（slew）。由於在初始化期間Pini中目標信號301的轉態速率不為0，因此在初始化期間Pini中轉態偵測結果302為高邏輯（表示目標信號301有轉態）。準位偵測電路330可以在初始化期間Pini中偵測目標信號301的準位。由於在初始化期間Pini中目標信號301的準位還沒有達到額定準位，因此在初始化期間Pini中準位偵測結果303為低邏輯。FIG. 5 is a schematic diagram of signal waveforms of the circuit shown in FIG. 3 in some embodiments. At time point t51, the target circuit 310 is activated, so the target circuit 310 can pull the level of the target signal 301 to the rated level during the initialization period Pini. The transition detection circuit 320 may detect a slew of the target signal 301 during the initialization period Pini. Since the transition rate of the target signal 301 during the initialization period is not 0, the transition detection result 302 during the initialization period of Pini is high logic (indicating that the target signal 301 has a transition state). The level detection circuit 330 can detect the level of the target signal 301 during the initialization period Pini. Since the level of the target signal 301 in the initialization period Pini has not reached the rated level, the level detection result 303 in the initialization period Pini is low logic.
當目標信號301的準位達到額定準位時，初始化期間Pini結束。由於在初始化期間Pini結束後的目標信號301的轉態速率幾乎為0，因此轉態偵測結果302為低邏輯（表示目標信號301沒有轉態）。由於在初始化期間Pini結束後的目標信號301的準位已達到額定準位，因此準位偵測結果303為高邏輯。When the level of the target signal 301 reaches the rated level, the initialization period Pini ends. Since the transition rate of the target signal 301 after the end of the initialization period Pini is almost 0, the transition detection result 302 is low logic (indicating that the target signal 301 has no transition). Since the level of the target signal 301 after the end of the initialization period Pini has reached the rated level, the level detection result 303 is high logic.
步驟S440可以依據轉態偵測結果302與準位偵測結果303來判斷目標電路310的初始化是否正常。當目標信號301的準位於額定期間Pra內達到額定準位時（如圖5所示），相關的檢查電路（未繪示，例如外部測試治具、外部分析平台或是內部控制電路）可以判定目標電路310的初始化為正常。假設目標信號301的準位於額定期間Pra內未達額定準位且目標信號301的轉態速率不為0，亦即初始化期間Pini大於額定期間Pra，則相關的檢查電路（未繪示，例如外部測試治具、外部分析平台或是內部控制電路）可以判定目標電路310的初始化為正常，但需要將額定期間Pra加大。當目標信號301的準位於額定期間Pra內未達到額定準位，且目標信號301的轉態速率幾乎為0時，相關的檢查電路（未繪示，例如外部測試治具、外部分析平台或是內部控制電路）可以判定目標電路310的初始化為失敗，亦即目標電路310可能是損壞的。Step S440 may determine whether the initialization of the target circuit 310 is normal according to the transition detection result 302 and the level detection result 303. When the target signal 301 reaches the rated level within the rated period Pra (as shown in Figure 5), the relevant inspection circuit (not shown, such as an external test fixture, external analysis platform or internal control circuit) can determine The initialization of the target circuit 310 is normal. Assuming that the quasi-target signal 301 is not within the rated period Pra and the transition rate of the target signal 301 is not 0, that is, the initialization period Pini is greater than the rated period Pra, then the relevant inspection circuit (not shown, such as external The test fixture, external analysis platform, or internal control circuit) can determine that the initialization of the target circuit 310 is normal, but it is necessary to increase the rated period Pra. When the quasi-target signal 301 is not within the rated period Pra and does not reach the rated level, and the transition rate of the target signal 301 is almost 0, the relevant inspection circuit (not shown, such as an external test fixture, external analysis platform, or The internal control circuit) can determine that the initialization of the target circuit 310 has failed, that is, the target circuit 310 may be damaged.
圖6繪示了在另一些實施例中，圖3所示電路的信號波形示意圖。於時間點t61，目標電路310被啟動，因此目標電路310在初始化期間Pini中可以將目標信號301的準位拉至額定準位。轉態偵測電路320可以在第一期間P1中偵測目標信號301的轉態（slew）。當步驟S440判斷目標信號301的準位於第一期間P1未達額定準位，且目標信號301的轉態速率不為0時，目標電路310可以在第二期間P2中加大目標信號301的轉態速率，以便即時地縮短初始化期間Pini。當目標信號301的準位達到額定準位時，初始化期間Pini結束。由於初始化期間Pini並未超出額定期間Pra，因此目標信號301的準位於額定期間Pra內可以達到額定準位。FIG. 6 is a schematic diagram of signal waveforms of the circuit shown in FIG. 3 in other embodiments. At time point t61, the target circuit 310 is activated, so the target circuit 310 can pull the level of the target signal 301 to the rated level during the initialization period Pini. The transition detection circuit 320 may detect a slew of the target signal 301 in the first period P1. When it is determined in step S440 that the target signal 301 is located in the first period P1 not reaching the rated level and the transition rate of the target signal 301 is not 0, the target circuit 310 may increase the target signal 301 in the second period P2. State rate in order to instantly shorten the Pini during initialization. When the level of the target signal 301 reaches the rated level, the initialization period Pini ends. Since Pini does not exceed the rated period Pra during the initialization period, the target signal 301 can be located within the rated period Pra to reach the rated level.
圖7是依照本發明的一實施例說明圖3所示目標電路310與轉態偵測電路320的電路方塊示意圖。於圖7所示實施例中，目標電路310包括電源供應電路311、回授電路312與電壓比較電路313，而轉態偵測電路320包括濾波器321。依照設計需求，轉態偵測電路320還可以選擇性地配置閂鎖電路322，例如閂鎖器、正反器或是其他閂鎖電路/元件。FIG. 7 is a circuit block diagram illustrating the target circuit 310 and the transition detection circuit 320 shown in FIG. 3 according to an embodiment of the present invention. In the embodiment shown in FIG. 7, the target circuit 310 includes a power supply circuit 311, a feedback circuit 312, and a voltage comparison circuit 313, and the transition detection circuit 320 includes a filter 321. According to the design requirements, the transition detection circuit 320 can also optionally configure a latch circuit 322, such as a latch, a flip-flop or other latch circuits / components.
依照電源供應電路311的回授控制端的比較結果CPR7，電源供應電路311可以提供電源電壓作為目標信號301，其中所述電源電壓可以供電給積體電路晶片300的其他電路/元件。依照設計需求，電源供應電路311可以是電壓調整器（voltage regulator）、功率轉換電路或是其他電源供應電路/元件。在一些實施例中，電源供應電路311可以是習知的電壓調整器。回授電路312耦接至電源供應電路311，以接收電源電壓（目標信號301），並且提供回授電壓VFB7給電壓比較電路313。電壓比較電路313耦接至回授電路312，以接收回授電壓VFB7。電壓比較電路313可以比較回授電壓VFB7與參考電壓VREF7，以產生比較結果CPR7給電源供應電路311的回授控制端。According to the comparison result CPR7 of the feedback control terminal of the power supply circuit 311, the power supply circuit 311 can provide a power supply voltage as the target signal 301, wherein the power supply voltage can supply power to other circuits / components of the integrated circuit chip 300. According to design requirements, the power supply circuit 311 may be a voltage regulator, a power conversion circuit, or other power supply circuits / components. In some embodiments, the power supply circuit 311 may be a conventional voltage regulator. The feedback circuit 312 is coupled to the power supply circuit 311 to receive the power supply voltage (target signal 301), and provides the feedback voltage VFB7 to the voltage comparison circuit 313. The voltage comparison circuit 313 is coupled to the feedback circuit 312 to receive the feedback voltage VFB7. The voltage comparison circuit 313 can compare the feedback voltage VFB7 with the reference voltage VREF7 to generate a comparison result CPR7 to the feedback control terminal of the power supply circuit 311.
圖8繪示了在一些實施例中，圖7所示電路的信號波形示意圖。於時間點t81，目標電路310被啟動（例如開始提供輸入電壓Vin給電源供應電路311），因此目標電路310在初始化期間Pini中可以將目標信號301的準位拉至額定準位。在初始化期間Pini中，由於回授電壓VFB7小於參考電壓VREF7，因此比較結果CPR7為高邏輯。當目標信號301的準位達到額定準位時，初始化期間Pini結束。FIG. 8 is a schematic diagram of signal waveforms of the circuit shown in FIG. 7 in some embodiments. At time point t81, the target circuit 310 is activated (for example, the input voltage Vin is started to be supplied to the power supply circuit 311), so the target circuit 310 can pull the level of the target signal 301 to the rated level during the initialization period Pini. During the initialization period Pini, since the feedback voltage VFB7 is smaller than the reference voltage VREF7, the comparison result CPR7 is high logic. When the level of the target signal 301 reaches the rated level, the initialization period Pini ends.
濾波器321耦接至電壓比較電路313，以接收比較結果CPR7。濾波器321可以對比較結果CPR7進行濾波，以獲得轉態偵測結果302’。依照設計需求，濾波器321可以是低通濾波器、待通濾波器或是其他濾波電路/元件。在一些實施例中，電源供應電路311可以是習知的低通濾波器。閂鎖電路322耦接至濾波器321的輸出端，以接收並閂鎖轉態偵測結果302’，以及輸出閂鎖結果作為轉態偵測結果302。因此，轉態偵測電路320可以在初始化期間Pini中偵測目標信號301的轉態（slew）。The filter 321 is coupled to the voltage comparison circuit 313 to receive the comparison result CPR7. The filter 321 may filter the comparison result CPR7 to obtain a transition detection result 302 '. According to design requirements, the filter 321 may be a low-pass filter, a to-be-passed filter, or other filter circuits / components. In some embodiments, the power supply circuit 311 may be a conventional low-pass filter. The latch circuit 322 is coupled to the output terminal of the filter 321 to receive and latch the transition detection result 302 ', and output the latch result as the transition detection result 302. Therefore, the transition detection circuit 320 can detect the slew of the target signal 301 during the initialization period Pini.
由於在初始化期間Pini中目標信號301的轉態速率不為0，因此在初始化期間Pini中轉態偵測結果302’為高邏輯（表示目標信號301有轉態）。準位偵測電路330可以在初始化期間Pini中偵測目標信號301的準位。由於在初始化期間Pini中目標信號301的準位還沒有達到額定準位，因此在初始化期間Pini中準位偵測結果303為低邏輯。由於在初始化期間Pini結束後的目標信號301的轉態速率幾乎為0，因此轉態偵測結果302為低邏輯（表示目標信號301沒有轉態）。由於在初始化期間Pini結束後的目標信號301的準位已達到額定準位，因此準位偵測結果303為高邏輯。Since the transition rate of the target signal 301 during the initialization period is not 0, the transition detection result 302 'in the initialization period Pini is high logic (indicating that the target signal 301 has a transition state). The level detection circuit 330 can detect the level of the target signal 301 during the initialization period Pini. Since the level of the target signal 301 in the initialization period Pini has not reached the rated level, the level detection result 303 in the initialization period Pini is low logic. Since the transition rate of the target signal 301 after the end of the initialization period Pini is almost 0, the transition detection result 302 is low logic (indicating that the target signal 301 has no transition). Since the level of the target signal 301 after the end of the initialization period Pini has reached the rated level, the level detection result 303 is high logic.
綜上所述，本發明諸實施例所述積體電路晶片300被配置了轉態偵測電路320。於初始化期間，轉態偵測電路320可以偵測目標電路310的目標信號301的轉態，以產生轉態偵測結果302。也就是說，積體電路晶片300可以自我監視目標信號301的轉態。依據轉態偵測結果302可以判斷目標電路310的初始化是否正常，而不需要昂貴的測試機台。In summary, the integrated circuit chip 300 according to the embodiments of the present invention is configured with a transition detection circuit 320. During the initialization period, the transition detection circuit 320 can detect the transition of the target signal 301 of the target circuit 310 to generate a transition detection result 302. That is, the integrated circuit chip 300 can monitor the transition state of the target signal 301 by itself. According to the transition detection result 302, it can be determined whether the initialization of the target circuit 310 is normal, without the need for expensive test equipment.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
100‧‧‧積體電路晶片100‧‧‧Integrated Circuit Chip
110‧‧‧目標電路110‧‧‧ target circuit
111‧‧‧電壓調整器111‧‧‧Voltage Regulator
112‧‧‧回授電路112‧‧‧Feedback circuit
113‧‧‧電壓比較電路113‧‧‧Voltage comparison circuit
120‧‧‧電壓偵測電路120‧‧‧Voltage detection circuit
300‧‧‧積體電路晶片300‧‧‧Integrated Circuit Chip
301‧‧‧目標信號301‧‧‧ target signal
302、302’‧‧‧轉態偵測結果302, 302’‧‧‧ transition detection results
303‧‧‧準位偵測結果303‧‧‧Level detection result
310‧‧‧目標電路310‧‧‧Target Circuit
311‧‧‧電源供應電路311‧‧‧Power supply circuit
312‧‧‧回授電路312‧‧‧Feedback circuit
313‧‧‧電壓比較電路313‧‧‧Voltage comparison circuit
320‧‧‧轉態偵測電路320‧‧‧Transition detection circuit
321‧‧‧濾波器321‧‧‧Filter
322‧‧‧閂鎖電路322‧‧‧Latch circuit
330‧‧‧準位偵測電路330‧‧‧level detection circuit
CPR1、CPR7‧‧‧比較結果CPR1, CPR7‧‧‧Comparison results
LOK‧‧‧準位偵測結果LOK‧‧‧ Level Detection Results
P1‧‧‧第一期間P1‧‧‧First Period
P2‧‧‧第二期間P2‧‧‧Second Period
Pini‧‧‧初始化期間Pini‧‧‧ during initialization
Pra‧‧‧額定期間Pra‧‧‧ rated period
S210～S250、S410～S440‧‧‧步驟S210 ～ S250, S410 ～ S440‧‧‧step
t51、t61、t81‧‧‧時間點t51, t61, t81‧‧‧
VFB1、VFB7‧‧‧回授電壓VFB1, VFB7‧‧‧Feedback voltage
Vin‧‧‧輸入電壓Vin‧‧‧ input voltage
Vout‧‧‧電源電壓Vout‧‧‧ supply voltage
VREF1、VREF7‧‧‧參考電壓VREF1, VREF7‧‧‧ reference voltage
圖1繪示一種積體電路晶片100的電路方塊（circuit block）示意圖。 圖2繪示一種檢查方法的流程示意圖。 圖3是依照本發明的一實施例所繪示的一種積體電路晶片的電路方塊示意圖。 圖4是依照本發明的一實施例所繪示的一種積體電路晶片的檢查方法的流程示意圖。 圖5繪示了在一些實施例中，圖3所示電路的信號波形示意圖。 圖6繪示了在另一些實施例中，圖3所示電路的信號波形示意圖。 圖7是依照本發明的一實施例說明圖3所示目標電路與轉態偵測電路的電路方塊示意圖。 圖8繪示了在一些實施例中，圖7所示電路的信號波形示意圖。FIG. 1 is a schematic diagram of a circuit block of an integrated circuit chip 100. FIG. 2 is a schematic flowchart of an inspection method. FIG. 3 is a schematic circuit block diagram of an integrated circuit chip according to an embodiment of the present invention. FIG. 4 is a schematic flowchart of an inspection method of an integrated circuit wafer according to an embodiment of the present invention. FIG. 5 is a schematic diagram of signal waveforms of the circuit shown in FIG. 3 in some embodiments. FIG. 6 is a schematic diagram of signal waveforms of the circuit shown in FIG. 3 in other embodiments. FIG. 7 is a circuit block diagram illustrating the target circuit and the transition detection circuit shown in FIG. 3 according to an embodiment of the present invention. FIG. 8 is a schematic diagram of signal waveforms of the circuit shown in FIG. 7 in some embodiments.
Claims (8)
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| US20050083206A1 (en) * | 2003-09-05 | 2005-04-21 | Couch Philip R. | Remote electrical power monitoring systems and methods |
| TW200928654A (en) * | 2007-12-31 | 2009-07-01 | Powerchip Semiconductor Corp | Voltage adjusting circuits |
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| TW442945B (en) * | 1998-11-20 | 2001-06-23 | Sony Computer Entertainment Inc | Integrated circuit chip, integrated circuit device, printed circuit board and electronic machine |
| US6161213A (en) * | 1999-02-17 | 2000-12-12 | Icid, Llc | System for providing an integrated circuit with a unique identification |
| US7197680B2 (en) * | 2003-04-17 | 2007-03-27 | Arm Limited | Communication interface for diagnostic circuits of an integrated circuit |
| US8674355B2 (en) * | 2010-12-29 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit test units with integrated physical and electrical test regions |
| CN104142839B (en) * | 2014-07-15 | 2018-01-12 | 惠州市德赛西威汽车电子股份有限公司 | A kind of method for preventing audio chip initialization failure |
| CN104502883B (en) * | 2014-12-30 | 2017-07-07 | 宁波三星医疗电气股份有限公司 | The abnormality detection and solution of computation chip |
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| US20050083206A1 (en) * | 2003-09-05 | 2005-04-21 | Couch Philip R. | Remote electrical power monitoring systems and methods |
| TW200928654A (en) * | 2007-12-31 | 2009-07-01 | Powerchip Semiconductor Corp | Voltage adjusting circuits |
| US20100030393A1 (en) * | 2008-07-29 | 2010-02-04 | Masters Gilbert J | Apparatus Using Time-Based Electrical Characteristics to Identify an Electrical Appliance |
| TW201116844A (en) * | 2009-11-11 | 2011-05-16 | Inventec Corp | Voltage measuring apparatus for printed circuit board |
| TW201221974A (en) * | 2010-11-19 | 2012-06-01 | Hon Hai Prec Ind Co Ltd | Power-on and power-off test system and method |
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