TWI637271B - Coordinating device and application break events for platform power saving - Google Patents
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
本發明之用於管理中斷事件的數個系統與方法可供用於:檢測來自於一第一事件來源的一第一中斷事件、以及檢測來自於一第二事件來源的一第二中斷事件。在一個範例中,這些事件來源可包括耦接至一個平臺的裝置以及在此平臺上的作動應用程式。可至少部份基於與平臺相關聯的運行時間資訊而協調第一和第二中斷事件至平臺之發出。 Several systems and methods of the present invention for managing interrupt events are available for detecting a first interrupt event from a first event source and detecting a second interrupt event from a second event source. In one example, these event sources may include devices coupled to one platform and actuating applications on the platform. The issuance of the first and second interrupt events to the platform can be coordinated based at least in part on the runtime information associated with the platform.
Description
本發明的數個實施例大體上係有關平臺中斷事件之管理。尤其是,本發明的數個實施例係有關對來自於不同來源的中斷事件之發出作協調,以改良節省平臺電力之能力。 Several embodiments of the present invention are generally related to the management of platform interrupt events. In particular, several embodiments of the present invention relate to the coordination of the issuance of interrupt events from different sources to improve the ability to save platform power.
在傳統的行動運算平台中,多輸入/輸出(input/output,IO)裝置(例如,通訊介面)和軟體應用程式可能會產生不協調的中斷事件,這可使平臺及其部件無法快速地進入低功率狀態並在那些狀態中待上較長的時間。確實,較短且次於最佳的電池壽命可導致平臺比所需更頻繁地持續待在較高功率狀態中。 In traditional mobile computing platforms, multiple input/output (IO) devices (eg, communication interfaces) and software applications may create uncoordinated interrupt events that prevent the platform and its components from entering quickly. Low power state and stay in those states for a longer period of time. Indeed, a shorter and less than optimal battery life can result in the platform staying in a higher power state more frequently than needed.
依據本發明之一實施例,係特地提出一種具有機器可執行指令之機器可讀儲存媒體,當該等指令被執行時,致使一處理器用以進行一方法,該方法包含:檢測與 一第一處理程序相關聯之一第一計時器,該第一計時器指出一等待時段,該第一處理程序係在此等待時段之前執行;檢測與一第二處理程序相關聯之一第二計時器,該第二計時器指出一等待時段,該第二處理程序係在此等待時段之前執行;以及根據與該等第一及第二處理程序相關聯之一條件而將該等第一及第二計時器作時間性聯合。 In accordance with an embodiment of the present invention, a machine readable storage medium having machine executable instructions is provided that, when executed, cause a processor to perform a method, the method comprising: detecting and first a first timer associated with the processing program, the first timer indicating a waiting period, the first processing program being executed prior to the waiting period; detecting a second timer associated with a second processing program, The second timer indicates a waiting period, the second processing program is executed prior to the waiting period; and the first and second timings are based on a condition associated with the first and second processing programs Time for unity.
10、20‧‧‧中斷事件 10, 20‧‧‧ interrupted events
10a、10c、10d‧‧‧輸入/輸出(IO)事件 10a, 10c, 10d‧‧‧ Input/Output (IO) events
10b、10e、10f‧‧‧計時器事件 10b, 10e, 10f‧‧‧ timer events
12、14、16‧‧‧經延長閒置時段 12, 14, 16‧‧ ‧ extended idle time
18、50、82‧‧‧中斷事件管理單元(BMU) 18, 50, 82‧‧‧ Interrupt Event Management Unit (BMU)
22‧‧‧經協調中斷事件 22‧‧‧Coordinated Interruption
24‧‧‧運行時間資訊 24‧‧‧Runtime information
26‧‧‧平臺/作業系統(OS) 26‧‧‧Platform/Operating System (OS)
28‧‧‧來源 28‧‧‧Source
30‧‧‧方法 30‧‧‧Method
32~46‧‧‧方塊 32~46‧‧‧
48、60‧‧‧系統 48, 60‧‧‧ system
52‧‧‧處理器/平臺 52‧‧‧Processor/platform
54‧‧‧計時器 54‧‧‧Timer
56(56a~56c)‧‧‧裝置 56 (56a~56c)‧‧‧ device
58‧‧‧聯合單元 58‧‧‧Union unit
62‧‧‧處理器 62‧‧‧Processor
64‧‧‧輸入/輸出(IO)模組 64‧‧‧Input/Output (IO) Module
66‧‧‧系統記憶體 66‧‧‧System Memory
68‧‧‧網路控制器 68‧‧‧Network Controller
70‧‧‧固態磁碟(SSD) 70‧‧‧Solid Disk (SSD)
72‧‧‧音訊輸入/輸出(IO)裝置 72‧‧‧Optical input/output (IO) devices
74‧‧‧積體記憶體控制器(IMC) 74‧‧‧Integrated Memory Controller (IMC)
76‧‧‧核心 76‧‧‧ core
78‧‧‧功率管理單元(PMU) 78‧‧‧Power Management Unit (PMU)
80‧‧‧其他控制器 80‧‧‧Other controllers
t1~t6、t1d~t6d‧‧‧瞬時 t 1 ~t 6 , t 1d ~t 6d ‧‧‧ instantaneous
藉由閱讀下文中之說明與後附申請專利範圍,並參考下面的圖式,熟於此技者可明顯看出本發明的數個實施例之多種優點,在這些圖式中:第1圖為依據本發明之一實施例的多個經協調中斷事件之一範例的方塊圖;第2圖為依據本發明之一實施例的一個中斷事件管理單元之方塊圖;第3圖為依據本發明之一實施例的用於協調中斷事件之發出的一個方法之流程圖;第4圖為依據本發明之一實施例的一個中斷事件管理單元和多個聯合單元之方塊圖;並且第5圖為依據本發明之一實施例的一個平臺之一範例的方塊圖。 The various advantages of several embodiments of the present invention will become apparent to those skilled in the <RTIgt; </ RTI> <RTIgt; Block diagram of an example of a plurality of coordinated interrupt events in accordance with an embodiment of the present invention; FIG. 2 is a block diagram of an interrupt event management unit in accordance with an embodiment of the present invention; A flowchart of a method for coordinating the issuance of an interrupt event in an embodiment; FIG. 4 is a block diagram of an interrupt event management unit and a plurality of joint units in accordance with an embodiment of the present invention; and FIG. A block diagram of an example of a platform in accordance with an embodiment of the present invention.
本發明的數個實施例可提供一種方法,於此方法中,係檢測到來自於一第一事件來源的一第一中斷事件, 並檢測到來自於一第二事件來源的一第二中斷事件。此方法可亦供用於至少部份基於與一個平臺相關聯的運行時間資訊而協調第一和第二中斷事件至此平臺之發出。 Several embodiments of the present invention may provide a method in which a first interrupt event from a first event source is detected and a second interrupt event from a second event source is detected . The method can also be used to coordinate the issuance of the first and second interrupt events to the platform based at least in part on runtime information associated with a platform.
其他數個實施例可包括具有一組指令的一種電腦可讀儲存媒體,此組指令在由一個處理器執行時會致使一個電腦檢測來自於一第一事件來源的一第一中斷事件,及檢測來自於一第二事件來源的一第二中斷事件。這些指令可亦致使一個電腦至少部份基於與一個平臺相關聯的運行時間資訊而協調第一和第二中斷事件至此平臺之發出。 Other embodiments may include a computer readable storage medium having a set of instructions that, when executed by a processor, cause a computer to detect a first interrupt event from a first event source, and to detect A second interrupt event from a second event source. The instructions may also cause a computer to coordinate the issuance of the first and second interrupt events to the platform based at least in part on runtime information associated with a platform.
此外,本發明的數個實施例可包括一種設備,其具有一個輸入輸出(IO)模組,此IO模組具有用於檢測來自於一第一事件來源之一第一中斷事件以及檢測來自於一第二事件來源之一第二中斷事件的邏輯。此邏輯可亦至少部份基於與一個平臺相關聯的運行時間資訊而協調第一和第二中斷事件至此平臺之發出。 Moreover, several embodiments of the present invention can include an apparatus having an input/output (IO) module having a first interrupt event for detecting a source from a first event and detecting from The logic of one of the second event sources is the second interrupt event. The logic can also coordinate the issuance of the first and second interrupt events to the platform based, at least in part, on runtime information associated with a platform.
本發明的數個實施例可亦包括一種系統,其具有一第一事件來源、一第二事件來源、一個處理器、和耦接至此處理器的一個輸入輸出(IO)模組。此IO模組可具有用於檢測來自於一第一事件來源之一第一中斷事件以及檢測來自於一第二事件來源之一第二中斷事件的邏輯。此外,此邏輯可至少部份基於與此系統相關聯的運行時間資訊而協調第一和第二中斷事件至此系統之發出。 Several embodiments of the present invention can also include a system having a first event source, a second event source, a processor, and an input/output (IO) module coupled to the processor. The IO module can have logic for detecting a first interrupt event from a first event source and detecting a second interrupt event from a second event source. Additionally, the logic can coordinate the issuance of the first and second interrupt events to the system based at least in part on the runtime information associated with the system.
現在,請看向第1圖,其示出在協調多個中斷事件10(10a~10f)至一個平臺之發出之前與之後的來自於 不同來源(例如,功率管理實體)的中斷事件10。於所例示之此範例中,係針對一個瞬時t1而請求來自於一個裝置,像是滑鼠等,的一個輸入/輸出(IO)事件10a(例如,岔斷),且係針對瞬時t2而請求來自於運行於此平臺上之一作動應用程式的一個計時器事件10b。此外,可係針對瞬時t3而請求來自於另一個裝置,像是一個網路介面卡(network interface card,NIC)等,的一連串IO事件10c。如將更詳細論述的,IO事件10c本身可係藉由設置在此NIC上或一個中央位置處的一個聯合單元而被群聚在一起。可亦針對瞬時t4而請求來自於一個音訊裝置的一個IO事件10d。此外,所例示之範例亦顯示出對於分別針對瞬時t5和t6的來自於作動應用程式之計時器事件10e和10f之檢測。於其自然狀態中,中斷事件10可係具有會阻止平臺進入某些省電狀態較長時間的一個時間設定檔(time profile)。 Turning now to Figure 1, there is shown an interrupt event 10 from a different source (e.g., a power management entity) before and after coordinating a plurality of interrupt events 10 (10a~10f) to the issuance of a platform. In the illustrated example of this, a transient system for t 1 and a request from a device, such as a mouse input and the like, in / output (IO) event 10a (e.g., was interrupted), and the system for transient t 2 The request comes from a timer event 10b running on one of the active applications on the platform. Further, based transient t 3 for the requested from another device, such as a network interface card (network interface card, NIC) and the like, a series of IO events 10c. As will be discussed in more detail, the IO event 10c itself may be grouped together by a joint unit disposed on the NIC or at a central location. Also available for instantaneous t 4 and a request from the IO event 10d in a audio device. Further, the illustrated example also shows detection timer 10e and 10f of the event for each instant t for t. 6 and 5 from the actuation of the application. In its natural state, the interrupt event 10 may have a time profile that would prevent the platform from entering certain power saving states for a longer period of time.
因此,可協調中斷事件10至平臺之發出,以使平臺能夠減少功率損耗。例如,所例示之來自於滑鼠的IO事件10a被延緩至一個經延緩瞬時t1d,以使其可與在經延緩瞬時t2d被發出的應用程式計時器事件10b之發出對齊。在另一個實施例中,計時器事件10b可為一個無延緩事件。在這樣的情況中,可延緩IO事件10a,而計時器事件10b可如排程發出。在此二者當中的任何一種情況中,均可創造出一個經延長閒置時段12,於此經延長閒置時段12中,平臺可較快地進入較深層的省電狀態(例如,先進組態與電力介面規格(Advanced Configuration and Power Interface Specification,ACPI),2009年六月16日的ACPI規格4.0揭示版,低功率狀態),並且因為經延長閒置時段12而待上較長的時間。此外,來自於NIC的IO事件10c可分別於經延緩瞬時t3d和t4d與來自於音訊裝置的IO事件10d對齊,以創造出另一個經延長閒置時段14。類似地,可分別將應用程式計時器事件10e和10f延緩至瞬時t5d和t6d,這可導致一個經延長閒置時段16。簡單來說,經延長閒置時段12、14、16可致能改良的節省平臺電力之能力和較長的電池壽命。 Therefore, the interrupt event 10 can be coordinated to the launch of the platform to enable the platform to reduce power loss. For example, the illustrated IO event 10a from the mouse is deferred to a delayed instant t1d so that it can be aligned with the issuance of the application timer event 10b that was issued at the delayed instant t2d . In another embodiment, the timer event 10b can be a no-delay event. In such a case, the IO event 10a can be deferred and the timer event 10b can be issued as scheduled. In either case, an extended idle period 12 can be created, in which the platform can enter the deeper power saving state faster (for example, advanced configuration and Advanced Configuration and Power Interface Specification (ACPI), ACPI Specification 4.0 Rev. June 16, 2009, low power state), and stays longer due to extended idle time period 12. Further, from the NIC IO events 10c may be respectively delayed by t 4d 10d is aligned with the instantaneous event from the audio IO device 3d and t, to create a further 14 over an extended period of inactivity. Similarly, application timer events 10e and 10f may be deferred to instants t5d and t6d , respectively, which may result in an extended idle period 16. Briefly, extended idle periods 12, 14, 16 can result in improved platform power savings and longer battery life.
第2圖示出一個中斷事件管理單元(break event management unit,BMU)18,其可檢測出中斷事件20並至少部份基於與一個平臺/作業系統(operating system,OS)26相關聯的運行時間資訊24而將其對齊成經協調中斷事件22。BMU 18可係實施在平臺26的一個模組中,例如一個行動網際網路裝置(mobile Internet device,MID)平臺的系統控制單元(system control unit,SCU),或是一個膝上型平臺的平臺控制器集線器(platform controller hub,PCH)。確實,BMU 18可係以稍微不同的介面和實作技術而常駐在作業系統(OS)核心空間中,或是在使用者空間中。在所例示的範例中,運行時間資訊24可係從中斷事件20之來源28以及平臺26本身獲得。例如,獲得自耦接至此平臺的一個裝置的運行時間資訊24可包括有識別針對一或多個IO事件之最大延遲時間的服務品質(quality of service,QoS)規格。此外,獲得自一個應用程式的運行時間資訊24可亦識別一或多個計時器事件的可延緩性特性。例如,若一個計 時器事件是不可延緩的,則BMU 18可試著使其他中斷事件與此不可延緩計時器事件對齊。在其他情況中,BMU 18可管理計時器事件以求最佳平臺功率節省能力和效能。 Figure 2 illustrates an interrupt event management unit (BMU) 18 that can detect an interrupt event 20 and is based, at least in part, on the runtime associated with a platform/operating system (OS) 26. The information 24 is aligned to the coordinated interrupt event 22. The BMU 18 can be implemented in a module of the platform 26, such as a system control unit (SCU) of a mobile Internet device (MID) platform, or a platform for a laptop platform. Controller controller hub (PCH). Indeed, the BMU 18 can reside in the core space of the operating system (OS) with a slightly different interface and implementation technology, or in user space. In the illustrated example, runtime information 24 may be obtained from source 28 of interrupt event 20 and platform 26 itself. For example, runtime information 24 that obtains a device that is auto-coupled to the platform can include a quality of service (QoS) specification that identifies the maximum delay time for one or more IO events. In addition, runtime information 24 obtained from an application may also identify deferrable characteristics of one or more timer events. For example, if a timer event is not deferred, BMU 18 may try to align other interrupt events with this non-delay timer event. In other cases, the BMU 18 can manage timer events for optimal platform power savings and performance.
舉例來說,若一個應用程式請求要使一個計時器事件每50ms發生,且可延緩至每100ms的最大頻率,則BMU 18可在平臺26相對未作動時每100ms觸發此計時器事件。然而,若平臺26變得更具作動性,則由於由其他來源所產生的中斷事件的關係,BMU 18可將對此計時器事件的發出朝向50ms改換(adapt)以求較佳的效能,而不在功率損耗上帶來負面衝擊。 For example, if an application requests that a timer event occur every 50 ms and can be deferred to a maximum frequency of every 100 ms, the BMU 18 can trigger this timer event every 100 ms when the platform 26 is relatively inactive. However, if the platform 26 becomes more motivating, the BMU 18 may adapt the issuance of this timer event towards 50 ms for better performance due to the interrupt event generated by other sources. Does not have a negative impact on power loss.
此外,平臺26也可係以低功率狀態中斷均等時間、可規劃效能需求等等形式來提供運行時間資訊24。低功率狀態中斷均等時間可指出平臺26應該待在一個特定低功率狀態中的時間量,以推移/緩衝與進入和離開此低功率狀態相關聯的任何功率成本負擔。如將更詳細說明的,BMU 18可使用低功率狀態中斷均等時間來判定針對各個經延緩中斷事件的保持時間。在這方面,當保持時間變得比中斷事件時間長很多的時候,省電效益可能會快速地下降,且效能會顯著降低。因此,BMU 18可基於中斷事件時間和所想要的效能而判定一個合理的保持時間。 In addition, platform 26 may also provide runtime information 24 in the form of low power state interrupt equalization time, programmable performance requirements, and the like. The low power state interrupt equalization time may indicate the amount of time the platform 26 should be in a particular low power state to shift/buffer any power cost burden associated with entering and leaving this low power state. As will be explained in more detail, the BMU 18 can use the low power state interrupt equalization time to determine the hold time for each of the deferred interrupt events. In this regard, when the hold time becomes much longer than the interrupt event time, the power saving benefit may drop rapidly and the performance may be significantly reduced. Therefore, the BMU 18 can determine a reasonable hold time based on the interrupt event time and the desired performance.
可規劃效能需求可係由平臺的使用者界定。因此,若使用者想要較高的效能,則保持時間可被向下調至較短的值,以提供較快速的回應及增進的效能(可能同時會失去一些省電機會)。另一方面,若使用者要求較長的電 池壽命,則可將保持時間設為相對較長的值,以提供平臺更多機會來維持在較低功率狀態中。 The programmable performance requirements can be defined by the users of the platform. Therefore, if the user wants higher performance, the hold time can be adjusted down to a shorter value to provide a faster response and improved performance (may also lose some of the motor savings). On the other hand, if the user requires a longer battery life, the hold time can be set to a relatively long value to provide more opportunities for the platform to remain in the lower power state.
現在請看向第3圖,其示出用於協調中斷事件之發出的一種示範方法。此方法30可係利用電路技術,像是ASIC、補償金氧半導體(complementary metal oxide semiconductor,CMOS)或電晶體電晶體邏輯(transistor-transistor logic,TTL)技術等,而實施在固定功能硬體中,或是實施在可執行軟體中,像是儲存在一個記憶體之機器可讀或電腦可讀儲存媒體,例如隨機存取記憶體(random access memory,RAM)、唯讀記憶體(read only memory,ROM)、可規劃ROM(programmable ROM,PROM)、快閃記憶體等等,中的一組韌體和/或邏輯指令,或是其任何組合。處理方塊32供用於收集來自於裝置、應用程式和平臺的運行時間資訊,並基於運行時間資訊而判定一個保持時間。如先前已經提過的,對保持時間之判定可將低功率中斷事件時間和可規劃效能需求、以及針對IO事件的最大延遲時間和計時器事件之可延緩性特性納入考量。 Turning now to Figure 3, an exemplary method for coordinating the issuance of an interrupt event is shown. The method 30 can be implemented in a fixed function hardware using a circuit technology such as an ASIC, a complementary metal oxide semiconductor (CMOS), or a transistor-transistor logic (TTL) technology. Or implemented in executable software, such as a machine-readable or computer-readable storage medium stored in a memory, such as random access memory (RAM), read-only memory (read only memory) , ROM), programmable ROM (PROM), flash memory, etc., a set of firmware and / or logic instructions, or any combination thereof. Processing block 32 is provided for collecting runtime information from devices, applications, and platforms, and determining a hold time based on runtime information. As previously mentioned, the determination of hold time can take into account the low power interrupt event time and programmable performance requirements, as well as the maximum delay time for IO events and the delay characteristics of timer events.
若在方塊34檢測到一個中斷事件,則可在方塊36做出對於保持時間是否已到期的判定。若否,則可在方塊38延緩此中斷事件。視環境而定,係可以多種不同方式來完成中斷事件之延緩。例如,可將中斷事件置於一個佇列中,其中這個佇列可係與BMU 18(第2圖)並列、與發出此中斷事件之裝置並列、在與此裝置相關聯的一個聯合單 元中、或以此類推。確實,若中斷事件係與一個匯流排主控異動相關連(例如,直接記憶體存取(direct memory access,DMA)),則可藉由解宣告一個快速週邊組件互連(Peripheral Components Interconnect Express,PCIe)機會緩衝器清除/填充(opportunistic buffer flush/fill,OBFF)信號來通知來源裝置此PCIe匯流排不可用,而延緩此中斷事件。 If an interrupt event is detected at block 34, a determination can be made at block 36 as to whether the hold time has expired. If not, the interrupt event can be deferred at block 38. Depending on the environment, the delay in the interruption event can be accomplished in a number of different ways. For example, an interrupt event can be placed in a queue, which can be juxtaposed with BMU 18 (Fig. 2), juxtaposed with the device that issued the interrupt event, in a joint unit associated with the device, Or so on. Indeed, if the interrupt event is associated with a bus master transaction (for example, direct memory access (DMA)), a fast peripheral component interconnect (Peripheral Components Interconnect Express) can be declared by the solution. PCIe) opportunistic buffer flush/fill (OBFF) signal to inform the source device that this PCIe bus is not available, and delays this interrupt event.
若在方塊40檢測到一個不可延緩中斷事件,或者是在方塊36判定出保持時間已經到期,則所有經延緩的中斷事件皆可在方塊42被釋放/發出至平臺。所例示之方塊44供用於基於所收集到的運行時間資訊而安排下一個保持時間。如先前已經提過的,保持時間係可被動態地調整。可在方塊46將下一個保持時間告知平臺功率管理單元。 If a non-delayable interrupt event is detected at block 40, or if it is determined at block 36 that the hold time has expired, then all of the deferred interrupt events may be released/issued to the platform at block 42. The illustrated block 44 is for scheduling the next hold time based on the collected runtime information. As already mentioned before, the hold time can be dynamically adjusted. The platform power management unit can be informed of the next hold time at block 46.
第4圖示出一個系統48,其中,一個BMU 50耦接至從應用程式計時器54和裝置56(56a~56c)接收多種中斷事件的一個處理器/平臺52,其中這些中斷事件可致使處理器/平臺52離開(或避免進入)一或多個低功率狀態。於所例示的這個範例中,可係使用聯合單元58來減少中斷事件之數目,例如藉由將否則可能會導致複數個中斷事件的複數個封包組合成單一個中斷事件。因而,對於通訊裝置,例如網路控制器,來說,聯合單元58可以是特別有用處的,雖然其他裝置和應用程式亦可從此聯合處理程序中獲益。 Figure 4 illustrates a system 48 in which a BMU 50 is coupled to a processor/platform 52 that receives various interrupt events from application timer 54 and devices 56 (56a-56c), wherein these interrupt events can cause processing The device/platform 52 leaves (or avoids entering) one or more low power states. In the illustrated example, association unit 58 may be used to reduce the number of interrupt events, such as by combining a plurality of packets that may otherwise result in a plurality of interrupt events into a single interrupt event. Thus, for a communication device, such as a network controller, the federated unit 58 can be particularly useful, although other devices and applications can also benefit from this joint processing program.
從啟動時間的初始化階段開始,聯合單元58可獲得,或可能已經知道,數個系統參數,例如置換政策、裝 置緩衝器大小、裝置潛伏容忍需求等等。這些參數可由聯合單元58使用,以判定以初始裝置/應用程式為基礎的一個保持時間,此保持時間可在之後有需要時基於運行時間行為而被調整。在運行時間當中,聯合單元58可追蹤各個有中斷能力的裝置來判定此裝置是否已經安靜了一段預定時間(例如,在前α ms中沒有產生任何岔斷)。依據這樣的無活動性,所述聯合單元可進入一個保持區間(例如,長達βms),於此保持區間中,沒有任何來自於此特定來源的岔斷會被中繼至BMU 50和/或處理器/平臺52。此途徑可係於一種逐裝置/應用程式基礎上實施,且具有針對各個裝置/應用程式的不同參數。此外,係可使用某些策略來繞過聯合單元58,像是高效能/評量基準模式等等。 From the initialization phase of the start-up time, federated unit 58 may obtain, or may already be aware of, several system parameters, such as replacement policy, device buffer size, device latency tolerance requirements, and the like. These parameters can be used by the federation unit 58 to determine a hold time based on the initial device/application, which can be adjusted based on runtime behavior when needed later. During runtime, the federation unit 58 can track each interrupt capable device to determine if the device has been quiet for a predetermined period of time (e.g., without causing any breaks in the previous alpha ms). Based on such inactivity, the joint unit can enter a hold interval (eg, up to βms) in which no breaks from this particular source are relayed to the BMU 50 and/or Processor/platform 52. This approach can be implemented on a device-by-device/application basis with different parameters for each device/application. In addition, certain strategies can be used to bypass the federation unit 58, such as the high performance/rating benchmark mode and the like.
雖然聯合單元58係可被實施在裝置56和應用程式計時器中,但將其定位在BMU 50中可能會由於消除任何需要裝置製造商來支援中斷事件對齊的需求而比較易於擴充。將聯合單元58實施在BMU 50中可能會涉及對保持計時器β之上限可與此裝置之內部緩衝器大小相容的保證,以避免緩衝器超限運轉。此外,無活動性計時器α可被設定成一個夠大的值,以使得能夠避免早熟到期和在最大系統效能上的任何負面衝擊。 While the federated unit 58 can be implemented in the device 56 and the application timer, positioning it in the BMU 50 may be relatively easy to augment by eliminating any need for the device manufacturer to support interrupt event alignment. Implementing the syndication unit 58 in the BMU 50 may involve guaranteeing that the upper limit of the hold timer β is compatible with the internal buffer size of the device to avoid buffer overruns. Furthermore, the inactivity timer a can be set to a value large enough to avoid premature expiration and any negative impact on maximum system performance.
在聯合計時器改換上係有多種不同的策略可以使用。例如,一種「靜態策略」可能會涉及將聯合行為連結至一個使用者設定的(或以OS設定檔為基礎的)系統偏好。因此,若使用者偏好高效能設定檔,則可藉由β=0來繞 過聯合動作。針對平衡效能/功率設定檔而言,係可選擇β=5ms的一個典型值。針對具有最大省電效果的低功率模式而言,可選擇β=10ms的一個典型值。或者是,可使用一種「動態策略」,於此動態策略中,係基於在某段計數時期中所觀察到的平均中斷事件數,而以一種閉迴路基礎來控制β。此途徑可因而使聯合動作儘可能地為無打擾狀態,以使中斷事件行為(平均來講)沒有明顯改變。從一個典型上很小的β值開始,可在一段相對較長的時段(例如,為以秒計的量級)中觀察來自於數個個別裝置的中斷事件之數量,並且可累進地增加β,直到事件的平均數量有顯著改變為止。取決於改變而定,β可被重設成從起點開始改換或者是以倍數減少。 There are a number of different strategies that can be used in the joint timer change. For example, a "static strategy" might involve linking a federation behavior to a user-set (or OS-based) system preference. Therefore, if the user prefers the high performance profile, the joint action can be bypassed by β=0. For a balanced performance/power profile, a typical value of β = 5ms can be selected. For a low power mode with maximum power savings, a typical value of β = 10 ms can be selected. Alternatively, a "dynamic strategy" can be used in which the beta is controlled on a closed loop basis based on the average number of interruption events observed during a certain counting period. This approach can thus make the joint action as unobtrusive as possible so that the interrupt event behavior (on average) does not change significantly. Starting from a typically small beta value, the number of interruption events from several individual devices can be observed over a relatively long period of time (eg, in the order of seconds), and β can be progressively increased. Until the average number of events has changed significantly. Depending on the change, β can be reset to change from the starting point or to decrease in multiples.
現在請看向第5圖,其示出一個系統60。系統60可為具有運算功能(例如,個人數位助理(personal digital assistant,PDA)、膝上型電腦)、通訊功能(例如,無線智慧型手機)、影像功能、媒體播放功能、或其任何組合(例如,行動網際網路裝置(mobile Internet device,MID))的一個行動平臺的一部分。於所例示之範例中,系統60包括有一個處理器62、一個積體記憶體控制器(integrated memory controller,IMC)74、一個IO模組64、系統記憶體66、一個網路控制器(例如,網路介面卡)68、一個音訊IO裝置72、一個固態磁碟(solid state disk,SSD)70、以及一或多個其他控制器80。可包括有具有一或數個處理器核心76的一個核心區域的處理器62可利用一個功率管理單 元(power management unit,PMU)78來基於如先前所述的效能和/或功率管理考慮條件,而將其核心76和其他系統部件置於一或多個作動或閒置狀態中。 Turning now to Figure 5, a system 60 is shown. System 60 can be a computing function (eg, a personal digital assistant (PDA), laptop), a communication function (eg, a wireless smart phone), an imaging function, a media playback function, or any combination thereof ( For example, a part of a mobile platform of a mobile internet device (MID). In the illustrated example, system 60 includes a processor 62, an integrated memory controller (IMC) 74, an IO module 64, system memory 66, and a network controller (eg, , a network interface card 68, an audio IO device 72, a solid state disk (SSD) 70, and one or more other controllers 80. Processor 62, which may include a core region having one or more processor cores 76, may utilize a power management unit (PMU) 78 based on performance and/or power management considerations as previously described. The core 76 and other system components are placed in one or more active or idle states.
所例示之IO模組64,有時候亦稱為晶片之南橋(Southbridge)或南複合體(South Complex),係作用為一個主機裝置,並與網路控制器68通訊,網路控制器68可針對多種用途,像是行動電話(例如,W-CDMA(UMTS)、CDMA2000(IS-856/IS-2000)等等)、WiFi(例如,1999年版的IEEE 802.11,LAN/MAN無線LANS(LAN/MAN Wireless LANS))、藍牙(Bluetooth)(例如,IEEE 802.15.1-2005,無線個人區域網路(Wireless Personal Area Networks))、WiMax(例如,IEEE 802.16-2004,LAN/MAN寬頻無線LANS(LAN/MAN Broadband Wireless LANS))、全球定位系統(Global Positioning System,GPS)、展開頻譜(例如,900MHz)、及其他無線電頻率(radio frequency,RF)通話用途等,而提供平臺外通訊功能。IO模組64可亦包括有一或多個無線硬體電路區塊,以支援這樣的功能性。 The illustrated IO module 64, sometimes referred to as the Southbridge or South Complex of the chip, functions as a host device and communicates with the network controller 68, which can be For a variety of purposes, such as mobile phones (eg, W-CDMA (UMTS), CDMA2000 (IS-856/IS-2000), etc.), WiFi (for example, the 1999 version of IEEE 802.11, LAN/MAN wireless LANS (LAN/ MAN Wireless LANS)), Bluetooth (for example, IEEE 802.15.1-2005, Wireless Personal Area Networks), WiMax (for example, IEEE 802.16-2004, LAN/MAN Broadband Wireless LANS (LAN) /MAN Broadband Wireless LANS)), Global Positioning System (GPS), unfolded spectrum (eg, 900MHz), and other radio frequency (RF) call uses provide off-platform communication. The IO module 64 can also include one or more wireless hardware circuit blocks to support such functionality.
SSD 70可包括有一或多個NAND晶片,並且可用於提供高容量資料儲存體和/或很大量的平行性。可亦有包括有被作為分開的數個特定應用積體電路(application specific integrated circuit,ASIC)控制器實施的NAND控制器之解決方案,此等ASIC控制器在標準匯流排,像是串列ATA(Serial ATA,SATA,例如,SATA國際組織(SATA International Organization,SATA-IO)於2009年五月27日之 SATA揭示版3.0規格)匯流排、或快速週邊組件互連圖形(PCI Express Graphics,PEG,例如,PCI特別興趣群的快速週邊組件互連/PCI x16圖形150W-ATX規格1.0)匯流排,上連接至IO模組64。可亦將SSD 70用作通用串列匯流排(Universal Serial Bus,USB,例如,USB實施者論壇(USB Implementers Forum)的USB規格2.0)快閃儲存體裝置。 The SSD 70 can include one or more NAND wafers and can be used to provide high volume data storage and/or a large amount of parallelism. There may also be solutions including NAND controllers implemented as separate application specific integrated circuit (ASIC) controllers in standard busses, such as serial ATA (Serial ATA, SATA, for example, SATA International Organization (SATA-IO) on May 27, 2009 SATA Rev. 3.0 specification) Busbar, or Fast Peripheral Component Interconnect Graphics (PCI Express Graphics, PEG For example, the PCI Express Special Group's Fast Peripheral Component Interconnect/PCI x16 Graphics 150W-ATX Specification 1.0) busbar is connected to the IO module 64. The SSD 70 can also be used as a flash memory device for a Universal Serial Bus (USB, for example, USB Specification 2.0 of the USB Implementers Forum).
所例示之IO模組64包括有一個BMU 82,其係組配來檢測來自於多個不同來源,像是網路控制器68、音訊IO裝置72、SSD 70、在處理器62上執行的作動應用程式等等,的中斷事件,並基於與系統60相關聯的運行時間資訊而協調中斷事件至處理器62之發出。在一個範例中,對於中斷事件之發出的協調動作包括基於運行時間資訊而判定一個保持時間、以及基於保持時間而延緩這些中斷事件中的至少一個。例如,系統60可執行一個網際網路協定上的語音(voice over Internet Protocol,VoIP)應用程式,於此應用程式中,網路控制器68和音訊IO裝置72各在只有稍微或完全沒有考慮由其他裝置所產生的IO事件的情況下主動產生IO事件。藉由利用BMU 82來協調來自於網路控制器68和音訊IO裝置72的中斷事件,所例示之IO模組64可使系統60的部件能夠進入較深層的低功率狀態較長的時間,並且因而可顯著地增進由系統60所達到的省電效果。 The illustrated IO module 64 includes a BMU 82 that is configured to detect actions from a plurality of different sources, such as the network controller 68, the audio IO device 72, the SSD 70, and the processor 62. The interrupt event of the application, etc., coordinates the interrupt event to the processor 62 based on the runtime information associated with the system 60. In one example, the coordinated action for the issuance of the interrupt event includes determining a hold time based on the runtime information, and deferring at least one of the interrupt events based on the hold time. For example, system 60 can execute a voice over internet protocol (VoIP) application in which network controller 68 and audio IO device 72 are each only slightly or completely unconsidered by IO events are actively generated in the case of IO events generated by other devices. By utilizing the BMU 82 to coordinate interrupt events from the network controller 68 and the audio IO device 72, the illustrated IO module 64 can enable components of the system 60 to enter a deeper low power state for a longer period of time, and Thus, the power saving effect achieved by the system 60 can be significantly enhanced.
因此,上文中所述的技術可提供一個全面的途徑來界定運算系統架構和介面,以使其協調並對齊多個IO裝置和應用程式之活動。如此一來,可最大化平臺閒置以求 最佳平臺省電效果。此外,這樣的協調和對齊動作可使平臺能夠更近一步接近理想的「呈工作負載比例」功率消耗,並具有穩健的效能。 Thus, the techniques described above provide a comprehensive way to define the computing system architecture and interface to coordinate and align the activities of multiple IO devices and applications. In this way, the platform can be maximized to achieve the best platform power saving effect. In addition, such coordination and alignment actions allow the platform to get closer to the ideal "payload ratio" power consumption and have robust performance.
本發明之實施例可應用於對於所有類型的半導體積體電路(integrated circuit,「IC」)晶片之使用。這些IC晶片的範例包括但不受限於處理器、控制器、晶片組部件、可規劃邏輯陣列(programmable logic arrays,PLA)、記憶體晶片、網路晶片、單晶片系統(systems on chip,SoC)、SSD/NAND控制器ASIC、及其他諸如此類者。此外,在一些圖式中,信號導體線路係以線條表示。有一些可能會粗一點以指出較多成份信號路徑、具有數字標號以指出成份信號路徑之數量,並/或在一或更多端具有箭頭以指出主要資訊流向。然而,這不應被解讀為一種限制行為。相反地,這樣的增入細節可配合一或多個示範實施例使用,以有助於更容易地瞭解一個電路。所表示出來的任何信號線路,無論是否具有額外資訊,皆可實際上包含可以多方向行進的一或多個信號,並可就任何合適的信號架構類型實施,例如,以差動對實施的數位或類比線路、光纖線路及/或單端線路。 Embodiments of the present invention are applicable to the use of all types of semiconductor integrated circuit ("IC") chips. Examples of such IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoC) ), SSD/NAND controller ASICs, and others. Moreover, in some of the figures, the signal conductor lines are represented by lines. Some may be thicker to indicate more component signal paths, have numerical labels to indicate the number of component signal paths, and/or have arrows at one or more ends to indicate the primary information flow direction. However, this should not be interpreted as a restrictive act. Rather, such additional details may be used in conjunction with one or more exemplary embodiments to facilitate an easier understanding of a circuit. Any signal line represented, whether or not with additional information, may actually contain one or more signals that may travel in multiple directions and may be implemented in any suitable signal architecture type, for example, digitally implemented with a differential pair Or analog lines, fiber optic lines, and/or single-ended lines.
於本文中可能已給出示範尺寸/模型/數值/範圍,雖然本發明之數個實施例並不受限於此等尺寸/模型/數值/範圍。由於製造技術(例如,光微影術)隨著時間愈趨成熟,可預期較小尺寸的裝置可被製造。此外,對IC晶片及其他部件的習知電源/接地連接可以或可以不被示於 圖式中,以利例示與論述之簡明性,並以使本發明之數個實施例的某些面相不被混淆。更進一步地,可係於方塊圖之形式中示出數個配置,以避免混淆本發明之數個實施例,並且,如此係有鑑於這樣的事實,即,針對此等方塊圖配置之實作的細節係高度倚賴於要在當中實施此實施例的平台,亦即,此等細節應完全係落於熟於此技者的眼界內。當闡明特定細節(例如,電路)以說明本發明之數個示範實施例時,對於熟於此技者而言,應可明顯看出,本發明之數個實施例可係在無此等特定細節,或變更此等特定細節的情況下實踐。此說明因此應被看作是例示性的,而非限制性的。 Exemplary dimensions/models/values/ranges may have been given herein, although several embodiments of the invention are not limited by such dimensions/models/values/ranges. As manufacturing techniques (eg, photolithography) mature over time, smaller sized devices can be expected to be fabricated. In addition, conventional power/ground connections to IC chips and other components may or may not be shown in the drawings for the sake of simplicity and clarity of the description, and so that certain aspects of the various embodiments of the present invention are not Be confused. Further, several configurations may be shown in the form of block diagrams in order to avoid obscuring the various embodiments of the present invention, and in the light of the fact that the implementation of such block diagrams is implemented. The details are highly dependent on the platform in which the embodiment is to be implemented, that is, such details should be completely within the purview of those skilled in the art. When specific details (e.g., circuits) are set forth to illustrate several exemplary embodiments of the present invention, it will be apparent to those skilled in the art that the various embodiments of the invention may be Practice with details or changes to these specific details. This description is therefore to be regarded as illustrative and not restrictive.
「耦接」此詞於本文中可係用於指涉在所論部件之間的任何類型的關係,直接或間接,並可適用於電氣的、機械的、流體的、光學的、電磁的、電機的或其他連接。此外,除非已指出其他情況,否則「第一」、「第二」等等詞語於本文中僅係用來有助於論述,而不帶任何特定時間性或時間順序性意義。 The term "coupled" is used herein to refer to any type of relationship between the components in question, either directly or indirectly, and is applicable to electrical, mechanical, fluid, optical, electromagnetic, electrical Or other connections. In addition, the terms "first," "second," and the like are used herein to facilitate the discussion, without any particular temporal or chronological meaning, unless otherwise indicated.
從前文之說明中,熟於此技者會可識出,本發明之數個實施例的寬廣技術可係以多種形式來實施。因此,雖然已以相關於前文中之特定範例的方式來說明本發明之此等實施例,本發明之此等實施例的真實範圍亦不應被這樣限制,因為對於熟鍊的專業人員而言,經參讀圖式、說明書與後附申請專利範圍後,其他修改體會是很明顯可見的。 From the foregoing description, it will be appreciated by those skilled in the art that the various embodiments of the invention can be practiced in various forms. Accordingly, while such embodiments of the present invention have been described in terms of the specific examples hereinabove, the true scope of the embodiments of the present invention should not be limited as such After reading the schema, the manual and the attached patent application scope, other modifications will be obvious.
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US8612998B2 (en) | 2013-12-17 |
US8959531B2 (en) | 2015-02-17 |
US20120079482A1 (en) | 2012-03-29 |
WO2012040068A1 (en) | 2012-03-29 |
JP5628431B2 (en) | 2014-11-19 |
TW201812601A (en) | 2018-04-01 |
GB2497025B (en) | 2018-06-06 |
KR20130048786A (en) | 2013-05-10 |
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