TWI636952B - Use of dielectric film to reduce resistivity of transparent conductive oxide in nanowire leds - Google Patents

Use of dielectric film to reduce resistivity of transparent conductive oxide in nanowire leds Download PDF

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TWI636952B
TWI636952B TW103143125A TW103143125A TWI636952B TW I636952 B TWI636952 B TW I636952B TW 103143125 A TW103143125 A TW 103143125A TW 103143125 A TW103143125 A TW 103143125A TW I636952 B TWI636952 B TW I636952B
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layer
depositing
dielectric material
transparent conductive
nanowire
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TW201531439A (en
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史考特 布萊德 海納
丹尼爾 布萊斯 湯普森
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瑞典商Ｇｌｏ公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/84—Manufacture, treatment, or detection of nanostructure
    • Y10S977/89—Deposition of materials, e.g. coating, cvd, or ald
    • Y10S977/891—Vapor phase deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/949—Radiation emitter using nanostructure
    • Y10S977/95—Electromagnetic energy

Abstract

各種實施例包括製造發光二極體(LED)裝置(諸如奈米線LED裝置)之方法，該等方法包括在LED裝置之非平面表面之至少一部分上形成透明導電材料層，及在該透明導電材料層之至少一部分上沉積介電材料層，其中沉積該介電材料層包括以下至少一者：(a)利用化學氣相沉積(CVD)法沉積該層，(b)在200℃或更高之溫度下沉積該層，及(c)利用該介電材料之一或多種化學活性前驅體沉積該層。 Various embodiments include a method of fabricating a light emitting diode (LED) device, such as a nanowire LED device, the method comprising forming a layer of transparent conductive material on at least a portion of a non-planar surface of the LED device, and at the transparent conductive Depositing a layer of dielectric material on at least a portion of the layer of material, wherein depositing the layer of dielectric material comprises at least one of: (a) depositing the layer by chemical vapor deposition (CVD), (b) at 200 ° C or higher The layer is deposited at a temperature, and (c) the layer is deposited using one or more chemically active precursors of the dielectric material.

Description

使用介電膜以減少奈米線發光二極體中之透明導電氧化物之電阻率 Using a dielectric film to reduce the resistivity of the transparent conductive oxide in the nanowire light-emitting diode

奈米線發光二極體(LED)作為平面LED之替代物越來越受到關注。與以習知整平技術生產之LED相比，奈米線LED因為奈米線之三維本質而提供獨特的性質，因為晶格匹配限制較少而在材料組合中具有改良可撓性及提供在較大基板上加工之機會。 Nanowire light-emitting diodes (LEDs) are receiving increasing attention as a replacement for planar LEDs. Compared to LEDs produced by conventional leveling techniques, nanowire LEDs offer unique properties due to the three-dimensional nature of the nanowires, because of the limited lattice matching limitations and improved flexibility in the material combination and The opportunity to process on larger substrates.

儘管奈米線LED具有優勢，但希望進一步提高奈米線LED之光提取效率。 Although the nanowire LED has advantages, it is desirable to further improve the light extraction efficiency of the nanowire LED.

實施例包括製造發光二極體(LED)裝置(諸如奈米線LED裝置)之方法，該等方法包括在LED裝置之非平面表面之至少一部分上形成透明導電材料層，及在該透明導電材料層之至少一部分上沉積介電材料層，其中沉積該介電材料層包括以下至少一者：(a)利用化學氣相沉積(CvD)法沉積該層，(b)在200℃或更高(例如200℃至600℃)之溫度下沉積該層，及(c)利用該介電材料之一或多種化學活性前驅體沉積該層。 Embodiments include a method of fabricating a light emitting diode (LED) device, such as a nanowire LED device, the method comprising forming a layer of transparent conductive material on at least a portion of a non-planar surface of the LED device, and at the transparent conductive material Depositing a layer of dielectric material on at least a portion of the layer, wherein depositing the layer of dielectric material comprises at least one of: (a) depositing the layer by chemical vapor deposition (CvD), (b) at 200 ° C or higher ( The layer is deposited, for example, at a temperature of from 200 ° C to 600 ° C, and (c) the layer is deposited using one or more chemically active precursors of the dielectric material.

在各種實施例中，在透明導電材料(例如，電極)層上沉積介電材料層可減少該透明導電材料層之電阻率，從而使電流擁擠最小化或消除，並提高非平面LED裝置(諸如奈米線LED裝置)之光提取效率。在 實施例中，在透明導電材料層上添加介電材料層可使裝置中之透明導電材料層之電阻率減少至無介電材料層之裝置中之透明導電材料之電阻率之50%或更小之值。 In various embodiments, depositing a layer of dielectric material on a layer of transparent conductive material (eg, an electrode) can reduce the resistivity of the layer of transparent conductive material, thereby minimizing or eliminating current crowding, and improving non-planar LED devices (such as Light extraction efficiency of the nanowire LED device). in In an embodiment, adding a layer of dielectric material to the layer of transparent conductive material reduces the resistivity of the layer of transparent conductive material in the device to 50% or less of the resistivity of the transparent conductive material in the device without the layer of dielectric material. The value.

其他實施例包括根據該等實施例方法製造之發光二極體(LED)裝置(諸如奈米線LED裝置)。 Other embodiments include light emitting diode (LED) devices (such as nanowire LED devices) fabricated in accordance with the methods of the embodiments.

1‧‧‧奈米線 1‧‧‧Nami Line

2‧‧‧n型奈米線核 2‧‧‧n type nanowire core

3‧‧‧p型殼 3‧‧‧p-shell

4‧‧‧中間主動層 4‧‧‧Intermediate active layer

5‧‧‧生長基板 5‧‧‧ Growth substrate

6‧‧‧生長遮罩或介電遮罩層 6‧‧‧Growth mask or dielectric mask

7‧‧‧緩衝層 7‧‧‧ Buffer layer

100‧‧‧奈米線LED 100‧‧‧Nano line LED

101‧‧‧n-GaN核 101‧‧‧n-GaN core

103‧‧‧n-GaN緩衝層 103‧‧‧n-GaN buffer layer

105‧‧‧InGaN量子井主動區域 105‧‧‧InGaN quantum well active region

106‧‧‧介電或遮罩層 106‧‧‧ Dielectric or mask layer

107‧‧‧GaN量子井主動區域 107‧‧‧GaN quantum well active area

109‧‧‧p-AlGaN外部殼 109‧‧‧p-AlGaN outer shell

111‧‧‧p-GaN外部殼/p-GaN外層/p-GaN層 111‧‧‧p-GaN outer shell/p-GaN outer layer/p-GaN layer

113‧‧‧垂直側壁 113‧‧‧Vertical sidewall

115‧‧‧圓錐形尖端 115‧‧‧Conical tip

117‧‧‧電接觸材料層/電接觸材料/ITO層 117‧‧‧Electrical contact material layer/electrical contact material/ITO layer

119‧‧‧介電材料層 119‧‧‧ dielectric material layer

400‧‧‧奈米線LED裝置/LED裝置/裝置 400‧‧‧Nano line LED device / LED device / device

401‧‧‧奈米線 401‧‧‧Nami Line

402‧‧‧半導體核/奈米線核 402‧‧‧Semiconductor core/nanocore

403‧‧‧奈米殼/外部殼 403‧‧‧Nano Shell/Outer Shell

406‧‧‧遮罩層 406‧‧‧mask layer

407‧‧‧緩衝層/n-型緩衝層 407‧‧‧buffer layer/n-type buffer layer

408‧‧‧支撐件/底部基板層 408‧‧‧Support/Bottom substrate layer

411‧‧‧透明導電氧化物層/ITO電極層/TCO層 411‧‧‧Transparent Conductive Oxide Layer/ITO Electrode Layer/TCO Layer

413‧‧‧p-側金屬接觸件/金屬接觸件 413‧‧‧p-side metal contacts/metal contacts

415‧‧‧n-側接觸區域 415‧‧‧n-side contact area

417‧‧‧n-側金屬接觸件 417‧‧‧n-side metal contacts

500‧‧‧奈米線LED裝置/LED裝置/裝置 500‧‧‧Nano line LED device / LED device / device

501‧‧‧奈米線 501‧‧‧Nami Line

502‧‧‧第一導電型半導體核/奈米線核 502‧‧‧First Conductive Semiconductor Core/Nanocore Core

503‧‧‧第二導電型奈米殼/外部殼 503‧‧‧Second Conductive Nano Shell/Outer Shell

506‧‧‧介電遮罩層 506‧‧‧ dielectric mask

507‧‧‧n型緩衝層/緩衝層/n-GaN緩衝層 507‧‧‧n type buffer layer/buffer layer/n-GaN buffer layer

508‧‧‧支撐件/底部基板層 508‧‧‧Support/Bottom substrate layer

510‧‧‧介電層/介電材料層/SiO2層/介電材料 510‧‧‧Dielectric/dielectric material layer/SiO 2 layer/dielectric material

511‧‧‧透明導電氧化物(TCO)材料層/TCO層/電極層/ITO層 511‧‧‧Transparent Conductive Oxide (TCO) Material Layer/TCO Layer/Electrode Layer/ITO Layer

513‧‧‧p-側金屬接觸件/金屬接觸件 513‧‧‧p-side metal contacts/metal contacts

515‧‧‧n-側接觸區域/n接觸區域 515‧‧‧n-side contact area/n contact area

516‧‧‧p-側接觸區域/p接觸區域 516‧‧‧p-side contact area/p contact area

517‧‧‧n-側金屬接觸件/金屬接觸件 517‧‧‧n-side metal contacts/metal contacts

併入本文中並構成本說明書之一部分之附圖圖解說明本發明之實例實施例，並與上文給出之一般說明及下文給出之詳細說明一起用於解釋本發明之特徵。 BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in FIG.

圖1示意性地圖解說明根據一實施例之在透明導電氧化物(TCO)層上具有介電材料層之奈米線LED之側橫截面視圖。 1 schematically illustrates a side cross-sectional view of a nanowire LED having a layer of dielectric material on a layer of transparent conductive oxide (TCO), in accordance with an embodiment.

圖2示意性地圖解說明根據本發明實施例之奈米線LED陣列之基元之側橫截面視圖。 2 schematically illustrates a side cross-sectional view of a cell of a nanowire LED array in accordance with an embodiment of the present invention.

圖3示意性地圖解說明根據本發明實施例之緩衝層上之奈米線LED陣列之基元之側橫截面視圖。 3 is a schematic cross-sectional side view of a cell of a nanowire LED array on a buffer layer in accordance with an embodiment of the present invention.

圖4A係先前技術之奈米線LED裝置之部分橫截面視圖。 4A is a partial cross-sectional view of a prior art nanowire LED device.

圖4B係圖4A之先前技術奈米線LED裝置之俯視圖。 4B is a top plan view of the prior art nanowire LED device of FIG. 4A.

圖4C係根據圖4A-B製造之奈米線LED裝置之橫截面SEM圖像。 4C is a cross-sectional SEM image of a nanowire LED device fabricated in accordance with FIGS. 4A-B.

圖4D係根據圖4A-B製造之奈米線LED裝置之照片。 Figure 4D is a photograph of a nanowire LED device made in accordance with Figures 4A-B.

圖5A示意性地圖解說明根據一實施例之在透明導電氧化物(TCO)層上具有介電材料層之奈米線LED裝置之部分側橫截面視圖。 5A schematically illustrates a partial side cross-sectional view of a nanowire LED device having a layer of dielectric material on a layer of transparent conductive oxide (TCO), in accordance with an embodiment.

圖5B係圖5A之奈米線LED裝置之部分橫截面視圖，其圖解說明n-金屬接觸件。 Figure 5B is a partial cross-sectional view of the nanowire LED device of Figure 5A illustrating the n-metal contact.

圖5C係圖5A之奈米線LED裝置之俯視圖。 Figure 5C is a top plan view of the nanowire LED device of Figure 5A.

圖5D係根據圖5A-C製造之奈米線LED裝置之橫截面SEM圖像。 Figure 5D is a cross-sectional SEM image of a nanowire LED device fabricated in accordance with Figures 5A-C.

圖5E係根據圖5A-C製造之奈米線LED裝置之照片。 Figure 5E is a photograph of a nanowire LED device made in accordance with Figures 5A-C.

將參考附圖詳盡地描述各種實施例。只要可能，該等圖式始終將使用相同的參考數字指代相同或相似部份。參考特定實例及實施案係用於說明性目的，且無意限制本發明或申請專利範圍之範疇。 Various embodiments will be described in detail with reference to the accompanying drawings. Whenever possible, the drawings will always refer to the same or similar parts. The specific examples and embodiments are for illustrative purposes and are not intended to limit the scope of the invention or the scope of the claims.

本發明實施例包括奈米線基半導體裝置(諸如奈米線LED)及製造具有低電流擁擠及高光提取效率之奈米線LED之方法。與習知平面LED相比，奈米線LED(諸如GaN奈米線LED)在提高效率及波長穩定性方面具有前景性。然而，此等裝置之光提取效率可能並非最佳，因為透明導電氧化物(TCO)材料電極之電阻率相對較高，其可導致電流擁擠及效率降低。 Embodiments of the invention include nanowire-based semiconductor devices, such as nanowire LEDs, and methods of fabricating nanowire LEDs having low current crowding and high light extraction efficiency. Nanowire LEDs, such as GaN nanowire LEDs, are promising in terms of improved efficiency and wavelength stability compared to conventional planar LEDs. However, the light extraction efficiency of such devices may not be optimal because the resistivity of the transparent conductive oxide (TCO) material electrodes is relatively high, which can result in current crowding and reduced efficiency.

各種實施例包括LED裝置，其非平面表面之至少一部分上具有透明導電材料層及在該透明導電材料層之至少一部分上具有介電材料層。該LED裝置可包括奈米線LED陣列，且該LED裝置之非平面表面可包括大體上垂直於支撐基板表面(例如，在直角±60°內)配置之奈米線陣列之上表面。該介電材料可具有比該透明導電材料之電阻率大102倍(例如，大1010倍，諸如大於1014倍，包括103至1015倍)之電阻率。該透明導電材料可係透明導電氧化物(TCO)，諸如氧化銦錫(ITO)。該介電材料可係(例如)SiO2、SiN及/或Al2O3。在實施例中，該介電材料層可藉由化學氣相沉積(CVD)沉積於該透明導電材料層上。在實施例中，該介電材料層可在高溫(例如200℃或更高，諸如200℃-600℃)下沉積於該透明導電材料層上。在實施例中，該介電材料層可利用該介電材料之一或多種化學活性前驅體沉積於該透明導電材料層上。 Various embodiments include LED devices having a layer of transparent conductive material on at least a portion of the non-planar surface and a layer of dielectric material on at least a portion of the layer of transparent conductive material. The LED device can include a nanowire LED array, and the non-planar surface of the LED device can include an upper surface of the nanowire array disposed substantially perpendicular to the surface of the support substrate (eg, within a right angle ± 60°). The dielectric material may have a resistivity that is 10 2 times greater than the resistivity of the transparent conductive material (eg, 10 10 times greater, such as greater than 10 14 times, including 10 3 to 10 15 times). The transparent conductive material may be a transparent conductive oxide (TCO) such as indium tin oxide (ITO). The dielectric material can be, for example, SiO 2 , SiN, and/or Al 2 O 3 . In an embodiment, the layer of dielectric material may be deposited on the layer of transparent conductive material by chemical vapor deposition (CVD). In an embodiment, the layer of dielectric material may be deposited on the layer of transparent conductive material at a high temperature (eg, 200 ° C or higher, such as 200 ° C to 600 ° C). In an embodiment, the layer of dielectric material may be deposited on the layer of transparent conductive material using one or more chemically active precursors of the dielectric material.

該介電材料層可具有針對該LED裝置之至少一種發射波長(其可係可見波長、紅外(IR)波長或紫外(UV)波長)之高透射率(例如，大於85%，諸如大於90%或95%)。在一實施例中，該LED裝置之至少一種 發射波長可係可見波長，諸如在390-700nm(例如，450-550nm)之間。在透明導電材料(例如，電極)層上添加介電材料層可減少該透明導電材料層之電阻率，從而使電流擁擠最小化或消除，並提高非平面LED裝置(諸如奈米線LED裝置，包括GaN奈米線LED裝置)之光提取效率。在實施例中，在透明導電材料層上添加介電材料層可使裝置中之透明導電材料層之電阻率減少至無介電材料層之裝置中之透明導電材料之電阻率之50%或更小(例如，10-50%)之值。 The layer of dielectric material can have a high transmittance (eg, greater than 85%, such as greater than 90%) for at least one emission wavelength of the LED device (which can be a visible wavelength, an infrared (IR) wavelength, or an ultraviolet (UV) wavelength) Or 95%). In an embodiment, at least one of the LED devices The emission wavelength can be a visible wavelength, such as between 390-700 nm (eg, 450-550 nm). Adding a layer of dielectric material to the layer of transparent conductive material (eg, an electrode) can reduce the resistivity of the layer of transparent conductive material, thereby minimizing or eliminating current crowding, and improving non-planar LED devices (such as nanowire LED devices, Light extraction efficiency including GaN nanowire LED devices). In an embodiment, adding a layer of dielectric material to the layer of transparent conductive material reduces the resistivity of the layer of transparent conductive material in the device to 50% or more of the resistivity of the transparent conductive material in the device without the layer of dielectric material. Small (for example, 10-50%) value.

在奈米技術領域中，奈米線通常被理解為具有奈米級或奈米尺寸之橫向尺寸(例如，圓柱體奈米線之直徑或者錐體或六邊形奈米線之寬度)，而其軸向尺寸無限制之奈米結構。此等奈米結構通常亦稱為奈米鬚、一維奈米元件、奈米棒、奈米管等。該等奈米線可具有上至約2微米之直徑或寬度。該等奈米線之小尺寸提供獨特物理、光學及電子性質。此等性質可(例如)用於形成利用量子力學效應(例如，利用量子線)之裝置或形成組成上具有通常因大晶格失配而無法組合之不同材料之異質結構。如術語奈米線所暗示，一維本質可與細長形狀相關聯。因為奈米線可具有各種橫截面形狀，所以直徑意指有效直徑。所謂有效直徑，其意指該結構之橫截面之長軸及短軸之平均值。雖然在圖式中奈米元件顯示呈柱狀且基於奈米線核，但應注意，該等核亦可具有其他幾何結構，諸如具有各種多邊形底面(諸如正方形、六邊形、八邊形等)之錐體。因此，如本文所使用，該核可包括寬度或直徑小於2微米且長度大於1微米之任何適宜元件，且可包括單一結構或多部件結構。例如，該核可包括具有一種導電型之半導體奈米線，或其可包括被一或多個具有相同導電型之半導體殼包圍之具有一種導電型之半導體奈米線，且該核具有柱狀或錐體形狀。為簡便起見，單部件奈米線柱狀核將在下文中描述並示於圖式中。 In the field of nanotechnology, the nanowire is generally understood to have a lateral dimension of the nanometer or nanometer size (for example, the diameter of a cylindrical nanowire or the width of a cone or hexagonal nanowire), and A nanostructure with unlimited axial dimensions. These nanostructures are also commonly referred to as nanobes, one-dimensional nanocomponents, nanorods, nanotubes, and the like. The nanowires can have a diameter or width up to about 2 microns. The small size of these nanowires provides unique physical, optical and electronic properties. Such properties can be used, for example, to form devices that utilize quantum mechanical effects (e.g., using quantum wires) or to form heterostructures that are composed of different materials that are typically incapable of being combined due to large lattice mismatch. As implied by the term nanowire, a one-dimensional nature can be associated with an elongated shape. Since the nanowires can have various cross-sectional shapes, the diameter means the effective diameter. By effective diameter, it is meant the average of the major and minor axes of the cross section of the structure. Although the nano-elements are shown in the figure as columnar and based on the nanowire core, it should be noted that the cores may also have other geometric structures, such as having various polygonal bottom surfaces (such as squares, hexagons, octagons, etc.) ) The cone. Thus, as used herein, the core can include any suitable element having a width or diameter of less than 2 microns and a length greater than 1 micron, and can include a single structure or a multi-part construction. For example, the core may comprise a semiconductor nanowire having a conductivity type, or it may comprise a semiconductor nanowire having a conductivity type surrounded by one or more semiconductor shells having the same conductivity type, and the core has a columnar shape Or cone shape. For simplicity, the single-component nanowire columnar core will be described below and shown in the drawings.

所有提及上部、頂部、下部、向下等之情形均將基板視為在底 部，且奈米線自該基板向上延伸。垂直係指垂直於該基板所形成之平面之方向，且水平係指平行於該基板所形成之平面之方向。該命名法僅係出於便於理解而引入，且不應視作對具體總成取向等之限制。 All references to the top, top, bottom, down, etc. regard the substrate as the bottom And the nanowire extends upward from the substrate. Vertical means the direction perpendicular to the plane formed by the substrate, and horizontal means the direction parallel to the plane formed by the substrate. This nomenclature is introduced merely for ease of understanding and should not be construed as limiting the specific assembly orientation or the like.

在實施例方法中，光學透射性介電材料(例如，SiO2、SiN、Al2O3等)層可形成於LED裝置(奈米線LED)之非平面表面上之透明導電材料層之至少一部分上。該介電材料層可如下形成：藉由化學氣相沉積(CVD)或另一在高溫(例如，200℃至600℃，諸如200℃至約510℃)下之方法及/或涉及該介電材料之化學活性前驅體。添加介電材料層可減少該透明導電材料之電阻率，從而減少電流擁擠及提高LED裝置之效率。 In an embodiment method, a layer of optically transmissive dielectric material (eg, SiO 2 , SiN, Al 2 O 3 , etc.) may be formed on at least a layer of transparent conductive material on a non-planar surface of an LED device (nano-line LED) Part of it. The dielectric material layer can be formed by chemical vapor deposition (CVD) or another method at elevated temperatures (eg, 200 ° C to 600 ° C, such as 200 ° C to about 510 ° C) and/or involving the dielectric Chemically active precursor of the material. The addition of a layer of dielectric material reduces the resistivity of the transparent conductive material, thereby reducing current crowding and increasing the efficiency of the LED device.

任何適宜的LED裝置(諸如如此項技術中所已知之奈米線LED結構)均可用於本發明方法中。 Any suitable LED device, such as the nanowire LED structure known in the art, can be used in the method of the present invention.

圖1中圖解說明根據一實施例之實例奈米線LED 100。在該實例中，奈米線LED 100包括與n-GaN緩衝層103電接觸之n-GaN核101、InGaN/GaN量子井主動區域105、107之中間層或殼以及p-AlGaN及p-GaN外部殼109、111，及垂直側壁113及圓錐形尖端115。在各種實施例中，可部分或完全除去圓錐形尖端，以得到在尖端上具有實質上平面表面之奈米結構。在p-GaN外層111上提供電接觸材料層117(ITO)，並在ITO層117上提供介電材料層119(SiO2)。介電或遮罩層106(SiN)可位於p-GaN層111及電接觸材料117(ITO)與n-GaN緩衝層103之間。 An example nanowire LED 100 is illustrated in FIG. 1 in accordance with an embodiment. In this example, the nanowire LED 100 includes an n-GaN core 101 in electrical contact with the n-GaN buffer layer 103, an intermediate layer or shell of InGaN/GaN quantum well active regions 105, 107, and p-AlGaN and p-GaN. The outer casing 109, 111, and the vertical side wall 113 and the conical tip 115. In various embodiments, the conical tip can be partially or completely removed to provide a nanostructure having a substantially planar surface on the tip. An electrical contact material layer 117 (ITO) is provided on the p-GaN outer layer 111, and a dielectric material layer 119 (SiO 2 ) is provided on the ITO layer 117. A dielectric or mask layer 106 (SiN) may be located between the p-GaN layer 111 and the electrical contact material 117 (ITO) and the n-GaN buffer layer 103.

奈米線LED通常係基於一或多個pn-或p-i-n-接面。pn接面與p-i-n-接面間之區別在於後者具有更寬主動區域。更寬的主動區域使得更有可能在i-區域中再結合。各奈米線包括第一導電型(例如，n-型)奈米線核及封閉第二導電型(例如，p-型)殼，以形成在操作中提供產生光之主動區域之pn或pin接面。雖然本文將該第一導電型核描述為n-型 半導體核，且本文將該第二導電型殼描述為p型半導體殼，但應理解，其導電型可顛倒。 Nanowire LEDs are typically based on one or more pn- or p-i-n- junctions. The difference between the pn junction and the p-i-n- junction is that the latter has a wider active area. A wider active area makes it more likely to recombine in the i-region. Each nanowire includes a first conductivity type (eg, n-type) nanowire core and a closed second conductivity type (eg, p-type) shell to form a pn or pin that provides an active region for generating light during operation. Junction. Although the first conductivity type core is described herein as n-type A semiconductor core, and the second conductivity type case is described herein as a p-type semiconductor case, but it should be understood that its conductivity type may be reversed.

圖2示意性圖解說明根據本發明之一些實施例之可使用之奈米線LED結構。原則上，單一奈米線足以形成奈米線LED，但由於尺寸小，奈米線較佳配置成包含數百、數千、數萬或更多根並列的奈米線之陣列，以形成LED結構。出於說明目的，本文將個別奈米線LED裝置描述為由奈米線1組成，奈米線1具有n-型奈米線核2及至少部分封閉該奈米線核2及中間主動層4之p-型殼3。然而，出於本發明實施例之目的，奈米線LED並不限於此。例如，奈米線核2、主動層4及p-型殼3可係由許多層或片段構成。藉由控制生長條件，LED之最終幾何結構可自細長狹窄的「柱狀結構」橫跨至相對寬的錐體結構。 Figure 2 schematically illustrates a nanowire LED structure that can be used in accordance with some embodiments of the present invention. In principle, a single nanowire is sufficient to form a nanowire LED, but due to its small size, the nanowire is preferably configured to include an array of hundreds, thousands, tens of thousands or more of parallel nanowires to form an LED. structure. For illustrative purposes, individual nanowire LED devices are described as being composed of a nanowire 1 having an n-type nanowire core 2 and at least partially enclosing the nanowire core 2 and the intermediate active layer 4 P-type shell 3. However, for the purpose of embodiments of the present invention, the nanowire LED is not limited thereto. For example, the nanowire core 2, the active layer 4, and the p-type shell 3 may be composed of a plurality of layers or segments. By controlling the growth conditions, the final geometry of the LED can span from an elongated narrow "columnar structure" to a relatively wide pyramid structure.

在替代性實施例中，僅核2可包括寬度或直徑小於1微米之奈米結構或奈米線，而殼3可具有大於1微米之寬度或直徑。 In an alternative embodiment, only the core 2 may comprise a nanostructure or a nanowire having a width or diameter of less than 1 micron, while the shell 3 may have a width or diameter greater than 1 micrometer.

III-V半導體尤其受到關注，因為其性質有利於高速低功率電子及光電裝置，諸如LED及雷射器。該等奈米線可包括任何半導體材料，且適用於該等奈米線之材料包括(但不限於)：GaAs(p)、InAs、Ge、ZnO、InN、GaInN、GaN、AlGaInN、BN、InP、InAsP、GaInP、InGaP：Si、InGaP：Zn、GaInAs、AlInP、GaAlInP、GaAlInAsP、GaInSb、InSb、Si。可用於(例如)GaP之供體摻雜劑為Si、Sn、Te、Se、S等，且其受體摻雜劑為Zn、Fe、Mg、Be、Cd等。應注意，奈米線技術使其可使用氮化物，諸如GaN、InN及AlN，此有助於製造在習知技術不容易達到之波長區域中發光之LED。尤其受到商業關注之其他組合包括(但不限於)GaAs、GaInP、GaAIInP、Gap系統。典型的摻雜濃度介於1018至1020之範圍內。熟習此項技術者熟悉此等及其他材料，且認識到其他材料及材料組合亦可。 III-V semiconductors are of particular interest because of their properties for high speed low power electronic and optoelectronic devices such as LEDs and lasers. The nanowires may comprise any semiconductor material, and materials suitable for the nanowires include, but are not limited to: GaAs(p), InAs, Ge, ZnO, InN, GaInN, GaN, AlGaInN, BN, InP InAsP, GaInP, InGaP: Si, InGaP: Zn, GaInAs, AlInP, GaAlInP, GaAlInAsP, GaInSb, InSb, Si. The donor dopants usable for, for example, GaP are Si, Sn, Te, Se, S, etc., and the acceptor dopants thereof are Zn, Fe, Mg, Be, Cd, and the like. It should be noted that the nanowire technology makes it possible to use nitrides such as GaN, InN and AlN, which contributes to the fabrication of LEDs that emit light in wavelength regions that are not readily achievable by conventional techniques. Other combinations that are of particular commercial interest include, but are not limited to, GaAs, GaInP, GaAIInP, Gap systems. Typical doping concentrations range from 10 18 to 10 20 . Those skilled in the art are familiar with these and other materials and recognize that other materials and combinations of materials are also possible.

用於奈米線LED之較佳材料為III-V半導體(諸如III-氮化物半導體 (例如，GaN、AlInGaN、AlGaN及InGaN等))或其他半導體(例如，InP、GaAs)。為充當LED，各奈米線1之n-側及p-側必須接觸，且本發明提供與使LED結構中之奈米線之n-側及p-側接觸之方法及組合物。 A preferred material for the nanowire LED is a III-V semiconductor (such as a III-nitride semiconductor) (for example, GaN, AlInGaN, AlGaN, InGaN, etc.) or other semiconductors (for example, InP, GaAs). In order to act as an LED, the n-side and p-side of each nanowire 1 must be in contact, and the present invention provides methods and compositions for contacting the n-side and p-side of the nanowires in the LED structure.

雖然本文所述之示例性製造方法較佳使用奈米線核來在該等核上生長半導體殼層，以形成核-殼奈米線(如(例如)Seifert等人之美國專利案第7,829,443號中所述，該案以引用的方式併入本文中，以教示奈米線製造方法)，但應注意本發明並不因此受限。例如，在替代性實施例中，僅核可構成奈米結構(例如，奈米線)，而殼可視情況具有大於典型奈米線殼之尺寸。此外，該裝置可經塑型以包括許多面，且可控制不同類型的面間之面積比。此在圖式中係藉由「錐體」面及垂直側壁面例示。可製造使得發射層形成於具有主要錐體面或側壁面之模板上之LED。對於接觸層同樣如此，與發射層之形狀無關。 Although the exemplary fabrication methods described herein preferably use a nanowire core to grow a semiconductor shell on the core to form a core-shell nanowire (eg, for example, US Pat. No. 7,829,443 to Seifert et al. The present invention is incorporated herein by reference to teach the nanowire manufacturing method, but it should be noted that the invention is not limited thereby. For example, in an alternative embodiment, only the nanostructures (e.g., nanowires) may be constructed, and the shell may optionally be larger than the size of a typical nanowire shell. In addition, the device can be shaped to include a number of faces and control the area ratio between different types of faces. This is illustrated in the drawings by the "cone" surface and the vertical side wall surface. LEDs can be fabricated such that the emissive layer is formed on a template having a major conical or sidewall surface. The same is true for the contact layer, regardless of the shape of the emissive layer.

使用連續(例如，殼)層可得到形狀在錐體形(亦即，頂部或尖端較窄且底面較寬)及柱形(例如，尖端與底面大約同寬)之間之最終個別裝置(例如，pn或pin裝置)，其中圓形或六邊形或其他多邊形橫截面垂直於該裝置之長軸。因此，具有完整殼之個別裝置可具有各種尺寸。例如，尺寸可變化，其中底面寬度介於100nm至幾(例如，5)μm，諸如100nm至小於1微米之範圍內，且高度介於幾百nm至幾(例如，10)μm之範圍內。 The use of a continuous (eg, shell) layer results in a final individual device having a shape between the cone shape (ie, the top or tip is narrower and the bottom surface is wider) and the column shape (eg, the tip end is approximately the same width as the bottom surface) (eg, Pn or pin device) wherein the circular or hexagonal or other polygonal cross section is perpendicular to the long axis of the device. Thus, individual devices having a complete housing can have a variety of sizes. For example, the size may vary, wherein the width of the bottom surface is in the range of 100 nm to several (eg, 5) μm, such as from 100 nm to less than 1 μm, and the height is in the range of several hundred nm to several (eg, 10) μm.

圖3圖解說明提供用於奈米線之支撐件之示例性結構。藉由在生長基板5上生長奈米線1，視情況使用生長遮罩或介電遮罩層6(例如，氮化物層，諸如氮化矽介電遮罩層)來界定奈米線1之位置及確定其底部界面區域，基板5至少在加工期間充當自基板5突出之奈米線1之載體。該等奈米線之底部界面區域包括核2之位於介電遮罩層6之各開口內之區域。基板5可包括不同材料，諸如III-V或II-VI半導體、Si、Ge、Al2O3、SiC、石英、玻璃等，如瑞典專利申請案SE 1050700-2 (受讓於GLO AB)中所述，該案之全文以引用的方式併入本文中。其他適用於基板之材料包括(但不限於)：GaAs、GaP、GaP：Zn、GaAs、InAs、InP、GaN、GaSb、ZnO、InSb、SOI(絕緣物上矽)、CdS、ZnSe、CdTe。在一實施例中，奈米線1直接生長於生長基板5上。 Figure 3 illustrates an exemplary structure for providing a support for a nanowire. By growing the nanowire 1 on the growth substrate 5, a growth mask or a dielectric mask layer 6 (for example, a nitride layer such as a tantalum nitride dielectric mask layer) is optionally used to define the nanowire 1 The substrate and the bottom interface region thereof are determined, and the substrate 5 serves as a carrier for the nanowire 1 protruding from the substrate 5 at least during processing. The bottom interface region of the nanowires includes the regions of the core 2 that are located within the openings of the dielectric mask layer 6. Substrate 5 may comprise different materials such as III-V or II-VI semiconductors, Si, Ge, Al 2 O 3 , SiC, quartz, glass, etc., as in Swedish patent application SE 1050700-2 (assigned to GLO AB) The entire text of the disclosure is hereby incorporated by reference. Other materials suitable for the substrate include, but are not limited to, GaAs, GaP, GaP: Zn, GaAs, InAs, InP, GaN, GaSb, ZnO, InSb, SOI (insulator on insulator), CdS, ZnSe, CdTe. In one embodiment, the nanowire 1 is grown directly on the growth substrate 5.

在使用介電遮罩(生長遮罩)層之實施例中，生長遮罩6可藉由光微影術圖案化，以界定用於奈米線生長之開口，如(例如)美國專利案第7,829,443號中所述，該案之全文以引用的方式併入本文中。在該實施案中，奈米線聚集於n-襯墊區域、非主動區域、LED區域(亦即，發光區)及p-襯墊區域。然而，本發明實施例並不限於此。例如，p-襯墊區域可配置於形成奈米線LED結構之發光部件之奈米線頂部，藉此該p-襯墊區域與LED區域重合，如2010年2月4日公開之Konsek等人之PCT國際申請公開案第WO 2010/014032 A1號中所述，且該案之全文以引用的方式併入本文中。 In embodiments using a dielectric mask (growth mask) layer, the growth mask 6 can be patterned by photolithography to define openings for nanowire growth, such as, for example, US Patent No. The entire text of the case is incorporated herein by reference. In this embodiment, the nanowires are concentrated in the n-pad region, the inactive region, the LED region (i.e., the light-emitting region), and the p-pad region. However, embodiments of the invention are not limited thereto. For example, the p-pad region can be disposed on top of the nanowire forming the light-emitting component of the nanowire LED structure, whereby the p-pad region coincides with the LED region, such as Konsek et al., published on February 4, 2010. PCT International Application Publication No. WO 2010/014032 A1, the entire disclosure of which is incorporated herein by reference.

較佳地，基板5亦適於充當連接至各奈米線1之n-側之電流傳輸層。此可藉由使基板5包括配置於基板5之面向奈米線1之表面上之緩衝層7(如圖3中所示，舉例言之，在Si基板5上之III-氮化物層(諸如GaN及/或AlGaN)緩衝層7)來完成。緩衝層7提供用於接觸奈米線1之n-側之結構。緩衝層7通常與所需奈米線材料相匹配，且因此在製造過程中充當生長模板。就n-型核2而言，緩衝層7較佳亦係摻雜n-型。緩衝層7可包括單一層(例如，GaN)、若干子層(例如，GaN及AlGaN)或自高Al含量AlGaN遞變至較低Al含量AlGaN或GaN之遞變層。該等奈米線可包括任何半導體材料，但就奈米線LED而言，通常以III-V半導體(諸如III-氮化物半導體(例如，GaN、AlInGaN、AlGaN及InGaN等))或其他半導體(例如，InP、GaAs)較佳。奈米線之生長可藉由採用美國專利案第7,396,696號、第7,335,908號及第7,829,443號以及WO201014032、WO2008048704及WO 2007102781中所述方法實現， 所有該等案之全文以引用的方式併入本文中。應注意，奈米線1可包括若干種不同材料(例如，GaN核、GaN/InGaN主動層及In對Ga比率不同於該主動層之InGaN殼)。一般而言，本文將基板5及/或緩衝層7稱為奈米線之支撐件或支撐層。在某些實施例中，替代基板5及/或緩衝層7或除此之外，可使用導電層(例如，鏡樣物或透明接觸件)作為支撐件。因此，術語「支撐層」或「支撐件」可包括此等元件中之任一者或多者。 Preferably, the substrate 5 is also adapted to serve as a current transport layer connected to the n-side of each nanowire 1. This can be achieved by including the substrate 5 on the buffer layer 7 disposed on the surface of the substrate 5 facing the nanowire 1 (as shown in FIG. 3, for example, an III-nitride layer on the Si substrate 5 (such as The GaN and/or AlGaN buffer layer 7) is completed. The buffer layer 7 provides a structure for contacting the n-side of the nanowire 1. The buffer layer 7 is typically matched to the desired nanowire material and thus acts as a growth template during the manufacturing process. For the n-type core 2, the buffer layer 7 is preferably doped n-type. The buffer layer 7 may include a single layer (eg, GaN), several sub-layers (eg, GaN and AlGaN), or a graded layer that is tapered from a high Al content AlGaN to a lower Al content AlGaN or GaN. The nanowires may comprise any semiconductor material, but in the case of nanowire LEDs, typically a III-V semiconductor (such as a III-nitride semiconductor (eg, GaN, AlInGaN, AlGaN, InGaN, etc.)) or other semiconductor ( For example, InP, GaAs) is preferred. The growth of the nanowires can be achieved by the methods described in U.S. Patent Nos. 7,396,696, 7,335,908 and 7,829,443, and WO201014032, WO2008048704 and WO 2007102781, The entire contents of all of these are incorporated herein by reference. It should be noted that the nanowire 1 may include several different materials (eg, a GaN core, a GaN/InGaN active layer, and an InGaN shell having an In-to-Ga ratio different from the active layer). In general, substrate 5 and/or buffer layer 7 is referred to herein as a support or support layer for the nanowire. In some embodiments, instead of or in addition to the substrate 5 and/or the buffer layer 7, a conductive layer (eg, a mirror or transparent contact) can be used as the support. Thus, the term "support layer" or "support" can include any or more of these elements.

以上關於LED結構之示例性實施例之描述將充當描述本發明方法及裝置之基礎；然而，應暸解，在作出如熟習此項技術者所知曉之任何必要修改下，亦可不脫離本發明地將任何適宜的奈米線LED結構或其他適宜奈米線結構或LED結構用於該等方法及裝置中。 The above description of the exemplary embodiments of the LED structure will serve as a basis for describing the method and apparatus of the present invention; however, it will be appreciated that any modifications necessary to those skilled in the art can be made without departing from the invention. Any suitable nanowire LED structure or other suitable nanowire structure or LED structure is used in such methods and devices.

圖4A-D示意性圖解說明先前技術之奈米線LED裝置400。圖4A係LED裝置400沿著圖4B之俯視圖中之線A-A觀察時之部分橫截面視圖。裝置400包括奈米線陣列(諸如上文圖3中所示)，其包括複數個奈米線401，諸如配置於支撐件408上之錐形奈米線，其中奈米線401包括第一導電型(例如，n-型)半導體核402及第二導電型(例如，p-型)殼403，其等經組態以形成pn或pin接面，該接面在操作中提供產生光之主動區域(例如，亦可添加中間主動層，如圖3中所示)。該固體支撐件可包括與奈米線核402電接觸之緩衝層407及使奈米殼403與緩衝層407絕緣之介電(例如，SiN)遮罩層406，兩者均可提供於底部基板層408上。可選的中間層(未顯示)亦可提供於該支撐件上，且可包括未摻雜GaN層，以減小奈米線中晶體缺陷之密度。 4A-D schematically illustrate a prior art nanowire LED device 400. 4A is a partial cross-sectional view of the LED device 400 as viewed along line A-A of the top view of FIG. 4B. Device 400 includes a nanowire array (such as shown in Figure 3 above) that includes a plurality of nanowires 401, such as tapered nanowires disposed on support 408, wherein nanowire 401 includes a first conductive Type (eg, n-type) semiconductor core 402 and second conductivity type (eg, p-type) case 403, etc., configured to form a pn or pin junction that provides active light generation during operation Region (for example, an intermediate active layer can also be added, as shown in Figure 3). The solid support can include a buffer layer 407 in electrical contact with the nanowire core 402 and a dielectric (eg, SiN) mask layer 406 that insulates the nanoshell 403 from the buffer layer 407, both of which can be provided on the base substrate. On layer 408. An optional intermediate layer (not shown) may also be provided on the support and may include an undoped GaN layer to reduce the density of crystal defects in the nanowire.

將透明導電氧化物(TCO)層411(諸如ITO層)沉積於奈米線結構上，以與奈米線401之外部殼403電接觸，及提供p-電極。如圖4A中所顯示，可在TCO層411上形成p-側金屬接觸件413。n-型緩衝層407可曝露於n-側接觸區域415中，且n-側金屬接觸件417可形成於n-側接觸區 域415中之n-型緩衝層407上。 A transparent conductive oxide (TCO) layer 411, such as an ITO layer, is deposited over the nanowire structure to make electrical contact with the outer shell 403 of the nanowire 401 and to provide a p-electrode. As shown in FIG. 4A, a p-side metal contact 413 can be formed on the TCO layer 411. The n-type buffer layer 407 may be exposed in the n-side contact region 415, and the n-side metal contact 417 may be formed in the n-side contact region On the n-type buffer layer 407 in the field 415.

氧化銦錫(ITO)通常用作透明導電氧化物層411，以與奈米線401之第二導電型(p-型)殼403接觸。圖4C係ITO層411在GaN奈米線401上之SEM圖像。與鋁薄膜之約3μΩ．cm之電阻率相比，呈薄膜形式之ITO具有約100-300μΩ．cm之相對高電阻率。然而，儘管具有此相對高電阻率，但ITO因其具有導電且對可見光而言係透明的能力而受到重視。 Indium tin oxide (ITO) is generally used as the transparent conductive oxide layer 411 to be in contact with the second conductivity type (p-type) case 403 of the nanowire 401. 4C is an SEM image of ITO layer 411 on GaN nanowire 401. About 3μΩ with aluminum film. Compared with the resistivity of cm, the ITO in the form of a film has about 100-300 μΩ. The relatively high resistivity of cm. However, despite this relatively high electrical resistivity, ITO has received attention due to its ability to be electrically conductive and transparent to visible light.

透明導電氧化物(ITO)層411通常係利用物理氣相沉積(PVD)(諸如濺鍍或蒸鍍)形成。膜如ITO之物理氣相沉積將不會使非平面表面(諸如由支撐基板上之垂直配向奈米線陣列所形成之表面)上所沉積之膜具有均勻厚度或密度。例如，就自平面表面(半導體晶圓表面或其他支撐件表面)延伸之奈米線而言，該等奈米線之側壁通常將具有比該等奈米線間之平面表面薄得多的物理沉積ITO塗層。在一些情形下，此相對於晶圓表面以大角度覆蓋表面之能力之缺乏導致LED晶粒表面上之膜平均具有高效薄片電阻。此高薄片電阻可導致稱為「電流擁擠」之現象，在該現象中，位置較靠近ITO電極層411上之金屬接觸件413之LED接面(奈米線核402與各別外層殼403間之主動區域)比遠離金屬接觸件413之LED接面發射更多光。此示於圖4D中，該圖係諸如圖4A-B中所示LED裝置400之照片。在圖4D中可見，LED裝置400在靠近p-側金屬接觸件413處比靠近n-側金屬接觸件417處發射更多光。此係由於接觸奈米線之p-型GaN殼之ITO膜之高串聯電阻所引起。電流擁擠係非所需，因為其降低LED效率(亦即，對於提供給該裝置之給定電流而言，光輸出減少了)，且導致發射出在空間上圖案不均勻之光。 The transparent conductive oxide (ITO) layer 411 is typically formed using physical vapor deposition (PVD) such as sputtering or evaporation. Physical vapor deposition of a film such as ITO will not impart a uniform thickness or density to the film deposited on a non-planar surface such as the surface formed by the array of vertically aligned nanowires on the support substrate. For example, in the case of nanowires extending from a planar surface (semiconductor wafer surface or other support surface), the sidewalls of the nanowires will typically have a much thinner physical surface than the planar surface between the nanowires. An ITO coating was deposited. In some cases, this lack of ability to cover the surface at a large angle relative to the wafer surface results in a film on the surface of the LED die having an average high sheet resistance. This high sheet resistance can cause a phenomenon called "current crowding" in which the LED junction of the metal contact 413 on the ITO electrode layer 411 is located (between the nanowire core 402 and the respective outer shell 403). The active area emits more light than the LED junction away from the metal contact 413. This is illustrated in Figure 4D, which is a photograph of an LED device 400 such as that shown in Figures 4A-B. As seen in FIG. 4D, the LED device 400 emits more light near the p-side metal contact 413 than near the n-side metal contact 417. This is caused by the high series resistance of the ITO film contacting the p-type GaN shell of the nanowire. Current crowding is undesirable because it reduces LED efficiency (i.e., the light output is reduced for a given current supplied to the device) and results in the emission of spatially non-uniform light.

各種實施例包括非平面LED裝置(諸如奈米線LED裝置)，其具有形成於透明導電氧化物(TCO)材料層(諸如ITO層)之至少一部分上之光 學透射性介電材料層(例如SiO2、SiN、Al2O3等)。申請者已發現，在高溫(例如，200℃或更高，諸如200℃至600℃，200℃至約500℃)下及/或使用介電材料之化學活性前驅體(諸如利用化學氣相沉積(CVD)法)在物理沉積之TCO材料層上沉積介電材料層可顯著減少TCO層之電阻率，從而使電流擁擠最小化或消除及提高LED裝置之效率。該介電材料層可係透明，以使LED裝置正常工作。同樣，該介電材料層可充當該裝置之鈍化層，意指其可對原本會損害該裝置之移動離子提供保護性障壁。 Various embodiments include non-planar LED devices (such as nanowire LED devices) having an optically transmissive dielectric material layer (eg, SiO) formed on at least a portion of a layer of transparent conductive oxide (TCO) material, such as an ITO layer. 2 , SiN, Al 2 O 3, etc.). Applicants have discovered that at high temperatures (eg, 200 ° C or higher, such as 200 ° C to 600 ° C, 200 ° C to about 500 ° C) and/or chemically active precursors using dielectric materials (such as by chemical vapor deposition) (CVD) Method The deposition of a layer of dielectric material on a physically deposited TCO material layer can significantly reduce the resistivity of the TCO layer, thereby minimizing or eliminating current crowding and improving the efficiency of the LED device. The layer of dielectric material can be transparent to allow the LED device to function properly. Likewise, the layer of dielectric material can act as a passivation layer for the device, meaning that it can provide a protective barrier to mobile ions that would otherwise damage the device.

圖5A-E圖解說明根據一實施例之奈米線LED裝置500。圖5A係LED裝置500沿著圖5C之俯視示意圖中之線B-B觀察時之部分橫截面視圖。圖5B係LED裝置500沿著圖5C中之線C-C觀察時之部分橫截面視圖。裝置500可與圖4A-B之裝置類似，且可包括奈米線陣列，其包括複數個奈米線501，諸如配置於支撐件508上之錐形奈米線，其中奈米線501包括第一導電型(例如，n-型)半導體核502及第二導電型(例如，p-型)殼503，其等經組態以形成pn或pin接面，該接面在操作中提供產生光之主動區域(例如，亦可添加中間主動層，如圖3中所示)。該固體支撐件可包括與奈米線核502電接觸之緩衝層507及使奈米殼503與緩衝層507絕緣之介電(例如，SiN)遮罩層506，兩者均可提供於底部基板層508上。可選的中間層(未顯示)亦可提供於該支撐件上，且可包括未摻雜GaN層，以減小奈米線中晶體缺陷之密度。 5A-E illustrate a nanowire LED device 500 in accordance with an embodiment. 5A is a partial cross-sectional view of the LED device 500 as viewed along line B-B in the top plan view of FIG. 5C. Fig. 5B is a partial cross-sectional view of the LED device 500 as viewed along line C-C in Fig. 5C. Device 500 can be similar to the device of Figures 4A-B, and can include a nanowire array that includes a plurality of nanowires 501, such as a tapered nanowire disposed on support 508, wherein nanowire 501 includes A conductive (e.g., n-type) semiconductor core 502 and a second conductivity type (e.g., p-type) housing 503, etc., are configured to form a pn or pin junction that provides light during operation The active area (for example, an intermediate active layer may also be added, as shown in FIG. 3). The solid support can include a buffer layer 507 in electrical contact with the nanowire core 502 and a dielectric (eg, SiN) mask layer 506 that insulates the nanoshell 503 from the buffer layer 507, both of which can be provided on the base substrate. On layer 508. An optional intermediate layer (not shown) may also be provided on the support and may include an undoped GaN layer to reduce the density of crystal defects in the nanowire.

可藉由任何適宜方法(例如，濺射沉積、蒸鍍等)將透明導電氧化物(TCO)材料層511(諸如ITO層)沉積於奈米線結構上，以與奈米線501之外部殼503電接觸，及提供p-電極。層511可使用其他適宜的TCO材料，諸如經鋁摻雜之氧化鋅(AZO)。然後可將介電材料層510沉積於TCO材料層511上。在一實施例中，介電材料層510可包括藉由化學氣相沉積(CVD)沉積之SiO2。在一實例中，介電材料(例如，SiO2)層510 之CVD沉積可在高溫(例如200℃至600℃，較佳低於510℃，包括在約350℃下)下，利用SiO2之化學活性前驅體氣流(諸如SiH4及O2)，在次大氣壓(例如，25托或更小，諸如280毫托)下進行。圖5D係顯示在一實施例中經由CVD沉積在ITO層511及GaN奈米線501上之SiO2層510之SEM圖像。 A layer of transparent conductive oxide (TCO) material 511 (such as an ITO layer) may be deposited on the nanowire structure by any suitable method (eg, sputter deposition, evaporation, etc.) to form an outer shell with the nanowire 501. 503 electrical contact, and provide p-electrode. Layer 511 can use other suitable TCO materials, such as aluminum doped zinc oxide (AZO). Dielectric material layer 510 can then be deposited on TCO material layer 511. In an embodiment, the dielectric material layer 510 can include SiO 2 deposited by chemical vapor deposition (CVD). In one example, CVD deposition of dielectric material (eg, SiO 2 ) layer 510 can be performed at high temperatures (eg, 200 ° C to 600 ° C, preferably below 510 ° C, including at about 350 ° C), using SiO 2 carried out chemically active precursor gas stream (such as SiH 4 and O 2), at sub-atmospheric pressure (e.g., 25 Torr or less, such as 280 mTorr). Figure 5D shows an SEM image of a SiO 2 layer 510 deposited on ITO layer 511 and GaN nanowire 501 via CVD in one embodiment.

如圖5A中所顯示，可在p-側接觸區域516中形成與TCO層511接觸之p-側金屬接觸件513。如圖5B中所顯示，可在n-側接觸區域515中形成n-側金屬接觸件517，並與n-型緩衝層507接觸。 As shown in FIG. 5A, a p-side metal contact 513 in contact with the TCO layer 511 can be formed in the p-side contact region 516. As shown in FIG. 5B, an n-side metal contact 517 may be formed in the n-side contact region 515 and contacted with the n-type buffer layer 507.

n-側接觸區域515可如下形成：藉由移除一部份奈米線501(諸如藉由透過遮罩蝕刻或藉由雷射剝蝕)，以在遠處n-金屬接觸位點(例如，圖5C中之裝置之右下角)曝露n-型緩衝層507。p-側及n-側金屬接觸件513、517可利用標準光微影技術以沉積覆蓋除n及p接觸區域515、516以外之所有特徵之遮罩(例如抗蝕劑)來形成。曝露的n及p接觸區域515、516可經濕式或乾式蝕刻，以分別曝露n-GaN緩衝層507及TCO層511。然後可在n及p接觸區域515、516中之曝露的n-GaN緩衝層507及TCO層511上形成金屬接觸件。示例性金屬接觸件513、517可包括Al/Ti/Au堆疊件，其中Al與n-GaN(n-接觸)或TCO(p-接觸)接觸。然後可自基板剝離具有金屬之光阻遮罩，以提供圖5A-C之裝置500。 The n-side contact region 515 can be formed by removing a portion of the nanowire 501 (such as by etching through a mask or by laser ablation) to a distant n-metal contact site (eg, The lower right corner of the device in Fig. 5C exposes the n-type buffer layer 507. The p-side and n-side metal contacts 513, 517 can be formed using standard photolithography techniques to deposit a mask (e.g., a resist) that covers all features except the n and p contact regions 515, 516. The exposed n and p contact regions 515, 516 can be wet or dry etched to expose the n-GaN buffer layer 507 and the TCO layer 511, respectively. Metal contacts can then be formed on the exposed n-GaN buffer layer 507 and TCO layer 511 in the n and p contact regions 515, 516. Exemplary metal contacts 513, 517 can include an Al/Ti/Au stack in which Al is in contact with n-GaN (n-contact) or TCO (p-contact). A photoresist mask with a metal can then be stripped from the substrate to provide the device 500 of Figures 5A-C.

一或兩個金屬接觸件513、517之形成可在將介電材料510沉積於奈米線陣列上之前或之後進行。因此，在介電材料510係在形成金屬接觸件513、517之前沉積之實施例中，可藉由雷射剝蝕、蝕刻穿過圖案化遮罩等自n及/或p接觸區域515、516移除介電材料510，然後形成如上所述之金屬接觸件513、517。在介電材料510係在形成金屬接觸件513、517之後沉積之實施例中，可將介電材料510沉積於整個裝置上，然後可移除一部份介電材料510(例如，經由蝕刻)，以曝露金屬接觸件513、517。 The formation of one or both of the metal contacts 513, 517 can be performed before or after depositing the dielectric material 510 on the array of nanowires. Thus, in embodiments in which the dielectric material 510 is deposited prior to forming the metal contacts 513, 517, it may be removed from the n and/or p contact regions 515, 516 by laser ablation, etching through a patterned mask, and the like. In addition to the dielectric material 510, metal contacts 513, 517 as described above are then formed. In embodiments in which the dielectric material 510 is deposited after forming the metal contacts 513, 517, the dielectric material 510 can be deposited over the entire device, and then a portion of the dielectric material 510 can be removed (eg, via etching). To expose the metal contacts 513, 517.

在透明導電氧化物(TCO)層511上添加介電材料層510可顯著減少TCO層511之電阻率，從而使電流擁擠最小化或消除，並提高裝置500之光提取效率。此係圖解於圖5E中，圖5E係如圖5A-B中所示之LED裝置500之照片。圖5D之裝置500包括藉由CVD在ITO電極層上所形成之介電(SiO2)層510，要不然相當於圖4D之先前技術裝置400。與圖4D之裝置400中之~241Ω之實測ITO層薄片電阻相比，圖5D之裝置500中之ITO層之實測薄片電阻為~44Ω。因此，添加CVD SiO2層510導致ITO層之電阻率降至無介電層之數值之約18%(亦即，具有CVD SiO2層之裝置500中之~44Ω之實測電阻率係圖4D之無CVD SiO2層之同等裝置400中之~241Ω之實測電阻值之~18%)。在各種實施例中，在如上所述LED裝置中之透明導電材料電極層511上添加介電材料層510可使電極層511之電阻率減少至無介電材料層510之LED裝置中之電極層511之電阻率之50%或更小(例如，10至50%)之值。同樣地，據說，與無介電材料層510之LED裝置之電極層511之電阻率相比，添加介電材料層510可使電極層511之電阻率減少至少50%。較佳地，ITO層之薄片電阻小於100Ω，諸如30-100Ω。 The addition of the dielectric material layer 510 on the transparent conductive oxide (TCO) layer 511 can significantly reduce the resistivity of the TCO layer 511, thereby minimizing or eliminating current crowding and improving the light extraction efficiency of the device 500. This is illustrated in Figure 5E, which is a photograph of the LED device 500 as shown in Figures 5A-B. FIG. 5D apparatus 500 comprises the dielectric by CVD is formed on the ITO electrode layer (SiO 2) layer 510, or else corresponds to the prior art device of FIG. 4D 400. The measured sheet resistance of the ITO layer in device 500 of Figure 5D is ~44 ohms compared to the measured ITO layer sheet resistance of ~241 ohms in device 400 of Figure 4D. Therefore, the addition of the CVD SiO 2 layer 510 causes the resistivity of the ITO layer to decrease to about 18% of the value of the dielectric-free layer (ie, the measured resistivity of ~44 Ω in the device 500 having the CVD SiO 2 layer is shown in FIG. 4D). ~18% of the measured resistance of ~241 Ω in the equivalent device 400 without CVD SiO 2 layer. In various embodiments, the addition of the dielectric material layer 510 to the transparent conductive material electrode layer 511 in the LED device as described above can reduce the resistivity of the electrode layer 511 to the electrode layer in the LED device without the dielectric material layer 510. A value of 50% or less (for example, 10 to 50%) of the resistivity of 511. Similarly, it is said that the addition of the dielectric material layer 510 can reduce the resistivity of the electrode layer 511 by at least 50% compared to the resistivity of the electrode layer 511 of the LED device without the dielectric material layer 510. Preferably, the sheet resistance of the ITO layer is less than 100 Ω, such as 30-100 Ω.

另外，如圖5E中所示，裝置500在該裝置之整個發光表面上發射實質上相同量或更多光(例如，接近n-側金屬接觸件517所發射之光之量係在接近p-側金屬接觸件513所發射之光之量之約25%以內，諸如在約15%以內，例如在1-15%內)。因此，可如上所述藉由添加介電材料層510使圖4D之裝置400之電流擁擠效應最小化或消除。 Additionally, as shown in Figure 5E, device 500 emits substantially the same amount or more of light over the entire illuminated surface of the device (e.g., the amount of light emitted by near n-side metal contact 517 is near p- The amount of light emitted by the side metal contacts 513 is within about 25%, such as within about 15%, such as within 1-15%. Thus, the current crowding effect of device 400 of Figure 4D can be minimized or eliminated by the addition of dielectric material layer 510 as described above.

在其他實施例中，介電層510可係利用正矽酸四乙酯(Si(OC2H5)4或TEOS)，諸如利用TEOS及O2及/或TEOS及O3之氣流所沉積(例如，經由CVD)之SiO2。在其他實施例中，介電層510可包括SiN，且可利用適宜化學活性前驅體(諸如二氯矽烷(H2SiCl2)及氨(NH3)之氣流)沉積(例如，經由CVD)。在其他實施例中，介電層510可包括Al2O3，且可 利用適宜化學活性前驅體(諸如AlCl3、三甲基鋁(TMA)、烷醇鋁(例如，Al(O-i-Pr)3)、乙醯丙酮鋁、CO2/H2、O2、N2O及/或H2O)沉積(例如，經由CVD)。 In other embodiments, the dielectric layer 510 can be deposited using tetraethyl orthosilicate (Si(OC 2 H 5 ) 4 or TEOS), such as with a gas stream of TEOS and O 2 and/or TEOS and O 3 ( For example, SiO 2 via CVD). In other embodiments, the dielectric layer 510 can include SiN and can be deposited using a suitable chemically active precursor such as a stream of dichlorosilane (H 2 SiCl 2 ) and ammonia (NH 3 ) (eg, via CVD). In other embodiments, the dielectric layer 510 can include Al 2 O 3 and a suitable chemically active precursor such as AlCl 3 , trimethyl aluminum (TMA), aluminum alkoxide (eg, Al(Oi-Pr) can be utilized. 3 ), acetonitrile aluminum, CO 2 /H 2 , O 2 , N 2 O and/or H 2 O) are deposited (eg, via CVD).

不希望受任何特定理論之約束，據信，添加介電膜(例如，CVD SiO2)可藉由優化ITO膜中之氧空位之濃度來降低透明導電氧化物(例如，ITO)膜之電阻率。氧空位有助於ITO中之電荷載子之濃度。較高濃度的電荷載子可導致ITO之較低電阻率。其他機制亦可用於降低ITO膜之電阻率。 Without wishing to be bound by any particular theory, it is believed that the addition of a dielectric film (eg, CVD SiO 2 ) can reduce the resistivity of a transparent conductive oxide (eg, ITO) film by optimizing the concentration of oxygen vacancies in the ITO film. . Oxygen vacancies contribute to the concentration of charge carriers in the ITO. Higher concentrations of charge carriers can result in lower resistivity of ITO. Other mechanisms can also be used to reduce the resistivity of the ITO film.

另外，已發現，當利用物理沉積法(諸如蒸鍍)將介電材料沉積於TCO層511上時不會使TCO層511之電阻率出現類似下降。在一實例中，藉由在~100℃下蒸鍍沉積於GaN奈米線LED裝置中之ITO電極上之TiO2不會導致ITO之實測電阻率下降。不希望受任何特定理論之約束，據信，CVD沉積介電材料、沉積介電材料期間之高溫(例如，200℃至600℃)及/或在充足分壓下存在介電質之一或多種化學活性前驅體(例如，SiH4、O2、二氯矽烷、TEOS等)中之一或多者有助於觀察到TCO層之電阻率下降。 In addition, it has been found that when a dielectric material is deposited on the TCO layer 511 by a physical deposition method such as evaporation, a similar decrease in the resistivity of the TCO layer 511 is not caused. In one example, TiO 2 deposited on the ITO electrode in a GaN nanowire LED device at ~100 ° C does not cause a decrease in the measured resistivity of the ITO. Without wishing to be bound by any particular theory, it is believed that CVD deposits a dielectric material, a high temperature during deposition of the dielectric material (eg, 200 ° C to 600 ° C), and/or one or more dielectrics present under sufficient partial pressure. One or more of the chemically active precursors (eg, SiH 4 , O 2 , methylene chloride, TEOS, etc.) contribute to the observed decrease in resistivity of the TCO layer.

雖然本發明係依據奈米線LED進行描述，但應暸解，可在任何奈米線結構上實施其他奈米線基半導體裝置(場效電晶體、二極體及特定言之涉及光吸收或光產生之裝置，諸如光偵測器、太陽能電池、雷射器等)。另外，可將本發明之原理用於其他LED裝置(諸如在非平面表面上具有透明導電材料層之LED)中。 Although the present invention is described in terms of a nanowire LED, it should be understood that other nanowire-based semiconductor devices can be implemented on any nanowire structure (field effect transistors, diodes, and in particular light absorption or light). Devices produced, such as photodetectors, solar cells, lasers, etc.). Additionally, the principles of the present invention can be applied to other LED devices, such as LEDs having a layer of transparent conductive material on a non-planar surface.

例如，使用透明導電材料(諸如透明導電金屬氧化物(TCO)，例如ITO)之任何奈米線或塊體半導體裝置均可包括可降低透明導電材料之電阻或電阻率之介電材料層。例如，該裝置可包括使用TCO電極之太陽能電池，或使用TCO電極(例如，作為TFT主動矩陣裝置之透明電極或作為反電極)之顯示裝置，諸如液晶顯示裝置。 For example, any nanowire or bulk semiconductor device that uses a transparent conductive material, such as a transparent conductive metal oxide (TCO), such as ITO, can include a layer of dielectric material that reduces the electrical resistance or resistivity of the transparent conductive material. For example, the device may include a solar cell using a TCO electrode, or a display device using a TCO electrode (for example, as a transparent electrode of a TFT active matrix device or as a counter electrode), such as a liquid crystal display device.

本說明書中所引用之所有公開案及專利案係以引用的方式併入本文中，引用程度如同已特定地及個別地指示各個公開案或專利案以引用方式併入一般，且係以引用方式併入本文中以揭示及描述與所引用之該等公開案相關之方法及/或材料。任何公開案之引用係為了引用其先於申請日期之揭示內容，而不應視為承認本發明無權因為是先前發明而先於此等公開內容。另外，所提供的公開日期可不同於實際的公開日期，此需要進行獨立確認。 All publications and patent applications cited in this specification are herein incorporated by reference to the extent of The methods and/or materials associated with the publications cited are disclosed and described herein. The disclosure of any publication is for the purpose of citing its disclosure prior to the filing date, and is not to be construed as an admission In addition, the publication date provided may be different from the actual publication date, which requires independent confirmation.

前述方法說明僅提供作為說明性實例，且無意要求或暗示必須以所呈現次序進行各種實施例之步驟。如熟習此項技術者將暸解，該等前述實施例中之步驟次序可以任何次序進行。字詞(諸如)「此後」、「然後」、「接下來」等不一定旨在限制步驟次序；此等字詞可用於引導讀者通貫方法之說明。另外，任何時候以單數，例如使用冠詞「一」、「一個」或「該」提及所主張元件時不應視為將該元件侷限於單數。 The foregoing description of the method is provided as an illustrative example only, and is not intended to be As will be appreciated by those skilled in the art, the order of the steps in the foregoing embodiments can be performed in any order. Words such as "after", "then", "next", etc. are not necessarily intended to limit the order of steps; such words may be used to guide the reader through the description of the method. In addition, the use of the articles "a", "an" or "the"

提供所揭示態樣之先前說明係為了使任何熟習此項技術者能製造或使用本發明。熟習此項技術者將容易知曉此等態樣之各種修改，且本文所定義之一般原理可在不脫離本發明範圍的情況下應用於其他態樣。因此，不希望本發明局限於本文所示態樣，而是應具有以與本文所揭示原理及新穎特徵一致之最廣範圍。 The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the invention. Various modifications of the above-described aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the scope of the invention. Therefore, the present invention is not intended to be limited to the details shown herein, but rather,

Claims (18)

一種製造發光二極體(LED)裝置之方法，其包括：在該LED裝置之非平面表面之至少一部分上形成透明導電材料層；及在該透明導電材料層之至少一部分上沉積介電材料層，其中沉積該介電材料層包括以下至少一者：(a)利用化學氣相沉積(CVD)法沉積該層；(b)在200℃或更高之溫度下沉積該層；及(c)利用該介電材料之一或多種化學活性前驅體沉積該層。 A method of fabricating a light emitting diode (LED) device, comprising: forming a layer of transparent conductive material on at least a portion of a non-planar surface of the LED device; and depositing a layer of dielectric material on at least a portion of the layer of transparent conductive material Depositing the dielectric material layer comprising at least one of: (a) depositing the layer by chemical vapor deposition (CVD); (b) depositing the layer at a temperature of 200 ° C or higher; and (c) The layer is deposited using one or more chemically active precursors of the dielectric material. 如請求項1之方法，其中沉積該介電材料層包括在200℃至600℃之溫度下沉積該層。 The method of claim 1, wherein depositing the layer of dielectric material comprises depositing the layer at a temperature of from 200 °C to 600 °C. 如請求項1之方法，其另外包括：形成複數個位於支撐件上之第一導電型半導體奈米線核；及形成複數個在該等各別奈米線核上及周圍延伸之第二導電型半導體殼，以形成該具有非平面表面之LED裝置，其中該透明導電材料層係形成於該等複數個第二導電型半導體殼上。 The method of claim 1, further comprising: forming a plurality of first conductivity type semiconductor nanowire cores on the support member; and forming a plurality of second conductive lines extending on and around the respective nanowire cores a semiconductor housing to form the LED device having a non-planar surface, wherein the transparent conductive material layer is formed on the plurality of second conductive semiconductor shells. 如請求項1之方法，其中該透明導電材料層包含透明導電氧化物(TCO)。 The method of claim 1, wherein the transparent conductive material layer comprises a transparent conductive oxide (TCO). 如請求項4之方法，其中該透明導電氧化物包括氧化銦錫(ITO)。 The method of claim 4, wherein the transparent conductive oxide comprises indium tin oxide (ITO). 如請求項4之方法，其中該透明導電氧化物包括經鋁摻雜之氧化鋅(AZO)。 The method of claim 4, wherein the transparent conductive oxide comprises aluminum doped zinc oxide (AZO). 如請求項1之方法，其中該介電材料包括SiO2、SiN及Al2O3中之至少一者。 The method of claim 1, wherein the dielectric material comprises at least one of SiO 2 , SiN, and Al 2 O 3 . 如請求項1之方法，其中該介電材料層具有針對該LED裝置之至少一種發射波長大於85%之光學透射率。 The method of claim 1, wherein the layer of dielectric material has an optical transmittance of at least one emission wavelength greater than 85% for the LED device. 如請求項1之方法，其中該介電材料層使該透明導電材料層之電阻率減少至無該介電材料層之裝置中之該透明導電材料層之電阻率之50%或更少之值。 The method of claim 1, wherein the dielectric material layer reduces the resistivity of the transparent conductive material layer to a value of 50% or less of the resistivity of the transparent conductive material layer in the device without the dielectric material layer. . 如請求項1之方法，其中沉積該介電材料層包括(a)利用化學氣相沉積(CVD)法沉積該層。 The method of claim 1, wherein depositing the layer of dielectric material comprises (a) depositing the layer by chemical vapor deposition (CVD). 如請求項1之方法，其中沉積該介電材料層包括(b)在200℃或更高之溫度下沉積該層。 The method of claim 1, wherein depositing the layer of dielectric material comprises (b) depositing the layer at a temperature of 200 ° C or higher. 如請求項11之方法，其另外包括：將該LED裝置置於腔室中；及控制該腔室中包含該等一或多種化學活性前驅體之氣流，以沉積該介電材料層。 The method of claim 11, further comprising: placing the LED device in a chamber; and controlling a gas flow in the chamber comprising the one or more chemically active precursors to deposit the layer of dielectric material. 如請求項12之方法，其另外包括控制該腔室內之溫度，以使得該腔室內之溫度在沉積該介電材料期間為200℃至600℃。 The method of claim 12, further comprising controlling the temperature within the chamber such that the temperature within the chamber is between 200 ° C and 600 ° C during deposition of the dielectric material. 如請求項1之方法，其中沉積該介電材料層包括(c)利用該介電材料之一或多種化學活性前驅體沉積該層。 The method of claim 1, wherein depositing the layer of dielectric material comprises (c) depositing the layer with one or more chemically active precursors of the dielectric material. 如請求項14之方法，其中該介電材料之一或多種化學活性前驅體包括SiH4、二氯矽烷(DCS)、O2、正矽酸四乙酯(TEOS)、O3、H2SiCl2、NH3、AlCl3、三甲基鋁、烷醇鋁、乙醯丙酮鋁、CO2、N2O及H2O中之至少一者。 The method of claim 14, wherein the one or more chemically active precursors of the dielectric material comprise SiH 4 , dichlorodecane (DCS), O 2 , tetraethyl orthophthalate (TEOS), O 3 , H 2 SiCl 2 , at least one of NH 3 , AlCl 3 , trimethyl aluminum, aluminum alkoxide, aluminum acetonitrile, CO 2 , N 2 O and H 2 O. 如請求項1之方法，其中沉積該介電材料層包括以下中之至少兩者：(a)利用化學氣相沉積(CVD)法沉積該層；(b)在200℃或更高之溫度下沉積該層；及(c)利用該介電材料之一或多種化學活性前驅體沉積該層。 The method of claim 1, wherein depositing the dielectric material layer comprises at least two of: (a) depositing the layer by chemical vapor deposition (CVD); (b) at a temperature of 200 ° C or higher Depositing the layer; and (c) depositing the layer with one or more chemically active precursors of the dielectric material. 如請求項1之方法，其中沉積該介電材料層包括以下所有三者：(a)利用化學氣相沉積(CVD)法沉積該層； (b)在200℃或更高之溫度下沉積該層；及(c)利用該介電材料之一或多種化學活性前驅體沉積該層。 The method of claim 1, wherein depositing the dielectric material layer comprises all three of: (a) depositing the layer by chemical vapor deposition (CVD); (b) depositing the layer at a temperature of 200 ° C or higher; and (c) depositing the layer with one or more chemically active precursors of the dielectric material. 一種製造半導體裝置之方法，其包括：在該半導體裝置之至少一部分上形成透明導電材料層；及在該透明導電材料層之至少一部分上沉積介電材料層，其中沉積該介電材料層包括以下中之至少一者：(a)利用化學氣相沉積(CVD)法沉積該層；(b)在200℃或更高之溫度下沉積該層；及(c)利用該介電材料之一或多種化學活性前驅體沉積該層；及其中該介電材料使該透明導電材料之電阻率減少至無該介電材料層之裝置中之該透明導電材料之電阻率之50%或更少之值。 A method of fabricating a semiconductor device, comprising: forming a layer of transparent conductive material on at least a portion of the semiconductor device; and depositing a layer of dielectric material on at least a portion of the layer of transparent conductive material, wherein depositing the layer of dielectric material comprises At least one of: (a) depositing the layer by chemical vapor deposition (CVD); (b) depositing the layer at a temperature of 200 ° C or higher; and (c) utilizing one of the dielectric materials or Depositing the layer with a plurality of chemically active precursors; and wherein the dielectric material reduces the resistivity of the transparent conductive material to a value of 50% or less of the resistivity of the transparent conductive material in the device without the layer of dielectric material .
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