TWI634816B - Easy to test multilayer board - Google Patents
Easy to test multilayer board Download PDFInfo
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- TWI634816B TWI634816B TW105106208A TW105106208A TWI634816B TW I634816 B TWI634816 B TW I634816B TW 105106208 A TW105106208 A TW 105106208A TW 105106208 A TW105106208 A TW 105106208A TW I634816 B TWI634816 B TW I634816B
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- wiring layer
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- 238000012360 testing method Methods 0.000 title claims abstract description 18
- 239000000463 material Substances 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 230000003014 reinforcing effect Effects 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000005728 strengthening Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 230000002787 reinforcement Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 7
- 230000003064 anti-oxidating effect Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000005253 cladding Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
本發明係易於測試的多層電路板，包含有一第一電路板、複數個導電塊、一第二電路板、複數個導電凹槽、一絕緣層；該第一電路板設有一第一佈線層，該些導電塊設置於該第一電路板並與該第一佈線層電連接，該第二電路板朝向該第一電路板的表面設有一第二佈線層，該些導電凹槽形成於該第二電路板的表面，且該些導電凹槽內設有一導電層，該導電層與該第二佈線層電連接，該些導電塊設置於該些導電凹槽內時，該第一佈線層與該第二佈線層經由該些導電塊與該導電層電連接，而該絕緣層位於該第一佈線層與該第二佈線層間，避免兩者短路，該第二電路板可分離於該第一電路板，以單獨測試該第二佈線層，用以提升良率。The invention is an easy-to-test multilayer circuit board comprising a first circuit board, a plurality of conductive blocks, a second circuit board, a plurality of conductive recesses, and an insulating layer; the first circuit board is provided with a first wiring layer, The conductive blocks are disposed on the first circuit board and electrically connected to the first circuit layer, the second circuit board is provided with a second wiring layer facing the surface of the first circuit board, and the conductive grooves are formed on the first circuit board And a conductive layer is electrically connected to the second wiring layer, and the conductive layer is disposed in the conductive grooves, the first wiring layer is The second wiring layer is electrically connected to the conductive layer via the conductive blocks, and the insulating layer is located between the first wiring layer and the second wiring layer to avoid short circuit between the two, and the second circuit board can be separated from the first The board is tested separately for the second wiring layer to increase the yield.
Description
本發明係一種電路板，尤其指一種各電路板之間的佈線層，經由導電塊及導電凹槽進行電連接的易於測試的多層電路板。 The present invention relates to a circuit board, and more particularly to a wiring layer between each circuit board, an easily testable multilayer circuit board electrically connected via a conductive block and a conductive recess.
電路板係為了減少電子元件之間的配線、降低成本所衍生的產物，然而，隨著電路複雜化，使用多層電路板已成為工業電子的常態。目前多層電路板的結構，請參閱圖3A及3B所示，該多層電路板包含有一第一電路板70、一第一佈線層71、一第二電路板80、一第二佈線層81。該第一佈線層71設置於該第一電路板70上，該第一佈線層71可為該第一電路板70經由黃光製程及電鍍製程後所形成。該第二電路板80設置於該第一佈線層71，於該第二電路80板上形成一開孔82，該開孔82貫穿該第二電路板80，並且同樣透過黃光製程及電鍍製程於該第二電路板80上形成該第二佈線層81，以及於該開孔82內形成一傳導層83，利用該傳導層83電連接該第二佈線層81與該第一佈線層71。可重覆該第二電路板80的製程，持續堆疊形成第三、第四電路板(未示)，以完成該多層電路板。 Circuit boards are products derived from the reduction of wiring between electronic components and cost reduction. However, as circuits are complicated, the use of multilayer boards has become the norm of industrial electronics. The structure of the multi-layer circuit board is shown in FIGS. 3A and 3B. The multi-layer circuit board includes a first circuit board 70, a first wiring layer 71, a second circuit board 80, and a second wiring layer 81. The first wiring layer 71 is disposed on the first circuit board 70. The first wiring layer 71 can be formed after the first circuit board 70 is processed through a yellow light process and an electroplating process. The second circuit board 80 is disposed on the first circuit layer 71, and an opening 82 is formed in the second circuit 80. The opening 82 extends through the second circuit board 80, and also passes through the yellow light process and the plating process. The second wiring layer 81 is formed on the second circuit board 80, and a conductive layer 83 is formed in the opening 82. The second wiring layer 81 and the first wiring layer 71 are electrically connected by the conductive layer 83. The process of the second circuit board 80 can be repeated, and the third and fourth circuit boards (not shown) are continuously stacked to complete the multilayer circuit board.
目前的多層電路板由於製程關係，必須完成該多層電路板後，才可進行測試，包含該第二電路板80與其後續堆疊的電路板，由於無法單獨進行測試，因此無法確認各電路板之佈線層是否有誤，若其中一佈線層出現缺陷只能於測試該多層電路板時才會發現。使的即便有其中一電路板上的佈線層產生缺陷，但由於各電路板無法單獨進行測試，無法由製程中得知電路板發生異 常，異常之電路板經與其他電路板持續堆疊後完成該多層電路板，對該多層電路板測試後才發現無法使用，導致成本上升。並且測試該多層電路板若發生問題時，由於無法單獨測量，因此難以尋找發生問題的電路板，無法快速排除問題，難以提升其良率。 Due to the process relationship, the current multi-layer circuit board must be completed after the multi-layer circuit board is completed, including the second circuit board 80 and its subsequent stacked circuit boards. Since the test cannot be performed separately, it is impossible to confirm the wiring of each circuit board. If the layer is faulty, if one of the wiring layers is defective, it can only be found when testing the multilayer board. Even if there is a defect in the wiring layer on one of the boards, since the boards cannot be tested separately, it is impossible to know that the board is different in the process. Often, the abnormal circuit board is continuously stacked with other circuit boards to complete the multi-layer circuit board, and the multi-layer circuit board is tested and found to be unusable, resulting in an increase in cost. Moreover, if a problem occurs in the test of the multilayer circuit board, since it cannot be separately measured, it is difficult to find a board in which the problem occurs, and it is difficult to quickly eliminate the problem, and it is difficult to increase the yield.
由上述可以得知，目前的多層電路板中，無法對其中任一電路板上的佈線層進行測試，僅能夠完成該多層電路板後，進行整體的測量，若其中一佈線層發生問題時，難以馬上尋找、排除問題，造成良率難以提升。 It can be known from the above that in the current multi-layer circuit board, the wiring layer on any of the circuit boards cannot be tested, and only after the multi-layer circuit board is completed, the overall measurement is performed, and if one of the wiring layers has a problem, It is difficult to find and eliminate problems immediately, which makes it difficult to increase the yield.
有鑑於此，本發明係提供一種易於測試的多層電路板，將各電路板之間的佈線層利用第一導電塊進行電連接，使的各電路板完成後，可單獨進行測量，若該電路板有缺陷時，可即時處理，避免完成該多層電路板後，才發現其中一佈線層有問題，導致該多層電路板為廢品，無法使用，造成資源上的浪費，而且，難以尋找問題的電路板，使良率不佳。 In view of the above, the present invention provides a multi-layer circuit board that is easy to test, and the wiring layers between the circuit boards are electrically connected by using the first conductive blocks, so that after each circuit board is completed, the measurement can be performed separately, if the circuit When the board is defective, it can be processed immediately. After the completion of the multi-layer circuit board, it is found that one of the wiring layers has a problem, which causes the multi-layer circuit board to be waste, cannot be used, which causes waste of resources, and is difficult to find a problem circuit. Board, making the yield poor.
為了達到上述目的所採用的主要技術手段，係令前述的易於測試的多層電路板，包含：一第一電路板，其表面設有一第一佈線層；複數個第一導電塊，其設置於該第一電路板的該表面並電連接該第一佈線層；一第二電路板，其設置於該第一電路板的該表面，該第二電路板具有面向該第一電路板的一第一表面，於該第一表面形成有一第二佈線層；複數個導電凹槽，其形成於該第一表面，該些導電凹槽與該第二佈線層電連接並對應該些導電塊；一絕緣層，其設置於該第一佈線層與該第二佈線層之間； 其中，該些導電塊分別對應設置於該些導電凹槽，以電連接該第一佈線層及該第二佈線層。 The main technical means for achieving the above object is the above-mentioned easy-to-test multilayer circuit board, comprising: a first circuit board having a first wiring layer on its surface; and a plurality of first conductive blocks disposed on the The surface of the first circuit board is electrically connected to the first wiring layer; a second circuit board is disposed on the surface of the first circuit board, the second circuit board has a first surface facing the first circuit board Forming a second wiring layer on the first surface; a plurality of conductive recesses formed on the first surface, the conductive recesses electrically connected to the second wiring layer and corresponding to the conductive blocks; a layer disposed between the first wiring layer and the second wiring layer; The conductive blocks are respectively disposed on the conductive grooves to electrically connect the first wiring layer and the second wiring layer.
由以上結構可以得知，本發明的易於測試的多層電路板，各電路板之間，藉由該些導電塊與該些導電凹槽分別與其電路板上的佈線層電連接，並將該些導電塊分別設置於該導電凹槽，使各電路板之間的佈線層能夠經由該導電塊與導電凹槽進行電連接，以完成該多層電路板的結構，其中，各電路板使用導電塊與導電凹槽進行連接，使各電路板上的佈線層完成後，可單獨進行電路測試，確認佈線層是否有問題，無需完成該多層電路板後，進行整體測試時，才發現問題，造成資源浪費、成本上升，並且難以尋找發生問題的電路板，導致良率難以提升。此外，利用絕緣層設置於兩相鄰的電路板其佈線層間，避免佈線層之間發生短路。 It can be seen from the above structure that the multi-layer circuit board of the present invention is easy to test, and each of the circuit boards is electrically connected to the wiring layers on the circuit board by the conductive blocks and the conductive grooves, and the The conductive blocks are respectively disposed on the conductive recesses, so that the wiring layer between the circuit boards can be electrically connected to the conductive recesses through the conductive blocks to complete the structure of the multilayer circuit board, wherein each circuit board uses a conductive block and After the conductive grooves are connected so that the wiring layers on each circuit board are completed, the circuit test can be performed separately to confirm whether there is a problem in the wiring layer. When the multilayer circuit board is not completed, the overall test is performed, and the problem is discovered, resulting in waste of resources. The cost rises and it is difficult to find the board in which the problem occurs, which makes it difficult to increase the yield. In addition, an insulating layer is disposed between the wiring layers of two adjacent circuit boards to avoid short circuit between the wiring layers.
10‧‧‧第一電路板 10‧‧‧First board
11‧‧‧第一佈線層 11‧‧‧First wiring layer
20‧‧‧第一導電塊 20‧‧‧First conductive block
21‧‧‧基底層 21‧‧‧ basal layer
22‧‧‧強化層 22‧‧‧ Strengthening layer
23‧‧‧抗氧化層 23‧‧‧Antioxidant layer
30‧‧‧第二電路板 30‧‧‧Second circuit board
31‧‧‧第一表面 31‧‧‧ first surface
32‧‧‧第二佈線層 32‧‧‧Second wiring layer
33‧‧‧第一導電凹槽 33‧‧‧First conductive groove
331‧‧‧第一導電層 331‧‧‧First conductive layer
332‧‧‧連接層 332‧‧‧Connection layer
333‧‧‧披覆層 333‧‧‧coating
34‧‧‧第二表面 34‧‧‧second surface
35‧‧‧第三佈線層 35‧‧‧ Third wiring layer
36‧‧‧傳導層 36‧‧‧Transmission layer
40‧‧‧絕緣層 40‧‧‧Insulation
50‧‧‧第二導電塊 50‧‧‧Second conductive block
60‧‧‧第三電路板 60‧‧‧ third circuit board
61‧‧‧第三表面 61‧‧‧ third surface
62‧‧‧第四佈線層 62‧‧‧fourth wiring layer
63‧‧‧第二導電凹槽 63‧‧‧Second conductive groove
631‧‧‧第二導電層 631‧‧‧Second conductive layer
70‧‧‧第一電路板 70‧‧‧First board
71‧‧‧第一佈線層 71‧‧‧First wiring layer
80‧‧‧第二電路板 80‧‧‧second board
81‧‧‧第二佈線層 81‧‧‧Second wiring layer
82‧‧‧開孔 82‧‧‧Opening
83‧‧‧傳導層 83‧‧‧Transmission layer
圖1A係本發明的剖面示意圖。 Figure 1A is a schematic cross-sectional view of the present invention.
圖1B係本發明之導電塊的剖面示意圖。 Figure 1B is a schematic cross-sectional view of a conductive block of the present invention.
圖1C係本發明之導電凹槽的剖面示意圖。 1C is a schematic cross-sectional view of a conductive recess of the present invention.
圖1D係本發明的剖面分解示意圖。 Figure 1D is a schematic exploded view of the present invention.
圖2A係本發明另一實施例之剖面示意圖。 2A is a schematic cross-sectional view showing another embodiment of the present invention.
圖2B係本發明另一實施例之剖面分解示意圖。 2B is a schematic cross-sectional view showing another embodiment of the present invention.
圖3A係目前多層電路板之第一電路板的剖面示意圖。 3A is a schematic cross-sectional view of a first circuit board of a current multilayer circuit board.
圖3B係目前多層電路板之剖面示意圖。 3B is a schematic cross-sectional view of a current multilayer circuit board.
請參閱圖1A所示，本發明係一種易於測試的多層電路板，用以將多層電路板加以結合，易於測試的該多層電路板包含有：一第一電路板10、複數個第一導電塊20、一第二電路板30、一絕緣層40。 Referring to FIG. 1A, the present invention is an easy-to-test multilayer circuit board for combining a plurality of circuit boards. The multi-layer circuit board which is easy to test comprises: a first circuit board 10, and a plurality of first conductive blocks. 20. A second circuit board 30 and an insulating layer 40.
請參閱圖1B所示，該第一電路板10的表面設有一第一佈線層11，該些第一導電塊20設置於該第一電路板10的該表面，各該第一導電塊20的截面寬度為自該第一電路板10的該表面由下至上呈現漸縮，該第一導電塊20的頂端面積小於底端面積，且各該第一導電塊20包含有：一基底層21、一強化層22、一抗氧化層23。 The first circuit board 10 is provided with a first wiring layer 11 on the surface of the first circuit board 10, and the first conductive block 20 is disposed on the surface of the first circuit board 10. The first conductive block 20 has a top end area that is smaller than the bottom end area, and each of the first conductive blocks 20 includes: a base layer 21, A strengthening layer 22, an anti-oxidation layer 23.
該基底層21可設置於該第一電路板10的該表面，且該基底層21與該第一佈線層11鄰接，使該第一導電塊20與該第一佈線層11電連接，其中，由於銅的導電性較佳，且其成本較低，因此該基底層21的材料可為銅或其合金。 The base layer 21 can be disposed on the surface of the first circuit board 10, and the base layer 21 is adjacent to the first wiring layer 11 to electrically connect the first conductive block 20 to the first wiring layer 11, wherein Since the conductivity of copper is better and the cost thereof is lower, the material of the base layer 21 may be copper or an alloy thereof.
該強化層22覆蓋該基底層21，其中，該強化層22的硬度高於該基底層21的硬度，用以強化該些第一導電塊20的強度，避免該基底層21的材料因硬度不足而無法提供足夠的支撐力，因此，於基底層21的外表面包覆硬度較高的該強化層22，該強化層22的材料可為鈀、鎳、鎢或其合金。 The reinforcing layer 22 covers the base layer 21, wherein the hardness of the reinforcing layer 22 is higher than the hardness of the base layer 21 to strengthen the strength of the first conductive blocks 20, and the material of the base layer 21 is prevented from being insufficient in hardness. However, sufficient supporting force cannot be provided. Therefore, the reinforcing layer 22 having a higher hardness is coated on the outer surface of the base layer 21. The material of the reinforcing layer 22 may be palladium, nickel, tungsten or an alloy thereof.
該抗氧化層23用以避免該些第一導電塊20氧化。由於該些第一導電塊20其中一功能為導電，為了避免該些第一導電塊20因為氧化導致第一導電塊20的電阻增加，造成導電性降低、傳遞訊號的品質下降，甚至是無法傳送訊號，因此，藉由該抗氧化層23包覆該強化層22，避免該強化層22與該基底層21氧化，其中，該抗氧化層23的材料可為金或其合金。 The anti-oxidation layer 23 is used to prevent oxidation of the first conductive blocks 20. Since one of the first conductive blocks 20 is electrically conductive, in order to prevent the first conductive block 20 from increasing in resistance due to oxidation, the conductivity is lowered, the quality of the transmitted signal is degraded, or even the transmission cannot be transmitted. The reinforcing layer 22 is prevented from being oxidized by the anti-oxidation layer 23, and the material of the anti-oxidation layer 23 may be gold or an alloy thereof.
請參閱圖1C及1D所示，該第二電路板30具有一第一表面31，該第一表面31面向該第一電路板10的該表面，該第一表面31上形成有一第二佈線層32及複數個第一導電凹槽33，且該些第一導電凹槽33內分別設有一第一導電 層331，該第一導電層331與該第二佈線層32電連接。其中，該些第一導電凹槽33的形狀與該些第一導電塊20匹配，使該些第一導電凹槽33分別供該些第一導電塊20對應容置。當該些第一導電塊20設置於該些第一導電凹槽33內時，該第二電路板30上的該第二佈線層32經由該些第一導電凹槽33、第一導電塊20而電連接至該第一佈線層11，以傳遞訊號。此外，該第一導電層331更包含有一連接層332與一披覆層333，該連接層332與該第二佈線層32電連接，且該連接層332於本實施例中，該連接層332的材料為銅，而該披覆層333覆蓋於連接層332，用以保護該連接層332，該披覆層333其材料可為金或其合金。 Referring to FIGS. 1C and 1D, the second circuit board 30 has a first surface 31 facing the surface of the first circuit board 10. A second wiring layer is formed on the first surface 31. 32 and a plurality of first conductive grooves 33, and each of the first conductive grooves 33 is respectively provided with a first conductive The layer 331 has the first conductive layer 331 electrically connected to the second wiring layer 32. The shape of the first conductive grooves 33 is matched with the first conductive blocks 20, so that the first conductive grooves 33 are respectively received by the first conductive blocks 20. When the first conductive blocks 20 are disposed in the first conductive grooves 33, the second wiring layer 32 on the second circuit board 30 passes through the first conductive grooves 33 and the first conductive blocks 20 And electrically connected to the first wiring layer 11 to transmit a signal. In addition, the first conductive layer 331 further includes a connection layer 332 and a cladding layer 333. The connection layer 332 is electrically connected to the second wiring layer 32. In the embodiment, the connection layer 332 is connected. The material is copper, and the cladding layer 333 covers the connection layer 332 to protect the connection layer 332. The material of the cladding layer 333 may be gold or an alloy thereof.
該絕緣層40設置於該第一電路板10與該第二電路板30之間，以隔離該第一佈線層11與該第二佈線層32，避免該第一佈線層11與該第二佈線層32在非預設的連接位置直接接觸而產生短路。於本實施方式中，該絕緣層40可設置於該第一佈線層11上，並覆蓋該第一佈線層11。另外，該絕緣層40亦可設置於該第二佈線層32的表面。請參閱圖1A，於一實施例中，絕緣層40設置於第一佈線層11與第二佈線層32之間而不設置於該些第一導電塊20與該些第一導電凹槽33之間。 The insulating layer 40 is disposed between the first circuit board 10 and the second circuit board 30 to isolate the first wiring layer 11 and the second wiring layer 32 from the first wiring layer 11 and the second wiring layer. Layer 32 is in direct contact at a non-predetermined connection location to create a short circuit. In the embodiment, the insulating layer 40 may be disposed on the first wiring layer 11 and cover the first wiring layer 11 . In addition, the insulating layer 40 may be disposed on the surface of the second wiring layer 32. Referring to FIG. 1A , in an embodiment, the insulating layer 40 is disposed between the first wiring layer 11 and the second wiring layer 32 , and is not disposed on the first conductive blocks 20 and the first conductive grooves 33 . between.
本發明的另一實施例，請參考圖2A、2B所示，與前述實施例其結構大致相同，其差異點在於：該第二電路板30包含有與該第一表面31相對的一第二表面34，該第二表面34設有一第三佈線層35及複數個第二導電塊50，該些第二導電塊50與該第三佈線層35電連接，該第三佈線層35經由一開孔內的一傳導層36與該第二佈線層32電連接；此外，該第二表面34上設有一第三電路板60，該第三電路板60具有面向該第二表面34的一第三表面61，該第三表面61上形成有一第四佈線層62及複數個第二導電凹槽63，該些第二導電凹槽63內形成有一第二導電層631用以與該第四佈線層62電連接，且該第二導電凹槽63形狀與該第二導電塊50匹配以供該些第二導電塊50設置，使該第三佈線層35與該第 四佈線層62可經由該些第二導電塊50及該第二導電凹槽63進行電連接，最後於該第三佈線層35與該第四佈線層62之間設置另一絕緣層40，避免該第三佈線層35與該第四佈線層62之間發生短路，完成該多層電路板的結構；其中，該些第二導電塊50與前述該些第一導電塊20其結構與功能相同，該些第二導電凹槽63與前述該些第一導電凹槽33其結構與功能亦相同，故不加以贅述。請參閱圖2A，於一實施例中，各絕緣層40設置於二個相鄰電路板的二個相鄰佈線層之間，而不設置於該二個相鄰電路板的該些導電塊與該些導電凹槽之間。 Another embodiment of the present invention, please refer to FIG. 2A, FIG. 2B, which is substantially the same as the foregoing embodiment, and the difference is that the second circuit board 30 includes a second surface opposite to the first surface 31. The surface 34 is provided with a third wiring layer 35 and a plurality of second conductive blocks 50. The second conductive blocks 50 are electrically connected to the third wiring layer 35. The third wiring layer 35 is opened. A conductive layer 36 in the hole is electrically connected to the second wiring layer 32. Further, the second surface 34 is provided with a third circuit board 60 having a third surface facing the second surface 34. a fourth wiring layer 62 and a plurality of second conductive recesses 63 are formed on the surface 61. The second conductive recesses 63 are formed in the second conductive recesses 63 to form a fourth conductive layer 631. 62 electrically connected, and the second conductive groove 63 is shaped to match the second conductive block 50 for the second conductive blocks 50 to be disposed, such that the third wiring layer 35 and the first The four wiring layers 62 are electrically connected via the second conductive blocks 50 and the second conductive grooves 63, and finally another insulating layer 40 is disposed between the third wiring layer 35 and the fourth wiring layer 62 to avoid A short circuit occurs between the third wiring layer 35 and the fourth wiring layer 62 to complete the structure of the multilayer circuit board. The second conductive blocks 50 and the first conductive blocks 20 have the same structure and function. The second conductive recesses 63 and the first conductive recesses 33 have the same structure and function, and therefore will not be described again. Referring to FIG. 2A, in an embodiment, each of the insulating layers 40 is disposed between two adjacent wiring layers of two adjacent circuit boards, and is not disposed on the conductive blocks of the two adjacent circuit boards. Between the conductive grooves.
綜上所述，本發明係一種易於測試的多層電路板，可應用於多個電路板疊設，其中，各電路板之間相鄰的佈線層經由導電塊與導電凹槽進行電連接，使本發明各電路板上的該些佈線層完成後，可單獨進行測試，當電路板發生缺陷時，可以馬上發現、替換，並尋找出缺陷發生原因。避免完成該多層電路板後才進行整體測試，能夠有效減少報廢的多層電路板數量，提升多層電路板的良率，進而降低多層電路板的製造成本。 In summary, the present invention is an easy-to-test multilayer circuit board that can be applied to a plurality of circuit board stacks, wherein adjacent circuit layers between the circuit boards are electrically connected to the conductive grooves via the conductive blocks, so that After the wiring layers on each circuit board of the present invention are completed, they can be tested separately. When a defect occurs in the circuit board, the circuit board can be immediately found and replaced, and the cause of the defect is found. The overall test is completed after the completion of the multi-layer circuit board, which can effectively reduce the number of discarded multi-layer circuit boards, improve the yield of the multi-layer circuit board, and thereby reduce the manufacturing cost of the multi-layer circuit board.
另外，本發明的電路板的上、下表面皆可設置佈線層，可以經由貫穿電路板的穿孔內的傳導層進行電連接，可減少電路板的使用量，降低成本。 In addition, the upper and lower surfaces of the circuit board of the present invention can be provided with a wiring layer, which can be electrically connected via a conductive layer penetrating through the through holes of the circuit board, thereby reducing the amount of use of the circuit board and reducing the cost.
最後，本發明其內部結構經由本發明內容揭示，已充分說明內部結構、動作說明及功效，實乃具備了申請專利之要件；其中，本發明所述之內容，僅作為實施例之說明，並不以此限定本發明欲保護之範圍，任何局部的更改、變動之結構，仍為本發明保護之範圍。 Finally, the internal structure of the present invention is disclosed by the content of the present invention, and the internal structure, the operation description and the effect are fully explained, and the requirements of the patent application are provided; wherein the content of the present invention is only described as an embodiment, and The scope of the present invention is not to be construed as limiting the scope of the invention.
Claims (12)
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| TW105106208A TWI634816B (en) | 2016-03-01 | 2016-03-01 | Easy to test multilayer board |
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| TW105106208A TWI634816B (en) | 2016-03-01 | 2016-03-01 | Easy to test multilayer board |
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| TWI634816B true TWI634816B (en) | 2018-09-01 |
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| CN115842254B (en) * | 2023-03-01 | 2023-05-12 | 上海合见工业软件集团有限公司 | Stacked interconnection system and circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI250555B (en) * | 2005-05-24 | 2006-03-01 | Advanced Semiconductor Eng | Substrate and method of fabricating the same |
| TW200942278A (en) * | 2007-11-29 | 2009-10-16 | Glaxo Group Ltd | A dispensing device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI250555B (en) * | 2005-05-24 | 2006-03-01 | Advanced Semiconductor Eng | Substrate and method of fabricating the same |
| TW200942278A (en) * | 2007-11-29 | 2009-10-16 | Glaxo Group Ltd | A dispensing device |
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