TWI634635B - Semiconductor package structure and manufacturing method thereof - Google Patents
Semiconductor package structure and manufacturing method thereof Download PDFInfo
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- TWI634635B TWI634635B TW106101661A TW106101661A TWI634635B TW I634635 B TWI634635 B TW I634635B TW 106101661 A TW106101661 A TW 106101661A TW 106101661 A TW106101661 A TW 106101661A TW I634635 B TWI634635 B TW I634635B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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- General Physics & Mathematics (AREA)
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
一種半導體封裝結構，包括晶圓、多個第一導電凸塊以及第一封裝膠體。晶圓具有相對的第一表面以及第二表面。晶圓包括兩個半導體元件層。此兩個半導體元件層分別從第一表面以及第二表面延伸至晶圓內。第一表面與第二表面上分別設置有包括多個接墊的兩個圖案化線路層。此兩個半導體元件層分別與此兩個圖案化線路層電性連接。這些第一導電凸塊分別設置於第一表面的這些接墊上。第一封裝膠體設置於第一表面，並暴露這些第一導電凸塊的多個頂面。另，一種半導體封裝結構的製作方法亦被提出。A semiconductor package structure includes a wafer, a plurality of first conductive bumps, and a first encapsulant. The wafer has opposing first and second surfaces. The wafer includes two layers of semiconductor elements. The two semiconductor element layers extend from the first surface and the second surface into the wafer, respectively. Two patterned circuit layers including a plurality of pads are respectively disposed on the first surface and the second surface. The two semiconductor element layers are electrically connected to the two patterned circuit layers, respectively. The first conductive bumps are respectively disposed on the pads of the first surface. The first encapsulant is disposed on the first surface and exposes the plurality of top surfaces of the first conductive bumps. In addition, a method of fabricating a semiconductor package structure has also been proposed.
Description
本發明是有關於一種封裝結構及其製作方法，且特別是有關於一種半導體封裝結構及其製作方法。The present invention relates to a package structure and a method of fabricating the same, and more particularly to a semiconductor package structure and a method of fabricating the same.
晶圓級晶片尺寸封裝（Wafer Level Chip Scale Package, WLCSP）技術指的是晶圓在生產完成後直接在整片晶圓上進行全部或大部分的封裝以及測試程序後，再進行切割（Singulation）以形成單顆元件。由於晶圓級晶片尺寸封裝技術具有較小封裝尺寸、較佳電性表現、較容易的組裝製程以及較低的生產成本等優勢，因而吸引晶圓製造業者以及封測代工業者大舉投入此技術中。Wafer Level Chip Scale Package (WLCSP) technology refers to the wafer after the production is completed, after all or most of the package and test procedures are performed on the entire wafer, and then the cutting process is performed. To form a single component. Because wafer-level chip-scale packaging technology has the advantages of smaller package size, better electrical performance, easier assembly process, and lower production cost, it attracts wafer manufacturers and manufacturers in the test industry to invest heavily in this technology. in.
在現有的晶圓級晶片尺寸封裝技術中，晶圓的單面上通常會植球以使晶圓的電性訊號傳遞至外部的印刷電路板（Printed Circuit Board, PCB），然而，這樣的方式卻無法滿足高接腳數（I/O）的需求。In the existing wafer level wafer size packaging technology, a single side of the wafer is usually implanted to transfer the electrical signal of the wafer to an external printed circuit board (PCB). However, in such a manner However, it cannot meet the demand for high pin count (I/O).
本發明提供一種半導體封裝結構，其具有較高的接腳數。The present invention provides a semiconductor package structure having a higher number of pins.
本發明提供一種半導體封裝結構的製造方法，用以製造上述的半導體封裝結構。The present invention provides a method of fabricating a semiconductor package structure for fabricating the above-described semiconductor package structure.
本發明的一實施例提出一種半導體封裝結構，半導體封裝結構包括晶圓、多個第一導電凸塊以及第一封裝膠體。晶圓具有相對的第一表面以及第二表面。晶圓包括第一半導體元件層以及第二半導體元件層。第一半導體元件層以及第二半導體元件層分別從第一表面以及第二表面延伸至晶圓內。第一表面與第二表面上分別設置有第一圖案化線路層及第二圖案化線路層。第一圖案化線路層與第二圖案化線路層分別包括多個第一接墊及多個第二接墊。第一半導體元件層與第二半導體元件層分別與第一圖案化線路層以及第二圖案化線路層電性連接。這些第一導電凸塊分別設置於這些第一接墊上。第一封裝膠體設置於第一表面，並暴露這些第一導電凸塊的多個頂面。An embodiment of the invention provides a semiconductor package structure including a wafer, a plurality of first conductive bumps, and a first encapsulant. The wafer has opposing first and second surfaces. The wafer includes a first semiconductor element layer and a second semiconductor element layer. The first semiconductor device layer and the second semiconductor device layer extend from the first surface and the second surface, respectively, into the wafer. A first patterned circuit layer and a second patterned circuit layer are respectively disposed on the first surface and the second surface. The first patterned circuit layer and the second patterned circuit layer respectively include a plurality of first pads and a plurality of second pads. The first semiconductor element layer and the second semiconductor element layer are electrically connected to the first patterned circuit layer and the second patterned circuit layer, respectively. The first conductive bumps are respectively disposed on the first pads. The first encapsulant is disposed on the first surface and exposes the plurality of top surfaces of the first conductive bumps.
在本發明的一實施例中，上述的晶圓更包括多個第二導電凸塊，分別設置於這些第二接墊上。In an embodiment of the invention, the wafer further includes a plurality of second conductive bumps disposed on the second pads.
在本發明的一實施例中，上述的晶圓更包括第二封裝膠體。第二封裝膠體設置於第二表面，且暴露這些第二導電凸塊的多個頂面。In an embodiment of the invention, the wafer further includes a second encapsulant. The second encapsulant is disposed on the second surface and exposes the plurality of top surfaces of the second conductive bumps.
在本發明的一實施例中，上述的這些第二導電凸塊的這些頂面設置有銲球。In an embodiment of the invention, the top surfaces of the second conductive bumps are provided with solder balls.
在本發明的一實施例中，上述的這些第一導電凸塊的這些頂面設置有銲球。In an embodiment of the invention, the top surfaces of the first conductive bumps are provided with solder balls.
本發明的一實施例提出一種半導體封裝結構的製造方法，包括下列步驟。提供晶圓。晶圓具有相對的第一表面以及背面。晶圓包括由第一表面延伸至晶圓內的第一半導體元件層。第一表面設置有第一圖案化線路層。第一圖案化線路層包括多個第一接墊。第一半導體元件層與第一圖案化線路層電性連接。形成多個第一導電凸塊分別於這些第一接墊上。形成第一封裝膠體於第一表面上，且第一封裝膠體覆蓋這些第一導電凸塊。對晶圓的背面進行薄化製程，以使晶圓暴露出第二表面。形成第二半導體元件層於第二表面，第二半導體元件層由第二表面延伸至晶圓內。形成第二圖案化線路層於第二表面上，第二圖案化線路層包括多個第二接墊。第二半導體元件層與第二圖案化線路層電性連接。移除至少部分第一封裝膠體以暴露出這些第一導電凸塊的多個頂面。An embodiment of the invention provides a method of fabricating a semiconductor package structure comprising the following steps. Provide wafers. The wafer has opposing first and back sides. The wafer includes a first semiconductor element layer that extends from the first surface into the wafer. The first surface is provided with a first patterned circuit layer. The first patterned circuit layer includes a plurality of first pads. The first semiconductor element layer is electrically connected to the first patterned circuit layer. A plurality of first conductive bumps are formed on the first pads. Forming a first encapsulant on the first surface, and the first encapsulant covers the first conductive bumps. A thinning process is performed on the back side of the wafer to expose the wafer to the second surface. A second semiconductor device layer is formed on the second surface, and the second semiconductor device layer is extended from the second surface into the wafer. Forming a second patterned wiring layer on the second surface, the second patterned wiring layer including a plurality of second pads. The second semiconductor device layer is electrically connected to the second patterned circuit layer. At least a portion of the first encapsulant is removed to expose a plurality of top surfaces of the first conductive bumps.
在本發明的一實施例中，上述的製作方法更包括形成多個第二導電凸塊分別於這些第二接墊上。In an embodiment of the invention, the manufacturing method further includes forming a plurality of second conductive bumps on the second pads.
在本發明的一實施例中，上述的製作方法更包括形成第二封裝膠體於第二表面上。第二封裝膠體覆蓋這些第二導電凸塊。移除至少部分第二封裝膠體以暴露出第二導電凸塊的多個頂面。In an embodiment of the invention, the manufacturing method further includes forming a second encapsulant on the second surface. The second encapsulant covers the second conductive bumps. At least a portion of the second encapsulant is removed to expose the plurality of top surfaces of the second electrically conductive bumps.
在本發明的一實施例中，上述的製作方法更包括形成銲球於這些第二導電凸塊的這些頂面上。In an embodiment of the invention, the manufacturing method further includes forming solder balls on the top surfaces of the second conductive bumps.
在本發明的一實施例中，上述的製作方法更包括形成銲球於這些第一導電凸塊的這些頂面上。In an embodiment of the invention, the manufacturing method further includes forming solder balls on the top surfaces of the first conductive bumps.
基於上述，在本發明實施例的半導體封裝結構中，晶圓的第一半導體元件層以及第二半導體元件層分別電性連接於位於第一表面上的第一圖案化線路層以及位於第二表面上的第二圖案化線路層，第一圖案化線路層與第二圖案化線路層分別包括多個第一接墊以及多個第二接墊，以將第一半導體元件層以及第二半導體元件層的電性訊號傳遞至外部基板或晶片。透過上述的配置，本發明實施例的半導體封裝結構具有較高的接腳數（即高I/O數）。此外，本發明另提供一種半導體封裝結構的製造方法，以製造出上述的半導體封裝結構，透過本發明的半導體封裝結構的製造方法製造出的半導體封裝結構具有較高的接腳數。In the semiconductor package structure of the embodiment of the present invention, the first semiconductor device layer and the second semiconductor device layer of the wafer are electrically connected to the first patterned circuit layer on the first surface and the second surface, respectively. The second patterned circuit layer, the first patterned circuit layer and the second patterned circuit layer respectively comprise a plurality of first pads and a plurality of second pads to connect the first semiconductor device layer and the second semiconductor device The electrical signals of the layers are transferred to an external substrate or wafer. Through the above configuration, the semiconductor package structure of the embodiment of the present invention has a higher number of pins (ie, a high I/O number). Furthermore, the present invention further provides a method of fabricating a semiconductor package structure for fabricating the above-described semiconductor package structure, and the semiconductor package structure manufactured by the method of fabricating the semiconductor package structure of the present invention has a high number of pins.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A至圖1K’為本發明的多個實施例的半導體封裝結構的製造方法。1A to 1K' illustrate a method of fabricating a semiconductor package structure in accordance with various embodiments of the present invention.
於以下段落中介紹本發明實施例的半導體封裝結構的製造方法，其例如是適用於製造晶圓級（Wafer Level）的半導體封裝結構。請先參照圖1A，提供一晶圓110。晶圓110具有相對的第一表面S1以及背面BS。晶圓110包括由第一表面S1延伸至晶圓110內的第一半導體元件層112。第一表面S1可被視為主動表面（Active Surface）。第一表面S1設置有第一圖案化線路層112a。第一半導體元件層112與第一圖案化線路層112a電性連接。第一圖案化線路層112a包括多個第一接墊P1。第一半導體元件層112與第一圖案化線路層112a電性連接。A method of fabricating a semiconductor package structure according to an embodiment of the present invention is described in the following paragraphs, for example, a semiconductor package structure suitable for fabricating a wafer level. Referring first to FIG. 1A, a wafer 110 is provided. The wafer 110 has opposing first and second surfaces S1 and S1. Wafer 110 includes a first semiconductor device layer 112 that extends from first surface S1 into wafer 110. The first surface S1 can be regarded as an active surface. The first surface S1 is provided with a first patterned wiring layer 112a. The first semiconductor element layer 112 is electrically connected to the first patterned wiring layer 112a. The first patterned wiring layer 112a includes a plurality of first pads P1. The first semiconductor element layer 112 is electrically connected to the first patterned wiring layer 112a.
在本實施例中，晶圓110的材料例如是矽（Silicon, Si），但本發明並不以此為限。第一圖案化線路層112a的材料例如是金屬材料，但本發明並不以此為限。晶圓110的厚度T例如是150微米（Micrometer, µm），但本發明並不以此為限。第一半導體元件層112例如是包括薄膜電晶體（Thin film Transistor, TFT）、金屬氧化物半導體場效電晶體（Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET）或互補式金屬氧化物半導體（Complementary Metal-Oxide-Semiconductor, CMOS），但本發明並不以此為限。In the present embodiment, the material of the wafer 110 is, for example, Silicon (Si), but the invention is not limited thereto. The material of the first patterned circuit layer 112a is, for example, a metal material, but the invention is not limited thereto. The thickness T of the wafer 110 is, for example, 150 micrometers (micrometer, μm), but the invention is not limited thereto. The first semiconductor device layer 112 includes, for example, a thin film transistor (TFT), a metal oxide semiconductor field effect transistor (MOSFET), or a complementary metal oxide semiconductor (Complementary). Metal-Oxide-Semiconductor, CMOS), but the invention is not limited thereto.
請參照圖1B，形成多個第一導電凸塊120分別於第一表面S1的這些第一接墊P1上。這些導電凸塊120與這些第一接墊P1電性連接。在本實施例中，這些第一導電凸塊120的材料例如是銅（Cu）、鋁（Al）或其合金（Cu/Al）。形成導電凸塊120的方式例如是電鍍，但本發明並不以此為限。Referring to FIG. 1B, a plurality of first conductive bumps 120 are formed on the first pads P1 of the first surface S1. The conductive bumps 120 are electrically connected to the first pads P1. In this embodiment, the material of the first conductive bumps 120 is, for example, copper (Cu), aluminum (Al), or an alloy thereof (Cu/Al). The manner of forming the conductive bumps 120 is, for example, electroplating, but the invention is not limited thereto.
接著，請參照圖1C，形成一第一封裝膠體130於第一表面S1上，且第一封裝膠體130覆蓋這些第一導電凸塊120。在本實施例中，第一封裝膠體130的材料例如是環氧模壓樹脂（Epoxy Molding Compound, EMC），但本發明並不以此為限。更具體來說，在本實施例中，第一封裝膠體130的厚度例如是300微米，但本發明並不以此為限。Next, referring to FIG. 1C , a first encapsulant 130 is formed on the first surface S1 , and the first encapsulant 130 covers the first conductive bumps 120 . In the present embodiment, the material of the first encapsulant 130 is, for example, an Epoxy Molding Compound (EMC), but the invention is not limited thereto. More specifically, in the present embodiment, the thickness of the first encapsulant 130 is, for example, 300 micrometers, but the invention is not limited thereto.
請參照圖1D，對晶圓110的背面BS進行薄化製程（Thinning Process），以使晶圓110暴露出第二表面S2。在本實施例中，經薄化製程後的晶圓110的厚度T’例如是50微米，但本發明並不以此為限。薄化製程例如是透過研磨製程（Grinding Process）、蝕刻製程（Etching Process）或拋光製程（Polishing Process），但本發明並不以此為限。Referring to FIG. 1D, a thinning process is performed on the back surface BS of the wafer 110 to expose the wafer 110 to the second surface S2. In the present embodiment, the thickness T' of the wafer 110 after the thinning process is, for example, 50 micrometers, but the invention is not limited thereto. The thinning process is, for example, a Grinding process, an Etching process, or a Polishing process, but the invention is not limited thereto.
請參照圖1E，形成一第二半導體元件層114於第二表面S2。第二半導體元件層114由第二表面S2延伸至晶圓110內。於此時，第二表面S2可被視為主動表面。在晶圓110中，第一半導體元件層112與第二半導體元件層114彼此分離。詳言之，形成第二半導體元件層114的方法例如是透過半導體製程。半導體製程例如是包括磊晶製程（Epitaxy Process）、熱處理製程（Thermal Process）、黃光製程（Photolithography Process）、摻雜製程（Doping Process）、離子佈植製程（Ion Implantation Process）、蝕刻製程（Etching Process）或沉積製程（Deposition Process）等多道製程組合，本發明並不以此為限。第二半導體元件層114例如是包括薄膜電晶體（Thin film Transistor, TFT）、金屬氧化物半導體場效電晶體（Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET）或互補式金屬氧化物半導體（Complementary Metal-Oxide-Semiconductor, CMOS），本發明並不以此為限。Referring to FIG. 1E, a second semiconductor device layer 114 is formed on the second surface S2. The second semiconductor device layer 114 extends from the second surface S2 into the wafer 110. At this time, the second surface S2 can be regarded as an active surface. In the wafer 110, the first semiconductor element layer 112 and the second semiconductor element layer 114 are separated from each other. In detail, the method of forming the second semiconductor device layer 114 is, for example, a semiconductor process. The semiconductor process includes, for example, an Epidaxy Process, a Thermal Process, a Photolithography Process, a Doping Process, an Ion Implantation Process, and an Etching Process (Etching). Process or a multi-process combination such as a deposition process, the invention is not limited thereto. The second semiconductor device layer 114 includes, for example, a Thin Film Transistor (TFT), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), or a Complementary Metal Oxide Semiconductor (Complementary). Metal-Oxide-Semiconductor, CMOS), the invention is not limited thereto.
請參照圖1F，形成一第二圖案化線路層114a於第二主動表面S2上，第二圖案化線路層114a包括多個第二接墊P2。第二半導體元件層114與第二圖案化線路層114a電性連接。詳言之，形成第二圖案化線路層114a的方式例如是透過黃光製程（Photolithography Process）以及沉積製程（Deposition Process）來形成第二圖案化線路層114a，但本發明並不以此為限。第二圖案化線路層114a的材料例如是金屬材料，但本發明並不以此為限。Referring to FIG. 1F, a second patterned wiring layer 114a is formed on the second active surface S2, and the second patterned wiring layer 114a includes a plurality of second pads P2. The second semiconductor device layer 114 is electrically connected to the second patterned wiring layer 114a. In detail, the second patterned circuit layer 114a is formed by, for example, a photolithography process and a deposition process to form the second patterned circuit layer 114a, but the invention is not limited thereto. . The material of the second patterned circuit layer 114a is, for example, a metal material, but the invention is not limited thereto.
請參照圖1G，移除至少部分第一封裝膠體130以暴露出這些第一導電凸塊120的多個頂面122。移除的方式例如是研磨或是雷射燒蝕等方式。至此，本發明實施例中的半導體封裝結構100大體上已製作完成。在本實施例中，半導體封裝結構100包括晶圓110、多個第一導電凸塊120以及第一封裝膠體130。晶圓110具有相對的第一表面S1以及第二表面S2。晶圓110包括第一半導體元件層112以及第二半導體元件層114。第一半導體元件層112以及第二半導體元件層114分別從第一表面S1以及第二表面S2延伸至晶圓110內。第一表面S1以及第二表面S2上分別設置有第一圖案化線路層112a及第二圖案化線路層114a。第一圖案化線路層112a包括多個第一接墊P1。第二圖案化線路層114a包括多個第二接墊P2。Referring to FIG. 1G, at least a portion of the first encapsulant 130 is removed to expose the plurality of top surfaces 122 of the first conductive bumps 120. The method of removal is, for example, grinding or laser ablation. So far, the semiconductor package structure 100 in the embodiment of the present invention has been substantially completed. In the embodiment, the semiconductor package structure 100 includes a wafer 110 , a plurality of first conductive bumps 120 , and a first encapsulant 130 . The wafer 110 has opposing first and second surfaces S1 and S2. The wafer 110 includes a first semiconductor element layer 112 and a second semiconductor element layer 114. The first semiconductor element layer 112 and the second semiconductor element layer 114 extend from the first surface S1 and the second surface S2 into the wafer 110, respectively. The first patterned circuit layer 112a and the second patterned circuit layer 114a are respectively disposed on the first surface S1 and the second surface S2. The first patterned wiring layer 112a includes a plurality of first pads P1. The second patterned wiring layer 114a includes a plurality of second pads P2.
承上述，在本發明的實施例中的半導體封裝結構100中，晶圓110的第一半導體元件層112以及第二半導體元件層114分別電性連接於位於第一表面S1上的第一圖案化線路層112a以及位於第二表面S2上的第二圖案化線路層114a（即晶圓110具有可被視為主動表面的第一表面S1以及第二表面S2）。第一圖案化線路層112a以及第二圖案化線路層114a分別包括多個第一接墊P1以及多個第二接墊P2，以將第一半導體元件層112以及第二半導體元件層114的電性訊號傳遞至外部基板或晶片。因此，本發明實施例中的半導體封裝結構100具有較高的接腳數（即高I/O數）。As described above, in the semiconductor package structure 100 of the embodiment of the present invention, the first semiconductor device layer 112 and the second semiconductor device layer 114 of the wafer 110 are electrically connected to the first pattern on the first surface S1, respectively. The wiring layer 112a and the second patterned wiring layer 114a on the second surface S2 (i.e., the wafer 110 has a first surface S1 and a second surface S2 that can be regarded as active surfaces). The first patterned wiring layer 112a and the second patterned wiring layer 114a respectively include a plurality of first pads P1 and a plurality of second pads P2 to electrically charge the first semiconductor element layer 112 and the second semiconductor element layer 114. The signal is transmitted to an external substrate or wafer. Therefore, the semiconductor package structure 100 in the embodiment of the present invention has a higher number of pins (ie, a high I/O number).
於以下段落中會繼續說明本發明多個實施例的製作方法。沿續圖1A至圖1G的半導體結構製造方法，請參照圖1H，形成銲球B於這些第一導電凸塊120的這些頂面122上。在本實施例中，銲球B例如是錫球、錫膏或錫層，但本發明並不以此為限。至此，本發明實施例的半導體封裝結構100a大體上已製作完成。因此，圖1H的半導體封裝結構100a與圖1G的半導體封裝結構100的主要差異在於：在圖1H的半導體封裝結構100a中，這些第一導電凸塊120的這些頂面122上設置有銲球B。The method of making various embodiments of the present invention will continue to be described in the following paragraphs. 1A to FIG. 1G, referring to FIG. 1H, solder balls B are formed on the top surfaces 122 of the first conductive bumps 120. In the present embodiment, the solder ball B is, for example, a solder ball, a solder paste or a tin layer, but the invention is not limited thereto. Thus far, the semiconductor package structure 100a of the embodiment of the present invention has been substantially completed. Therefore, the main difference between the semiconductor package structure 100a of FIG. 1H and the semiconductor package structure 100 of FIG. 1G is that in the semiconductor package structure 100a of FIG. 1H, the top surfaces 122 of the first conductive bumps 120 are provided with solder balls B. .
沿續圖1A至圖1G的半導體結構製造方法，請參照圖1H’，形成多個第二導電凸塊140分別於第二表面S2的這些第二接墊P2上。在本實施例中，這些第二導電凸塊140的材料例如是銅（Cu）、鋁（Al）或其合金，但本發明並不以此為限。請參照圖1I’，形成第二封裝膠體150於第二表面S2上，第二封裝膠體150覆蓋這些第二導電凸塊140。請參照圖1J’，移除至少部分第二封裝膠體150以暴露出這些第二導電凸塊140的多個頂面142。至此，本發明實施例的半導體封裝結構100b大體上已製作完成。因此，圖1J’的半導體封裝結構100b與圖1G的半導體封裝結構100的主要差異在於：在圖1J’的半導體封裝結構100b中，更包括多個第二導電凸塊140以及第二封裝膠體150。這些第二導電凸塊140分別設置於這些第二接墊P2上。第二封裝膠體150設置於第二表面S2，且暴露這些第二導電凸塊140的多個頂面142。1A to 1G, referring to FIG. 1H', a plurality of second conductive bumps 140 are formed on the second pads P2 of the second surface S2. In this embodiment, the material of the second conductive bumps 140 is, for example, copper (Cu), aluminum (Al) or an alloy thereof, but the invention is not limited thereto. Referring to FIG. 1I', a second encapsulant 150 is formed on the second surface S2, and a second encapsulant 150 covers the second conductive bumps 140. Referring to FIG. 1J', at least a portion of the second encapsulant 150 is removed to expose the plurality of top surfaces 142 of the second conductive bumps 140. Thus far, the semiconductor package structure 100b of the embodiment of the present invention has been substantially completed. Therefore, the main difference between the semiconductor package structure 100b of FIG. 1J' and the semiconductor package structure 100 of FIG. 1G is that, in the semiconductor package structure 100b of FIG. 1J', a plurality of second conductive bumps 140 and a second encapsulant 150 are further included. . The second conductive bumps 140 are respectively disposed on the second pads P2. The second encapsulant 150 is disposed on the second surface S2 and exposes the plurality of top surfaces 142 of the second conductive bumps 140.
沿續圖1A至圖1J’的半導體封裝結構的製造方法，請參照圖1K’，形成銲球B於這些第二導電凸塊140的這些頂面142上。至此，本發明再一實施例的半導體封裝結構100c大體上已製作完成。因此，圖1K’的半導體封裝結構100c與圖1J’的半導體封裝結構100b的主要差異在於：在圖1K’的半導體封裝結構100c中，這些第二導電凸塊140的這些頂面142設置有銲球B。Referring to FIG. 1K', a method of manufacturing the semiconductor package structure of FIGS. 1A to 1J' is performed to form solder balls B on the top surfaces 142 of the second conductive bumps 140. Thus far, the semiconductor package structure 100c of still another embodiment of the present invention has been substantially completed. Therefore, the main difference between the semiconductor package structure 100c of FIG. 1K' and the semiconductor package structure 100b of FIG. 1J' is that in the semiconductor package structure 100c of FIG. 1K', the top surfaces 142 of the second conductive bumps 140 are provided with solder. Ball B.
圖2是圖1H中的半導體封裝結構100經過切割後的單體晶片封裝結構外接於基板的示意圖。FIG. 2 is a schematic diagram of the diced monolithic package structure of the semiconductor package structure 100 of FIG. 1H circumscribed to the substrate.
請參照圖2，半導體封裝結構100經過切割後形成多個單體晶片封裝結構10，圖2示例性地繪示一個單體晶片封裝結構10透過銲球B以及金屬導線160以與外部的一基板200電性連接的方式。也就是說，單顆晶片封裝結構10可以透過銲球B、金屬導線160、導電柱（Conductive Pillar，未示出）或者是其他形式的導電件（未示出）以使單顆晶片封裝結構與外部的基板（基板例如是印刷電路板或者是經由其他種類的製程所製作的線路板，但本發明並不以此為限）電性連接，以分別將單顆晶片封裝結構10中的第一半導體元件層112與第二半導體元件層114的電性訊號傳遞至外部基板。或者是，在其他未繪示的實施例中，也可以另外堆疊晶片於單顆晶片封裝結構10上，並透過導電件將晶片與單顆晶片封裝結構10以使兩者彼此電性連接，以分別將單顆晶片封裝結構10中的第一半導體元件層112與第二半導體元件層114的電性訊號傳遞至外部的晶片。因此，本發明實施例的半導體封裝結構100在電路設計上具有較高的彈性。Referring to FIG. 2, the semiconductor package structure 100 is diced to form a plurality of single chip package structures 10. FIG. 2 exemplarily shows a single chip package structure 10 through the solder balls B and the metal wires 160 to be external to a substrate. 200 electrical connection. That is, the single chip package structure 10 can pass through the solder ball B, the metal wire 160, the conductive pillar (not shown) or other forms of conductive members (not shown) to make the single chip package structure and The external substrate (the substrate is, for example, a printed circuit board or a circuit board manufactured by other kinds of processes, but the invention is not limited thereto) is electrically connected to respectively replace the first one of the single chip package structures 10 The electrical signals of the semiconductor device layer 112 and the second semiconductor device layer 114 are transferred to the external substrate. Alternatively, in other embodiments not shown, the wafer may be additionally stacked on the single chip package structure 10, and the wafer and the single chip package structure 10 are electrically connected through the conductive member to electrically connect the two to each other. The electrical signals of the first semiconductor device layer 112 and the second semiconductor device layer 114 in the single chip package structure 10 are respectively transferred to the external wafer. Therefore, the semiconductor package structure 100 of the embodiment of the present invention has high flexibility in circuit design.
綜上所述，在本發明實施例的半導體封裝結構中，晶圓的第一半導體元件層以及第二半導體元件層分別電性連接於位於第一表面上的第一圖案化線路層以及位於第二表面上的第二圖案化線路層，第一圖案化線路層與第二圖案化線路層分別包括多個第一接墊以及第二接墊，以將第一半導體元件層以及第二半導體元件層的電性訊號傳遞至外部基板或晶片。透過上述的配置，本發明實施例的半導體封裝結構具有較高的接腳數（即高I/O數）。In the semiconductor package structure of the embodiment of the present invention, the first semiconductor device layer and the second semiconductor device layer of the wafer are electrically connected to the first patterned circuit layer on the first surface and the first a second patterned circuit layer on the two surfaces, the first patterned circuit layer and the second patterned circuit layer respectively include a plurality of first pads and second pads to connect the first semiconductor device layer and the second semiconductor device The electrical signals of the layers are transferred to an external substrate or wafer. Through the above configuration, the semiconductor package structure of the embodiment of the present invention has a higher number of pins (ie, a high I/O number).
進一步來說，本發明實施例的半導體封裝結構經過後續的切割製程形成多個單體晶片封裝結構，單體晶片封裝結構可以透過不同型式的導電件（例如是銲球、金屬導線、導電柱或其他形式的導電件）以使單顆晶片封裝結構與外部的基板或晶片電性連接。因此，本發明實施例的半導體封裝結構在電路設計上具有較高的彈性。Further, the semiconductor package structure of the embodiment of the present invention forms a plurality of single chip package structures through a subsequent dicing process, and the single chip package structure can transmit different types of conductive members (for example, solder balls, metal wires, conductive posts, or Other forms of conductive members) are used to electrically connect a single wafer package structure to an external substrate or wafer. Therefore, the semiconductor package structure of the embodiment of the present invention has high flexibility in circuit design.
此外，本發明另提供一種半導體封裝結構的製造方法，以製造出上述的半導體封裝結構，透過本發明的半導體封裝結構的製造方法製造出的半導體封裝結構具有較高的接腳數，且電路設計上具有較高的彈性。In addition, the present invention further provides a method of fabricating a semiconductor package structure to fabricate the above-described semiconductor package structure, and the semiconductor package structure manufactured by the method for fabricating the semiconductor package structure of the present invention has a high number of pins, and the circuit design It has a high elasticity.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10：單顆晶片封裝結構 100、100a、100b、100c：半導體封裝結構 110：晶圓 112：第一半導體元件層 112a：第一圖案化線路層 114：第二半導體元件層 114a：第二圖案化線路層 120：第一導電凸塊 122、142：頂面 130：第一封裝膠體 140：第二導電凸塊 150：第二封裝膠體 160：金屬導線 200：基板 B：銲球 BS：背面 S1：第一表面 S2：第二表面 T、T’：厚度 P1：第一接墊 P2：第二接墊10: Single chip package structure 100, 100a, 100b, 100c: semiconductor package structure 110: wafer 112: first semiconductor element layer 112a: first patterned circuit layer 114: second semiconductor element layer 114a: second patterning Circuit layer 120: first conductive bumps 122, 142: top surface 130: first encapsulant 140: second conductive bump 150: second encapsulant 160: metal wire 200: substrate B: solder ball BS: back S1: First surface S2: second surface T, T': thickness P1: first pad P2: second pad
圖1A至圖1K’為本發明的多個實施例的半導體封裝結構的製造方法。 圖2是圖1G中的半導體封裝結構經過切割後的單體晶片封裝結構外接於基板的示意圖。1A to 1K' illustrate a method of fabricating a semiconductor package structure in accordance with various embodiments of the present invention. 2 is a schematic diagram of the diced monolithic package structure of the semiconductor package structure of FIG. 1G circumscribed to the substrate.
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