TWI633561B - Seven-transistor dual port static random access memory with fast write speed - Google Patents
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Abstract
本發明提出一種具高寫入速度之7T雙埠靜態隨機存取記憶體,其主要包括一記憶體陣列(1)、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)、複數個高電壓位準控制電路(5)以及複數個寫入驅動電路(6),該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成,每一列記憶體晶胞設置一個控制電路(2)以及一個高電壓位準控制電路(5),且每一行記憶體晶胞設置一個預充電電路(3)以及一個寫入驅動電路(6)。藉此,於寫入模式時,可藉由該複數個控制電路(2)以及該複數個寫入驅動電路(6)以有效防止寫入邏輯1困難之同時,亦提高寫入邏輯1之速度,於讀取模式時,可藉由該複數個控制電路(2)以及該複數個高電壓位準控制電路(5)以於提高讀取速度的同時,亦避免無謂的功率耗損,於待機模式時,可藉由該複數個控制電路(2)以有效降低漏電流,且可藉由該待機啟動電路(4)的設計,以有效促使靜態隨機存取記憶體快速進入待機模式。 The invention proposes a 7T dual-port static random access memory with high writing speed, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby A start circuit (4), a plurality of high voltage level control circuits (5), and a plurality of write drive circuits (6), the memory array is composed of a plurality of rows of memory cell units and a plurality of rows of memory unit cells, Each column of memory cells is provided with a control circuit (2) and a high-voltage level control circuit (5), and each row of memory cells is provided with a precharge circuit (3) and a write drive circuit (6). Therefore, in the write mode, the plurality of control circuits (2) and the plurality of write driving circuits (6) can be used to effectively prevent the difficulty of writing the logic 1 while increasing the speed of writing the logic 1 In the reading mode, the plurality of control circuits (2) and the plurality of high-voltage level control circuits (5) can be used to improve the reading speed while avoiding unnecessary power consumption. In the standby mode At this time, the plurality of control circuits (2) can effectively reduce the leakage current, and the design of the standby start circuit (4) can effectively promote the static random access memory to quickly enter the standby mode.
Description
本發明係有關於一種具高寫入速度之7T雙埠(dual port)靜態隨機存取記憶體(Static Random Access Memory,簡稱SRAM),尤指一種有效提高7T SRAM待機效能,並能有效提高讀取速度與寫入速度,且能有效降低漏電流(leakage current)、降低讀取時之半選定晶胞干擾以及避免無謂的功率耗損之SRAM。 The invention relates to a 7T dual port static random access memory (SRAM) with high write speed, and particularly to a 7T SRAM which can effectively improve the standby performance of the 7T SRAM and can effectively improve the read performance. SRAM with fast access speed and write speed, which can effectively reduce leakage current, reduce half-selected cell interference during reading, and avoid unnecessary power loss.
習知之單埠靜態隨機存取記憶體(SRAM)如第1a圖所示,其主要包括一記憶體陣列(memory array),該記憶體陣列係由複數個記憶體區塊(memory block,MB1、MB2等)所組成,每一記憶體區塊更由複數列記憶體晶胞(a plurality of rows of memory cells)與複數行記憶體晶胞(a plurality of columns of memory cells)所組成,每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞;複數條字元線(word line,WL1、WL2等),每一字元線對應至複數列記憶體晶胞中之一列;以及複數位元線對(bit line pairs,BL1、BLB1...BLm、BLBm等),每一位元線對係對應至複數行記憶體晶胞中之一行,且每一位元線對係由一位元線(BL1...BLm)及一互補位元線(BLB1...BLBm)所組成。 As shown in Figure 1a, the conventional static random access memory (SRAM) in the port includes a memory array. The memory array is composed of a plurality of memory blocks (MB 1). , MB 2 etc.), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL 1 , WL 2, etc.), each character line corresponds to a plurality of rows of memory One column in the unit cell; and multiple bit line pairs (BL 1 , BLB 1 ... BL m , BLB m, etc.), each bit line pair corresponds to the multiple row memory cell One row, and each bit line pair is composed of a bit line (BL 1 ... BL m ) and a complementary bit line (BLB 1 ... BLB m ).
第1b圖所示即是6T單埠靜態隨機存取記憶體(SRAM)晶胞之電路示意圖,其中,PMOS電晶體(P1)和(P2)稱為負載電晶體(load transistor),NMOS電晶體(M1)和(M2)稱為驅動電晶體(driving transistor),NMOS電晶體(M3)和(M4)稱為存取電晶體(access transistor),WL為字元線(word line),而BL及BLB分別為位元線(bit line)及互補位元線(complementary bit line),由於該單埠SRAM晶胞需要6個電晶體,且於讀取邏輯0時,為了避免讀取操作初始瞬間(initial instant)另一驅動電晶體導通,節點A之讀取初始瞬間電壓(VAR)必須滿足方程式(1):VAR=VDD×(RM1)/(RM1+RM3)<VTM2 (1)以防止讀取時之半選定晶胞干擾(half-selected cell disturbance),其中,VAR表示節點A之讀取初始瞬間電壓,RM1與RM3分別表示該NMOS電晶體(M1)與該NMOS電晶體(M3)之導通電阻,而VDD與VTM2分別表示電源供應電壓與該NMOS電晶體(M2)之臨界電壓,此導致驅動電晶體與存取電晶體之間的電流驅動能力比(即單元比率,cell ratio)通常設定在2.2至3.5之間(請參考98年10月20日第US76060B2號專利說明書第2欄第8-10行)。 Figure 1b is a schematic circuit diagram of a 6T port static random access memory (SRAM) cell. Among them, the PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL BLB and BLB are bit line and complementary bit line, respectively. Since this port SRAM cell requires 6 transistors, and to read the logic 0, in order to avoid the initial instant of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V AR ) read by node A must satisfy equation (1): V AR = V DD × (R M1 ) / (R M1 + R M3 ) <V TM2 (1) to prevent half-selected cell disturbance during reading, where V AR represents the initial instantaneous voltage of node A and R M1 and R M3 respectively represent the NMOS transistor (M1 ) And the on-resistance of the NMOS transistor (M3), and V DD and V TM2 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), which leads to driving the transistor The current drive capability ratio (ie, the cell ratio) between the body and the access transistor is usually set between 2.2 and 3.5 (please refer to US Patent No. US76060B2 of October 20, 1998, column 2 columns 8-10 Row).
第1b圖所示6T單埠靜態隨機存取記憶體晶胞於寫入操作時之HSPICE暫態分析模擬結果,如第2圖所示,其係使用TSMC 90奈米CMOS製程參數加以模擬。 Figure 1b shows the simulation results of HSPICE transient analysis during the write operation of the 6T-port static random access memory cell. As shown in Figure 2, it is simulated using TSMC 90nm CMOS process parameters.
用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T單埠靜態隨機存取記憶體晶胞之電路示意圖,與第1b圖之6T單埠靜態隨機存取記憶體晶胞相比,此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶體 晶胞少一個電晶體及少一條位元線,惟該5T單埠靜態隨機存取記憶體晶胞在不變更PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3的通道寬長比的情況下存在寫入邏輯1相當困難之問題。茲考慮記憶體晶胞左側節點A原本儲存邏輯0的情況,由於節點A之電荷僅單獨自位元線(BL)傳送,因此在將節點A中先前寫入的邏輯0蓋寫成邏輯1之寫入初始瞬間電壓(VAW)等於方程式(2):VAW=VDD×(RM1)/(RM1+RM3) (2)其中,VAW表示節點A之寫入初始瞬間電壓,RM1與RM3分別表示NMOS電晶體(M1)與NMOS電晶體(M3)之導通電阻,比較方程式(1)與方程式(2)可知,寫入初始瞬間電壓(VAW)小於NMOS電晶體(M2)之臨界電壓(VTM2),因而無法完成寫入邏輯1之操作。第3圖所示5T靜態隨機存取記憶體晶胞,於寫入操作時之HSPICE暫態分析模擬結果,如第4圖所示,其係使用TSMC 90奈米CMOS製程參數加以模擬,由該模擬結果可証實,具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a circuit diagram of a 5T SRAM cell with a single bit line. Compared with the 6T SRAM cell in Figure 1b, this 5T static The RAM cell has one transistor and one bit line less than the 6T SRAM cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2. And in the case of the channel width-to-length ratio of the NMOS transistors M1, M2, and M3, there is a problem that it is quite difficult to write a logic 1. Consider the case where node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL), the logic 0 previously written in node A is overwritten by the logic 1 The initial instantaneous voltage (V AW ) is equal to equation (2): V AW = V DD × (R M1 ) / (R M1 + R M3 ) (2) where V AW represents the initial instantaneous voltage of node A, R M1 and R M3 represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), respectively. Comparing equation (1) and equation (2), it can be seen that the initial instantaneous voltage (V AW ) is less than the NMOS transistor (M2) ) Threshold voltage (V TM2 ), so the operation of writing logic 1 cannot be completed. The simulation results of HSPICE transient analysis during the write operation of the 5T SRAM cell shown in Figure 3, as shown in Figure 4, are simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T SRAM cell with a single bit line has the problem of writing logic 1 quite difficult.
接下來討論靜態隨機存取記憶體(SRAM)之單埠及雙埠架構,第1b圖之6T靜態隨機存取記憶體(SRAM)晶胞即是單埠靜態隨機存取記憶體(SRAM)晶胞之一例,其係使用兩條位元線BL及BLB做讀寫的動作,也就是讀與寫均是經由同樣的一對位元線來達成,是以在同一時間內只能進行讀或寫的動作,因此,當欲設計具有同時讀寫能力之雙埠靜態隨機存取記憶體時,便需要多加入兩顆存取電晶體以及另一對位元線(請參考第5圖所示電路,其中WBL及WBLB為寫入用位元線對、RBL及RBLB為讀取用位元線對、WWL為寫入用字元線、RWL為讀取用字元線),這使得記憶體 晶胞的面積大大地增加,如果我們能夠簡化記憶體晶胞的架構,使得一條位元線負責讀取的動作,而另一條位元線負責寫入的動作,則在設計雙埠靜態隨機存取記憶體時,記憶體晶胞便不需要多加入兩顆電晶體及一對位元線,這樣記憶體晶胞的面積便會減小許多,傳統的雙埠靜態隨機存取記憶體晶胞之所以不採用這種方法,是因為如前所述存在寫入邏輯1相當困難之問題。 Next, we discuss the SRAM and dual-port architecture. The 6T SRAM cell in Figure 1b is the SRAM static-access memory (SRAM) crystal. For example, it uses two bit lines BL and BLB for reading and writing, that is, reading and writing are achieved through the same pair of bit lines, so that only reading or writing can be performed at the same time. Write operation, therefore, when you want to design dual-port static random access memory with simultaneous read and write capabilities, you need to add two more access transistors and another pair of bit lines (refer to Figure 5) Circuit, where WBL and WBLB are bit line pairs for writing, RBL and RBLB are bit line pairs for reading, WWL is a word line for writing, and RWL is a word line for reading), which makes the memory The area of the cell is greatly increased. If we can simplify the structure of the memory cell, so that one bit line is responsible for reading and the other bit line is responsible for writing. When taking the memory, the memory cell does not need to add two more transistors and a pair of bit lines, so the area of the memory cell will be much reduced. The traditional dual-port static random access memory cell The reason why this method is not adopted is that it is quite difficult to write a logic 1 as described above.
迄今,有許多具單一位元線之雙埠靜態隨機存取記憶體晶胞之技術被提出,例如專利文獻1(105年7月11日第TWI541802號)所提出之「7T雙埠靜態隨機存取記憶體(一)」、專利文獻2(105年5月10日第US9336863B2號)所提出之「Dual write wordline memory cell」、專利文獻3(105年3月1日第US 9275724B2號)所提出之「Method of writing to and reading data from a three-dimensional two port register file」、專利文獻4(103年6月11日第TWI441178號)所提出之「雙埠靜態隨機存取記憶體」、專利文獻5(103年5月27日第US8737117B2號)所提出之「System and method to read a memory cell with a complementary metal-oxide-semiconductor(CMOS)read transistor」、專利文獻6(103年5月6日第US8717807B2號)所提出之「Independently-controlled-gate SRAM」、專利文獻7(103年4月1日第TWI433152號)所提出之「7T雙埠SRAM」、專利文獻8(103年2月1日第TWI425509號)所提出之「具放電路徑之雙埠靜態隨機存取記憶體」、專利文獻9(103年1月11日第TWI423257號)所提出之「寫入操作時降低電源電壓之雙埠SRAM」、專利文獻10(103年1月11日第TWI423258號)所提出之「寫入操作時提高寫入用字元線電壓位準之雙埠靜態隨機存取記憶體」,該 等專利雖可有效解決寫入邏輯1困難之問題,惟由於該等專利均未考慮到製程20奈米以下操作電壓將降為1伏特以下時所造成寫入速度與讀取速度降低之問題,因此仍有改進空間。 To date, many technologies for dual-port static random access memory cells with a single bit line have been proposed, such as the "7T dual-port static random access memory" proposed in Patent Document 1 (TWI541802 on July 11, 105). "Access Memory (1)", "Dual write wordline memory cell" proposed in Patent Document 2 (US9336863B2, May 10, 105), and Patent Document 3 (US 9275724B2, March 1, 105) "Method of writing to and reading data from a three-dimensional two port register file", "Dual-Port Static Random Access Memory" proposed by Patent Document 4 (June 11, 103, TWI441178), Patent Document No. 5 (US8737117B2, May 27, 103), "System and method to read a memory cell with a complementary metal-oxide-semiconductor (CMOS) read transistor", Patent Document 6 (No. 6, May 103, US8717807B2) "Independently-controlled-gate SRAM", Patent Document 7 (April 1, 103, TWI433152), "7T Dual-Port SRAM", Patent Document 8 (February 1, 103 TWI425509) proposed `` dual port with discharge path State random access memory ", Patent Document 9 (TWI423257 of January 11, 103)," Dual-port SRAM with reduced power supply voltage during write operation ", Patent Document 10 (No. 11 of January 103, 103 TWI423258) proposed "Dual-port static random access memory to increase the voltage level of the word line for writing during a write operation", which Although other patents can effectively solve the problem of writing logic 1, these patents do not take into account the problem of lowering the writing speed and reading speed caused by the operating voltage of the process below 20 nanometers will be reduced to less than 1 volt. So there is still room for improvement.
有鑑於此,本發明之主要目的係提出一種具高寫入速度之7T雙埠靜態隨機存取記憶體,其能藉由控制電路與高電壓位準控制電路之雙重機制以有效提高讀取速度。 In view of this, the main object of the present invention is to propose a 7T dual-port static random access memory with high writing speed, which can effectively improve the reading speed by the dual mechanism of the control circuit and the high voltage level control circuit. .
本發明之次要目的係提出一種具高寫入速度之7T雙埠靜態隨機存取記憶體,其能藉由將位元線電壓位準拉高至高於電源供應電壓之寫入驅動電路,以有效防止寫入邏輯1困難之同時,亦能有效提高寫入速度。 A secondary object of the present invention is to provide a 7T dual-port static random access memory with high write speed, which can write the drive circuit to drive the bit line voltage level higher than the power supply voltage to While effectively preventing write logic 1 from being difficult, it can also effectively improve write speed.
本發明之再一目的係提出一種具高寫入速度之7T雙埠靜態隨機存取記憶體,其能藉由二階段的讀取控制以於提高讀取速度的同時,亦能避免無謂的功率耗損。 Another object of the present invention is to provide a 7T dual-port static random access memory with high write speed, which can improve the read speed by using two-stage read control while avoiding unnecessary power. Attrition.
本發明提出一種具高寫入速度之7T雙埠靜態隨機存取記憶體,其主要包括一記憶體陣列(1)、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)、複數個高電壓位準控制電路(5)以及複數個寫入驅動電路(6),該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成,每一列記憶體晶胞設置一個控制電路(2)以及一個高電壓位準控制電路(5),且每一行記憶體晶胞設置一個預充電電路(3)以及一個寫入驅動電路(6)。藉此,於寫入模式時,可藉由該複數個控制電路(2)以及該複數個寫入驅動電路(6)以有效防止寫入邏輯1困難之同時,亦提高寫入邏輯1之速度,於讀取模式時,可藉由該複數個控制電路(2) 以及該複數個高電壓位準控制電路(5)以於提高讀取速度的同時,亦避免無謂的功率耗損,於待機模式時,可藉由該複數個控制電路(2)以有效降低漏電流,且可藉由該待機啟動電路(4)的設計,以有效促使靜態隨機存取記憶體快速進入待機模式。 The invention proposes a 7T dual-port static random access memory with high writing speed, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby A start circuit (4), a plurality of high voltage level control circuits (5), and a plurality of write drive circuits (6), the memory array is composed of a plurality of rows of memory cell units and a plurality of rows of memory unit cells, Each column of memory cells is provided with a control circuit (2) and a high-voltage level control circuit (5), and each row of memory cells is provided with a precharge circuit (3) and a write drive circuit (6). Therefore, in the write mode, the plurality of control circuits (2) and the plurality of write driving circuits (6) can be used to effectively prevent the difficulty of writing the logic 1 while increasing the speed of writing the logic 1 In the reading mode, the plurality of control circuits can be used (2) And the plurality of high voltage level control circuits (5) are used to improve the reading speed and avoid unnecessary power consumption. In the standby mode, the plurality of control circuits (2) can be used to effectively reduce the leakage current. The design of the standby start circuit (4) can effectively promote the static random access memory to quickly enter the standby mode.
1‧‧‧SRAM晶胞 1‧‧‧SRAM cell
2‧‧‧控制電路 2‧‧‧Control circuit
3‧‧‧預充電電路 3‧‧‧ pre-charge circuit
4‧‧‧待機啟動電路 4‧‧‧ Standby start circuit
5‧‧‧高電壓位準控制電路 5‧‧‧high voltage level control circuit
6‧‧‧寫入驅動電路 6‧‧‧write drive circuit
P11‧‧‧第一PMOS電晶體 P11‧‧‧The first PMOS transistor
P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS transistor
M11‧‧‧第一NMOS電晶體 M11‧‧‧The first NMOS transistor
M12‧‧‧第二NMOS電晶體 M12‧‧‧Second NMOS transistor
M13‧‧‧第三NMOS電晶體 M13‧‧‧Third NMOS transistor
A‧‧‧儲存節點 A‧‧‧Storage Node
B‧‧‧反相儲存節點 B‧‧‧ Inverted Storage Node
C‧‧‧節點 C‧‧‧node
M14‧‧‧第一讀取用電晶體 M14‧‧‧First reading transistor
M15‧‧‧第二讀取用電晶體 M15‧‧‧Second reading transistor
WBL‧‧‧寫入用位元線 WBL‧‧‧Bit line for writing
WWL‧‧‧寫入用字元線 WWL‧‧‧writing character line
RBL‧‧‧讀取用位元線 RBL‧‧‧Bit line for reading
RWL‧‧‧讀取用字元線 RWL‧‧‧Read Character Line
S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal
/S‧‧‧反相待機模式控制信號 / S ‧‧‧ Inverted standby mode control signal
VL1‧‧‧第一低電壓節點 VL1‧‧‧The first low voltage node
VL2‧‧‧第二低電壓節點 VL2‧‧‧Second Low Voltage Node
M21‧‧‧第四NMOS電晶體 M21‧‧‧Fourth NMOS transistor
M22‧‧‧第五NMOS電晶體 M22‧‧‧Fifth NMOS transistor
M23‧‧‧第六NMOS電晶體 M23‧‧‧sixth NMOS transistor
M24‧‧‧第七NMOS電晶體 M24‧‧‧Seventh NMOS transistor
M25‧‧‧第八NMOS電晶體 M25‧‧‧eighth NMOS transistor
M26‧‧‧第九NMOS電晶體 M26‧‧‧Ninth NMOS transistor
M27‧‧‧第十NMOS電晶體 M27‧‧‧Tenth NMOS Transistor
P21‧‧‧第三PMOS電晶體 P21‧‧‧The third PMOS transistor
RC‧‧‧讀取控制信號 RC‧‧‧Read control signal
RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage
INV‧‧‧第三反相器 INV‧‧‧Third Inverter
D1‧‧‧第一延遲電路 D1‧‧‧first delay circuit
P31‧‧‧第四PMOS電晶體 P31‧‧‧Fourth PMOS transistor
P‧‧‧預充電信號 P‧‧‧Pre-charge signal
M41‧‧‧第十一NMOS電晶體 M41‧‧‧11th NMOS transistor
P41‧‧‧第五PMOS電晶體 P41‧‧‧Fifth PMOS transistor
D2‧‧‧第二延遲電路 D2‧‧‧Second Delay Circuit
VDD‧‧‧電源供應電壓 V DD ‧‧‧ Power supply voltage
VDDH1‧‧‧第一高電源供應電壓 V DDH1 ‧‧‧ Highest power supply voltage
VDDH2‧‧‧第二高電源供應電壓 V DDH2 ‧‧‧ the second highest power supply voltage
P51‧‧‧第六PMOS電晶體 P51‧‧‧Sixth PMOS transistor
P52‧‧‧第七PMOS電晶體 P52‧‧‧The seventh PMOS transistor
I53‧‧‧第四反相器 I53‧‧‧Fourth inverter
VH‧‧‧高電壓節點 VH‧‧‧High Voltage Node
P61‧‧‧第八PMOS電晶體 P61‧‧‧eighth PMOS transistor
P62‧‧‧第九PMOS電晶體 P62‧‧‧9th PMOS transistor
P63‧‧‧第十PMOS電晶體 P63‧‧‧Tenth PMOS transistor
P64‧‧‧第十一PMOS電晶體 P64‧‧‧11th PMOS transistor
M61‧‧‧第十二NMOS電晶體 M61‧‧‧Twelfth NMOS Transistor
M62‧‧‧第十三NMOS電晶體 M62‧‧‧Thirteenth NMOS Transistor
I63‧‧‧第五反相器 I63‧‧‧Fifth inverter
Din‧‧‧輸入資料 Din‧‧‧Enter data
WC‧‧‧寫入控制信號 WC‧‧‧ write control signal
BLB1 …BLBm‧‧‧互補位元線 BLB 1 … BLB m ‧‧‧ complementary bit line
BLB‧‧‧互補位元線 BLB‧‧‧ Complementary Bit Line
MB1 …MBk‧‧‧記憶體區塊 MB 1 … MB k ‧‧‧Memory block
WL1 …WLn‧‧‧字元線 WL 1 … WL n ‧‧‧Character line
BL1 …BLm‧‧‧位元線 BL 1 … BL m ‧‧‧bit line
M1…M4‧‧‧NMOS電晶體 M1 … M4‧‧‧NMOS transistor
P1…P2‧‧‧PMOS電晶體 P1 … P2‧‧‧PMOS transistor
I1、I2、I3、I4‧‧‧漏電流 I 1 , I 2 , I 3 , I 4 ‧‧‧ Leakage current
第1a圖 係顯示習知之靜態隨機存取記憶體;第1b圖 係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖;第2圖 係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖;第3圖 係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖;第4圖 係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖;第5圖 係顯示習知8T雙埠靜態隨機存取記憶體晶胞之電路示意圖;第6圖 係顯示本發明較佳實施例所提出之電路示意圖;第7圖 係顯示第6圖之本發明較佳實施例於寫入邏輯1期間之簡化電路圖;第8圖 係顯示第6圖之本發明較佳實施例之寫入動作時序圖;第9圖 係顯示第6圖之本發明較佳實施例於讀取期間之簡化電路圖;第10圖 係顯示第6圖之本發明較佳實施例於待機期間之簡化電路圖。 Figure 1a shows a conventional static random access memory cell; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; Figure 2 shows a conventional 6T static random access memory cell Figure 3 is a timing diagram of a conventional 5T SRAM cell; Figure 4 is a timing diagram of a conventional 5T SRAM cell; FIG. 5 is a circuit diagram showing a conventional 8T dual-port static random access memory cell; FIG. 6 is a circuit diagram showing a circuit proposed by a preferred embodiment of the present invention; FIG. 7 is a diagram showing the present invention of FIG. 6 A simplified circuit diagram of the preferred embodiment during a write logic 1; FIG. 8 is a timing diagram of the write operation of the preferred embodiment of the present invention in FIG. 6; FIG. 9 is a preferred implementation of the present invention in FIG. 6 Example is a simplified circuit diagram during reading; Figure 10 is a simplified circuit diagram of the preferred embodiment of the present invention shown in Figure 6 during standby.
根據上述之主要目的,本發明提出一種具高寫入速度之7T雙埠靜態隨機存取記憶體,其主要包括一記憶體陣列,該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成,每一列記憶體晶胞與每一行記憶體晶胞均包括有複數個記憶體晶胞(1);複數個控制電路(2), 每一列記憶體晶胞設置一個控制電路(2);複數個預充電電路(3),每一行記憶體晶胞設置一個預充電電路(3);一待機啟動電路(4),該待機啟動電路(4)係促使雙埠SRAM快速進入待機模式,以有效提高雙埠SRAM之待機效能;複數個高電壓位準控制電路(5),每一列記憶體晶胞設置一個高電壓位準控制電路(5),以在於讀取邏輯0時進一步提高讀取速度;以及複數個寫入驅動電路(6),每一行記憶體晶胞設置一個寫入驅動電路(6)。 According to the above-mentioned main purpose, the present invention provides a 7T dual-port static random access memory with high write speed, which mainly includes a memory array. The memory array is composed of a plurality of memory cells and a plurality of rows. The body unit cell is composed of a plurality of memory unit cells in each column and a plurality of memory unit cells (1); a plurality of control circuits (2), Each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory cells is provided with a precharge circuit (3); a standby start circuit (4), the standby start circuit (4) It promotes the dual-port SRAM to quickly enter the standby mode to effectively improve the standby performance of the dual-port SRAM; a plurality of high-voltage level control circuits (5), each column of memory cells is provided with a high-voltage level control circuit ( 5), so as to further improve the reading speed when reading logic 0; and a plurality of write driving circuits (6), one write driving circuit (6) is provided for each row of memory cells.
為了便於說明起見,第6圖所示之7T靜態隨機存取記憶體僅以一個記憶體晶胞(1)、一條寫入用字元線(WWL)、一條寫入用位元線(WBL)、一條讀取用字元線(RWL)、一條讀取用位元線(RBL)、一控制電路(2)、一預充電電路(3)、一待機啟動電路(4)、一高電壓位準控制電路(5)以及一寫入驅動電路(6)做為實施例來說明。該記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體M11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體M12所組成)、一第三NMOS電晶體(M13)、一第一讀取用電晶體(M14)以及一第二讀取用電晶體(M15),其中,該第一反相器及該第二反相器係呈交互耦合連接,亦即該第一反相器之輸出(即節點A)係連接該第二反相器之輸入,而該第二反相器之輸出(即節點B)則連接該第一反相器之輸入,並且該第一反相器之輸出(節點A)係用於儲存SRAM晶胞之資料,而該第二反相器之輸出(節點B)則用於儲存SRAM晶胞之反相資料。 For ease of explanation, the 7T SRAM shown in Figure 6 consists of only one memory cell (1), one writing word line (WWL), and one writing bit line (WBL). ), A read word line (RWL), a read bit line (RBL), a control circuit (2), a precharge circuit (3), a standby start circuit (4), a high voltage The level control circuit (5) and a write driving circuit (6) are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) Crystal P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first reading transistor (M14), and a second reading transistor (M15), among which, The first inverter and the second inverter are connected by mutual coupling, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second inverter The output of the phase inverter (node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the second inverter The output (node B) is used to store the inverted data of the SRAM cell.
該記憶體晶胞(1)之該第一反相器(由該第一PMOS電晶體P11與該第一NMOS電晶體M11所組成)係連接在一電源供應電壓(VDD)與一第一低電壓節點(VL1)之間,該第二反相器(由該第二PMOS電晶體 P12與該第二NMOS電晶體M12所組成)係連接在一高電壓節點(VH)與一第二低電壓節點(VL2)之間,該第一讀取用電晶體(M14)之源極、閘極與汲極係分別連接至該第二讀取用電晶體(M15)之汲極、該讀取用字元線(RWL)與該讀取用位元線(RBL),而該第二讀取用電晶體(M15)之源極、閘極與汲極則分別連接至該第二低電壓節點(VL2)、該第二反相器之輸出(即節點B)與該第一讀取用電晶體(M14)之源極。 The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11) of the memory cell (1) is connected to a power supply voltage (V DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected between a high voltage node (VH) and a second low Between the voltage node (VL2), the source, gate and drain of the first reading transistor (M14) are connected to the drain and reading of the second reading transistor (M15), respectively. A word line (RWL) and the read bit line (RBL) are used, and a source, a gate, and a drain of the second read transistor (M15) are respectively connected to the second low-voltage node (VL2), the output of the second inverter (ie, node B) and the source of the first reading transistor (M14).
請再參考第6圖,該控制電路(2)係由一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第三PMOS電晶體(P21)、一讀取控制信號(RC)、一第三反相器(INV)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一寫入控制信號(WC)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)所組成。該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與該第二低電壓節點(VL2);該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該待機模式控制信號(S)與該第二低電壓節點(VL2);該第六NMOS電晶體(M23)之源極係連接至接地電壓,而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1);該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第二低電壓節點(VL2);該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出 與該第七NMOS電晶體(M24)之源極;該第一延遲電路(D1)係連接在該第三反相器(INV)之輸出與該第八NMOS電晶體(M25)之該閘極之間;該第三反相器(INV)之輸入係供接收該讀取控制信號(RC),而輸出則連接至該第一延遲電路(D1)之輸入;該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至接地電壓、該第十NMOS電晶體(M27)之汲極與該第一低電壓節點(VL1);該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至該接地電壓、該寫入控制信號(WC)與該第九NMOS電晶體(M26)之閘極;而該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該反相待機模式控制信號(/S)、該寫入控制信號(WC)與該第十NMOS電晶體(M27)之汲極。其中,該反相待機模式控制信號(/S)係由該待機模式控制信號(S)經一反相器而獲得。 Please refer to FIG. 6 again. The control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control signal (S), and An inverting standby mode control signal (/ S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverting standby mode control signal (/ S) and the second low voltage node (VL2); the fifth The source, gate, and drain of the NMOS transistor (M22) are connected to the first low-voltage node (VL1), the standby mode control signal (S), and the second low-voltage node (VL2); the first The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate, and drain are connected to the drain, the read control signal (RC), and the second low voltage node (VL2) of the eighth NMOS transistor (M25); the eighth NMOS transistor (M25) ) 'S source, gate, and drain are connected to the accelerated read voltage (RGND) and the output of the first delay circuit (D1), respectively. And the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25) Between; the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth NMOS transistor (M26 ) 'S source, gate, and drain are connected to the ground voltage, the drain of the tenth NMOS transistor (M27), and the first low-voltage node (VL1); the tenth NMOS transistor (M27), The source, gate, and drain are connected to the gate of the ground voltage, the write control signal (WC), and the ninth NMOS transistor (M26), respectively; and the source of the third PMOS transistor (P21) The gate, the gate, and the drain are connected to the drain of the inverted standby mode control signal (/ S), the write control signal (WC), and the tenth NMOS transistor (M27), respectively. The inverting standby mode control signal (/ S) is obtained by the inverting standby mode control signal (S) through an inverter.
在此值得注意的是,該第三PMOS電晶體(P21)之汲極、該第十NMOS電晶體(M27)之汲極及該第九NMOS電晶體(M26)之閘極係連接在一起並形成一節點(C),當該寫入控制信號(WC)為邏輯低位準時,該節點(C)之電壓位準係為該反相待機模式控制信號(/S)之邏輯電壓位準,而當該寫入控制信號(WC)為邏輯高位準時,該節點(C)之電壓位準係為該接地電壓,藉此以穩定地完成寫入操作(由於寫入操作期間該節點C之電壓位準恆為該接地電壓)。 It is worth noting here that the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together and A node (C) is formed. When the write control signal (WC) is at a logic low level, the voltage level of the node (C) is the logic voltage level of the inverted standby mode control signal (/ S), and When the write control signal (WC) is at a logic high level, the voltage level of the node (C) is the ground voltage, thereby stably completing the write operation (due to the voltage level of the node C during the write operation) Quasi-constant is the ground voltage).
該控制電路(2)係設計成可因應不同操作模式而控制該第一低電壓節點(VL1)與該第二低電壓節點(VL2)之電壓位準,於寫入模式時,將選定晶胞中較接近該寫入用位元線(WBL)之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓(即該第一低電壓節點VL1)設定成較 接地電壓為高之一預定電壓(即該第六NMOS電晶體(M23)之閘源極電壓VGS(M23))且將選定晶胞中另一驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成接地電壓,以便防止寫入邏輯1困難之問題。 The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes. In the write mode, the unit cell is selected. The source voltage (that is, the first low-voltage node VL1) of the driving transistor (that is, the first NMOS transistor M11) that is closer to the bit line (WBL) for writing is set to be one higher than the ground voltage The predetermined voltage (i.e., the gate-source voltage V GS (M23) of the sixth NMOS transistor (M23)) and the source voltage of another driving transistor (i.e., the second NMOS transistor M12) in the selected cell ( That is, the second low voltage node VL2) is set to a ground voltage in order to prevent the problem of writing logic 1 from being difficult.
於讀取模式之第一階段時,將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成呈較接地電壓為低之電壓,該較接地電壓為低之該第二低電壓節點VL2可有效提高讀取速度,而於讀取模式之第二階段時,將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓設定回接地電壓,以便減少無謂的功率消耗,其中該讀取模式之該第二階段與該第一階段相隔之時間,係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算,並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間,其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。 In the first stage of the read mode, the source voltage (that is, the second lowest value) of the driving transistor (that is, the second NMOS transistor M12) that is closer to the read bit line (RBL) in the selected cell is selected. The voltage node VL2) is set to a voltage lower than the ground voltage. The second low-voltage node VL2, which is lower than the ground voltage, can effectively improve the reading speed. During the second stage of the reading mode, the crystal is selected. The source voltage of the driving transistor (ie, the second NMOS transistor M12) that is closer to the bit line (RBL) for reading in the cell is set back to the ground voltage in order to reduce unnecessary power consumption. The time interval between the second stage and the first stage is equal to that when the read control signal (RC) changes from a logic low level to a logic high level, and the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off. The time up to the eighth NMOS transistor (M25) can be adjusted by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1).
於待機模式時,將所有記憶體晶胞中之驅動電晶體的源極電壓設定成較接地電壓為高之該預定電壓,以便降低漏電流;而於保持模式時則將記憶體晶胞中之驅動電晶體的源極電壓設定成接地電壓,以便維持原來之保持特性,其詳細工作電壓位準如下述表1所示。 In the standby mode, the source voltages of the driving transistors in all memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current; while in the hold mode, the voltages in the memory cells are set to The source voltage of the driving transistor is set to the ground voltage in order to maintain the original holding characteristics. The detailed operating voltage levels are shown in Table 1 below.
表1中之該寫入控制信號(WC)係為一寫入信號(W)與該字元線(WL)信號的及閘(AND gate)運算結果,此時僅於該寫入信號(W)信號與該字元線(WL)信號均為邏輯高位準時,該寫入控制信號(WC)方為邏輯高位準;該讀取控制信號(RC)為一讀取致能(Read Enable,簡稱RE)信號與對應之讀取用字元線(RWL)信號的及閘運算結果。在此值得注意的是,對於非選定字元線及非選定位元線係設定為浮接(floating)狀態,而對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準,以防止該第七NMOS電晶體(M24)之漏電流。 The write control signal (WC) in Table 1 is an AND gate operation result of a write signal (W) and the word line (WL) signal. At this time, only the write signal (W ) Signal and the word line (WL) signal are at a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is a read enable (Read Enable for short) RE) signal and the corresponding result of the word line (RWL) signal for reading. It is worth noting here that, for non-selected word lines and non-selected positioning element lines, the floating state is set, and the read control signal (RC) during the non-read mode is set to the acceleration. The level of the voltage (RGND) is read to prevent the leakage current of the seventh NMOS transistor (M24).
請參考第6圖,該預充電電路(3)係由一第四PMOS電晶體(P31)以及一預充電信號(P)所組成,該第四PMOS電晶體(P31)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該預充電信號(P)與相對應之讀取用位元線(RBL),以便於預充電期間,藉由邏輯低位準之該預充電信號(P),以將相對應之讀取用位元線(RBL)預充電至該電源供應電壓(VDD)之位準。 Please refer to Fig. 6. The precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P). The source and gate of the fourth PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V DD ), the precharge signal (P) and the corresponding read bit line (RBL), in order to facilitate the precharge period, The precharge signal (P) is used to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V DD ).
請再參考第6圖,該待機啟動電路(4)係由一第五PMOS電晶體(P41)、一第十一NMOS電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成。該第五PMOS電晶體(P41)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十一NMOS電晶體(M41)之汲極;該第十一NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第五PMOS電晶體(P41)之汲極;該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S),而該第二延遲電路(D2)之輸出則連接至該第十一NMOS電晶體(M41)之閘極。 Please refer to FIG. 6 again, the standby start circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2), and the inverting standby Mode control signal (/ S). The source, gate, and drain of the fifth PMOS transistor (P41) are connected to the power supply voltage (V DD ), the inverting standby mode control signal (/ S), and the eleventh NMOS transistor. The drain of (M41); the source, gate and drain of the eleventh NMOS transistor (M41) are connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) respectively And the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) is Connected to the gate of the eleventh NMOS transistor (M41).
請再參考第6圖,該高電壓位準控制電路(5)係由一第六PMOS電晶體(P51)、一第七PMOS電晶體(P52)、一第四反相器(I53)、該讀取控制信號(RC)以及一第一高電源供應電壓(VDDH1)所組成,其中該第六PMOS電晶體(P51)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該讀取控制信號(RC)與該高電壓節點(VH),該第七PMOS電晶體(P52)之源極、閘極與汲極係分別連接至該第一高電源供應電壓(VDDH1)、該第四反相器(I53)之輸出與該高電壓節點(VH),而該第四反相器(I53)之輸入係供接收該讀取控制信號(RC),而輸出則連接至該第七PMOS電晶體(P52)之閘極。在此值得注意的是,該第一反相器係連接在該電源供應電壓(VDD)與該第一低電壓節點(VL1)之間,而該第二反相器則連接在該高電壓節點(VH)與該第二低電壓節點(VL2)之間。 Please refer to FIG. 6 again, the high voltage level control circuit (5) is composed of a sixth PMOS transistor (P51), a seventh PMOS transistor (P52), a fourth inverter (I53), the The read control signal (RC) and a first high power supply voltage (V DDH1 ). The source, gate and drain of the sixth PMOS transistor (P51) are connected to the power supply voltage ( V DD ), the read control signal (RC) and the high voltage node (VH), the source, gate and drain of the seventh PMOS transistor (P52) are connected to the first high power supply voltage, respectively. (V DDH1 ), the output of the fourth inverter (I53) and the high voltage node (VH), and the input of the fourth inverter (I53) is for receiving the read control signal (RC), and The output is connected to the gate of the seventh PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).
請再參考第6圖,該寫入驅動電路(6)係由一第八PMOS電晶體(P61)、一第九PMOS電晶體(P62)、一第十PMOS電晶體(P63)、 一第十一PMOS電晶體(P64)、一第十二NMOS電晶體(M61)、一第十三NMOS電晶體(M62)、一第五反相器(I63)、一輸入資料(Din)以及一第二高電源供應電壓(VDDH2)所組成,其中該第八PMOS電晶體(P61)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(VDDH2)、該輸入資料(Din)與該第十二NMOS電晶體(M61)之汲極,該第九PMOS電晶體(P62)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(VDDH2)、該第十三NMOS電晶體(M62)之汲極與該第十二NMOS電晶體(M61)之汲極,該第十PMOS電晶體(P63)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(VDDH2)、該第十二NMOS電晶體(M61)之汲極與該第十三NMOS電晶體(M62)之汲極,該第十一PMOS電晶體(P64)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(VDDH2)、該第五反相器(I63)之輸出與該第十三NMOS電晶體(M62)之汲極,該第十二NMOS電晶體(M61)之源極、閘極與汲極係分別連接至該接地電壓、該輸入資料(Din)與該第八PMOS電晶體(P61)之汲極,該第十三NMOS電晶體(M62)之源極、閘極與汲極係分別連接至該接地電壓、該第五反相器(I63)之輸出與該第十一PMOS電晶體(P64)之汲極,而該第五反相器(I63)之輸入係供接收該輸入資料(Din),而該輸出則連接至該第十一PMOS電晶體(P64)之閘極以及該第十三NMOS電晶體(M62)之閘極,其中,該第十PMOS電晶體(P63)之汲極、該第十一PMOS電晶體(P64)之汲極與該第十三NMOS電晶體(M62)之汲極係共同連接至該寫入用位元線(WBL),該寫入用位元線(WBL)於寫入邏輯0時係為該接地電壓之位準,而於寫入邏輯1時則為該第二高電源供應電壓(VDDH2)之位準。在此值得注意的是,該第二 高電源供應電壓(VDDH2)之電壓位準係設計成高於該電源供應電壓(VDD)之電壓位準,以加速寫入邏輯1之速度。 Please refer to FIG. 6 again. The write driving circuit (6) is composed of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), a tenth PMOS transistor (P63), and a tenth A PMOS transistor (P64), a twelfth NMOS transistor (M61), a thirteenth NMOS transistor (M62), a fifth inverter (I63), an input data (Din), and a second It consists of a high power supply voltage (V DDH2 ), where the source, gate, and drain of the eighth PMOS transistor (P61) are connected to the second high power supply voltage (V DDH2 ), the input data ( Din) and the drain of the twelfth NMOS transistor (M61), and the source, gate, and drain of the ninth PMOS transistor (P62) are respectively connected to the second high power supply voltage (V DDH2 ) The drain of the thirteenth NMOS transistor (M62) and the drain of the twelfth NMOS transistor (M61), and the source, gate and drain of the tenth PMOS transistor (P63) are connected respectively To the second highest power supply voltage (V DDH2 ), the drain of the twelfth NMOS transistor (M61) and the drain of the thirteenth NMOS transistor (M62), and the eleventh PMOS transistor (P64 ) The source, gate and drain are connected separately The second high power supply voltage (V DDH2), which fifth inverter (I63) and the output of the thirteenth NMOS transistor (the M62) of the drain, the twelfth NMOS transistor (M61) the source of The electrode, gate and drain are connected to the ground voltage, the input data (Din) and the drain of the eighth PMOS transistor (P61), and the source and gate of the thirteenth NMOS transistor (M62). The pole and the drain are respectively connected to the ground voltage, the output of the fifth inverter (I63) and the drain of the eleventh PMOS transistor (P64), and the input of the fifth inverter (I63) Is for receiving the input data (Din), and the output is connected to the gate of the eleventh PMOS transistor (P64) and the gate of the thirteenth NMOS transistor (M62), wherein the tenth PMOS The drain of the transistor (P63), the drain of the eleventh PMOS transistor (P64), and the drain of the thirteenth NMOS transistor (M62) are commonly connected to the write bit line (WBL) The writing bit line (WBL) is the level of the ground voltage when writing logic 0, and the level of the second high power supply voltage (V DDH2 ) when writing logic 1. It is worth noting here that the voltage level of the second high power supply voltage (V DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V DD ) to accelerate the speed of writing to logic one.
茲說明第6圖之本發明較佳實施例的工作原理如下: The working principle of the preferred embodiment of the present invention shown in FIG. 6 is as follows:
(I)寫入模式(write mode) (I) write mode
於寫入操作開始前,該寫入控制信號(WC)為邏輯低位準,使得該第三PMOS電晶體(P21)導通(ON),並使得該第十NMOS電晶體(M27)截止(OFF),於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準,該邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通該第九NMOS電晶體(M26),並使得該第一低電壓節點(VL1)呈接地電壓。 Before the write operation starts, the write control signal (WC) is at a logic low level, so that the third PMOS transistor (P21) is turned on (ON), and the tenth NMOS transistor (M27) is turned off (OFF) Therefore, the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at the logic high level will turn on the ninth NMOS transistor (M26) and make The first low voltage node (VL1) is at a ground voltage.
而於寫入操作期間內,該寫入控制信號(WC)為邏輯高位準,使得該第三PMOS電晶體(P21)截止,該第十NMOS電晶體(M27)導通,並使得該第三PMOS電晶體(P21)之汲極呈邏輯低位準,該邏輯低位準之該第三PMOS電晶體(P21)之汲極會使得該第九NMOS電晶體(M26)截止,並使得該第一低電壓節點(VL1)等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M26),藉此得以有效防止寫入邏輯1困難之問題。第7圖所示為第6圖之本發明較佳實施例於寫入期間之簡化電路圖。 During the write operation period, the write control signal (WC) is at a logic high level, so that the third PMOS transistor (P21) is turned off, the tenth NMOS transistor (M27) is turned on, and the third PMOS transistor is turned on. The drain of the transistor (P21) is at a logic low level. The drain of the third PMOS transistor (P21) at the logic low level will cause the ninth NMOS transistor (M26) to turn off and make the first low voltage The node (VL1) is equal to the gate-source voltage V GS (M26 ) of the sixth NMOS transistor (M23 ) , thereby effectively preventing the problem of writing logic 1 from being difficult. FIG. 7 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during a writing period.
接下來依4種寫入狀態來說明第7圖之本發明較佳實施例如何完成寫入動作。 The following describes how the writing operation of the preferred embodiment of the present invention shown in FIG. 7 is completed according to four writing states.
(一)節點A原本儲存邏輯0,而現在欲寫入邏輯0:在寫入動作發生前(該寫入用字元線WWL為接地電壓),該第一NMOS電晶體(M11)為導通(ON)。因為該第一NMOS電晶體(M11)為ON, 所以當寫入動作開始時,該寫入用字元線(WWL)由Low(接地電壓)轉High(電源供應電壓VDD)。當該寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)(即存取電晶體)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為寫入用位元線(WBL)是接地電壓,所以會將該節點A放電,而完成邏輯0的寫入動作,直到寫入週期結束。 (1) Node A originally stored logic 0, but now wants to write logic 0: before the writing operation occurs (the writing word line WWL is the ground voltage), the first NMOS transistor (M11) is on ( ON). Since the first NMOS transistor (M11) is ON, the writing word line (WWL) changes from Low (ground voltage) to High (power supply voltage V DD ) when a writing operation is started. When the voltage of the writing word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13) (that is, the access transistor), the third NMOS transistor (M13) transitions from OFF. In order to be turned on, the write bit line (WBL) is grounded at this time, so the node A will be discharged, and a logic 0 write operation is completed until the write cycle ends.
(二)節點A原本儲存邏輯0,而現在欲寫入邏輯1:在寫入動作發生前(該寫入用字元線WWL為接地電壓),該第一NMOS電晶體(M11)為導通(ON)。在此值得注意的是,因為該第一NMOS電晶體(M11)為ON,所以當寫入動作開始時,該寫入用字元線(WWL)由Low(接地電壓)轉High(該電源供應電壓VDD),該節點A的電壓會由於寄生電容耦合效應而跟隨該寫入用字元線(WWL)的電壓呈現些微上升。當該寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為該寫入用位元線(WBL)為該第二高電源供應電壓(VDDH2)之電壓位準,並且因為該第一NMOS電晶體(M11)仍為ON且該節點B仍處於電壓位準為接近於該電源供應電壓(VDD)之電壓位準的初始狀態,所以該第一PMOS電晶體(P11)仍為截止(OFF),而該節點A之寫入初始瞬間電壓(VAWI)滿足方程式(3):VAWI=VDDH2×(RM11+RM23)/(RM13+RM11+RM23)>VTM12 (3)其中,VAWI表示節點A之寫入初始瞬間電壓,RM13表示該第三NMOS電晶 體(M13)之導通電阻,RM11表示該第一NMOS電晶體(M11)之導通電阻,RM23表示該第六NMOS電晶體(M23)之導通電阻,而VDDH2與VTM12分別表示該第二高電源供應電壓(VDDH2)與該第二NMOS電晶體(M12)之臨界電壓。由於該第二高電源供應電壓(VDDH2)之電壓位準係設計成高於該電源供應電壓(VDD)之電壓位準,且於該第一低電壓節點(VL1)處提供一等於該第六NMOS電晶體(M23)之閘-源極電壓VGS(M23)之電壓位準,因此可輕易地將節點A之電壓位準設定成比第4圖之習知5T靜態隨機存取記憶體晶胞之該節點A之電壓位準還要高許多。該還要高許多之分壓電壓位準係足以使該第二NMOS電晶體(M12)導通,於是使得節點B放電至一較低電壓位準,該節點B之較低電壓位準會使得該第一NMOS電晶體(M11)之導通等效電阻(RM11)呈現較高的電阻值,該第一NMOS電晶體(M11)之該較高的電阻值會於該節點A獲得較高電壓位準,該節點A之較高電壓位準又會經由該第二反相器(由第二PMOS電晶體P12與第二NMOS電晶體M12所組成),而使得該節點B呈現更低電壓位準,該節點B之更低電壓位準又會經由該第一反相器(由第一PMOS電晶體P11與第一NMOS電晶體M11所組成),而使得該節點A獲得更高電壓位準,依此循環,即可將該節點A充電至該電源供應電壓(VDD),而完成邏輯1的寫入動作。 (2) Node A originally stored logic 0, but now wants to write logic 1: before the writing operation occurs (the writing word line WWL is the ground voltage), the first NMOS transistor (M11) is on ( ON). It is worth noting here that because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line (WWL) changes from Low (ground voltage) to High (the power supply Voltage V DD ), the voltage of the node A will follow the writing word line (WWL) voltage slightly due to the parasitic capacitance coupling effect. When the voltage of the word line for writing (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. Because the write bit line (WBL) is the voltage level of the second high power supply voltage (V DDH2 ), and because the first NMOS transistor (M11) is still ON and the node B is still at voltage The level is the initial state close to the voltage level of the power supply voltage (V DD ), so the first PMOS transistor (P11) is still OFF, and the initial instantaneous voltage (V) written by the node A AWI ) satisfies equation (3): V AWI = V DDH2 × (R M11 + R M23 ) / (R M13 + R M11 + R M23 )> V TM12 (3) where V AWI represents the initial moment of node A's writing Voltage, R M13 represents the on-resistance of the third NMOS transistor (M13), R M11 represents the on-resistance of the first NMOS transistor (M11), R M23 represents the on-resistance of the sixth NMOS transistor (M23), V DDH2 and V TM12 represent the second high power supply voltage (V DDH2 ) and the threshold voltage of the second NMOS transistor (M12), respectively. Because the voltage level of the second high power supply voltage (V DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V DD ), and a voltage equal to the voltage level at the first low voltage node (VL1) is provided. The voltage level of the gate-source voltage V GS (M23) of the sixth NMOS transistor (M23), so the voltage level of the node A can be easily set to be higher than the conventional 5T static random access memory of FIG. 4 The voltage level of the node A of the bulk cell is much higher. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that the node B is discharged to a lower voltage level. The lower voltage level of the node B will make the The on-resistance (R M11 ) of the first NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A Standard, the higher voltage level of the node A will pass through the second inverter (consisting of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level , The lower voltage level of the node B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, According to this cycle, the node A can be charged to the power supply voltage (V DD ), and the writing operation of the logic 1 is completed.
在此值得注意的是,該第一低電壓節點VL1於節點A原本儲存邏輯0,而在寫入邏輯1之期間,係具有等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M23)的電壓位準,而於寫入邏輯1後,又會因經由該第九NMOS電晶體(M26)放電而具有接地電壓之位準。 It is worth noting here that the first low-voltage node VL1 originally stores logic 0 at node A, and during the writing of logic 1, it has a gate-source voltage V GS equal to the sixth NMOS transistor (M23). (M23) , and after the logic 1 is written, it will have a ground voltage level due to discharge through the ninth NMOS transistor (M26).
(三)節點A原本儲存邏輯1,而現在欲寫入邏輯1:在寫入動作發生前(該寫入用字元線WWL為接地電壓),該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線(WWL)由Low(接地電壓)轉High(該電源供應電壓VDD),由於該節點A為該電源供應電壓(VDD)之電壓位準,且該寫入用位元線(WBL)為該第二高電源供應電壓(VDDH2)之電壓位準,因此會使該第三NMOS電晶體(M13)繼續保持截止(OFF)狀態;此時因為該第一PMOS電晶體(P11)仍為ON,所以該節點A的電壓會維持於該電源供應電壓(VDD)之電壓位準,直到寫入週期結束。 (Three) node A originally stores logic 1, but now wants to write logic 1: before the writing operation occurs (the writing word line WWL is the ground voltage), the first PMOS transistor (P11) is on ( ON). When the writing word line (WWL) changes from Low (ground voltage) to High (the power supply voltage V DD ), since the node A is the voltage level of the power supply voltage (V DD ), and the write The bit line (WBL) is used as the voltage level of the second high power supply voltage (V DDH2 ), so the third NMOS transistor (M13) will remain in the OFF state. The PMOS transistor (P11) is still ON, so the voltage of the node A will be maintained at the voltage level of the power supply voltage (V DD ) until the end of the write cycle.
(四)節點A原本儲存邏輯1,而現在欲寫入邏輯0:在寫入動作發生前(該寫入用字元線WWL為接地電壓),該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線(WWL)由Low(接地電壓)轉High(該電源供應電壓VDD),且該寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為該寫入用位元線(WBL)是Low(接地電壓),所以會將該節點A以及該第一低電壓節點(VL1)放電而完成邏輯0的寫入動作,直到寫入週期結束。 (4) Node A originally stored logic 1, but now wants to write logic 0: before the writing operation occurs (the writing word line WWL is the ground voltage), the first PMOS transistor (P11) is on ( ON). When the writing word line (WWL) changes from Low (ground voltage) to High (the power supply voltage V DD ), and the voltage of the writing word line (WWL) is greater than the third NMOS transistor (M13) ), The third NMOS transistor (M13) changes from OFF to ON. At this time, because the write bit line (WBL) is Low (ground voltage), The node A and the first low voltage node (VL1) are discharged to complete a logic 0 writing operation until the writing cycle ends.
第7圖所示之本發明較佳實施例,於寫入操作時之HSPICE暫態分析模擬結果,如第8圖所示,其係使用TSMC 90奈米CMOS製程參數加以模擬,由該模擬結果可証實,本發明所提出之7T雙埠靜態隨機存取記憶體,能藉由寫入期間提高該第一低電壓節點(VL1)之電壓位準,並配合將該寫入用位元線(WBL)電壓位準拉高至高於該電源供應電壓(VDD)之該 寫入驅動電路(6),可在有效防止寫入邏輯1困難之同時,亦能有效提高寫入速度。 The HSPICE transient analysis simulation result during the write operation of the preferred embodiment of the invention shown in FIG. 7 is shown in FIG. 8, which is simulated using TSMC 90 nm CMOS process parameters. It can be confirmed that the 7T dual-port static random access memory proposed by the present invention can increase the voltage level of the first low voltage node (VL1) during the writing period and cooperate with the bit line for writing ( The write driving circuit (6) whose WBL) voltage level is raised higher than the power supply voltage (V DD ) can effectively prevent the writing logic 1 from being difficult, and can also effectively improve the writing speed.
(II)讀取模式(read mode) (II) read mode
於讀取操作開始前,該讀取控制信號(RC)、寫入控制信號(WC)及該待機模式控制信號(S)均為邏輯低位準,使得該第三PMOS電晶體(P21)導通,並使得該第十NMOS電晶體(M27)截止,於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準,邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通第九NMOS電晶體(M26),並使得該第一低電壓節點(VL1)呈接地電壓。另一方面,由於該讀取控制信號(RC)為邏輯低位準,使得該第七NMOS電晶體(M24)截止(OFF),並使得該第八NMOS電晶體(M25)導通(ON)。 Before the read operation starts, the read control signal (RC), write control signal (WC), and the standby mode control signal (S) are all logic low levels, so that the third PMOS transistor (P21) is turned on, And the tenth NMOS transistor (M27) is turned off, so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at a logic high level will be turned on. Nine NMOS transistors (M26), and the first low voltage node (VL1) is grounded. On the other hand, because the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off, and the eighth NMOS transistor (M25) is turned on.
在此值得注意的是,於讀取操作開始前之預充電期間,該預充電信號(P)係為邏輯低位準,藉此以將相對應之讀取用位元線(RBL)預充電至該電源供應電壓(VDD)之位準,惟由於例如20奈米以下製程技術之操作電壓將降為1伏特以下時將造成讀取速度降低而無法滿足規範之問題,因此,本發明提出二階段的讀取控制以於提高讀取速度並滿足規範的同時,亦避免無謂的功率耗損。 It is worth noting here that during the pre-charging period before the read operation starts, the pre-charging signal (P) is at a logic low level, thereby pre-charging the corresponding read bit line (RBL) to The level of the power supply voltage (V DD ), but because the operating voltage of the process technology below 20 nanometers will fall below 1 volt, the reading speed will be reduced and the specification cannot be met. Therefore, the present invention proposes two Phased read control is used to increase read speed and meet specifications while avoiding unnecessary power loss.
第6圖所示之本發明較佳實施例係藉由二階段的讀取控制以於提高讀取速度的同時,亦避免無謂的功率耗損,於讀取操作之第一階段,該讀取控制信號(RC)為邏輯高位準,使得該第七NMOS電晶體(M24)導通,由於此時該第八NMOS電晶體(M25)仍導通,於是該第二低電壓節點(VL2)大約呈較接地電壓為低之該加速讀取電壓(RGND),該較接地電壓為低之該 加速讀取電壓(RGND)可有效提高讀取速度。 The preferred embodiment of the present invention shown in FIG. 6 uses a two-stage read control to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the read operation, the read control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) is approximately grounded. The acceleration read voltage (RGND) is low, and the voltage is lower than the ground voltage. Accelerated reading voltage (RGND) can effectively improve reading speed.
而於讀取操作之第二階段,雖然該讀取控制信號(RC)仍為邏輯高位準,使得該第七NMOS電晶體(M24)仍為導通,惟由於此時該第八NMOS電晶體(M25)截止,於是該第二低電壓節點(VL2)會經由導通的該第四NMOS電晶體(M21)而呈接地電壓(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準),藉此可有效減少無謂的功率消耗。在此值得注意的是,該讀取操作之該第二階段與該第一階段相隔之時間,係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算,並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間,其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。再者,無論於讀取操作之第一階段抑是第二階段,該第四NMOS電晶體(M21)均呈導通狀態(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準)。第9圖所示為第6圖之本發明較佳實施例於讀取期間之簡化電路圖。 In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still on, but at this time the eighth NMOS transistor ( M25) is turned off, so the second low voltage node (VL2) will be grounded via the fourth NMOS transistor (M21) that is turned on (because the inverting standby mode control signal (/ S) is logic during read operation) High level), which can effectively reduce unnecessary power consumption. It is worth noting here that the time interval between the second stage and the first stage of the read operation is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level. The gate voltage of the eight NMOS transistor (M25) is enough time to turn off the eighth NMOS transistor (M25), and its value can be determined by the falling delay time of the third inverter (INV) and the first delay circuit. (D1) Adjust the delay time provided. Furthermore, the fourth NMOS transistor (M21) is in a conducting state regardless of whether it is the first stage or the second stage of the read operation (because the inverted standby mode control signal (/ S) is logic during the read operation) High level). FIG. 9 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during reading.
接下來依2種讀取狀態來說明第9圖之本發明較佳實施例如何藉由控制電路(2)以及高電壓位準控制電路(5)以於提高讀取速度的同時,亦避免無謂的功率耗損。 The following describes how the preferred embodiment of the present invention shown in FIG. 9 uses the control circuit (2) and the high-voltage level control circuit (5) to improve the reading speed while avoiding uselessness according to two read states. Power consumption.
(一)讀取邏輯1(節點A儲存邏輯1):在讀取動作發生前,該第一NMOS電晶體(M11)為截止(OFF)且該第二NMOS電晶體(M12)為導通(ON),該節點A與該節點B分別為該電源供應電壓(VDD)與接地電壓,而該讀取用位元線(RBL)則因該預充電電路(3)而等於該電源供應電壓(VDD)。於讀取期間,由於節點B為接地 電壓,因此該第二讀取用電晶體(M15)截止(OFF),藉此可有效保持該讀取用位元線(RBL)為該電源供應電壓(VDD)直到讀取週期結束而順利完成讀取邏輯1之操作。在此值得注意的是,於讀取操作之該第一階段,該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓(VRVL2I)必須滿足方程式(4):VRVL2I=RGND×RM21/(RM21+RM24+RM25)>-VTM12 (4)以有效地防止讀取時之半選定晶胞干擾,其中,VRVL2I表示該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓,RGND表示該加速讀取電壓,RM21表示該第四NMOS電晶體(M21)之導通電阻,RM24表示該第七NMOS電晶體(M24)之導通電阻,RM25表示該第八NMOS電晶體(M25)之導通電阻,而VTM12表示該第二NMOS電晶體(M12)之臨界電壓;而於該讀取操作之該第二階段,該第二低電壓節點(VL2)之電壓(VRVL2)可由方程式(5)表示VRVL2=接地電壓 (5)藉此,可有效地減少無謂的功率消耗。再者,為了有效降低讀取時之半選定晶胞干擾與有效降低漏電流,必須將較接地電壓為低之該加速讀取電壓(RGND)設定為使該第二低電壓節點(VL2)之電壓位準小於該第二NMOS電晶體(M12)之臨界電壓(VTM12),同時可更嚴謹地將較接地電壓為低之該加速讀取電壓(RGND)設定為低於該第二NMOS電晶體(M12)之臨界電壓(VTN12),亦即|RGND|<VTM12 (6)其中,|RGND|與VTM12分別表示該加速讀取電壓之絕對值與該第二 NMOS電晶體(M12)之臨界電壓。 (1) Read logic 1 (node A stores logic 1): before the read operation occurs, the first NMOS transistor (M11) is OFF and the second NMOS transistor (M12) is ON ), The node A and the node B are the power supply voltage (V DD ) and the ground voltage, respectively, and the read bit line (RBL) is equal to the power supply voltage (3) due to the precharge circuit (3) V DD ). During the reading period, since the node B is at the ground voltage, the second reading transistor (M15) is turned off, thereby effectively maintaining the reading bit line (RBL) as the power supply voltage ( V DD ) until the end of the read cycle, the read logic 1 operation is successfully completed. It is worth noting here that in the first stage of the read operation, the initial instantaneous voltage (V RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy equation (4): V RVL2I = RGND × R M21 / (R M21 + R M24 + R M25 )>-V TM12 (4) to effectively prevent half-selected cell interference during reading, where V RVL2I represents the second low voltage node ( VL2) read the initial instantaneous voltage when reading logic 1, RGND represents the accelerated read voltage, R M21 represents the on-resistance of the fourth NMOS transistor (M21), and R M24 represents the seventh NMOS transistor (M24) ), R M25 represents the on resistance of the eighth NMOS transistor (M25), and V TM12 represents the threshold voltage of the second NMOS transistor (M12); and in the second stage of the read operation, The voltage (V RVL2 ) of the second low-voltage node (VL2) can be represented by equation (5). V RVL2 = ground voltage (5). This can effectively reduce unnecessary power consumption. Furthermore, in order to effectively reduce the half-selected cell interference and effectively reduce the leakage current during reading, the accelerated reading voltage (RGND), which is lower than the ground voltage, must be set to the value of the second low voltage node (VL2). The voltage level is lower than the threshold voltage (V TM12 ) of the second NMOS transistor (M12), and the accelerated read voltage (RGND), which is lower than the ground voltage, can be set more strictly than the second NMOS transistor. The threshold voltage (V TN12 ) of the crystal (M12), that is, | RGND | <V TM12 (6), where | RGND | and V TM12 respectively represent the absolute value of the accelerated read voltage and the second NMOS transistor (M12 ).
再者,該第一高電源供應電壓(VDDH1)係設定為高於該電源供應電壓(VDD)但低於該電源供應電壓(VDD)與該第二PMOS電晶體(P12)臨界電壓之絕對值|VTP12|的總和,亦即VDD<VDDH1<VDD+|VTP12| (7)其中,|VTP12|表示該第二PMOS電晶體(P12)臨界電壓之絕對值。 Furthermore, the first high power supply voltage (V DDH1 ) is set to be higher than the power supply voltage (V DD ) but lower than the power supply voltage (V DD ) and the threshold voltage of the second PMOS transistor (P12). The sum of the absolute values | V TP12 |, that is, V DD <V DDH1 <V DD + | V TP12 | (7) where | V TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12).
(二)讀取邏輯0(節點A儲存邏輯0):在讀取動作發生前,該第一NMOS電晶體(M11)為導通(ON)且該第二NMOS電晶體(M12)為截止(OFF),該節點A與該節點B分別為接地電壓與該電源供應電壓(VDD),而該讀取用位元線(RBL)則因該預充電電路(3)而等於該電源供應電壓(VDD)。於讀取期間,由於節點B為該第一高電源供應電壓(VDDH1),且該第二低電壓節點(VL2)呈較接地電壓為低之電壓,由於該第一高電源供應電壓(VDDH1)係設定為高於該電源供應電壓(VDD),因此,可藉由增加該第二讀取用電晶體(M15)之導通程度,以提高讀取速度,同時配合較接地電壓為低之該第二低電壓節點(VL2)以進一步提高讀取速度。 (2) Read logic 0 (node A stores logic 0): Before the read operation occurs, the first NMOS transistor (M11) is on and the second NMOS transistor (M12) is off (OFF) ), The node A and the node B are the ground voltage and the power supply voltage (V DD ), and the read bit line (RBL) is equal to the power supply voltage (3) due to the precharge circuit (3). V DD ). During the reading period, since the node B is the first high power supply voltage (V DDH1 ), and the second low voltage node (VL2) is a voltage lower than the ground voltage, because the first high power supply voltage (V DDH1 ) is set to be higher than the power supply voltage (V DD ). Therefore, the reading speed can be increased by increasing the conduction degree of the second reading transistor (M15). This second low voltage node (VL2) further improves the read speed.
(III)待機模式(standby mode) (III) Standby mode
首先,說明第6圖之待機啟動電路(4)如何促使雙埠SRAM快速進入待機模式,以有效提高SRAM之待機效能:首先,於進入待機模式之前,該反相待機模式控制信號(/S)為邏輯High,該邏輯High之反相待機模式控制信 號(/S)使得該第五PMOS電晶體(P41)截止(OFF),並使得該第十一NMOS電晶體(M41)導通(ON);接著於進入待機模式後,該反相待機模式控制信號(/S)為邏輯Low,該邏輯Low之反相待機模式控制信號(/S)使得該第五PMOS電晶體(P41)導通(ON),惟於待機模式之初始期間內(該初始期間係等於該反相待機模式控制信號(/S)由邏輯High轉變為邏輯Low起算,至該第十一NMOS電晶體(M41)之閘極電壓足以關閉該第十一NMOS電晶體(M41)為止之時間,其可藉由該第二延遲電路(D2)所提供之一延遲時間來調整),該第十一NMOS電晶體(M41)仍導通(ON),於是可對該第一低電壓節點(VL1)快速充電到達該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準,亦即7T雙埠SRAM可快速進入待機模式。在此值得注意的是,於待機模式之初始期間後,該第十一NMOS電晶體(M41)關閉並停止供應電流。 First, explain how the standby startup circuit (4) in Figure 6 promotes the dual-port SRAM to enter the standby mode quickly, so as to effectively improve the standby performance of the SRAM: first, before entering the standby mode, the inverted standby mode control signal (/ S) Is logic High. The inverted standby mode control signal (/ S) of the logic High turns off the fifth PMOS transistor (P41) and turns on the eleventh NMOS transistor (M41). After entering the standby mode, the inverting standby mode control signal (/ S) is logic Low, and the inverting standby mode control signal (/ S) of the logic Low causes the fifth PMOS transistor (P41) to be turned on (ON). , But in the initial period of the standby mode (the initial period is equal to the inversion standby mode control signal (/ S) transition from logic High to logic Low, counting to the gate voltage of the eleventh NMOS transistor (M41) The time sufficient to turn off the eleventh NMOS transistor (M41) can be adjusted by a delay time provided by the second delay circuit (D2)), the eleventh NMOS transistor (M41) is still on (ON), so that the first low-voltage node (VL1) can be quickly charged to the sixth NMOS transistor The voltage level of the threshold voltage (V TM23 ) of the body (M23), that is, the 7T dual-port SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the eleventh NMOS transistor (M41) is turned off and stops supplying current.
請參考第6圖,於待機模式時,該待機模式控制信號(S)為邏輯高位準,而該反相待機模式控制信號(/S)為邏輯低位準,該邏輯低位準之該反相待機模式控制信號(/S)可使得該控制電路(2)中之該第四NMOS電晶體(M21)截止(OFF),而該邏輯高位準之該待機模式控制信號(S)則使得該第五NMOS電晶體(M22)導通(ON),此時該第五NMOS電晶體(M22)係作為等化器(equalizer)使用,因此可藉由呈導通狀態之該第五NMOS電晶體(M22),以使得該第一低電壓節點(VL1)之電壓位準相等於該第二低電壓節點(VL2)之電壓位準,且該等電壓位準均會等於該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準。第10圖所示為第6圖之本發明較佳實施例於待機期間之簡化電路圖。 Please refer to FIG. 6. In the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/ S) is a logic low level. The logic low level is the inverted standby The mode control signal (/ S) can turn off the fourth NMOS transistor (M21) in the control circuit (2), and the standby mode control signal (S) at the logic high level makes the fifth The NMOS transistor (M22) is turned on. At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) can be turned on. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are all equal to the voltage levels of the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V TM23 ). FIG. 10 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during the standby period.
接下來說明本發明於待機模式(standby mode)時如何減少漏電流,請參考第10圖,第10圖描述有本發明實施例處於待機模式時所產生之各漏電流(subthreshold leakage current)I1、I2、I3、I4,其中假設SRAM晶胞中之該第一反相器之輸出(即節點A)為邏輯Low(在此值得注意的是,由於待機模式時該第一低電壓節點(VL1)與該第二低電壓節點(VL2)之電壓位準均維持在該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準,因此節點A為邏輯Low之電壓位準亦維持在該VTM23的電壓位準),而該第二反相器之輸出(即節點B)為邏輯High(電源供應電壓VDD)。請參考第5圖之傳統8T雙埠SRAM與第10圖之本發明實施例,來說明本發明所提出之7T雙埠靜態隨機存取記憶體與第5圖之傳統8T雙埠SRAM於漏電流方面之比較,首先關於流經該第三NMOS電晶體(M13)之漏電流I1,由於本發明於待機模式時節點A之電壓位準係維持在該VTM23的電壓位準,且假設該寫入用字元線(WWL)於待機模式時係設定成接地電壓,而該寫入用位元線(WBL)於待機模式時則設定為該電源供應電壓(VDD),因此本發明之第三NMOS電晶體(M13)的閘源極電壓(VGS)為負值,反觀於待機模式時第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)的閘源極電壓(VGS)等於0,根據閘極引發汲極洩漏(Gate Induced Drain Leakage,簡稱GIDL)效應或2005年3月8日第US6865119號專利案第3(A)及3(B)圖之結果可知,對於NMOS電晶體而言,閘源極電壓為-0.1伏特時之次臨界電流約為閘源極電壓為0伏特時之次臨界電流的1%,因此導因於GIDL效應所引發之流經本發明之該第三NMOS電晶體(M13)之漏電流I1遠小於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)者;再者,本發明該第三NMOS 電晶體(M13)之汲源極電壓(VDS)為該電源供應電壓(VDD)扣減該VTM23的電壓位準,反觀於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)之汲源極電壓(VDS)係等於該電源供應電壓(VDD),根據汲極引發能障下跌(Drain-Induced Barrier Lowering,簡稱DIBL)效應,由於DIBL效應所引發之流經本發明之該第三NMOS電晶體(M13)之漏電流I1亦小於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)者;結果,流經本發明之該第三NMOS電晶體(M13)之漏電流I1遠小於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)者。 Next, how to reduce the leakage current in the standby mode of the present invention will be described. Please refer to FIG. 10, which describes the respective leakage currents (I 1 ) generated when the embodiment of the present invention is in the standby mode. , I 2 , I 3 , I 4 , where it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is logic Low (It is worth noting here that due to the first low voltage in the standby mode The voltage levels of the node (VL1) and the second low voltage node (VL2) are maintained at the voltage level of the threshold voltage (V TM23 ) of the sixth NMOS transistor (M23), so node A is a logic low voltage The level is also maintained at the voltage level of the V TM23 ), and the output of the second inverter (ie, node B) is logic High (power supply voltage V DD ). Please refer to the conventional 8T dual-port SRAM in FIG. 5 and the embodiment of the present invention in FIG. 10 to illustrate the leakage current of the 7T dual-port static random access memory proposed in the present invention and the conventional 8T dual-port SRAM in FIG. 5. In terms of comparison, first, regarding the leakage current I 1 flowing through the third NMOS transistor (M13), since the voltage level of the node A is maintained at the voltage level of the V TM23 in the standby mode of the present invention, and it is assumed that The writing word line (WWL) is set to the ground voltage in the standby mode, and the writing bit line (WBL) is set to the power supply voltage (V DD ) in the standby mode. a third NMOS transistor (M13) the gate-source voltage (V GS) is negative, on the other hand, when a conventional stand-by mode of FIG. 5 8T two-port SRAM of the NMOS transistor (M3) of the gate-source voltage (V GS ) Is equal to 0. According to the Gate Induced Drain Leakage (GIDL) effect or the results of Figures 3 (A) and 3 (B) of US6865119 patent case on March 8, 2005, we can know that for NMOS For transistors, the sub-critical current when the gate-source voltage is -0.1 volts is about 1% of the sub-critical current when the gate-source voltage is 0 volts. Therefore, the leakage current I 1 flowing through the third NMOS transistor (M13) of the present invention caused by the GIDL effect is much smaller than the NMOS transistor (M3) of the conventional 8T dual-port SRAM in FIG. 5; In the present invention, the drain-source voltage (V DS ) of the third NMOS transistor (M13) is the power supply voltage (V DD ) minus the voltage level of the V TM23 , in contrast to the traditional 8T dual port in FIG. 5 The drain-source voltage (V DS ) of the NMOS transistor (M3) of the SRAM is equal to the power supply voltage (V DD ). According to the drain-induced barrier lowering (DIBL) effect of the drain, due to the DIBL effect The leakage current I 1 flowing through the third NMOS transistor (M13) of the present invention is also smaller than that of the conventional 8T dual-port SRAM NMOS transistor (M3) of FIG. 5; as a result, the third NMOS transistor (M3) of the present invention flows through the third The leakage current I 1 of the NMOS transistor (M13) is much smaller than the NMOS transistor (M3) of the conventional 8T dual-port SRAM in FIG. 5.
接著關於流經該第一PMOS電晶體(P11)之漏電流I2,由於待機模式時該第一PMOS電晶體(P11)之源極係為該電源供應電壓(VDD),而該第一PMOS電晶體(P11)之汲極係維持在該VTM23的電壓位準,因此本發明之該第一PMOS電晶體(P11)之源汲極電壓(VSD)為該電源供應電壓(VDD)扣減該VTM23的電壓位準,反觀於第5圖之傳統8T雙埠SRAM之PMOS電晶體(P1)之源汲極電壓(VSD)係等於該電源供應電壓(VDD),根據DIBL效應,因此流經本發明之該第一PMOS電晶體(P11)之漏電流I2會小於第1b圖先前技藝之PMOS電晶體(P1)者。 Then regarding the leakage current I 2 flowing through the first PMOS transistor (P11), since the source of the first PMOS transistor (P11) is the power supply voltage (V DD ) in the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V TM23 , so the source drain voltage (V SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V DD ) The voltage level of the V TM23 is deducted. In contrast, the source-drain voltage (V SD ) of the PMOS transistor (P1) of the traditional 8T dual-port SRAM in Figure 5 is equal to the power supply voltage (V DD ). DIBL effect, so the leakage current I 2 flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the PMOS transistor (P1) of the prior art in FIG. 1b.
然後,關於流經該第二NMOS電晶體(M12)之漏電流I3,由於待機模式時該第二低電壓節點(VL2)之電壓位準係維持在該VTM23的電壓位準,節點A之電壓位準亦維持在該VTM23的電壓位準,而節點B之電壓位準係等於該電源供應電壓(VDD)且該第二NMOS電晶體(M12)之基底為接地電壓,因此本發明之該第二NMOS電晶體(M12)的基源極電壓(VBS)為負值,且該第二NMOS電晶體(M12)之汲源極電壓(VDS)為該電源供 應電壓(VDD)扣減該VTM23的電壓位準,反觀於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M2)的基源極電壓(VBS)等於0,且NMOS電晶體(M2)之汲源極電壓(VDS)等於該電源供應電壓(VDD),根據本體效應(body effect)及DIBL效應可知,流經本發明之該第二NMOS電晶體(M12)之漏電流I3遠小於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M2)者。 Then, regarding the leakage current I 3 flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V TM23 in the standby mode, the node A The voltage level of V TM23 is also maintained, and the voltage level of node B is equal to the power supply voltage (V DD ) and the substrate of the second NMOS transistor (M12) is ground voltage. The base-source voltage (V BS ) of the second NMOS transistor (M12) is negative, and the drain-source voltage (V DS ) of the second NMOS transistor (M12) is the power supply voltage (V DD ) The V TM23 voltage level is deducted. In contrast, the base-source voltage (V BS ) of the NMOS transistor (M2) of the traditional 8T dual-port SRAM in FIG. 5 is equal to 0, and the NMOS transistor (M2) The drain-source voltage (V DS ) is equal to the power supply voltage (V DD ). According to the body effect and DIBL effect, it can be known that the leakage current I 3 flowing through the second NMOS transistor (M12) of the present invention is much smaller than Figure 5 shows the NMOS transistor (M2) of a conventional 8T dual-port SRAM.
最後,關於流經該第一讀取用電晶體(M14)之漏電流I4,由於本發明與第5圖之傳統8T雙埠SRAM之讀取方式不同,且本發明待機模式下之讀取用位元線(RBL)可設定成接地電壓,而第5圖之傳統8T雙埠SRAM為了防止節點B之電壓位準下降,待機模式下之讀取用位元線對(RBL、RBLB)係設定成電源供應電壓,因此無從比較流經該第一讀取用電晶體(M14)之漏電流I4。綜合以上分析可知,本發明所提出之7T雙埠靜態隨機存取記憶體與第5圖之傳統8T雙埠SRAM相較具有較低之漏電流。 Finally, regarding the leakage current I 4 flowing through the first reading transistor (M14), the present invention is different from the conventional 8T dual-port SRAM in FIG. 5 in the reading method, and the reading in the standby mode of the present invention The bit line (RBL) can be set to ground voltage. In order to prevent the voltage level of node B from dropping, the conventional 8T dual-port SRAM in Figure 5 uses read bit line pairs (RBL, RBLB) in standby mode. Since the power supply voltage is set, the leakage current I 4 flowing through the first reading transistor (M14) cannot be compared. Based on the above analysis, it can be seen that the 7T dual-port static random access memory proposed by the present invention has a lower leakage current than the conventional 8T dual-port SRAM of FIG. 5.
(IV)保持模式(retension mode) (IV) Retension mode
保持模式時,由於該第一低電壓節點(VL1)與該第二低電壓節點(VL2)均設定成接地電壓,其工作原理相同於傳統具單一位元線之雙埠SRAM晶胞,於此不再累述。 In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to the ground voltage, the working principle is the same as that of a conventional dual-port SRAM cell with a single bit line. No more repetition.
本發明所提出之具高寫入速度之7T雙埠靜態隨機存取記憶體,具有如下功效: The 7T dual-port static random access memory with high write speed provided by the present invention has the following effects:
(1)高讀取速度並避免無謂的功率消耗:本發明所提出之具高寫入速度之7T靜態隨機存取記憶體係採用二階段讀取操作,於讀取邏輯0之第一階段藉由將該第二低電壓節點(VL2)設定成較接地電壓為低之電壓,並將該節點B設定為高於該電源供應電壓(VDD)之該第一高電源供應電壓(VDDH1),因此可藉此雙重機制以有效提高讀取速度,而於讀取邏輯0之第二階段則藉由將該第二低電壓節點(VL2)設定回接地電壓,以便減少無謂的功率消耗; (1) High read speed and avoid unnecessary power consumption: The 7T static random access memory system with high write speed proposed by the present invention uses a two-stage read operation. Setting the second low voltage node (VL2) to a voltage lower than the ground voltage, and setting the node B to the first high power supply voltage (V DDH1 ) higher than the power supply voltage (V DD ), Therefore, a dual mechanism can be used to effectively improve the reading speed, and in the second stage of reading logic 0, the second low voltage node (VL2) is set back to the ground voltage in order to reduce unnecessary power consumption;
(2)快速進入待機模式:由於本發明所提出之具高寫入速度之7T靜態隨機存取記憶體設置有待機啟動電路(4)以促使SRAM快速進入待機模式,並藉此以謀求提高7T雙埠SRAM之待機效能; (2) Quickly enter standby mode: As the 7T static random access memory with high write speed proposed by the present invention is provided with a standby startup circuit (4) to prompt the SRAM to enter the standby mode quickly, and thereby seek to improve 7T Standby performance of dual-port SRAM;
(3)提高寫入邏輯1之速度,並避免寫入邏輯1困難之問題:本發明於寫入操作時,可藉由該複數個控制電路(2)以及該複數個寫入驅動電路(6)以有效防止寫入邏輯1困難之同時,亦提高寫入邏輯1之速度; (3) Improve the speed of writing logic 1 and avoid the problem of writing logic 1. The invention can use the plurality of control circuits (2) and the plurality of write driving circuits (6) during the writing operation ) In order to effectively prevent the difficulty of writing logic 1, it also increases the speed of writing logic 1;
(4)低待機電流:由於本發明所提出之具高寫入速度之7T靜態隨機存取記憶體於待機模式時,可藉由呈導通狀態之該第五NMOS電晶體(M22),以使得該第一低電壓節點(VL1)之電壓位準相等於該第二低電壓節點(VL2)之電壓位準,並使得該等電壓位準均等於該第六NMOS電晶體(M23)之臨界電壓的位準,因此本發明所提出之7T雙埠靜態隨機存取記憶體亦具備低待機電流之功效; (4) Low standby current: As the 7T static random access memory with high writing speed proposed by the present invention is in standby mode, the fifth NMOS transistor (M22) can be turned on to make the The voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the threshold voltage of the sixth NMOS transistor (M23) Therefore, the 7T dual-port static random access memory proposed by the present invention also has the effect of low standby current;
(5)有效降低半選定晶胞干擾:本發明所提出之具高寫入速度之7T靜態隨機存取記憶體由於使用分離的讀/寫路徑,且該讀取路徑係設計成將該第一和第二讀取用電晶體(M14和M15)串聯連接在該讀取用位元線(RBL)與該第二低電壓節點(VL2)之間,並將該反相儲存節點(B)連接至該第二讀取用電晶體(M15)的閘極,因此可有效降低半選定晶胞干擾(half-selected cell disturbance),其中該半選定晶胞係指被該讀 取用字元線(RWL)選定但未被該讀取用位元線(RBL)選定之記憶體晶胞。 (5) Effectively reduce half-selected cell interference: The 7T static random access memory with high write speed proposed by the present invention uses a separate read / write path, and the read path is designed to change the first And a second reading transistor (M14 and M15) are connected in series between the reading bit line (RBL) and the second low voltage node (VL2), and the inverting storage node (B) is connected To the gate of the second reading transistor (M15), which can effectively reduce half-selected cell disturbance, where the half-selected cell refers to being read by the read A memory cell selected by a word line (RWL) but not selected by the read bit line (RBL) is taken.
(6)低電晶體數:對於具有1024列1024行之SRAM陣列而言,傳統第5圖之8T雙埠SRAM陣列共需1024×1024×8=8,388,608顆電晶體,而本發明所提出之7T雙埠靜態隨機存取記憶體僅需1024×1024×7+1024×27+6=7,367,686顆電晶體,其減少12.2%之電晶體數。 (6) Low transistor count: For a SRAM array with 1024 columns and 1024 rows, the traditional 8T dual-port SRAM array shown in Figure 5 requires a total of 1024 × 1024 × 8 = 8,388,608 transistors. The 7T proposed by the present invention The dual-port static random access memory only requires 1024 × 1024 × 7 + 1024 × 27 + 6 = 7,367,686 transistors, which reduces the number of transistors by 12.2%.
(7)高穩定度地完成寫入操作:當該寫入控制信號(WC)為邏輯高位準時,該節點(C)之電壓位準係為該接地電壓,藉此可高穩定度地完成寫入操作(由於寫入操作期間該節點C之電壓位準恆為該接地電壓)。 (7) Complete writing operation with high stability: When the writing control signal (WC) is at a logic high level, the voltage level of the node (C) is the ground voltage, thereby completing writing with high stability Input operation (because the voltage level of the node C is constant at the ground voltage during the write operation).
雖然本發明特別揭露並描述了所選之較佳實施例,但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本發明的精神與範圍。因此,所有相關技術範疇內之改變都包括在本發明之申請專利範圍內。 Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or detail may be changed without departing from the spirit and scope of the present invention. Therefore, all changes in the related technical scope are included in the scope of patent application of the present invention.
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