TWI631854B - Conversion device, imaging device, electronic device, conversion method - Google Patents

Abstract

本技術係關於一種可減小電路規模之轉換裝置、攝像裝置、電子機器、轉換方法。 The present technology relates to a conversion device, an imaging device, an electronic device, and a conversion method capable of reducing a circuit scale.

本發明之轉換裝置包含：比較部，其係將輸入信號之輸入電壓、與隨時間變動之斜坡信號之斜坡電壓進行比較；及記憶部，其保持來自比較部之比較結果反轉時之碼值；且藉由重複複數次由記憶部進行之碼值之保持，而產生特定之位元數之數位信號。將特定之位元數分成上階位元與下階位元，較上階位元更先取得下階位元，並組合所取得之下階位元與上階位元，而產生特定之位元數之數位信號。本技術可應用於影像感測器之進行AD轉換之部分。 The conversion device of the present invention includes: a comparison section that compares an input voltage of an input signal with a ramp voltage of a ramp signal that changes with time; and a memory section that holds a code value when the comparison result from the comparison section is inverted. ; And by repeating the holding of the code value by the memory section a plurality of times, a digital signal of a specific number of bits is generated. Divides a specific number of bits into higher-order bits and lower-order bits. The lower-order bits are obtained earlier than the upper-order bits, and the obtained lower-order bits and upper-order bits are combined to generate a specific bit. Digital signal of the quaternion. This technology can be applied to the AD conversion part of the image sensor.

Description

轉換裝置、攝像裝置、電子機器、轉換方法 Conversion device, imaging device, electronic device, conversion method

本技術係關於一種轉換裝置、攝像裝置、電子機器、轉換方法。詳細而言，係關於一種適於小型化之轉換裝置、攝像裝置、電子機器、轉換方法。 The present technology relates to a conversion device, an imaging device, an electronic device, and a conversion method. More specifically, it relates to a conversion device, an imaging device, an electronic device, and a conversion method suitable for miniaturization.

於近年來之攝像裝置中，期望多像素化、高畫質化、高速化，另一方面，亦期望進一步之小型化。作為滿足此種要求之攝像裝置，有人提出一種積層型之攝像裝置(例如參照專利文獻1)。 In recent years, imaging devices have been required to be multi-pixel, high-quality, and high-speed. On the other hand, further miniaturization is also desired. As an imaging device that satisfies such requirements, a laminated imaging device has been proposed (for example, refer to Patent Document 1).

積層型之攝像裝置係採用使用形成有信號處理電路之晶片替代攝像裝置之支持基板，且於其上重合像素部分之構造。有人提出藉由採用此種構成，將攝像裝置小型化。 The multi-layer imaging device is a structure in which a support substrate of the imaging device is replaced by a wafer formed with a signal processing circuit, and a pixel portion is superposed thereon. It has been proposed to reduce the size of the imaging device by adopting such a configuration.

[先前技術文獻] [Prior technical literature] [專利文獻] [Patent Literature]

[專利文獻1]日本特開2009-17720號公報 [Patent Document 1] Japanese Patent Laid-Open No. 2009-17720

積層型之攝像裝置係若將像素微細化，則必須亦減小搭載於其下模之晶片之電路。作為搭載於晶片之電路，例如有AD轉換電路。該AD轉換電路由於電晶體較多而難以小型化，故有人提出以複數個像素共有1個AD轉換電路。 For a multi-layer imaging device, if the pixels are miniaturized, the circuit of the chip mounted on the lower die must also be reduced. Examples of the circuit mounted on the chip include an AD conversion circuit. This AD conversion circuit is difficult to be miniaturized due to the large number of transistors, so it has been proposed that a total of one AD conversion circuit be used for a plurality of pixels.

然而，採用以複數個像素共有1個AD轉換電路之構成之情形時， 由於進行一面切換一面讀取來自複數個像素之信號之控制，故若1個AD轉換電路負責多個像素，則讀取之像素之時間差變大。因此，可設想於攝像移動之物體之情形時，將該物體攝像成失真，或於讀取1張圖像上花費時間。 However, when a configuration in which a plurality of pixels have one AD conversion circuit in common is used, Since the control of reading signals from a plurality of pixels is performed while switching, when one AD conversion circuit is responsible for a plurality of pixels, the time difference between the read pixels becomes large. Therefore, when imaging a moving object, it is conceivable that the object is distorted or that it takes time to read one image.

根據此種情況，配合像素之小型化，亦期望搭載於其下側之晶片之AD轉換電路之小型化。又，亦期望AD轉換電路負責之像素變少。 According to this situation, in accordance with the miniaturization of the pixel, the miniaturization of the AD conversion circuit of the chip mounted on the lower side is also expected. It is also expected that the number of pixels that the AD conversion circuit is responsible for will be reduced.

本技術係鑑於此種狀況而完成者，係可將產生特定之位元數之數位信號之電路構成小型化者。 This technology was completed in view of such a situation, and it is possible to miniaturize a circuit that generates a digital signal of a specific number of bits.

本技術之一態樣之轉換裝置包含：比較部，其係將輸入信號之輸入電壓、與隨時間變動之斜坡信號之斜坡電壓進行比較；及記憶部，其保持來自上述比較部之比較結果反轉時之碼值；且藉由重複複數次由上述記憶部進行之上述碼值之保持，而產生特定之位元數之數位信號。 A conversion device according to one aspect of the present technology includes: a comparison section that compares an input voltage of an input signal with a ramp voltage of a ramp signal that changes with time; and a memory section that holds the comparison result from the comparison section inversely. The code value at the time of rotation; and a digital signal of a specific number of bits is generated by repeating the holding of the code value by the memory section a plurality of times.

可將上述特定之位元數分成上階位元與下階位元，較上述上階位元更先取得上述下階位元，並組合所取得之上述下階位元與上述上階位元，而產生上述特定之位元數之數位信號。 The specific number of bits can be divided into upper-order bits and lower-order bits. The lower-order bits are obtained earlier than the upper-order bits, and the obtained lower-order bits and the upper-order bits are combined. , And generate a digital signal with the specified number of bits.

上述下階位元可為格雷碼。 The above-mentioned lower order bits may be Gray codes.

可共用上述下階位元與上述上階位元之至少1位元。 At least one bit of the lower order bit and the upper order bit may be shared.

可藉由上述共用之位元之一個下階之位元之值，修正上述數位信號。 The above-mentioned digital signal may be corrected by a value of a lower-order bit of the above-mentioned shared bit.

用以取得上述下階位元之上述斜坡信號與用以取得上述上階位元之上述斜坡信號可具有不同之週期。 The slope signal used to obtain the lower-order bits and the slope signal used to obtain the upper-order bits may have different periods.

上述輸入信號係自像素輸出之信號，且可包含於每個上述像素中。 The input signal is a signal output from a pixel, and may be included in each of the pixels.

本技術之一態樣之攝像裝置係積層上基板與下基板，於上述上基板配置像素、與將來自上述像素之信號之電壓與隨時間變動之斜坡信號之斜坡電壓進行比較之比較部，於上述下基板配置保持來自上述比較部之比較結果反轉時之碼值之記憶部，藉由重複複數次由上述記憶部進行之上述碼值之保持，而產生特定之位元數之數位信號。 An imaging device according to one aspect of the present technology is a comparison section that laminates an upper substrate and a lower substrate, arranges pixels on the upper substrate, and compares the voltage of the signal from the pixel with the ramp voltage of the ramp signal that changes with time. The lower substrate is configured to hold a memory portion of the code value when the comparison result from the comparison portion is reversed, and generates a digital signal of a specific number of bits by repeating the holding of the code value by the memory portion multiple times.

可將上述特定之位元數分成上階位元與下階位元，較上述上階位元更先取得上述下階位元，以上述像素之基準位準之下階位元、上述像素之基準位準之上階位元、上述像素之信號位準之下階位元、及上述像素之信號位準之上階位元之順序，取得上述基準位準之信號與上述信號位準之信號，並自該等信號之一者減去另一者，而產生表示累積於上述像素之電荷量之數位信號。 The specific number of bits can be divided into upper-order bits and lower-order bits. The lower-order bits are obtained earlier than the upper-order bits. Based on the reference level of the pixels, the lower-order bits and the pixels are obtained. The order of the upper order bit of the reference level, the lower order bit of the signal level of the pixel, and the upper order bit of the signal level of the pixel, to obtain the signal of the reference level and the signal of the signal level , And subtract one from the other to generate a digital signal representing the amount of charge accumulated in the pixel.

取得上述基準位準之信號時之上述斜坡電壓與取得上述信號位準時之上述斜坡電壓可不同。 The ramp voltage when the signal of the reference level is obtained may be different from the ramp voltage when the signal level is obtained.

取得上述信號位準之高亮度側之信號時之上述斜坡信號之電壓變化可較取得低亮度側之信號時之上述斜坡信號之電壓變化更為急劇，或，取得上述信號位準之高亮度側之信號時之對上述記憶部供給上述碼值之速度可較取得低亮度側之信號時之對上述記憶部供給上述碼值之速度更慢。 The voltage change of the ramp signal when obtaining the signal on the high-luminance side of the signal level may be more rapid than the voltage change of the ramp signal when obtaining the signal on the low-luminance side, or the high-luminance side on the signal level The speed at which the code value is supplied to the memory portion at the time of the signal may be slower than the speed at which the code value is supplied to the memory portion when the signal at the low brightness side is obtained.

可根據於上述斜坡信號之電壓變化變得急劇之時點、或上述碼值之供給之速度變化之時點所取得之信號、與上述基準位準之差分，而修正上述高亮度側之信號。 The signal on the high-luminance side can be corrected based on the difference between the signal obtained at the time when the voltage change of the ramp signal becomes sharp or the speed at which the code value is supplied and the reference level.

本技術之一態樣之電子機器包含：攝像裝置，其積層上基板與下基板，於上述上基板配置像素、與將來自上述像素之信號之電壓與隨時間變動之斜坡信號之斜坡電壓進行比較之比較部，於上述下基板配置保持來自上述比較部之比較結果反轉時之碼值之記憶部，藉由重複複數次由上述記憶部進行之上述碼值之保持，而產生特定之位元數 之數位信號；及信號處理部，其係對自上述半導體裝置輸出之像素信號進行信號處理。 An electronic device according to one aspect of the present technology includes: an imaging device, which includes an upper substrate and a lower substrate, and arranges pixels on the upper substrate, and compares the voltage of the signal from the pixel with the ramp voltage of the ramp signal that changes with time The comparison unit is a memory unit configured to hold the code value when the comparison result from the comparison unit is inverted on the lower substrate, and generates a specific bit by repeating the plurality of times the code value is maintained by the memory unit. number A digital signal; and a signal processing unit that performs signal processing on a pixel signal output from the semiconductor device.

本技術之一態樣之轉換方法係轉換裝置之轉換方法，該轉換裝置包含：比較部，其係將輸入信號之輸入電壓、與隨時間變動之斜坡信號之斜坡電壓進行比較；及記憶部，其保持來自上述比較部之比較結果反轉時之碼值；且該轉換方法包含如下步驟：藉由重複複數次由上述記憶部進行之上述碼值之保持，而產生特定之位元數之數位信號。 A conversion method of one aspect of the technology is a conversion method of a conversion device, the conversion device including: a comparison section that compares an input voltage of an input signal with a ramp voltage of a ramp signal that changes with time; and a memory section, It retains the code value when the comparison result from the comparison section is reversed; and the conversion method includes the steps of generating a specific number of digits by repeating the preservation of the code value by the memory section a plurality of times. signal.

於本技術之一態樣之轉換裝置、轉換方法中，將輸入信號之輸入電壓、與隨時間變動之斜坡信號之斜坡電壓進行比較，且保持該比較結果反轉時之碼值。藉由重複複數次該保持之處理，而產生特定之位元數之數位信號。 In the conversion device and method of one aspect of the present technology, the input voltage of the input signal is compared with the ramp voltage of the ramp signal that changes with time, and the code value when the comparison result is inverted is maintained. By repeating the holding process plural times, a digital signal of a specific number of bits is generated.

本技術之一態樣之攝像裝置係積層上基板與下基板，於上基板配置有像素、與將來自像素之信號之電壓與隨時間變動之斜坡信號之斜坡電壓進行比較之比較部，於下基板配置有保持來自比較部之比較結果反轉時之碼值之記憶部。藉由重複複數次由記憶部進行之碼值之保持，而產生特定之位元數之數位信號。 An aspect of the present invention is an imaging device in which an upper substrate and a lower substrate are laminated, and a pixel is disposed on the upper substrate, and a comparison section for comparing the voltage of the signal from the pixel with the ramp voltage of the ramp signal that changes with time. The substrate is provided with a memory section that holds a code value when the comparison result from the comparison section is inverted. A digital signal of a specific number of bits is generated by repeating the holding of the code value by the memory section a plurality of times.

於本技術之一態樣之電子機器中，採用包含上述攝像裝置之構成。 In an electronic device according to an aspect of the present technology, a configuration including the imaging device described above is adopted.

根據本技術之一態樣，可將產生特定之位元數之數位信號之電路構成小型化。 According to one aspect of the technology, the circuit configuration for generating a digital signal of a specific number of bits can be miniaturized.

另，此處所記載之效果並非完全限定者，亦可為本揭示中所記載之任一效果。 In addition, the effects described here are not completely limited, and any of the effects described in this disclosure may be used.

10‧‧‧上基板 10‧‧‧ Upper substrate

11‧‧‧下基板 11‧‧‧ lower substrate

21‧‧‧像素 21‧‧‧ pixels

22‧‧‧像素驅動電路 22‧‧‧pixel driving circuit

31‧‧‧ADC 31‧‧‧ADC

32‧‧‧輸出電路 32‧‧‧output circuit

33‧‧‧感測放大器 33‧‧‧Sense Amplifier

34‧‧‧V掃描電路 34‧‧‧V scan circuit

35‧‧‧時序產生電路 35‧‧‧ timing generation circuit

36‧‧‧DAC 36‧‧‧DAC

51‧‧‧比較器 51‧‧‧ Comparator

52‧‧‧閂鎖電路 52‧‧‧Latch circuit

101(101-1~101-4)‧‧‧光電二極體 101 (101-1 ~ 101-4) ‧‧‧Photodiode

102(102-1~102-4)‧‧‧傳送電晶體 102 (102-1 ~ 102-4) ‧‧‧Transistor

103‧‧‧浮動擴散 103‧‧‧ floating diffusion

104‧‧‧重設電晶體 104‧‧‧Reset transistor

105‧‧‧放大電晶體 105‧‧‧Amplified transistor

121‧‧‧負載MOS 121‧‧‧Load MOS

141‧‧‧電晶體 141‧‧‧Transistor

142‧‧‧電晶體 142‧‧‧Transistor

143‧‧‧電晶體 143‧‧‧Transistor

144‧‧‧電晶體 144‧‧‧Transistor

145‧‧‧電流源部 145‧‧‧Current source department

146‧‧‧緩衝器 146‧‧‧Buffer

161(161-1~161-10)‧‧‧閂鎖行 161 (161-1 ~ 161-10) ‧‧‧Latch row

171(171-1~171-10)‧‧‧電晶體 171 (171-1 ~ 171-10) ‧‧‧Transistor

181(181-1~181-10)‧‧‧電晶體 181 (181-1 ~ 181-10) ‧‧‧Transistor

201‧‧‧比較器 201‧‧‧ Comparator

202‧‧‧閂鎖電路 202‧‧‧Latch circuit

221‧‧‧比較電晶體 221‧‧‧Comparison Transistor

222‧‧‧SL 222‧‧‧SL

223‧‧‧Sr 223‧‧‧Sr

224‧‧‧緩衝器 224‧‧‧Buffer

261‧‧‧閂鎖電路 261‧‧‧Latch circuit

301‧‧‧訊框記憶體 301‧‧‧Frame memory

302‧‧‧減法器 302‧‧‧Subtractor

311‧‧‧減法器 311‧‧‧ Subtractor

401‧‧‧輸出段 401‧‧‧ output section

402‧‧‧閂鎖電路 402‧‧‧Latch circuit

500‧‧‧攝像裝置 500‧‧‧ camera

501‧‧‧透鏡群 501‧‧‧lens group

502‧‧‧攝像元件 502‧‧‧ camera element

503‧‧‧DSP電路 503‧‧‧DSP circuit

504‧‧‧訊框記憶體 504‧‧‧Frame memory

505‧‧‧顯示裝置 505‧‧‧ display device

506‧‧‧記錄裝置 506‧‧‧Recording device

507‧‧‧操作系統 507‧‧‧operating system

508‧‧‧電源系統 508‧‧‧Power System

509‧‧‧匯流排線 509‧‧‧bus line

510‧‧‧CPU 510‧‧‧CPU

Amp‧‧‧放大電晶體 Amp‧‧‧Amplified Transistor

FD‧‧‧浮動擴散 FD‧‧‧Floating Diffusion

PD‧‧‧光電二極體 PD‧‧‧Photodiode

Rst‧‧‧重設電晶體 Rst‧‧‧Reset transistor

SL‧‧‧信號線 SL‧‧‧Signal cable

T0‧‧‧時刻 T0‧‧‧time

T0’‧‧‧時刻 T0’‧‧‧time

T1‧‧‧時刻 T1‧‧‧time

T2‧‧‧時刻 T2‧‧‧time

T3‧‧‧時刻 T3‧‧‧time

T11‧‧‧時間 T11‧‧‧time

T12‧‧‧時間 T12‧‧‧time

T13‧‧‧時間 T13‧‧‧time

T14‧‧‧時間 T14‧‧‧time

Trf‧‧‧傳送電晶體 Trf‧‧‧Transistor Transistor

Vdd‧‧‧電源電壓 Vdd‧‧‧ supply voltage

V_FD‧‧‧Amp通道電壓 V _FD ‧‧‧Amp channel voltage

圖1係用以對攝像元件之構成進行說明之圖。 FIG. 1 is a diagram for explaining the configuration of an imaging element.

圖2係用以對配置於上基板與下基板之電路進行說明之圖。 FIG. 2 is a diagram for explaining circuits arranged on an upper substrate and a lower substrate.

圖3係顯示攝像元件之電路構成之圖。 FIG. 3 is a diagram showing a circuit configuration of the imaging element.

圖4係用以對配置於上基板與下基板之電路進行說明之圖。 FIG. 4 is a diagram for explaining circuits arranged on an upper substrate and a lower substrate.

圖5係顯示攝像元件之電路構成之圖。 FIG. 5 is a diagram showing a circuit configuration of the imaging element.

圖6係對比較電晶體反轉之時序進行說明之圖。 FIG. 6 is a diagram illustrating the timing of the comparison transistor inversion.

圖7係對比較電晶體反轉之時序進行說明之圖。 FIG. 7 is a diagram illustrating the timing of the comparison transistor inversion.

圖8係顯示攝像元件之電路構成之圖。 FIG. 8 is a diagram showing a circuit configuration of the imaging element.

圖9係用以對讀取動作進行說明之圖。 FIG. 9 is a diagram for explaining a reading operation.

圖10係用以對讀取動作進行說明之圖。 FIG. 10 is a diagram for explaining a reading operation.

圖11係顯示攝像元件之電路構成之圖。 FIG. 11 is a diagram showing a circuit configuration of the imaging element.

圖12係顯示攝像元件之電路構成之圖。 FIG. 12 is a diagram showing a circuit configuration of the imaging element.

圖13A、B係用以對讀取動作進行說明之圖。 13A and 13B are diagrams for explaining a reading operation.

圖14A、B係用以對讀取動作進行說明之圖。 14A and 14B are diagrams for explaining a reading operation.

圖15係用以對上階與下階之位元之統合進行說明之圖。 FIG. 15 is a diagram for explaining the integration of the upper and lower order bits.

圖16係用以對上階與下階之位元之統合進行說明之圖。 FIG. 16 is a diagram for explaining the integration of the upper and lower order bits.

圖17係用以對上階與下階之位元之統合進行說明之圖。 FIG. 17 is a diagram for explaining the integration of the upper and lower order bits.

圖18係用以對讀取動作進行說明之圖。 FIG. 18 is a diagram for explaining a reading operation.

圖19係用以對讀取動作進行說明之圖。 FIG. 19 is a diagram for explaining a reading operation.

圖20係顯示電子機器之構成之圖。 Fig. 20 is a diagram showing the configuration of an electronic device.

以下，對用以實施本技術之形態(以下稱為實施形態)進行說明。另，說明係按以下之順序進行。 Hereinafter, a mode for implementing the present technology (hereinafter referred to as an embodiment) will be described. The explanation is performed in the following order.

1.積層型之攝像裝置之構成 1. Structure of a multi-layer imaging device

2.各層之電路之配置之形態 2. The configuration of the circuits of each layer

3.各層之電路之配置之另一形態 3. Another form of circuit configuration of each layer

4.降低閂鎖數之構成 4. Composition of reducing the number of latches

5.電子機器 5. Electronic equipment

6.記錄媒體 6. Recording Media

<積層型之攝像裝置之構成> <Structure of Multi-layer Imaging Device>

圖1係顯示應用本技術之攝像裝置之構成之圖。本技術可應用於積層型之攝像裝置。積層型之攝像裝置係採用使用形成有信號處理電路之晶片替代像素之部分之支持基板，且於其上重合像素部分之構造。藉由採用此種構成，可實現攝像裝置之小型化。 FIG. 1 is a diagram showing the configuration of an imaging device to which the present technology is applied. This technology can be applied to a multi-layer imaging device. The multi-layered imaging device has a structure in which a pixel-supporting substrate is replaced with a wafer in which a signal processing circuit is formed, and the pixel portion is superposed thereon. By adopting such a configuration, miniaturization of the imaging device can be achieved.

如圖1所示，於上基板10，以矩陣狀配置有像素21，且配置有用以驅動各個像素21之像素驅動電路22。於下基板11，於與像素21對應之位置，以矩陣狀配置有ADC(A/D Converter：類比數位轉換器)31。於圖1所示之例中，顯示以2×2=4個像素作為1區塊，1個ADC31處理1區塊量之4個像素21之構成。此種構成之情形時，使ADC31並列動作，各ADC31係一面掃描4個像素一面進行AD轉換。 As shown in FIG. 1, on the upper substrate 10, pixels 21 are arranged in a matrix, and a pixel driving circuit 22 configured to drive each pixel 21 is arranged. On the lower substrate 11, ADCs (A / D Converters) 31 are arranged in a matrix shape at positions corresponding to the pixels 21. In the example shown in FIG. 1, it is shown that 2 × 2 = 4 pixels are used as one block, and one ADC 31 processes four pixels 21 of one block. In the case of such a configuration, the ADCs 31 are operated in parallel, and each ADC 31 performs AD conversion while scanning 4 pixels.

於下基板11亦搭載有輸出電路32、感測放大器33、V掃描電路34、時序產生電路35、及DAC(D/A Converter：數位類比轉換器)。來自ADC31之輸出係以經由感測放大器33與輸出電路32輸出至外部之方式構成。來自像素21之讀取之處理係藉由像素驅動電路22與V掃描電路34進行，且根據藉由時序產生電路35產生之時序進行控制。又，DAC36係產生斜坡信號之電路。 An output circuit 32, a sense amplifier 33, a V-scan circuit 34, a timing generation circuit 35, and a DAC (D / A Converter: Digital Analog Converter) are also mounted on the lower substrate 11. The output from the ADC 31 is configured to be output to the outside through the sense amplifier 33 and the output circuit 32. The processing of reading from the pixel 21 is performed by the pixel driving circuit 22 and the V scanning circuit 34, and is controlled according to the timing generated by the timing generating circuit 35. The DAC36 is a circuit that generates a ramp signal.

斜坡信號係供給至ADC31之比較器之信號。參照圖2，對ADC31之內部構成進行說明。圖2係顯示1區塊量之像素21與ADC31之構成之方塊圖。來自以2×2之4像素構成之1區塊量之像素21之信號係於ADC31之比較器51中，與斜坡信號之斜坡電壓進行比較。 The ramp signal is the signal supplied to the comparator of ADC31. The internal configuration of the ADC 31 will be described with reference to FIG. 2. FIG. 2 is a block diagram showing the structure of the pixel 21 and the ADC 31 with one block. The signal from the pixel 21 of 1 block composed of 2 × 2 4 pixels is compared in the comparator 51 of the ADC 31 with the ramp voltage of the ramp signal.

斜坡電壓係自特定之電壓逐漸變小之電壓，構成為該斜坡電壓開始下降，且來自像素21之信號被橫斷時(來自像素21之信號之電壓與斜坡電壓成為相同之電壓時)，比較器51之輸出反轉。比較器51之 輸出係輸入至閂鎖電路52。對閂鎖電路52採用如下構成：輸入表示此時之時刻之碼值，並保持比較器51之輸出反轉時之碼值，其後讀取。 The ramp voltage is a voltage that gradually decreases from a specific voltage. When the ramp voltage starts to fall and the signal from pixel 21 is traversed (when the voltage of the signal from pixel 21 and the ramp voltage become the same voltage), the comparison is made. The output of the device 51 is inverted. Comparator 51 of The output is input to the latch circuit 52. The latch circuit 52 is configured as follows: a code value indicating the time at this time is input, and the code value at the time when the output of the comparator 51 is inverted is held, and then read.

圖3中顯示包含ADC31之攝像裝置之電路圖。於圖3中，圖示有分別包含於圖1所示之上基板10與下基板11之電路。於上基板10包含像素21，其電路採用如圖3之左部所示之構成。此處，舉出以4像素共有1個FD(浮動擴散)之構成為例進行說明。 A circuit diagram of an imaging device including ADC31 is shown in FIG. 3. In FIG. 3, the circuits included in the upper substrate 10 and the lower substrate 11 shown in FIG. 1 are illustrated, respectively. The upper substrate 10 includes pixels 21, and the circuit is configured as shown in the left part of FIG. Here, a configuration in which one pixel has a total of one FD (floating diffusion) will be described as an example.

作為光電轉換部之光電二極體(PD)101-1至101-4係分別連接於傳送電晶體(Trf)102-1至102-4。以下，於無須個別區分光電二極體101-1至101-4之情形時，簡單記述為光電二極體101。關於其他部分亦相同地記述。 The photodiodes (PD) 101-1 to 101-4 as the photoelectric conversion sections are connected to the transmission transistors (Trf) 102-1 to 102-4, respectively. Hereinafter, when it is not necessary to individually distinguish the photodiodes 101-1 to 101-4, they are simply described as the photodiode 101. The same applies to the other parts.

傳送電晶體102-1至102-4係分別連接於浮動擴散(FD)103。傳送電晶體102係將由光電二極體101光電轉換且累積之信號電荷，於給予有傳送脈衝之時序傳送至浮動擴散103。 The transmission transistors 102-1 to 102-4 are connected to the floating diffusion (FD) 103, respectively. The transmission transistor 102 transmits the signal charge photoelectrically converted and accumulated by the photodiode 101 to the floating diffusion 103 at the timing given the transmission pulse.

浮動擴散103係作為將信號電荷轉換成電壓信號之電荷電壓轉換部發揮功能。重設電晶體(Rst)104係分別將汲極電極連接於電源電壓Vdd之像素電源，將源極電極連接於浮動擴散103。重設電晶體104係於自光電二極體101對浮動擴散103傳送信號電荷之前，對閘極電極給予重設脈衝RST，而將浮動擴散103之電壓重設成重設電壓。 The floating diffusion 103 functions as a charge-voltage conversion unit that converts a signal charge into a voltage signal. The reset transistor (Rst) 104 connects the drain electrode to the pixel power supply of the power supply voltage Vdd and the source electrode to the floating diffusion 103, respectively. The reset transistor 104 is provided with a reset pulse RST to the gate electrode before the signal charge is transmitted from the photodiode 101 to the floating diffusion 103, and the voltage of the floating diffusion 103 is reset to the reset voltage.

放大電晶體(Amp)105係分別將閘極電極連接於浮動擴散103，將汲極電極連接於電源電壓Vdd之像素電源。將藉由重設電晶體104重設之後之浮動擴散103之電壓作為重設位準輸出，再者將藉由傳送電晶體102傳送信號電荷之後之浮動擴散103之電壓作為信號位準輸出。 Amplifying transistor (Amp) 105 connects the gate electrode to the floating diffusion 103 and the drain electrode to the pixel power supply of the power supply voltage Vdd. The voltage of the floating diffusion 103 after resetting by the reset transistor 104 is used as the reset level output, and the voltage of the floating diffusion 103 after transmitting the signal charge by the transfer transistor 102 is used as the signal level output.

以放大電晶體105與設置於下基板11之負載MOS121之組作為源極跟隨器動作，將表示浮動擴散103之電壓之類比信號傳送至下基板11之比較器51。 The set of the amplification transistor 105 and the load MOS 121 provided on the lower substrate 11 acts as a source follower, and an analog signal indicating the voltage of the floating diffusion 103 is transmitted to the comparator 51 of the lower substrate 11.

比較器51可以差動放大電路構成。具備具有電晶體141、144之 差動電晶體對部、具有成為差動電晶體對部之輸出負載之電晶體142、143且配置於電源側之負載電晶體對部、及供給一定之動作電流且配置於接地(GND)側之電流源部145。 The comparator 51 may be configured by a differential amplifier circuit. With transistors 141, 144 Differential transistor pair, transistor 142, 143 with output load that becomes the differential transistor pair, load transistor pair arranged on the power supply side, and a certain operating current supplied and arranged on the ground (GND) side之 Current Source 部 145.

電晶體141、144之各源極係共通地與電流源部145之電晶體之汲極連接，於電晶體141、144之各汲極(輸出端子)連接有負載電晶體對部之對應之電晶體142、143之汲極。 Each source of the transistors 141 and 144 is connected in common to the drain of the transistor of the current source unit 145. The drain of each transistor (output terminal) of the transistors 141 and 144 is connected to the corresponding transistor of the load transistor. Drain of crystals 142, 143.

差動電晶體對部之輸出(於圖示之例中為電晶體144之汲極)係經過緩衝器146，完成充分之放大之後，輸出至閂鎖電路52。 The output of the opposite part of the differential transistor (the drain of the transistor 144 in the example shown in the figure) passes through the buffer 146, and after being fully amplified, is output to the latch circuit 52.

於電晶體141之閘極(輸入端子)供給自像素21傳送而來之像素信號，於電晶體144之閘極(輸入端子)係自DAC36供給斜坡信號。 The pixel signal transmitted from the pixel 21 is supplied to the gate (input terminal) of the transistor 141, and the ramp signal is supplied from the DAC 36 to the gate (input terminal) of the transistor 144.

閂鎖電路52包含10個閂鎖行161-1至161-10。於閂鎖行161-1至161-10，分別輸入CodeD0至D9(以下記述為碼值D)。該碼值D0至D9係表示此時之時刻之碼值。 The latch circuit 52 includes ten latch rows 161-1 to 161-10. In the latch lines 161-1 to 161-10, enter CodeD0 to D9 (hereinafter referred to as code value D). The code values D0 to D9 indicate the code values at this time.

為了小型化，各閂鎖行161係設為動態電路。又，於接通、斷開各閂鎖行161之電晶體171之閘極，輸入來自比較器51之輸出。於此種閂鎖電路52中，構成為保持比較器51之輸出反轉時之碼值，其後讀取，且輸出至感測放大器33(圖1)。 For miniaturization, each latch line 161 is a dynamic circuit. In addition, the gate of the transistor 171 of each latch row 161 is turned on and off, and the output from the comparator 51 is input. The latch circuit 52 is configured to hold the code value when the output of the comparator 51 is inverted, read it later, and output it to the sense amplifier 33 (FIG. 1).

於此種構成中，於上基板10配置有像素21，於下基板11配置有電路。上基板10與下基板11係可例如藉由Cu-Cu接合而接合。該Cu-Cu接合可使用本申請人先前申請之日本特開2011-54637號公報所揭示之技術。 In this configuration, the pixels 21 are arranged on the upper substrate 10, and the circuits are arranged on the lower substrate 11. The upper substrate 10 and the lower substrate 11 may be bonded by, for example, Cu-Cu bonding. For the Cu-Cu bonding, a technique disclosed in Japanese Patent Application Laid-Open No. 2011-54637 previously applied by the applicant can be used.

上基板10與下基板11由於積層，故較佳為基本上相同程度之大小。換言之，若任一基板較大，則該大小成為包含上基板10與下基板11之攝像裝置之大小之界限。 Since the upper substrate 10 and the lower substrate 11 are laminated, they are preferably substantially the same size. In other words, if any substrate is large, the size becomes a limit of the size of the imaging device including the upper substrate 10 and the lower substrate 11.

配置於上基板10之像素21係電晶體較少而容易小型化。下基板11之例如ADC31係電晶體較多而難以小型化。假設，將與配置於上基板 10之像素21之個數相同數量之ADC31配置於下基板11之情形時，下基板11大於上基板10之可能性較高。因此，考慮以複數個像素21共有1個ADC31。於圖1中，圖示以4像素共有1個ADC31之情形。 The pixel 21-based transistors arranged on the upper substrate 10 have fewer transistors and are easily miniaturized. There are many ADC31 series transistors in the lower substrate 11 and it is difficult to miniaturize them. It is assumed that the When the number of ADCs 31 with the same number of 10 pixels 21 is arranged on the lower substrate 11, it is highly possible that the lower substrate 11 is larger than the upper substrate 10. Therefore, it is considered that a plurality of pixels 21 have one ADC 31 in total. In FIG. 1, a case where a total of one ADC 31 is shown in four pixels is shown.

採用以複數個像素共有1個ADC31之情形時，由於進行一面切換一面讀取來自複數個像素21(該情形時為4個像素)之信號之控制，故若1個ADC31負責多個像素，則讀取之像素之時間差變大。因此，可設想於攝像例如移動之物體之情形時，將該物體攝像成失真，或於讀取1張圖像上花費時間。 In the case of a total of one ADC31 with a plurality of pixels, since the control of reading signals from the plurality of pixels 21 (four pixels in this case) is performed while switching, if one ADC31 is responsible for multiple pixels, then The time difference between the read pixels becomes larger. Therefore, when imaging a moving object, it is conceivable that the object is distorted, or that it takes time to read one image.

根據此種情況，配合像素21之小型化，期望積層之晶片(該情形時為下基板11)之ADC31之小型化。又，於將晶片小型化時，亦期望ADC31負責之像素變少。 According to this situation, in accordance with the miniaturization of the pixel 21, the miniaturization of the ADC 31 of the laminated wafer (the lower substrate 11 in this case) is desired. When miniaturizing the chip, it is also expected that the number of pixels that the ADC 31 is responsible for will be reduced.

又，參照圖3，比較器51與負載MOS121係類比電路，其性能有不均之可能性。因此，亦有難以減小電晶體，或降低電壓之背景。由於閂鎖電路52為數位電路，故較為容易小型化或低電壓化。 Referring to FIG. 3, the comparator 51 and the load MOS121 are analog circuits, and there is a possibility that the performance may be uneven. Therefore, there are backgrounds in which it is difficult to reduce the transistor or reduce the voltage. Since the latch circuit 52 is a digital circuit, it is easier to miniaturize or lower the voltage.

藉由將此種小規模之數位電路與類比電路以極為接近之狀態配置多數，難以將電源電壓或電晶體之耐壓分別最佳化。又，由於像素21與比較器51必需定常電流，故難以降低消耗電力。又，由於像素21流通電流並輸出，故產生熱雜訊。 By arranging a large number of such small-scale digital circuits and analog circuits in a very close state, it is difficult to optimize the power supply voltage or the withstand voltage of the transistor, respectively. In addition, since the pixels 21 and the comparator 51 need a constant current, it is difficult to reduce power consumption. In addition, since the pixel 21 flows and outputs current, thermal noise is generated.

如此，就於上基板10配置像素21，於下基板11配置電路而言，有產生如上所述之問題之可能性。 As described above, in the case where the pixels 21 are arranged on the upper substrate 10 and the circuits are arranged on the lower substrate 11, there is a possibility that the problems described above may occur.

<各層之電路之配置之形態> <Form of Circuit Arrangement of Each Layer>

因此，採用如圖4所示之構成。圖4所示之構成與圖2所示之構成對應，係顯示1區塊量之像素21與ADC31之構成之方塊圖。於圖4所示之構成中，將構成ADC31之比較器與閂鎖電路分開配置於上基板10與下基板11。 Therefore, the structure shown in FIG. 4 is adopted. The structure shown in FIG. 4 corresponds to the structure shown in FIG. 2, and is a block diagram showing the structure of the pixel 21 and the ADC 31 of one block. In the configuration shown in FIG. 4, the comparator and the latch circuit constituting the ADC 31 are separately disposed on the upper substrate 10 and the lower substrate 11.

為了與圖2所示之情形區分，配置於上基板10之比較器係將符號 改變為比較器201進行說明。如後述般，由於閂鎖電路52可採用與參照圖2、圖3說明之閂鎖電路52相同之構成，故閂鎖電路52不改變符號而繼續說明。 In order to distinguish it from the situation shown in FIG. 2, the comparators arranged on the upper substrate 10 have symbols The description is changed to the comparator 201. As described later, since the latch circuit 52 may have the same configuration as the latch circuit 52 described with reference to FIG. 2 and FIG. 3, the description of the latch circuit 52 is continued without changing the symbol.

參照圖4，對上基板10採用配置像素21與比較器201，而將來自像素21之信號與斜坡信號進行比較之構成。採用將來自比較器201之比較結果供給至配置於下基板11之閂鎖電路52之構成。對閂鎖電路52供給表示時間資訊之碼(Code)，將來自像素21之信號轉換成數位信號，而輸出至後段。 Referring to FIG. 4, a configuration is adopted in which a pixel 21 and a comparator 201 are arranged on the upper substrate 10 and a signal from the pixel 21 is compared with a ramp signal. A configuration is adopted in which the comparison result from the comparator 201 is supplied to the latch circuit 52 arranged on the lower substrate 11. A code (Time) indicating time information is supplied to the latch circuit 52, and a signal from the pixel 21 is converted into a digital signal and output to a subsequent stage.

於上基板10，可配置構成比較器201之全體之部分，亦可配置比較器201之主要部分。於下基板11，配置構成配置於上基板10之ADC31之其餘部分。 On the upper substrate 10, the entire part constituting the comparator 201 may be arranged, and the main part of the comparator 201 may also be arranged. On the lower substrate 11, the rest of the ADC 31 disposed on the upper substrate 10 is arranged.

如此，於上基板10配置像素21與比較器201，於下基板11配置閂鎖電路52。如此，於圖4所示之攝像裝置中，並非如圖2所示之以像素21與ADC31之區分於上基板10與下基板11分別配置像素21與ADC31，而是採用將ADC31分割而分別配置於上基板10與下基板11之構成。 In this way, the pixels 21 and the comparator 201 are arranged on the upper substrate 10, and the latch circuit 52 is arranged on the lower substrate 11. In this way, in the imaging device shown in FIG. 4, the pixels 21 and ADC 31 are not respectively arranged on the upper substrate 10 and the lower substrate 11 by dividing the pixels 21 and ADC 31 as shown in FIG. 2, but the ADC 31 is divided and arranged separately. The structure of the upper substrate 10 and the lower substrate 11.

圖5顯示與圖4對應之攝像裝置之電路構成例。對圖5所示之電路構成例中之與圖3所示之電路構成例相同之部分，標註相同之符號，並省略其說明。如上所述，像素21與閂鎖電路52之構成與圖3所示之電路構成相同，相當於比較器201之電路部分不同。 FIG. 5 shows an example of a circuit configuration of the imaging device corresponding to FIG. 4. In the circuit configuration example shown in FIG. 5, the same parts as those in the circuit configuration example shown in FIG. 3 are denoted by the same reference numerals, and descriptions thereof are omitted. As described above, the configuration of the pixel 21 and the latch circuit 52 is the same as the circuit configuration shown in FIG. 3, and it is equivalent to that the circuit portion of the comparator 201 is different.

於圖3所示之電路構成中，採用將浮動擴散103之電壓信號供給至放大電晶體105之構成，於圖5所示之電路構成中，係以供給至比較電晶體(Cmp)221之方式構成。 In the circuit configuration shown in FIG. 3, a configuration in which a voltage signal of the floating diffusion 103 is supplied to the amplification transistor 105 is adopted. In the circuit configuration shown in FIG. 5, a comparison transistor (Cmp) 221 is used. Make up.

即，於圖5所示之電路構成中，採用將浮動擴散103連接於比較電晶體(Cmp)221之閘極之構成。比較電晶體221不進行源極跟隨器動作，而是進行電壓值之比較動作。比較電晶體221之一主電極不連接於電源電壓，而是連接於斜坡(Ramp)信號之配線，另一主電極係通過 信號線(SL：Signal Line)與緩衝器224之閘極連接。 That is, in the circuit configuration shown in FIG. 5, a configuration in which the floating diffusion 103 is connected to a gate of a comparison transistor (Cmp) 221 is adopted. The comparison transistor 221 does not perform a source follower operation, but performs a comparison operation of a voltage value. One of the main electrodes of the comparison transistor 221 is not connected to the power supply voltage, but is connected to the wiring of the ramp signal, and the other main electrode is connected through A signal line (SL: Signal Line) is connected to the gate of the buffer 224.

SL222具有寄生電容，根據構成不同而具有電容元件。Sr223係作為將SL222重設成特定之電壓、例如此處為3V之電晶體而繼續說明。來自緩衝器224之輸出係供給至藉由例如Cu-Cu接合而接合之下基板11之閂鎖電路52。 SL222 has parasitic capacitance, and has a capacitive element depending on the configuration. Sr223 is continued as a transistor that resets SL222 to a specific voltage, for example, 3V here. The output from the buffer 224 is supplied to the latch circuit 52 of the lower substrate 11 which is bonded by, for example, Cu-Cu bonding.

下基板11側配置有包含閂鎖行161-1至161-10之閂鎖電路52。來自緩衝器224之輸出係輸入至接通、斷開閂鎖電路52之電晶體181之閘極。閂鎖電路202之構成與圖3所示之閂鎖電路52之構成相同，進行相同之處理，不同點係以PMOS(Positive channel Metal Oxide Semiconductor：正通道金屬氧化物半導體)構成電晶體181。 A latch circuit 52 including latch rows 161-1 to 161-10 is arranged on the lower substrate 11 side. The output from the buffer 224 is input to the gate of the transistor 181 which turns the latch circuit 52 on and off. The configuration of the latch circuit 202 is the same as that of the latch circuit 52 shown in FIG. 3, and the same processing is performed, except that a transistor 181 is formed by a PMOS (Positive Channel Metal Oxide Semiconductor).

如此，於圖5所示之電路構成中，與圖3所示之電路構成相比，比較器51之構成較為簡化。又，採用省略負載MOS121之構成。圖3所示之比較器51與負載MOS121係類比電路，於其性能有可能產生不均。因此，有難以減小電晶體，或降低電壓之背景。 Thus, in the circuit configuration shown in FIG. 5, the configuration of the comparator 51 is simplified compared with the circuit configuration shown in FIG. 3. A configuration in which the load MOS121 is omitted is adopted. Comparator 51 and load MOS121 shown in FIG. 3 are analog circuits, which may cause uneven performance. Therefore, there is a background in which it is difficult to reduce the transistor or reduce the voltage.

然而，由於圖5所示之比較器51係不使用差動放大電路，而以比較電晶體221構成，故其構成為簡化者。又，於圖5所示之電路構成中，採用削除負載MOS121之構成。藉由採用此種構成，可減少電晶體之數量，而可將比較器201之構成小型化。 However, since the comparator 51 shown in FIG. 5 is configured using a comparison transistor 221 without using a differential amplifier circuit, its configuration is simplified. In addition, in the circuit configuration shown in FIG. 5, a configuration in which the load MOS121 is removed is adopted. By adopting such a configuration, the number of transistors can be reduced, and the configuration of the comparator 201 can be miniaturized.

此處，於圖5所示之電路構成中，對將浮動擴散103之電壓數位化之機制進行說明。 Here, in the circuit configuration shown in FIG. 5, a mechanism for digitizing the voltage of the floating diffusion 103 will be described.

首先，於Sr223輸入脈衝，將SL222重設成3V。藉此，緩衝器224進行低位準(0V)之輸出。由於來自緩衝器224之輸出較低，故閂鎖行161之PMOS(電晶體181)接通，成為於閂鎖行161之電容元件流通表示時間之碼值D0至D9之狀態。 First, input a pulse to Sr223 to reset SL222 to 3V. As a result, the buffer 224 outputs a low level (0V). Since the output from the buffer 224 is low, the PMOS (transistor 181) of the latch line 161 is turned on, and a state in which the code values D0 to D9 representing time are flowing through the capacitive elements of the latch line 161 is turned on.

此處，圖6中顯示將斜坡電壓自2V逐漸降低時之斜坡電壓與SL222之SL信號之變化。於斜坡電壓(圖中記述為Ramp之實線)橫斷來 自比較電晶體221之通道電壓(圖中記述為Amp通道電壓之虛線)時(時刻T1)，比較電晶體221導通。 Here, FIG. 6 shows the change of the ramp voltage and the SL signal of SL222 when the ramp voltage is gradually decreased from 2V. Cross the ramp voltage (depicted as the solid line of Ramp in the figure) When the channel voltage of the comparison transistor 221 (shown as a dashed line of the Amp channel voltage in the figure) (time T1), the comparison transistor 221 is turned on.

當比較電晶體221導通時，SL222之電壓(圖中記述為SL之實線)以與斜坡電壓相等之方式瞬間降低。其結果，越過緩衝器224之PMOS之接通/斷開邊界，緩衝器224反轉成高位準。 When the comparison transistor 221 is turned on, the voltage of SL222 (depicted as the solid line of SL in the figure) decreases instantaneously in a manner equal to the ramp voltage. As a result, the PMOS on / off boundary of the buffer 224 is crossed, and the buffer 224 is inverted to a high level.

如此一來，閂鎖行161之PMOS(電晶體181)成為斷開，閂鎖電容與碼信號切斷，而保持該時點之值(碼D0至D9之各個值)。藉由此種處理，將浮動擴散103之電壓數位化。 In this way, the PMOS (transistor 181) of the latch row 161 is turned off, the latch capacitor is cut off from the code signal, and the value at that time (the values of the codes D0 to D9) is maintained. With this processing, the voltage of the floating diffusion 103 is digitized.

參照圖7，再次對斜坡電壓與SL222之SL信號之變化進行說明。圖7之上圖係比較電晶體221(Cmp221)，下圖係表示電位之圖。時刻T0時之斜坡(Ramp)電壓係2V，SL222之電壓係3V。圖7中下方向係正方向。又，Amp通道電壓於圖7中顯示為VFD。 Referring to FIG. 7, the change of the ramp voltage and the SL signal of SL222 will be described again. The upper graph of FIG. 7 is a comparison of the transistor 221 (Cmp221), and the lower graph is a graph of potentials. The ramp voltage at time T0 is 2V, and the voltage of SL222 is 3V. The lower direction in FIG. 7 is the positive direction. The Amp channel voltage is shown as VFD in FIG. 7.

斜坡電壓之電壓自時刻T0逐漸降低。時刻T0’係滿足 The voltage of the ramp voltage gradually decreases from time T0. Time T0 ’is satisfied

時刻T0<時刻T0’<時刻T1 Time T0 <Time T0 ’<Time T1

之時刻。於時刻T0’之時點，由於斜坡電壓仍為大於來自比較電晶體221之通道電壓(VFD)之狀態(於圖7所示之狀態下為電位較低之狀態)，故SL222之電壓仍為3V。 Moment. At time T0 ', the voltage of the SL222 is still 3V because the ramp voltage is still higher than the channel voltage (VFD) from the comparison transistor 221 (the state is lower in the state shown in Figure 7). .

當到達時刻T1時，斜坡電壓與Amp通道電壓(VFD)成為相同電壓(電位之狀態相同)。當超過時刻T1時，由於斜坡電壓之電位高於Amp通道電壓(VFD)之電位，故瞬間於SL222側流入電子。其後，如時刻T2所示，斜坡電壓之電位與SL222之電位係以相同大小上升。換言之，SL222之電壓係以與斜坡電壓之下降相同之方式下降。 When the time T1 is reached, the ramp voltage and the Amp channel voltage (VFD) become the same voltage (the state of the potential is the same). When the time T1 is exceeded, since the potential of the ramp voltage is higher than the potential of the Amp channel voltage (VFD), electrons flow into the SL222 side instantly. Thereafter, as shown at time T2, the potential of the ramp voltage and the potential of SL222 rise by the same magnitude. In other words, the voltage of SL222 drops in the same way as the drop of the ramp voltage.

如此，由於電位變化，故若顯示電壓之關係，則成為如圖6所示般。於比較電晶體221中，可檢測斜坡電壓與Amp通道電壓成為大致相同之時序。當斜坡電壓與Amp通道電壓成為大致相同時，如上所述，比較電晶體221成為導通之狀態，越過緩衝器224之PMOS之接通/ 斷開邊界，緩衝器224反轉成高位準。 In this way, since the potential changes, the relationship between the voltages is as shown in FIG. 6. In the comparison transistor 221, the detectable ramp timing and the Amp channel voltage become approximately the same timing. When the ramp voltage and the Amp channel voltage become approximately the same, as described above, the comparison transistor 221 is turned on, and the PMOS over the buffer 224 is turned on / Breaking the boundary, the buffer 224 is inverted to a high level.

此種動作係於所有ADC31中同時進行，其後，經閂鎖之信號係逐列依序讀取至感測放大器33。自感測放大器33經由輸出電路32而輸出。 This action is performed simultaneously in all ADCs 31, and thereafter, the latched signals are sequentially read to the sense amplifiers 33 one by one. The self-sense amplifier 33 is output via the output circuit 32.

藉由圖4、圖5所示之構成、及參照圖6說明之動作，將比較器201之尺寸大幅小型化。又，與比較器201之尺寸變小同時配置於上基板10。 With the configuration shown in FIGS. 4 and 5 and the operation described with reference to FIG. 6, the size of the comparator 201 is greatly reduced. The comparator 201 is arranged on the upper substrate 10 at the same time as the size of the comparator 201 becomes smaller.

藉由以緩衝器224之輸出連接上基板10與下基板11，可將上基板10設為3V系列，將下基板11設為1.5V系列。如此，藉由可分別以不同之電壓驅動上基板10與下基板11，可分開上基板10與下基板11之電源。又，可將上基板10與下基板11之製造過程分別最佳化。 By connecting the upper substrate 10 and the lower substrate 11 with the output of the buffer 224, the upper substrate 10 can be set as a 3V series, and the lower substrate 11 can be set as a 1.5V series. In this way, by driving the upper substrate 10 and the lower substrate 11 with different voltages, the power of the upper substrate 10 and the lower substrate 11 can be separated. In addition, the manufacturing processes of the upper substrate 10 and the lower substrate 11 can be optimized separately.

再者，上基板10可分配為類比電路，下基板11可分配為數位電路，而可消除較小之類比電路與數位電路接近而混雜之情況。其結果，於消除類比與數位之邊界區域方面亦可小型化，於消除如不同之電源混亂進入之浪費之方面亦可小型化。 Furthermore, the upper substrate 10 can be assigned as an analog circuit, and the lower substrate 11 can be assigned as a digital circuit, which can eliminate the situation where the smaller analog circuit is close to and mixed with the digital circuit. As a result, it can be miniaturized to eliminate the boundary area between analog and digital, and it can also be miniaturized to eliminate the wasteful entry of different power sources.

另，於圖5等中圖示1.5V、2.5V、3V等具體之電壓，該電壓係一例，並非表示限定之記載。又，於以下之說明中，作為一例，亦舉出具體之電壓進行說明，但並非表示限定之記載。 In addition, specific voltages such as 1.5V, 2.5V, and 3V are shown in FIG. 5 and the like. This voltage is an example and is not a description of limitation. In addition, in the following description, as an example, a specific voltage is also described, but it is not intended to indicate a limitation.

然而，Sr223之汲極側之電源較理想為高於緩衝器224之電源。於圖5中，Sr223之電源係例示為3V，緩衝器224之電源係例示為2.5V。作為其理由，原因在於，由於SL222浮動，故電壓隨時間變動，但藉由設定為較緩衝器224之電源高，可獲得PMOS之斷開狀態之容限。 However, the power on the drain side of Sr223 is preferably higher than the power on the buffer 224. In FIG. 5, the power supply of Sr223 is exemplified as 3V, and the power supply of buffer 224 is exemplified as 2.5V. As the reason, the reason is that the voltage varies with time because the SL222 is floating, but by setting it higher than the power supply of the buffer 224, the tolerance of the off state of the PMOS can be obtained.

可採用藉由將Sr223之閘極電壓升壓，或將Sr223設為耗盡型電晶體而通過3V之構成。或，雖未圖示，但亦可將Sr223設為PMOS電晶體而提高閾值，或將斷開時之閘極電壓升壓。 It can be configured by boosting the gate voltage of Sr223, or setting Sr223 as a depletion transistor and passing 3V. Or, although not shown, Sr223 can be set as a PMOS transistor to increase the threshold, or boost the gate voltage when it is turned off.

作為獲得PMOS之斷開狀態之容限之另一方法，若於SL222安裝 電容元件，則可抑制SL222因暗電流而電壓變化。 As another method to obtain the tolerance of the disconnected state of PMOS, if installed in SL222 Capacitive elements can suppress the voltage change of SL222 due to dark current.

像素21之重設汲極之電源、重設之閾值、及比較電晶體221之閾值較理想為以滿足以下之條件之方式設計。 The power of the reset drain of the pixel 21, the reset threshold, and the threshold of the comparison transistor 221 are ideally designed to satisfy the following conditions.

重設後之浮動擴散103之電壓係設計成能夠完全接收自光電二極體101傳送之電荷之電壓。又，重設後之浮動擴散103之電壓(比較電晶體221之閘極電壓)係設計成可於斜坡電壓為初始之2V時斷開比較電晶體221之電壓。 The voltage of the reset floating diffusion 103 is designed to be able to completely receive the voltage of the electric charge transmitted from the photodiode 101. In addition, the voltage of the floating diffusion 103 after resetting (the gate voltage of the comparison transistor 221) is designed to turn off the voltage of the comparison transistor 221 when the ramp voltage is the initial 2V.

閂鎖電路52之電源較理想為低於緩衝器224。理由在於，於PMOS電晶體斷開時，可確實地切斷閂鎖電容與碼(Code)信號。於將像素21之光電二極體101之面積最大化之情形時，亦可採用如以SL222連接上基板10與下基板11，將緩衝器224與Sr223配置於下基板11之構成。 The power of the latch circuit 52 is preferably lower than the buffer 224. The reason is that when the PMOS transistor is turned off, the latch capacitor and the code signal can be reliably cut off. When the area of the photodiode 101 of the pixel 21 is maximized, a configuration in which the upper substrate 10 and the lower substrate 11 are connected by SL222, and the buffer 224 and Sr223 are arranged on the lower substrate 11 may be adopted.

<各層之電路之配置之另一形態> <Another Configuration of Circuit Arrangement of Each Layer>

圖8中顯示用以實現攝像裝置之進一步之小型化之各層之電路之配置之另一形態之電路構成例。對與圖5相同之部分，標註相同之符號，並適當省略其說明。於圖8所示之電路構成中，採用以NMOS(Negative channel Metal Oxide Semiconductor：負通道金屬氧化物半導體)構成全部，使動作點一致之構造。 FIG. 8 shows a circuit configuration example of another configuration of the circuit arrangement of each layer for further miniaturization of the imaging device. The same parts as in FIG. 5 are denoted by the same reference numerals, and descriptions thereof are appropriately omitted. In the circuit configuration shown in FIG. 8, an NMOS (Negative channel Metal Oxide Semiconductor) structure is adopted to make all of them to make the operating points uniform.

於圖8所示之電路構成中，上基板10係基本上低電源為0V，高電源為3V，下基板11係基本上低電源為1.5V，高電源為3V。即，採用上基板10與下基板11之高電源側成為共通電壓之構成。 In the circuit configuration shown in FIG. 8, the upper substrate 10 is basically a low power 0V, the high power is 3V, and the lower substrate 11 is a low power 1.5V, and the high power is 3V. That is, a configuration is adopted in which the high power supply sides of the upper substrate 10 and the lower substrate 11 have a common voltage.

下基板11之與像素21對應之部分僅為閂鎖電路52。配置於上基板10之電路與配置於下基板11之閂鎖電路52全部包含NMOS。藉由全部以NMOS構成，可採用省略圖5所示之電路構成所必需之緩衝器224之構成。於圖8中顯示將Sr223配置於上基板10之例。 The portion of the lower substrate 11 corresponding to the pixel 21 is only the latch circuit 52. Both the circuit disposed on the upper substrate 10 and the latch circuit 52 disposed on the lower substrate 11 include NMOS. Since all of them are composed of NMOS, a configuration in which the buffer 224 necessary for the circuit configuration shown in FIG. 5 is omitted can be adopted. An example in which Sr223 is arranged on the upper substrate 10 is shown in FIG. 8.

圖8所示之電路構成之動作亦與圖5所示之電路構成之動作基本 相同。首先，於Sr223輸入脈衝，將SL222重設成3V。於該狀態下，閂鎖行161之電晶體181接通，對閂鎖行161之電容元件供給表示時間之碼值D0至D9。 The operation of the circuit configuration shown in FIG. 8 is also basically the same as the operation of the circuit configuration shown in FIG. 5. the same. First, input a pulse to Sr223 to reset SL222 to 3V. In this state, the transistor 181 of the latch row 161 is turned on, and the capacitor elements of the latch row 161 are supplied with code values D0 to D9 indicating time.

此處，使斜坡電壓自1.5V逐漸降低。該情形時，斜坡電壓並非自2V，而是自1.5V開始之方面係與圖5所示之電路構成時不同。自斜坡電壓橫斷比較電晶體221之通道電壓時，比較電晶體221導通。然後，SL222之電壓以與斜坡電壓相等之方式瞬間降低，閂鎖行161成為斷開，閂鎖電容與碼信號切斷，而保持該時點之值。 Here, the ramp voltage is gradually decreased from 1.5V. In this case, the point where the ramp voltage does not start from 2V is different from that when the circuit configuration shown in FIG. 5 is started from 1.5V. When the channel voltage of the comparison transistor 221 is crossed by the self-ramp voltage, the comparison transistor 221 is turned on. Then, the voltage of SL222 decreases instantaneously in a manner equal to the ramp voltage, the latch line 161 is turned off, the latch capacitor is cut off from the code signal, and the value at that time is maintained.

由於僅與閂鎖行161之像素連接之電晶體171之閘極較1.5V(下基板11之低電源)低，故可確實地斷開而保持信號。因此，閂鎖行161所包含之電晶體171-1至171-10之各閘極之絕緣膜較佳為厚且高耐壓化。 Since the gate of the transistor 171 connected to only the pixels of the latch row 161 is lower than 1.5V (low power of the lower substrate 11), it can be reliably disconnected to maintain the signal. Therefore, it is preferable that the insulating films of the gates of the transistors 171-1 to 171-10 included in the latch row 161 are thick and have a high withstand voltage.

於圖8所示之電路構成中，電壓容限較圖5所示之電路構成更少，可實現攝像裝置之進一步之小型化。 In the circuit configuration shown in FIG. 8, the voltage tolerance is smaller than that of the circuit configuration shown in FIG. 5, and further miniaturization of the imaging device can be achieved.

又，圖3所示之電路構成之放大電晶體105由於一面流通電流一面輸出信號，故消耗電力變大，但根據圖5或圖8所示之電路構成，由於獲得來自比較電晶體221之輸出方面無需定常電流，故可實現低消耗電力。 In addition, the amplified transistor 105 of the circuit configuration shown in FIG. 3 consumes a large amount of power because it outputs a signal while flowing a current. However, according to the circuit configuration shown in FIG. 5 or FIG. 8, the output from the comparison transistor 221 is obtained. Since no constant current is required, low power consumption can be achieved.

又，於放大電晶體105中，由於一面流通電流一面輸出信號，故產生熱雜訊之可能性較高，但根據圖5或圖8所示之電路構成，由於比較電晶體221不流通電流，故不會產生熱雜訊。因此，可降低由熱雜訊造成之影響。 Furthermore, in the amplified transistor 105, since a signal is output while a current is flowing, the possibility of generating thermal noise is high. However, according to the circuit configuration shown in FIG. 5 or FIG. Therefore, no thermal noise is generated. Therefore, the influence caused by thermal noise can be reduced.

另，SL(信號線)222成為浮動，由於如此一來會於缺陷像素中存在由暗電流引起之電壓變化，故此處亦可採用如以微小電流引導至電源側而避免浮動之構成。 In addition, the SL (signal line) 222 becomes floating. As a result, there is a voltage change caused by dark current in the defective pixel. Therefore, it is also possible to adopt a configuration in which a small current is guided to the power supply side to avoid floating.

參照圖9、圖10，對關於讀取之處理追加說明。於圖9、圖10 中，為了便於說明，以於1像素配置1個ADC31進行說明。 Referring to FIG. 9 and FIG. 10, a description will be given of the reading processing. In Figure 9, Figure 10 In the following description, for convenience of explanation, one ADC31 is arranged in one pixel.

藉由應用本技術，可將ADC31小型化，即使於1像素配置1個ADC31，亦可將上基板10與下基板11之任一基板小型化。因此，亦可採用如於1像素配置1個ADC31之構成。因此，此處，以於1像素配置1個ADC31繼續說明。 By applying this technology, the ADC 31 can be miniaturized, and even if one ADC 31 is arranged in one pixel, either one of the upper substrate 10 and the lower substrate 11 can be miniaturized. Therefore, it is also possible to adopt a configuration in which one ADC31 is arranged in one pixel. Therefore, here, the description will be continued with one ADC31 arranged in one pixel.

又，如參照圖5或圖8說明般，ADC31係分割而分別配置於上基板10與下基板11，於參照圖9、圖10之說明中，將分別配置於上基板10與下基板11之部分統一記載為ADC31。 In addition, as explained with reference to FIG. 5 or FIG. 8, the ADC 31 is divided and disposed on the upper substrate 10 and the lower substrate 11 respectively. In the description with reference to FIG. 9 and FIG. Partially documented as ADC31.

圖9、圖10之粗框之箭頭符號表示信號之流動。圖9之左側所示之圖顯示AD轉換為10bit，且具備10個閂鎖行161之情形，右側所示之圖顯示此種情形時之讀取之順序。 The arrows in the thick boxes in Figures 9 and 10 indicate the signal flow. The graph shown on the left side of FIG. 9 shows a case where AD is converted to 10 bits and has 10 latch rows 161, and the graph shown on the right side shows the reading order in this case.

於像素21中，進行利用重設電晶體104進行之重設動作、與利用傳送電晶體102進行之傳送動作。於重設動作中，將藉由重設電晶體104重設時之浮動擴散103之電壓作為重設成分(P相)自像素21輸出至垂直信號線(未圖示)。 In the pixel 21, a reset operation using the reset transistor 104 and a transfer operation using the transfer transistor 102 are performed. In the reset operation, the voltage of the floating diffusion 103 when the reset transistor 104 is reset is output as a reset component (P-phase) from the pixel 21 to a vertical signal line (not shown).

於傳送動作中，將藉由傳送電晶體102傳送累積於光電二極體101之電荷時之浮動擴散103之電壓作為信號成分(D相)輸出至垂直信號線。 In the transfer operation, the voltage of the floating diffusion 103 when the charge accumulated in the photodiode 101 is transferred by the transfer transistor 102 is output as a signal component (phase D) to the vertical signal line.

為了進行此種讀取，如圖9之右圖所示，首先進行曝光，曝光後，重設浮動擴散103，將其位準AD轉換(P相期間)。於P相期間自閂鎖電路261(圖5或圖8)輸出之值係於ADC31之每1列讀取，而儲存至訊框記憶體301。 In order to perform such reading, as shown in the right diagram of FIG. 9, exposure is performed first, and after exposure, the floating diffusion 103 is reset and its level is AD-converted (P-phase period). The value output from the latch circuit 261 (FIG. 5 or FIG. 8) during the P phase is read in each row of the ADC 31 and stored in the frame memory 301.

P相期間之後，將光電二極體101之光電子傳送至浮動擴散103，將其位準AD轉換(D相期間)。於D相期間，自閂鎖電路261(圖5或圖8)輸出之值係於ADC31之每1列讀取，而供給至減法器302。 After the P-phase period, the photoelectrons of the photodiode 101 are transferred to the floating diffusion 103, and their levels are AD-converted (D-phase period). During the D phase, the value output from the latch circuit 261 (FIG. 5 or FIG. 8) is read in each column of the ADC 31 and is supplied to the subtractor 302.

減法器302係自記憶於訊框記憶體301之於P相期間所讀取之值減 去於D相期間所讀取之值，而獲得信號。此種曝光、P相、D相係所有像素同時進行。 The subtracter 302 subtracts the value read from the frame memory 301 during the P phase. The signal is obtained by going to the value read during the D phase. This exposure, phase P, and phase D are all performed simultaneously.

將1個ADC31分配於複數個像素21之情形時，「P相-讀取-D相-讀取」係以每1像素依序進行。 When one ADC 31 is allocated to a plurality of pixels 21, the "P-phase-reading-D-phase-reading" is performed sequentially for each pixel.

圖10之左側所示之圖顯示AD轉換為10bit，且具備20個閂鎖行161之情形，右側所示之圖係顯示此種情形時之讀取之順序之圖。藉由具備20個閂鎖行161，成為可分別保持P相期間之10位元之值與D相期間之10位元之值之構成。 The diagram on the left side of FIG. 10 shows a case where AD is converted to 10 bits and has 20 latch rows 161. The diagram on the right side is a diagram showing the reading sequence in this case. By having 20 latch lines 161, it is possible to maintain a value of 10 bits in the P-phase period and a value of 10 bits in the D-phase period.

如此，於ADC31具有P相用與D相用之兩者之閂鎖之情形時，可採用削減訊框記憶體301之構成，而可省略對訊框記憶體301傳送來自ADC31之值之處理。 In this way, when the ADC 31 has latches for both the P-phase and the D-phase, the configuration of reducing the frame memory 301 can be adopted, and the process of transmitting the value from the ADC 31 to the frame memory 301 can be omitted.

圖10所示之構成之情形時，曝光後，重設浮動擴散103，將其位準AD轉換(P相期間)。於P相用之閂鎖保存值。然後，於下一個時序，將光電二極體101之光電子傳送至浮動擴散103，將該位準AD轉換(D相期間)，並保存於D相用之閂鎖。 In the case of the configuration shown in FIG. 10, after exposure, the floating diffusion 103 is reset, and its level is AD-converted (P-phase period). The value is stored in the latch for phase P. Then, at the next timing, the photoelectrons of the photodiode 101 are transferred to the floating diffusion 103, the level is AD-converted (D-phase period), and stored in the latch for the D-phase.

分別保存於P相用之閂鎖與D相用之閂鎖之值係於ADC31之每1列讀取，且以減法器311減去而輸出信號。 The values stored in the latches for phase P and the latches for phase D are read in each column of ADC31, and are subtracted by subtracter 311 to output signals.

如此進行來自ADC31之讀取。另，攝像裝置、訊框記憶體301、減法器302(或311)可一體化，亦可為不同晶片。 The reading from ADC31 is performed in this manner. In addition, the camera device, the frame memory 301, and the subtractor 302 (or 311) may be integrated, or may be different chips.

於上述實施形態中，雖主要對像素21與ADC31追加說明，但亦可加入ADC31以外之電路，亦可加入針對例如經閂鎖之資料之數位處理。 In the above-mentioned embodiment, although the pixel 21 and the ADC 31 are mainly described in addition, circuits other than the ADC 31 may be added, and digital processing for, for example, latched data may also be added.

另，於上述實施形態中，亦可採用將NMOS與PMOS全部對調之構成。且，於採用此種構成之情形時，可藉由將電壓設為相反而動作。 In addition, in the above-mentioned embodiment, a configuration in which all NMOS and PMOS are interchanged may be adopted. When such a configuration is adopted, the operation can be performed by setting the voltage to the opposite.

<降低閂鎖數之構成> <Composition for reducing the number of latches>

於上述實施形態中，舉出將ADC31所包含之比較器201與閂鎖電路52分別配置於上基板10與下基板11，且例如使用比較電晶體221構成比較器201之構成之情形為例進行說明。 In the above embodiment, the case where the comparator 201 and the latch circuit 52 included in the ADC 31 are arranged on the upper substrate 10 and the lower substrate 11 respectively, and the configuration of the comparator 201 using the comparison transistor 221 is taken as an example. Instructions.

接著，對藉由削減閂鎖電路52之閂鎖行161之數量，實現閂鎖電路52之小型化進行說明。 Next, the miniaturization of the latch circuit 52 will be described by reducing the number of the latch rows 161 of the latch circuit 52.

圖11係顯示攝像裝置之電路構成之圖。將圖3所示之攝像裝置之電路構成與圖11所示之電路構成進行比較，閂鎖電路52與閂鎖電路402之構成不同。不同點在於：圖3所示之閂鎖電路52具有閂鎖行161-1至161-10之10個閂鎖行161，但圖11所示之閂鎖電路402具有閂鎖行161-1至161-5之5個閂鎖行161。 FIG. 11 is a diagram showing a circuit configuration of the imaging device. Comparing the circuit configuration of the imaging device shown in FIG. 3 with the circuit configuration shown in FIG. 11, the configurations of the latch circuit 52 and the latch circuit 402 are different. The difference is that the latch circuit 52 shown in FIG. 3 has 10 latch rows 161 of the latch rows 161-1 to 161-10, but the latch circuit 402 shown in FIG. 11 has the latch rows 161-1 to 161-5 of 5 latch rows 161.

該情形時，顯示將閂鎖行161之數量自10個減半為5個之例。如此，即便為減少閂鎖行161之數量之情形，藉由進行如以下所說明之處理，亦可與具備10個閂鎖行161之情形相同，獲得10位元之值。 In this case, an example is shown in which the number of latch rows 161 is halved from ten to five. In this way, even in a case where the number of the latch rows 161 is reduced, by performing processing as described below, a value of 10 bits can be obtained in the same manner as in the case where ten latch rows 161 are provided.

圖11所示之電路構成例顯示相對於圖3所示之電路構成減少閂鎖行161之例，亦可採用相對於圖5或圖8所示之電路構成減少閂鎖行161之電路構成。圖12係顯示相對於圖5所示之電路構成減少閂鎖行161之電路構成之圖。 The example of the circuit configuration shown in FIG. 11 shows an example in which the latch line 161 is reduced compared to the circuit configuration shown in FIG. 3. The circuit configuration in which the latch line 161 is reduced compared to the circuit configuration shown in FIG. 5 or FIG. FIG. 12 is a diagram showing a circuit configuration in which the latch line 161 is reduced compared to the circuit configuration shown in FIG. 5.

將圖5所示之攝像裝置之電路構成與圖12所示之電路構成進行比較，閂鎖電路202與閂鎖電路402之構成不同。不同點在於：圖5所示之閂鎖電路202具有閂鎖行161-1至161-10之10個閂鎖行161，但圖12所示之閂鎖電路402具有閂鎖行161-1至161-5之5個閂鎖行161。 Comparing the circuit configuration of the imaging device shown in FIG. 5 with the circuit configuration shown in FIG. 12, the configurations of the latch circuit 202 and the latch circuit 402 are different. The difference is that the latch circuit 202 shown in FIG. 5 has 10 latch rows 161 of the latch rows 161-1 to 161-10, but the latch circuit 402 shown in FIG. 12 has the latch rows 161-1 to 161-5 of 5 latch rows 161.

於圖8所示之攝像裝置之電路構成中，雖未圖示，但藉由應用以下之處理，亦可削減閂鎖電路202所包含之閂鎖行161之數量。 Although the circuit configuration of the imaging device shown in FIG. 8 is not shown, the number of latch lines 161 included in the latch circuit 202 can be reduced by applying the following processing.

閂鎖電路402以外之構成可採用與圖3、圖5、或圖8所示之電路構成相同之構成，關於相同之構成之部分，由於說明重複，故於以下之說明中適當省略。於以下之說明中，使用圖11所示之電路構成繼續 說明。 The configuration other than the latch circuit 402 may be the same as the circuit configuration shown in FIG. 3, FIG. 5, or FIG. 8. Since the description of the same configuration is repeated, it is appropriately omitted in the following description. In the following description, the circuit configuration shown in FIG. 11 is used to continue Instructions.

圖11所示之電路構成之情形時，來自比較器51之輸出係輸入於接通、斷開閂鎖電路402之電晶體171之閘極。於閂鎖電路402中，由於包含5個閂鎖行161-1至161-5，故有5位元，輸入電壓為高或低之碼值D0至D4。 In the case of the circuit configuration shown in FIG. 11, the output from the comparator 51 is input to the gate of the transistor 171 that turns on and off the latch circuit 402. In the latch circuit 402, since there are five latch rows 161-1 to 161-5, there are 5 bits, and the input voltages are high or low code values D0 to D4.

於比較器51之輸出為高時，閂鎖電路402成為接通之狀態，碼值D0至D4進入閂鎖電容，為低時，閂鎖電路402成為斷開之狀態，碼值D0至D4不進入閂鎖電容。閂鎖電容之電壓之高/低係藉由下方之輸出段401，作為Out D0至D4(以下記述為輸出D0至D4)輸出至下一段之感測放大器33(圖1)。 When the output of the comparator 51 is high, the latch circuit 402 is turned on, and the code values D0 to D4 enter the latch capacitor. When it is low, the latch circuit 402 is turned off, and the code values D0 to D4 are not. Enter the latch capacitor. The high / low voltage of the latch capacitor is output to the sense amplifier 33 (Figure 1) as Out D0 to D4 (hereinafter referred to as outputs D0 to D4) through the output section 401 below.

於此種構成中，基本動作亦與上述之情形相同。即，於比較器51中，輸入如圖13A所示之斜坡信號。斜坡信號(表述為Ramp之實線)係隨著時間經過其電壓逐漸降低之信號。 In this configuration, the basic operation is the same as that described above. That is, the comparator 51 receives a ramp signal as shown in FIG. 13A. The ramp signal (expressed as a solid line of Ramp) is a signal whose voltage gradually decreases over time.

輸入至比較器51之斜坡信號之斜坡電壓高於自像素21側經由信號線輸入之信號之電壓(於圖13A中，表述為信號位準之虛線)之情形時，來自比較器51之輸出成為高，閂鎖電路402成為接通之狀態。於閂鎖電路402為接通之狀態時，於閂鎖電容中，將隨著時間遞增計數之碼值D0至D4供給至閂鎖行161-1至161-4之各者。 When the ramp voltage of the ramp signal input to the comparator 51 is higher than the voltage of the signal input from the pixel 21 side via the signal line (in FIG. 13A, expressed as a dotted line of the signal level), the output from the comparator 51 becomes High, the latch circuit 402 is turned on. When the latch circuit 402 is in the ON state, code values D0 to D4 which are counted up with time are supplied to each of the latch rows 161-1 to 161-4 in the latch capacitor.

然後，斜坡電壓逐漸變低、且變得低於信號線之電壓時，比較器51之輸出反轉，閂鎖電路402成為斷開之狀態。將成為斷開之狀態時之碼值保持於閂鎖電容。藉此，將像素21之輸出數位化。 When the ramp voltage gradually decreases and becomes lower than the voltage of the signal line, the output of the comparator 51 is inverted, and the latch circuit 402 is turned off. The code value at the time of the OFF state is held in the latch capacitor. This digitizes the output of the pixel 21.

如此般進行於閂鎖電路402之處理。此處，再次參照圖3。如圖3所示之閂鎖電路52般，具備閂鎖行161-1至161-10之10個閂鎖之情形時，如圖13B所示，輸出“0000000000”至“1111111111”之10位元之值。 The processing in the latch circuit 402 is performed in this manner. Here, refer to FIG. 3 again. As shown in the latch circuit 52 shown in FIG. 3, when there are ten latches in the latch rows 161-1 to 161-10, as shown in FIG. 13B, 10 bits of "0000000000" to "1111111111" are output Value.

即，閂鎖行161有10個，如圖13A般，一面比較斜坡電壓與來自 像素之信號，一面於10bit之閂鎖輸入自“0000000000”遞增計數至“1111111111”之碼值D0至D9。構成為於斜坡電壓與信號電壓之上下關係反轉時，由於自碼值切斷閂鎖，並保持該值，故只要讀取該保持之值，即可知曉信號位準。 That is, there are 10 latch rows 161, as shown in FIG. 13A. For the pixel signal, the 10-bit latch input counts up from "0000000000" to the code values D0 to D9 of "1111111111". It is configured that when the up-down relationship between the ramp voltage and the signal voltage is reversed, since the latch is cut off from the code value and held at that value, as long as the held value is read, the signal level can be known.

相對於此，閂鎖電路402與閂鎖電路52不同，採用閂鎖行161之數量僅具備一半之5個之構成。因此，若應用圖13A所示之斜坡信號，與上述之情形相同處理，則可獲得5位元之值，無法獲得10位元之值。因此，使用如圖14A所示之斜坡信號。 On the other hand, the latch circuit 402 is different from the latch circuit 52 in that the number of the latch rows 161 is only half of five. Therefore, if the ramp signal shown in FIG. 13A is applied and the same processing as in the above case is performed, a value of 5 bits can be obtained, and a value of 10 bits cannot be obtained. Therefore, a ramp signal as shown in FIG. 14A is used.

圖14A所示之斜坡信號係為了獲得10位元之值，而包含2次斜坡之信號。此處，將時刻T0至時刻T1之斜坡信號記述為第1次斜坡，將時刻T2至時刻T3之斜坡信號記述為第2次斜坡。 The ramp signal shown in FIG. 14A is a signal including two ramps in order to obtain a value of 10 bits. Here, the ramp signal from time T0 to time T1 is described as the first ramp, and the ramp signal from time T2 to time T3 is described as the second ramp.

時刻T1至時刻T2之期間出現之第1次斜坡係包含下階5bit作為碼值，而用以獲得下階5位元之輸出值之斜坡。由於為下階5bit，故如圖14B所示，碼值係自“00000”至“11111”重複32次，斜坡電壓與信號之電壓之上下關係於其間之某處反轉，將此時之碼值保持於閂鎖。其後，於時刻T1至時刻T2之期間，將下階5bit讀取至外部。 The first slope that occurs between time T1 and time T2 includes the lower-order 5 bits as the code value, and is used to obtain the lower-order 5-bit output value. Because it is the lower order 5bit, as shown in Figure 14B, the code value is repeated 32 times from "00000" to "11111". The up-down relationship between the ramp voltage and the signal voltage is reversed somewhere in between, and the code at this time is reversed. The value remains at the latch. After that, during the period from time T1 to time T2, the next 5 bits are read to the outside.

自時刻T1至時刻T2之時間係用以自第1次斜坡切換成第2次斜坡之時間，於該時間，自閂鎖電路402讀取下階5位元之值。 The time from the time T1 to the time T2 is a time for switching from the first slope to the second slope, and at this time, the value of the lower-order 5 bits is read from the latch circuit 402.

其後，於時刻T2至時刻T3之期間，包含第2次斜坡。第2次斜坡係將上階5bit作為碼值以32倍之緩慢之週期自“00000”遞增計數至“11111”。斜坡電壓與信號之電壓之上下關係於其間之某處反轉，將此時之碼值保持於閂鎖。其後，將上階5bit讀取至外部。 Thereafter, the second slope is included between time T2 and time T3. The second ramp is to count the upper 5 bits as the code value from "00000" to "11111" in a slow cycle of 32 times. The up and down relationship between the ramp voltage and the signal voltage is reversed somewhere in between, and the code value at this time is kept at the latch. After that, the upper 5 bits are read to the outside.

如此，藉由包含2次斜坡，將各個斜坡所獲得之5位元之值設為下階之5位元、及上階之5位元，而取得10位元之值。又，第1次斜坡之週期與第2次斜坡之週期不同，取得上階位元時之斜坡設為較取得下階位元時之斜坡更緩慢之週期。此處，已例示為32倍之週期之情 形。 In this way, by including two slopes, the value of the 5-bit obtained by each slope is set to the 5-bit of the lower stage and the 5-bit of the upper stage to obtain a value of 10 bits. In addition, the cycle of the first slope is different from the cycle of the second slope, and the slope when obtaining the upper-order bit is set to a slower cycle than the slope when obtaining the lower-order bit. Here, it has been exemplified that the cycle is 32 times. shape.

圖15中顯示一例。於圖15所示之例中，係於第1次斜坡取得“010110”之下階5位元之值，於第2次斜坡取得“10001”之上階5位元之值之例。藉由組合下階5位元與上階5位元，完成“1000101110”之10位元之數位值。 An example is shown in FIG. 15. The example shown in FIG. 15 is an example in which the first-order 5-bit value below “010110” is obtained on the first slope, and the 5--digit value above “10001” is obtained on the second slope. By combining the lower-order 5 bits and the upper-order 5 bits, the 10-bit digital value of "1000101110" is completed.

如此，藉由使用具有2次斜坡之斜坡信號，分別取得下階5位元與上階5位元，從而即便為具有5個閂鎖行161之閂鎖電路402，亦可獲得10位元之輸出值。 In this way, by using a ramp signal having a second slope, the lower-order 5 bits and the upper-order 5 bits are obtained respectively, so that even for the latch circuit 402 having 5 latch rows 161, a 10-bit output value.

另，於上述之說明中，第2次斜坡雖以32倍之週期包含上階5位元之碼值，但亦可將斜坡信號之傾斜度設為32倍而不改變碼值之週期。精度優先時前者較佳，速度優先時後者較佳。 In addition, in the above description, although the second ramp includes the upper-order 5-bit code value at a period of 32 times, the slope of the ramp signal can also be set to 32 times without changing the period of the code value. The former is better when accuracy is priority, and the latter is better when speed is priority.

又，於上述之說明中，雖以第1次斜坡決定下階位元，以第2次斜坡決定上階位元，但亦可以第1次斜坡決定上階位元，以第2次斜坡決定下階位元。 In the above description, although the lower order bit is determined by the first slope and the upper order bit is determined by the second slope, the upper order bit may be determined by the first slope and the second slope may be determined by Lower order bit.

然而，如上所述，可認為較佳的是以第1次斜坡決定下階位元，以第2次斜坡決定上階位元。其理由在於，來自像素21之信號有可能因暗電流等之影響而稍許變動，而可認為儘早決定下階位元較佳。 However, as described above, it can be considered that it is preferable to determine the lower order bit by the first slope and determine the upper order bit by the second slope. The reason is that the signal from the pixel 21 may change slightly due to the influence of dark current and the like, and it is considered that it is better to decide the lower order bit as soon as possible.

然而，雖為了獲得10位元之值而包含2次斜坡，但於第1次斜坡與第2次斜坡中存在時間差。於自第1次斜坡至第2次斜坡之期間，像素21之信號有可能移動。關於該情況，參照圖16進行說明。 However, although the second slope is included in order to obtain a 10-bit value, there is a time difference between the first slope and the second slope. During the period from the first slope to the second slope, the signal of the pixel 21 may move. This case will be described with reference to FIG. 16.

於第1次斜坡時，像素21之信號設為“0000100000”。於第1次斜坡時，由於係取得下階之5位元，故該情形時，取得“00000”。於第2次斜坡時，亦原本像素21之信號係“0000100000”，取得上階之5位元之“00001”。 At the first ramp, the signal of pixel 21 is set to "0000100000". At the first slope, since the lower 5 bits were obtained, in this case, "00000" was obtained. At the second slope, the signal of the original pixel 21 is “0000100000”, and the higher-order 5-bit “00001” is obtained.

然而，因某些影響，於第2次斜坡時，像素21之信號略微變動為“0000011111”之情形時，取得上階之5位元之“00000”。因此，該情形 時，如圖16所示，最終取得之值成為“0000000000”。於原本取得“0000100000”之值時，有可能取得“0000000000”之不同值。 However, due to some effects, when the signal of the pixel 21 slightly changed to "0000011111" during the second slope, the higher-order 5-bit "00000" was obtained. So the situation At this time, as shown in FIG. 16, the finally obtained value becomes “0000000000”. When the value of "0000100000" is originally obtained, it is possible to obtain a different value of "0000000000".

該情形時，於第1次斜坡與第2次斜坡之前之期間，像素21之信號於十進制中係自32向31僅變化1，於二進制中，自“0000000000”變化成“0000011111”。然而，包含2次斜坡，各取得5位元之情形時，如上所述，於應取得“0000100000”時，有可能取得“0000000000”之值。該情形時，若以十進制表示，則係指於原本取得32之值時，取得0。 In this case, during the period before the first slope and the second slope, the signal of the pixel 21 changes only 1 from 32 to 31 in decimal, and from “0000000000” to “0000011111” in binary. However, when two digits are included for each of the five slopes, as described above, when "0000100000" should be obtained, the value of "0000000000" may be obtained. In this case, if it is expressed in decimal, it means that when the value of 32 was originally obtained, 0 was obtained.

如此，像素信號以對第6位元造成影響之方式變動之情形時，雖然信號僅稍許變化，但AD轉換之結果有可能產生成為完全不同值之現象。為了避免如該值較大變化之情況，亦可進行如以下所述之對策。 In this way, when the pixel signal changes in a manner that affects the sixth bit, although the signal changes only slightly, the result of the AD conversion may cause a phenomenon that the value is completely different. In order to avoid a situation where the value changes greatly, countermeasures as described below can also be performed.

首先，作為對策1，可使用格雷碼作為碼值。格雷碼係利用於自某一值向鄰接之值變化時，始終僅變化1位元之點之碼。 First, as a countermeasure 1, a Gray code can be used as a code value. Gray code is a code that only changes by one bit when the value changes from a certain value to an adjacent value.

若為格雷碼，則於下階5位元為“00000”之部位之前後時，由於其正上方之位數不變化，故產生如上所述之值較大變化之情況之可能性變低。若考慮進位至第6位數，則成為...10001、10000、110000、110001...，由於在進位之前後，下階5位數成為對稱，故即便第6位數變化，亦不會如二進制碼之情形般成為完全不同之值。 In the case of Gray code, since the number of bits directly above it does not change before and after the position where the lower-order 5-bit is "00000", the possibility of a large change in the value as described above becomes low. If you consider the carry to the 6th digit, it will become ... 10001, 10000, 110000, 110001 ..., because the lower 5 digits become symmetrical before and after the carry, so even if the 6th digit changes, It becomes a completely different value as in the case of binary code.

例如，於第1次斜坡時以“0000110000”取得“10000”作為下階5位元，於第2次斜坡時，若假設信號之值變化成下降1之“0000010000”，而上階5位元成為“00000”，則組合成為“0000010000”，AD轉換之結果成為下降1之值。 For example, in the first slope, "0000110000" is used to obtain "10000" as the lower-order 5-bit. In the second slope, if the value of the signal is assumed to change to "0000010000" which decreases by 1, and the upper-order is 5 bits When it becomes "00000", the combination becomes "0000010000", and the result of the AD conversion becomes a value of "1".

又，例如，於第1次斜坡以“0000110001”取得“10001”作為下階5位元，於第2次斜坡時，若信號之值下降2，取得“00000”作為上階5位元，則組合成為“0000010001”，AD轉換之結果成為下降3之值。 For example, if the first slope is "0000110001" and "10001" is obtained as the lower-order 5 bits, and in the second slope, if the value of the signal decreases by 2 and "00000" is obtained as the upper-order 5 bits, then The combination becomes "0000010001", and the result of the AD conversion becomes a value which decreases by 3.

像素值相反變大而進位之情形亦為相同，於格雷碼中，不會如 二進制碼般，儘管像素之信號變化較小，但AD轉換之結果成為相距甚遠之值。 The pixel value becomes larger and the carry is the same. In Gray code, Binary code, although the signal of the pixel changes less, the result of the AD conversion becomes far away values.

另，亦可將所有位元設為格雷碼，但考慮像素信號之變動值或雜訊等，亦可如可能變化之範圍之下階位元為格雷碼，其上為二進制碼般，並用格雷碼與二進制碼。 In addition, all bits can be set to Gray code, but considering the change value or noise of the pixel signal, it is also possible to use Gray code if the lower order bit is Gray code and the binary code is above. Code and binary code.

於格雷碼中，若像素信號跨越第6位數之進位、退位移動，則AD轉換之結果亦與真實值不一致。作為對策2，可藉由於二進制碼中，共用第1次斜坡時所獲得之值與第2次斜坡所獲得之值中之1位數而解決。 In the Gray code, if the pixel signal moves across the 6th digit, the result of AD conversion is not consistent with the true value. As a countermeasure 2, it is possible to solve the problem by using one digit of the value obtained when the first slope is shared with the value obtained by the second slope in the binary code.

於第1次斜坡時，轉換下階5位數係與上述之情形相同。第2次係包含第5位數~第9位數作為碼值。其結果，並非成為10位元，而是成為9位元之AD轉換。第2次之第5位數與第1次之值不同之情形時，採用第1次之值，並與第6位數對照而修正。 At the first slope, the lower 5 digits are converted in the same way as above. The second series contains the 5th to 9th digits as the code value. As a result, it is not a 10-bit, but a 9-bit AD conversion. When the 5th digit of the 2nd time is different from the value of the 1st time, the value of the 1st time is used and it is corrected by comparing with the 6th digit.

例如，如圖17所示，考慮如下情形：第1次斜坡時之信號為“0000100000”，下階5位數為“00000”，第2次斜坡時之信號變化成“0000011111”，其結果，取得“00001”作為上階位數。該情形時，於圖17之左圖中，由橢圓包圍之部分、即第1次斜坡時所取得之第1位數之“0”與第2次斜坡時所取得之第5位數之“1”原本應成為相同之值，但不同。 For example, as shown in FIG. 17, consider the following situation: the signal at the first slope is "0000100000", the lower 5 digits are "00000", and the signal at the second slope is changed to "0000011111". As a result, Obtain "00001" as the upper digit. In this case, in the left diagram of FIG. 17, the part surrounded by the ellipse, that is, the “0” of the first digit obtained during the first slope and the “0” of the fifth digit obtained during the second slope 1 "should be the same value, but different.

此種情形時，參照第1次斜坡時所取得之值，根據下移進行判定，將上階5位數修正為“00010”，取得“000010000”作為最終結果。 In this case, refer to the value obtained during the first slope and make a judgment based on the downward movement. Correct the upper 5 digits to "00010" and obtain "000010000" as the final result.

第1次斜坡時所取得之值為“11111”等，第2次斜坡時所取得之值為“****0”之情形時，可判定為上移。即，只要判定為第1次之第4位數為0之情形時下移，為1之情形時上移即可。如此，亦可以根據共用之位元之下階一位之位元之值，修正數位信號之方式構成。 If the value obtained during the first slope is "11111", etc., if the value obtained during the second slope is "**** 0", it can be judged as an upward movement. That is, it is only necessary to move down when the fourth digit of the first time is 0, and move up when it is 1. In this way, the digital signal can also be constructed according to the value of the bit one bit lower than the shared bit.

若共有位數與其下1位數為二進制碼，則其他位數可為格雷碼。 If the common digits and the next digit are binary codes, the other digits can be Gray codes.

如此，即便減少閂鎖電路402之位元數，藉由包含2次斜坡，亦可創建10位元(或9位元)之值。此種情形時，像素21亦輸出重設位準與信號位準。重設位準係該像素之該時點之基準電壓。信號位準與重設位準之差成為真實信號值。圖18中顯示對應之動作。 In this way, even if the number of bits of the latch circuit 402 is reduced, by including the second slope, a value of 10 bits (or 9 bits) can be created. In this case, the pixel 21 also outputs a reset level and a signal level. The reset level is a reference voltage of the pixel at that point in time. The difference between the signal level and the reset level becomes the true signal value. The corresponding action is shown in FIG. 18.

重設位準、信號位準均如上述說明般，各包含2次斜坡而進行AD轉換。參照圖18，於時間T11，包含相對於重設位準之第1次斜坡，於其下一個時間T12，包含相對於重設位準之第2次斜坡。 The reset level and signal level are as described above, and each includes 2 slopes for AD conversion. Referring to FIG. 18, at time T11, the first slope relative to the reset level is included, and at the next time T12, the second slope relative to the reset level is included.

於其下一個時間T13，包含相對於信號位準之第1次斜坡，於時間T14，包含相對於信號位準之第2次斜坡。如此，以重設位準下階5位元→上階5位元→信號位準下階5位元→上階5位元之順序輸出數位值。 At its next time T13, it includes the first slope relative to the signal level, and at time T14, it includes the second slope relative to the signal level. In this way, the digital value is output in the order of resetting the lower level 5 bits → upper level 5 bits → signal level lower level 5 bits → upper level 5 bits.

該等數位信號與參照圖9說明之情形相同，係記憶於下一段之訊框記憶體301。於最後出現信號位準之上階5位元之階段，自信號位準減去重設位準係於減法器302中進行。攝像裝置與訊框記憶體301或減法器302可為不同半導體元件，亦可一體化。 These digital signals are the same as those described with reference to FIG. 9 and are stored in the frame memory 301 of the next paragraph. Subtracting the reset level from the signal level at the stage where the signal level last appears 5 bits above is performed in the subtractor 302. The camera device and the frame memory 301 or the subtractor 302 may be different semiconductor elements or integrated.

圖19係用以對藉由包含2次斜坡而創建10位元之輸出值時之ADC31之動作進行說明之圖。曝光後，重設像素21之浮動擴散103，將其位準AD轉換(P相期間)。P相1係下階5位元之轉換，且將其輸出至感測放大器33之期間。P相2係上階5位元之轉換，且將其輸出至感測放大器33之期間。 FIG. 19 is a diagram for explaining the operation of the ADC 31 when a 10-bit output value is created by including two slopes. After exposure, the floating diffusion 103 of the pixel 21 is reset, and its level is AD-converted (P-phase period). Phase P 1 is a period of lower-order 5-bit conversion and output to the sense amplifier 33. P-phase 2 is a period of upper-order 5-bit conversion and output to the sense amplifier 33.

P相2之輸出結束後，光電二極體101之光電子被傳送至浮動擴散103。然後同樣重複2次轉換與輸出。P相1、P相2、D相1、D相2之各個轉換係藉由使所有ADC31並行動作而進行。對感測放大器33之輸出係一面逐列掃描ADC31一面進行。1個ADC31對應於複數個像素21之情形時，以每1像素依序選擇，並重複該動作。 After the output of P phase 2 is completed, the photoelectrons of the photodiode 101 are transferred to the floating diffusion 103. Then repeat the conversion and output twice. Each conversion of P-phase 1, P-phase 2, D-phase 1, and D-phase 2 is performed by causing all ADCs 31 to operate in parallel. The output of the sense amplifier 33 is performed while scanning the ADC 31 column by column. When one ADC 31 corresponds to a plurality of pixels 21, the selection is performed sequentially for each pixel, and the operation is repeated.

由於重設位準分佈於狹窄之範圍，故如圖18所示，對應之斜坡 信號亦可較短。即，如圖18所示，重設位準之檢測時之斜坡信號之電壓之變動幅度亦可小於信號位準之檢測時之斜坡信號之電壓之變動幅度。又，重設位準之檢測時之斜坡信號之週期亦可較信號位準之檢測時之斜坡信號之週期短。 Since the reset levels are distributed in a narrow range, as shown in Figure 18, the corresponding slope The signal can also be shorter. That is, as shown in FIG. 18, the fluctuation range of the voltage of the ramp signal during the detection of the reset level may be smaller than the fluctuation range of the voltage of the ramp signal during the detection of the signal level. In addition, the period of the ramp signal during detection of the reset level may be shorter than the period of the ramp signal during detection of the signal level.

於包含信號位準之4次斜坡，僅該範圍將斜坡設為直線，相當於信號值較大處之部位，藉由使斜坡之傾斜急劇，或降低碼值之遞增計數之速度，可擴大高亮度側之AD轉換之刻度，而減少資料量。 In the 4 times of the slope including the signal level, only the range is set to a straight line, which is equivalent to the place where the signal value is larger. By making the slope of the slope sharp or reducing the speed of the increment of the code value, the height can be enlarged. The scale of the AD conversion on the brightness side reduces the amount of data.

即，亦可使用取得信號位準之高亮度側之信號時之斜坡信號之電壓變化較取得低亮度側之信號時之斜坡信號之電壓變化急劇之信號。或，亦可使取得信號位準之高亮度側之信號時之對閂鎖電路402供給碼值D之速度較取得低亮度側之信號時之對閂鎖電路402供給碼值D之速度慢。藉此，可減少資料量。 That is, it is also possible to use a signal in which the voltage change of the ramp signal when the signal on the high-luminance side of the signal level is obtained is sharper than the voltage change of the ramp signal when the signal on the low-luminance side is obtained. Alternatively, the speed at which the code value D is supplied to the latch circuit 402 when a signal at the high-luminance side of the signal level is obtained may be slower than the speed at which the code value D is supplied to the latch circuit 402 when a signal at the low-luminance side is obtained. This can reduce the amount of data.

以此方式設定之情形時，以減法器302參照重設位準值計算與轉折點之差，藉此，可藉由修正高亮度側之值，於減去後獲得正確值。轉折點係指斜坡信號之電壓變化變得急劇之時點、或碼值之供給之速度變化之時點。由於重設位準分佈於狹窄之範圍，故若將該範圍收斂於D相之1/32以下之範圍，則亦可以1次斜坡完成重設位準。 In the case of setting in this way, the subtracter 302 calculates the difference from the turning point with reference to the reset level value, whereby the correct value can be obtained by subtracting the value on the high-luminance side after the correction. The turning point refers to the point at which the voltage change of the ramp signal becomes sharp or the point at which the speed of the supply of code value changes. Since the reset levels are distributed in a narrow range, if the range is converged to a range below 1/32 of the D phase, the reset levels can also be completed in one slope.

然而，於上述實施形態中，以於使用包含10個閂鎖行161-1至161-10之閂鎖電路52時，包含1次斜坡，於使用包含5個閂鎖行161-1至161-5之閂鎖電路402時，包含2次斜坡進行說明。 However, in the above-mentioned embodiment, when the latch circuit 52 including 10 latch lines 161-1 to 161-10 is used, the ramp is included once, and when the latch circuit 52 including 5 latch lines 161-1 to 161- is used In the case of the latch circuit 402 of 5, the second ramp is described.

該閂鎖行之個數與包含斜坡之次數並非對此種組合表示限定之記載，而係顯示一例者。例如，亦可以具有3個閂鎖行，包含3次斜坡，而獲得9位元之輸出值之方式構成。 The number of the latch rows and the number of times including the slope are not records indicating the limitation of this combination, but are shown as an example. For example, it can also be constructed in such a way that it has three latch rows, including three ramps, and obtains a 9-bit output value.

又，例如，包含3次斜坡之情形時，亦可分別取得上階位元、下階位元、及上階位元與下階位元之間之中階位元，藉由上階位元、中階位元、及下階位元之組合產生數位值。 In addition, for example, when the slope is included three times, the upper-order bit, the lower-order bit, and the intermediate-order bit between the upper-order bit and the lower-order bit can be obtained separately. A combination of, middle-order bits, and lower-order bits produces digital values.

若考慮此種情況，則例如亦可考慮以位元數之量包含斜坡。應用本技術，以位元數之量包含複數次斜坡之情形時，亦成為傾斜型ADC之動作，即便擴張至包含位元數之量之次數之情形，任一斜坡均與傾斜型之ADC相同掃描。由於斜坡波形可為每次相同者，故再現性較佳。因此，可以高狀態保持AD轉換之精度。 If such a case is considered, for example, it may be considered to include a slope in the number of bits. Applying this technology, when the slope is included in the number of bits, it also becomes a sloped ADC. Even if it is expanded to the number of times including the number of bits, any slope is the same as the sloped ADC. scanning. Since the ramp waveform can be the same each time, the reproducibility is better. Therefore, the accuracy of AD conversion can be maintained in a high state.

因此，即便以位元數之量包含斜坡，根據本技術，亦可進行精度較高之AD轉換。 Therefore, even if the slope is included in the number of bits, according to the present technology, AD conversion with higher accuracy can be performed.

根據本技術，可實現固體攝像元件之小型化。又，由於以較少個數之像素保持1個ADC，故可使處理高速化。又，即便攝像之物體為有移動之物體，亦可實現失真較少之狀態下之攝像。 According to this technology, miniaturization of a solid-state imaging element can be achieved. Further, since one ADC is held by a small number of pixels, processing can be speeded up. In addition, even if the object to be imaged is a moving object, the image can be taken in a state with less distortion.

又，可採用低消耗電力之構成。又，可避免小規模之類比電路與數位電路之混雜，於上基板與下基板分別使電壓或製造過程最佳化。 It is also possible to adopt a configuration with low power consumption. In addition, the small-scale analog circuit and the digital circuit can be avoided, and the voltage or the manufacturing process can be optimized on the upper substrate and the lower substrate, respectively.

<電子機器> <Electronic equipment>

本揭示並不限於應用於攝像裝置，亦可對數位靜態相機或攝錄影機等攝像裝置、或行動電話機等具有攝像功能之移動終端裝置、或於圖像讀取部使用攝像裝置之影印機等、於圖像引入部(光電轉換部)使用攝像裝置之電子機器全般進行應用。另，亦有將搭載於電子機器之上述模組狀之形態、即相機模組設為攝像裝置之情形。 The present disclosure is not limited to the application to an imaging device, and may also be applied to an imaging device such as a digital still camera or a video camera, a mobile terminal device having an imaging function such as a mobile phone, or a photocopier using the imaging device in an image reading section. The electronic devices using the imaging device in the image introduction section (photoelectric conversion section) are generally applied. In addition, the above-mentioned module-like form mounted on an electronic device, that is, a camera module may be an imaging device.

圖20係顯示作為本揭示之電子機器之一例之攝像裝置之構成例之方塊圖。如圖20所示，本揭示之攝像裝置500具有包含透鏡群501等之光學系統、攝像元件502、相機信號處理部即DSP電路503、訊框記憶體504、顯示裝置505、記錄裝置506、操作系統507、及電源系統508等。 FIG. 20 is a block diagram showing a configuration example of an imaging device as an example of an electronic device of the present disclosure. As shown in FIG. 20, the imaging device 500 of the present disclosure includes an optical system including a lens group 501 and the like, an imaging element 502, a DSP circuit 503 which is a camera signal processing section, a frame memory 504, a display device 505, a recording device 506, and an operation. System 507, and power supply system 508, etc.

且，採用經由匯流排線509將DSP電路503、訊框記憶體504、顯示裝置505、記錄裝置506、操作系統507、及電源系統508相互連接之 構成。CPU510控制攝像裝置500內之各部。 In addition, a DSP circuit 503, a frame memory 504, a display device 505, a recording device 506, an operating system 507, and a power supply system 508 are connected to each other via a bus line 509. Make up. The CPU 510 controls each unit in the imaging device 500.

透鏡群501係引入來自被攝體之入射光(像光)而成像於攝像元件502之攝像面上。攝像元件502係將藉由透鏡群501成像於攝像面上之入射光之光量以像素單位轉換成電性信號而輸出作為像素信號。作為該攝像元件502，可使用前述之實施形態之固體攝像元件。 The lens group 501 introduces incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 502. The imaging element 502 converts the light amount of incident light imaged on the imaging surface by the lens group 501 into electrical signals in pixel units and outputs the electrical signals as pixel signals. As this imaging element 502, the solid-state imaging element of the aforementioned embodiment can be used.

顯示裝置505包含液晶顯示裝置或有機EL(electro luminescence：電致發光)顯示裝置等面板型顯示裝置，顯示以攝像元件502攝像之動態圖像或靜態圖像。記錄裝置506係將以攝像元件502攝像之動態圖像或靜態圖像記錄於錄影帶或DVD(Digital Versatile Disc：數位多功能光碟)等記錄媒體。 The display device 505 includes a panel-type display device such as a liquid crystal display device or an organic EL (electro luminescence) display device, and displays a moving image or a still image captured by the imaging element 502. The recording device 506 records a moving image or a still image captured by the imaging element 502 on a recording medium such as a video tape or a DVD (Digital Versatile Disc).

操作系統507係於使用者之操作下，對本攝像裝置所具有之各種功能發出操作指令。電源系統508係將成為DSP電路503、訊框記憶體504、顯示裝置505、記錄裝置506、及操作系統507之動作電源之各種電源，適當供給至該等供給對象。 The operating system 507 issues operation instructions to various functions of the camera device under the operation of the user. The power supply system 508 is to supply various power sources such as the DSP circuit 503, the frame memory 504, the display device 505, the recording device 506, and the operating power of the operating system 507 to these supply targets as appropriate.

此種攝像裝置500係應用於攝錄影機或數位靜態相機、進而應用於面向行動電話機等移動機器之相機模組。且，於該攝像裝置500中，可使用前述之實施形態之攝像裝置作為攝像元件502。 Such an imaging device 500 is applied to a camera module, a digital still camera, and a camera module for a mobile device such as a mobile phone. In addition, in the imaging device 500, the imaging device of the aforementioned embodiment can be used as the imaging element 502.

<關於記錄媒體> <About recording media>

上述之一系列處理可藉由硬體執行，亦可藉由軟體執行。於藉由軟體執行一系列處理之情形時，將構成該軟體之程式安裝於電腦中。此處，於電腦中，包含配置於專用之硬體之電腦、或可藉由安裝各種程式執行各種功能之例如通用之個人電腦等。 One of the series of processes described above can be executed by hardware or software. When a series of processing is performed by software, a program constituting the software is installed in a computer. Here, the computer includes a computer arranged in dedicated hardware or a general-purpose personal computer that can perform various functions by installing various programs.

例如，於圖20所示之攝像裝置500中，藉由使CPU510負載執行例如記錄於記錄裝置506之程式，而進行上述之一系列處理。 For example, in the imaging device 500 shown in FIG. 20, one of the above-mentioned series of processing is performed by causing the CPU 510 to load a program recorded in the recording device 506, for example.

電腦(CPU510)執行之程式例如可記錄於作為套裝媒體等之可卸除式媒體(未圖示)而提供。又，程式可經由局域網路、網際網路、數 位衛星廣播之類之有線或無線之傳送媒體提供。 The program executed by the computer (CPU 510) can be provided on a removable medium (not shown), for example, as a package medium. In addition, programs can be accessed via LAN, Internet, and Wired or wireless transmission media such as satellite broadcasting.

於攝像裝置500(電腦)中，程式可藉由將可卸除式媒體安裝於驅動器(未圖示)，而經由匯流排線509安裝於記錄裝置506。又，程式可經由有線或無線之傳送媒體，以通信部接收，而安裝於記錄裝置506。此外，程式可預先安裝於記錄裝置506。 In the imaging device 500 (computer), the program can be installed in the recording device 506 via a bus line 509 by installing a removable medium on a drive (not shown). The program may be received by the communication unit via a wired or wireless transmission medium and installed in the recording device 506. In addition, the program may be installed in the recording device 506 in advance.

另，電腦執行之程式可為沿著本說明書所說明之順序以時間序列進行處理之程式，亦可為並行或於進行呼叫時等之必要之時序進行處理之程式。 In addition, the program executed by the computer may be a program that processes in a time series along the order described in this manual, or a program that processes in parallel or at a necessary timing such as when a call is made.

又，於本說明書中，系統係表示藉由複數個裝置構成之裝置整體者。 In addition, in this specification, a system means the whole apparatus comprised by several apparatuses.

另，本技術之實施形態並不限定於上述實施形態，可於不脫離本技術之主旨之範圍內進行各種變更。 The embodiments of the present technology are not limited to the above-mentioned embodiments, and various changes can be made without departing from the spirit of the present technology.

另，本說明書所記載之效果僅為例示，並非限定者，又可有其他效果。 In addition, the effects described in this specification are merely examples, and are not limited, and may have other effects.

另，本技術亦可採取如以下所述之構成。 The present technology can also be configured as described below.

(1) (1)

一種轉換裝置，其包含：比較部，其係將輸入信號之輸入電壓、與隨時間變動之斜坡信號之斜坡電壓進行比較；及記憶部，其保持來自上述比較部之比較結果反轉時之碼值；且藉由重複複數次由上述記憶部進行之上述碼值之保持，而產生特定之位元數之數位信號。 A conversion device includes: a comparison section that compares an input voltage of an input signal with a ramp voltage of a ramp signal that changes with time; and a memory section that holds a code when the comparison result from the comparison section is reversed And by repeating the plurality of times of maintaining the code value by the memory section, a digital signal of a specific number of bits is generated.

(2) (2)

如上述技術方案(1)之轉換裝置，其中將上述特定之位元數分成上階位元與下階位元，較上述上階位元更先取得上述下階位元，並組合所取得之上述下階位元與上述上階 位元，而產生上述特定之位元數之數位信號。 The conversion device according to the above technical solution (1), wherein the specific number of bits is divided into upper-order bits and lower-order bits, and the lower-order bits are obtained earlier than the upper-order bits, and the obtained bits are combined The above lower order bit and the above upper order bit Bits, and a digital signal with the specified number of bits is generated.

(3) (3)

如上述技術方案(2)之轉換裝置，其中上述下階位元為格雷碼。 The conversion device according to the above technical solution (2), wherein the above-mentioned lower-order bits are Gray codes.

(4) (4)

如上述技術方案(2)之轉換裝置，其中共用上述下階位元與上述上階位元之至少1位元。 The conversion device according to the above technical solution (2), wherein at least one bit of the lower-order bit and the upper-order bit are shared.

(5) (5)

如上述技術方案(4)之轉換裝置，其中藉由上述共用之位元之一個下階之位元之值，修正上述數位信號。 The conversion device according to the above technical solution (4), wherein the digital signal is modified by a value of a lower-order bit of the shared bit.

(6) (6)

如上述技術方案(2)之轉換裝置，其中用以取得上述下階位元之上述斜坡信號與用以取得上述上階位元之上述斜坡信號具有不同之週期。 As in the conversion device of the above technical solution (2), the slope signal used to obtain the lower-order bit and the slope signal used to obtain the upper-order bit have different periods.

(7) (7)

如技術方案(1)至(6)中任一項之轉換裝置，其中上述輸入信號係自像素輸出之信號，且包含於每個上述像素中。 The conversion device according to any one of the technical solutions (1) to (6), wherein the input signal is a signal output from a pixel and is included in each of the pixels.

(8) (8)

一種攝像裝置，其係如下者：積層上基板與下基板；於上述上基板配置像素、與將來自上述像素之信號之電壓與隨時間變動之斜坡信號之斜坡電壓進行比較之比較部；於上述下基板配置保持來自上述比較部之比較結果反轉時之碼值之記憶部；且 藉由重複複數次由上述記憶部進行之上述碼值之保持，而產生特定之位元數之數位信號。 An imaging device is as follows: a laminated upper substrate and a lower substrate; a pixel configured on the upper substrate, and a comparison unit for comparing a voltage of a signal from the pixel with a ramp voltage of a ramp signal that changes with time; The lower substrate is configured with a memory unit that holds the code value when the comparison result from the above-mentioned comparison unit is inverted; and A digital signal of a specific number of bits is generated by repeating the holding of the code value by the memory section a plurality of times.

(9) (9)

如上述技術方案(8)之攝像裝置，其中將上述特定之位元數分成上階位元與下階位元，較上述上階位元更先取得上述下階位元；以上述像素之基準位準之下階位元、上述像素之基準位準之上階位元、上述像素之信號位準之下階位元、及上述像素之信號位準之上階位元之順序，取得上述基準位準之信號與上述信號位準之信號，並自該等信號之一者減去另一者，而產生表示累積於上述像素之電荷量之數位信號。 The imaging device according to the above technical solution (8), wherein the specific number of bits is divided into upper-order bits and lower-order bits, and the lower-order bits are obtained before the upper-order bits; based on the pixels The order of the lower order bit, the upper order bit of the reference level of the pixel, the lower order bit of the signal level of the pixel, and the upper order bit of the signal level of the pixel are obtained in order of the above reference. The signal of the level and the signal of the above-mentioned signal level are subtracted from one of the signals to generate a digital signal representing the amount of charge accumulated in the pixel.

(10) (10)

如上述技術方案(9)之攝像裝置，其中取得上述基準位準之信號時之上述斜坡電壓與取得上述信號位準時之上述斜坡電壓不同。 The imaging device according to the above technical solution (9), wherein the ramp voltage when the signal of the reference level is obtained is different from the ramp voltage when the signal level is obtained.

(11) (11)

如上述技術方案(9)之攝像裝置，其中取得上述信號位準之高亮度側之信號時之上述斜坡信號之電壓變化較取得低亮度側之信號時之上述斜坡信號之電壓變化更為急劇，或，取得上述信號位準之高亮度側之信號時之對上述記憶部供給上述碼值之速度較取得低亮度側之信號時之對上述記憶部供給上述碼值之速度更慢。 As in the imaging device of the above technical solution (9), the voltage change of the ramp signal when obtaining the signal on the high-luminance side of the signal level is more sharp than that of the ramp signal when obtaining the signal on the low-luminance side Or, the speed of supplying the code value to the memory portion when obtaining the signal of the high-luminance side of the signal level is slower than the speed of supplying the code value to the memory portion when obtaining the signal of the low-luminance side.

(12) (12)

如上述技術方案(11)之攝像裝置，其中根據於上述斜坡信號之電壓變化變得急劇之時點、或上述碼值之供給之速度變化之時點所取得之信號、與上述基準位準之差分，而 修正上述高亮度側之信號。 The imaging device according to the above technical solution (11), wherein the difference between the signal obtained from the point in time when the voltage change of the ramp signal becomes sharp or the point in time when the supply of the code value changes, and the reference level, and Correct the signal on the high-luminance side.

(13) (13)

一種電子機器，其包含：攝像裝置，該攝像裝置係如下者：積層上基板與下基板；於上述上基板配置像素、與將來自上述像素之信號之電壓與隨時間變動之斜坡信號之斜坡電壓進行比較之比較部；於上述下基板配置保持來自上述比較部之比較結果反轉時之碼值之記憶部；且藉由重複複數次由上述記憶部進行之上述碼值之保持，而產生特定之位元數之數位信號；及信號處理部，其係對自上述半導體裝置輸出之像素信號進行信號處理。 An electronic device includes: an imaging device, which is composed of: an upper substrate and a lower substrate are laminated; a pixel is arranged on the upper substrate, and a ramp voltage that changes a voltage of a signal from the pixel and a ramp signal that changes with time. A comparison section for comparison; a memory section configured to hold a code value when the comparison result from the comparison section is reversed is arranged on the lower substrate; and a specific code is generated by repeating the maintenance of the code value by the memory section a plurality of times And a signal processing unit that performs signal processing on a pixel signal output from the semiconductor device.

(14) (14)

一種轉換方法，其係轉換裝置之轉換方法，該轉換裝置包含：比較部，其係將輸入信號之輸入電壓、與隨時間變動之斜坡信號之斜坡電壓進行比較；及記憶部，其保持來自上述比較部之比較結果反轉時之碼值；且該轉換方法包含如下步驟：藉由重複複數次由上述記憶部進行之上述碼值之保持，而產生特定之位元數之數位信號。 A conversion method, which is a conversion method of a conversion device, the conversion device includes: a comparison section that compares an input voltage of an input signal with a ramp voltage of a ramp signal that changes with time; and a memory section that keeps from the above The code value when the comparison result of the comparison section is reversed; and the conversion method includes the steps of generating a digital signal of a specific number of bits by repeating the holding of the code value by the memory section a plurality of times.

Claims (14)

一種轉換裝置，其包含：比較部，其係將輸入信號之輸入電壓、與隨時間變動之斜坡信號(ramp signal)之斜坡電壓進行比較，上述斜坡信號具有第1斜坡及第2斜坡；及記憶部，其保持(holding)來自上述比較部之比較結果反轉時之碼值；且由上述記憶部進行之上述碼值之保持係被重複，以對上述第1斜坡取得下階位元(low-order bits)及對上述第2斜坡取得上階位元(high-order bits)，藉由組合所取得之上述下階位元及所取得之上述上階位元而產生特定之位元數之數位信號。A conversion device includes a comparison section that compares an input voltage of an input signal with a ramp voltage of a ramp signal that changes with time, the ramp signal having a first ramp and a second ramp; and a memory Part, which holds the code value when the comparison result from the comparison part is reversed; and the holding of the code value by the memory part is repeated to obtain a lower order bit for the first slope (low -order bits) and obtaining high-order bits for the second slope, and combining the obtained lower-order bits and the obtained upper-order bits to generate a specific number of bits Digital signals. 如請求項1之轉換裝置，其中在上述斜坡信號中，上述第1斜坡係先於上述第2斜坡。For example, in the conversion device of claim 1, in the above-mentioned slope signal, the first slope is prior to the second slope. 如請求項2之轉換裝置，其中上述下階位元為格雷碼。For example, the conversion device of claim 2, wherein the above-mentioned lower-order bits are Gray codes. 如請求項2之轉換裝置，其中共用上述下階位元與上述上階位元之至少1位元。For example, the conversion device of claim 2, wherein at least one bit of the above-mentioned lower order bit and the above-mentioned upper order bit are shared. 如請求項4之轉換裝置，其中藉由上述共用之位元之一個下階之位元之值，修正上述數位信號。For example, the conversion device of item 4, wherein the digital signal is corrected by a value of a lower-order bit of the shared bit. 如請求項2之轉換裝置，其中用以取得上述下階位元之上述第1斜坡與用以取得上述上階位元之上述第2斜坡具有不同之週期長度(cycle length)。For example, the conversion device of claim 2, wherein the first slope used to obtain the lower order bit and the second slope used to obtain the upper order bit have different cycle lengths. 如請求項1至6之任一轉換裝置，其中上述輸入信號係自像素輸出之信號，且包含於每個上述像素中。The conversion device according to any one of claims 1 to 6, wherein the input signal is a signal output from a pixel and is included in each of the pixels. 一種攝像裝置，其係包括：積層之上基板與下基板；於上述上基板配置像素、與將來自上述像素之信號之電壓與隨時間變動之斜坡信號之斜坡電壓進行比較之比較部，上述斜坡信號具有第1斜坡及第2斜坡；於上述下基板配置保持來自上述比較部之比較結果反轉時之碼值之記憶部；且由上述記憶部進行之上述碼值之保持係被重複，以對上述第1斜坡取得下階位元及對上述第2斜坡取得上階位元，藉由組合所取得之上述下階位元及所取得之上述上階位元而產生特定之位元數之數位信號。An imaging device includes: a laminated upper substrate and a lower substrate; a pixel disposed on the upper substrate, and a comparison unit that compares a voltage of a signal from the pixel with a ramp voltage of a ramp signal that changes with time, the ramp The signal has a first slope and a second slope; a memory unit configured to hold the code value when the comparison result from the comparison unit is inverted is arranged on the lower substrate; and the code value retention performed by the memory unit is repeated to Obtain a lower order bit for the first slope and an upper order bit for the second slope, and generate a specific number of bits by combining the obtained lower order bit and the obtained upper order bit. Digital signals. 如請求項8之攝像裝置，其中在上述斜坡信號中，上述第1斜坡係先於上述第2斜坡；以上述像素之基準位準之下階位元、上述像素之基準位準之上階位元、上述像素之信號位準之下階位元、及上述像素之信號位準之上階位元之順序，取得上述基準位準之信號與上述信號位準之信號，並自上述基準位準之信號與上述信號位準之信號之一者減去另一者，而產生表示累積於上述像素之電荷量之數位信號。The imaging device according to claim 8, wherein in the above-mentioned slope signal, the above-mentioned first slope is before the above-mentioned second slope; the lower-order bit is above the reference level of the pixel, and the upper-order bit is above the reference level of the pixel The order of the lower order bit of the signal level of the pixel and the upper order bit of the signal level of the pixel to obtain the signal of the reference level and the signal of the signal level from the reference level One of the signal and the signal of the aforementioned signal level is subtracted from the other to generate a digital signal representing the amount of charge accumulated in the aforementioned pixel. 如請求項9之攝像裝置，其中取得上述基準位準之信號時之上述斜坡電壓與取得上述信號位準時之上述斜坡電壓不同。For example, the imaging device of claim 9, wherein the ramp voltage when the signal of the reference level is obtained is different from the ramp voltage when the signal level is obtained. 如請求項9之攝像裝置，其中取得上述信號位準之高亮度側之信號時之上述斜坡信號之電壓變化較取得低亮度側之信號時之上述斜坡信號之電壓變化更為急劇，或，取得上述信號位準之高亮度側之信號時之對上述記憶部供給上述碼值之速度較取得低亮度側之信號時之對上述記憶部供給上述碼值之速度更慢。For example, if the imaging device of item 9 is used, the voltage change of the ramp signal when obtaining the signal on the high-luminance side of the signal level is more rapid than the voltage change of the ramp signal when obtaining the signal on the low-luminance side, or The speed of supplying the code value to the memory when the signal of the high-luminance side of the signal level is slower than the speed of supplying the code value to the memory when the signal of the low-luminance side is obtained. 如請求項11之攝像裝置，其中根據於上述斜坡信號之電壓變化變得急劇之時點、或上述碼值之供給之速度變化之時點所取得之信號、與上述基準位準之差分，而修正上述高亮度側之信號。For example, the imaging device according to claim 11, wherein the above-mentioned reference level is corrected based on the difference between the signal obtained at the time point when the voltage change of the ramp signal becomes sharp or the time point at which the supply of the code value changes and the reference level. Signal on the bright side. 一種電子機器，其包含：攝像裝置，其包括：上基板與下基板，於上述上基板配置像素、與將來自上述像素之信號之電壓與隨時間變動之斜坡信號之斜坡電壓進行比較之比較部，上述斜坡信號具有第1斜坡及第2斜坡，於上述下基板配置保持來自上述比較部之比較結果反轉時之碼值之記憶部，且由上述記憶部進行之上述碼值之保持係被重複，以對上述第1斜坡取得下階位元及對上述第2斜坡取得上階位元，藉由組合所取得之上述下階位元及所取得之上述上階位元而產生特定之位元數之數位信號；及信號處理部，其係對自上述攝像裝置輸出之像素信號進行信號處理。An electronic device includes an imaging device including an upper substrate and a lower substrate, on which pixels are arranged, and a comparison unit that compares a voltage of a signal from the pixel with a ramp voltage of a ramp signal that changes with time. The above-mentioned slope signal has a first slope and a second slope, and a memory unit configured to hold a code value when the comparison result from the comparison unit is reversed is arranged on the lower substrate, and the code value is maintained by the memory unit. Repeat to obtain the lower order bit for the first slope and the upper order bit for the second slope, and generate a specific bit by combining the obtained lower order bit and the obtained upper order bit. A digit digital signal; and a signal processing unit that performs signal processing on a pixel signal output from the imaging device. 一種轉換方法，其係轉換裝置之轉換方法，上述轉換裝置包含：比較部，其係將輸入信號之輸入電壓、與隨時間變動之斜坡信號之斜坡電壓進行比較，上述斜坡信號具有第1斜坡及第2斜坡；及記憶部，其保持來自上述比較部之比較結果反轉時之碼值；且上述轉換方法包含如下步驟：重複由上述記憶部進行之上述碼值之保持以對上述第1斜坡取得下階位元及對上述第2斜坡取得上階位元，並組合所取得之上述下階位元及所取得之上述上階位元，藉而產生特定之位元數之數位信號。A conversion method is a conversion method of a conversion device. The conversion device includes a comparison unit that compares an input voltage of an input signal with a ramp voltage of a ramp signal that changes with time. The ramp signal has a first ramp and A second slope; and a memory unit that retains the code value when the comparison result from the comparison unit is reversed; and the conversion method includes the steps of repeating the holding of the code value by the memory unit to the first slope Obtain a lower order bit and an upper order bit for the second slope, and combine the obtained lower order bit and the obtained upper order bit to generate a digital signal with a specific number of bits.