TWI630709B - Three-dimensional semiconductor device and method of manufacturing the same - Google Patents
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Abstract
一種三維半導體元件，包括：一基板，包括一陣列區域和鄰近陣列區域之一階梯區域，其中階梯區域包括N個梯級，N為大於或等於1的整數；一堆疊，具有多層結構疊置於該基板上，且多層結構包括主動層與絕緣層交錯設置於基板上方，該堆疊包括複數個次堆疊形成於基板上，該些次堆疊與階梯區域之N個梯級對應設置以分別形成接觸區域，其中於接觸區域中各次堆疊的一最上層主動層係包括一金屬矽化物層；和多層結構連接器，分別位於對應的接觸區域，且多層結構連接器係向下延伸以電性連接各個次堆疊之金屬矽化物層。A three-dimensional semiconductor device comprising: a substrate comprising an array region and a step region adjacent to the array region, wherein the step region comprises N steps, N is an integer greater than or equal to 1; a stack having a multi-layer structure stacked thereon On the substrate, the multi-layer structure includes an active layer and an insulating layer staggered above the substrate. The stack includes a plurality of sub-stacks formed on the substrate, and the sub-stacks are disposed corresponding to the N steps of the stepped regions to respectively form contact regions, wherein An uppermost active layer layer stacked in each of the contact regions includes a metal germanide layer; and a multilayer structure connector respectively located in the corresponding contact regions, and the multilayer structure connector extends downward to electrically connect the respective sub-stacks a metal telluride layer.
Description
本發明是有關於一種三維半導體元件及其製造方法，且特別是有關於一種具金屬矽化物(silicide)之三維半導體元件及其製造方法。The present invention relates to a three-dimensional semiconductor device and a method of fabricating the same, and more particularly to a three-dimensional semiconductor device having a metal silicide and a method of fabricating the same.
非揮發性記憶體元件在設計上有一個很大的特性是，當記憶體元件失去或移除電源後仍能保存資料狀態的完整性。目前業界已有許多不同型態的非揮發性記憶體元件被提出。不過相關業者仍不斷研發新的設計或是結合現有技術，進行含記憶胞之記憶體平面的堆疊以達到具有更高儲存容量的記憶體結構。例如已有一些多層薄膜電晶體堆疊之反及閘(NAND)型快閃記憶體結構被提出。相關業者已經提出各種不同結構的三維記憶體元件，例如具單閘極(Single-Gate)之記憶胞、雙閘極(double gate)之記憶胞，和環繞式閘極(surrounding gate)之記憶胞等三維半導體元件。A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cells with memory cells to achieve a memory structure with higher storage capacity. For example, some NAND type flash memory structures have been proposed for multilayer thin film transistor stacks. Related companies have proposed three-dimensional memory components of various structures, such as memory cells with single-gate, double-gate memory cells, and memory cells of a surrounding gate. Three-dimensional semiconductor components.
相關設計者無不期望可以建構出一三維半導體結構，不僅具有許多層堆疊平面(記憶體層)而達到更高的儲存容量，更具有優異的電子特性(例如具有良好的資料保存可靠性和操作速度)，使記憶體可以被穩定和快速的如進行抹除和編程等操作。一般而言，傳統三維半導體元件會在階梯區域(staircase area)沈積一蝕刻停止層(例如氮化矽層)覆蓋接觸區域之次堆疊的多層結構(multi-layers)，使對應各接觸區域的所有接觸孔都能一致地停在蝕刻停止層上。之後，所有的接觸孔同步穿過蝕刻停止層而到達其對應的主動層(例如多晶矽層)上。然而，由於蝕刻停止層的形成會影響接觸降落窗口(contact landing windows)。若在發展一三維半導體元件時需要形成更多對的氧化層-多晶矽層(即習稱之OP層)堆疊，則需要形成更厚的蝕刻停止層，則此更厚的蝕刻停止層之形成會對接觸降落窗口造成更大的不良影響。再者，在縮小三維半導體元件尺寸時，蝕刻停止層的存在會留下更少的空間給接觸降落窗口，這對於製程和結構都會造成問題。It is hoped by the relevant designers that a three-dimensional semiconductor structure can be constructed, which not only has many layer stacking planes (memory layers) but also achieves higher storage capacity and superior electronic characteristics (for example, good data storage reliability and operation speed). ), so that the memory can be stabilized and fast as operations such as erasing and programming. In general, a conventional three-dimensional semiconductor device deposits an etch stop layer (for example, a tantalum nitride layer) in a staircase area to cover a multi-layered layer of a contact region, so that all the corresponding contact regions are The contact holes are uniformly stopped on the etch stop layer. Thereafter, all of the contact holes are synchronized through the etch stop layer to their corresponding active layers (eg, polysilicon layers). However, the formation of the etch stop layer affects the contact landing windows. If more pairs of oxide-polysilicon layers (ie, known as OP layers) are required to be formed in the development of a three-dimensional semiconductor device, a thicker etch stop layer needs to be formed, and the thicker etch stop layer is formed. It has a greater adverse effect on the contact landing window. Moreover, when the size of the three-dimensional semiconductor component is reduced, the presence of the etch stop layer leaves less space for contacting the landing window, which causes problems for both the process and the structure.
本發明係有關於一種三維半導體元件及其製造方法。根據實施例之三維半導體元件，藉由形成金屬矽化物(silicide)可大幅增加接觸降落窗口(contact landing windows)。The present invention relates to a three-dimensional semiconductor device and a method of fabricating the same. According to the three-dimensional semiconductor element of the embodiment, the contact landing windows can be greatly increased by forming a metal silicide.
根據實施例，係提出一種三維半導體元件，包括：一基板，包括一陣列區域(array area)和鄰近陣列區域之一階梯區域(staircase area)，其中階梯區域包括N個梯級(N steps)，N為大於或等於1的整數；一堆疊，具有多層結構(multi-layers)疊置於該基板上，且多層結構包括主動層與絕緣層交錯設置於基板上方，該堆疊包括複數個次堆疊(sub-stacks)形成於基板上，該些次堆疊與階梯區域之N個梯級對應設置以分別形成接觸區域(contact regions)，其中於接觸區域中各次堆疊的一最上層主動層(an uppermost active layer)係包括一金屬矽化物層(silicide layer)；和多層結構連接器(multilayered connectors)，分別位於對應的接觸區域，且多層結構連接器係向下延伸以電性連接各個次堆疊之金屬矽化物層。According to an embodiment, a three-dimensional semiconductor device is provided, comprising: a substrate comprising an array area and a staircase area adjacent to the array area, wherein the step area comprises N steps, N An integer greater than or equal to 1; a stack having multi-layers stacked on the substrate, and the multilayer structure including an active layer and an insulating layer interleaved over the substrate, the stack including a plurality of sub-stacks (sub -stacks) formed on the substrate, the sub-stacks being disposed corresponding to the N steps of the stepped regions to respectively form contact regions, wherein an uppermost active layer is stacked in each of the contact regions a system comprising a metal silicide layer; and a multilayered connector, respectively located in the corresponding contact regions, and the multilayer structure connector extending downwardly to electrically connect the metal halides of each of the sub-stacks Floor.
根據實施例，係提出一種三維半導體元件之製造方法，包括：提供具有一陣列區域和鄰近陣列區域之一階梯區域之一基板，其中階梯區域包括N個梯級，N為大於或等於1的整數；形成具有多層結構之一堆疊於該基板上，且多層結構包括主動層與絕緣層交錯設置於該基板上方，該堆疊包括複數個次堆疊形成於基板上，該些次堆疊與階梯區域之N個梯級對應設置以分別形成接觸區域，其中於接觸區域中各次堆疊的一最上層主動層係包括一金屬矽化物層；和形成多層結構連接器分別位於對應的接觸區域，且多層結構連接器係向下延伸以電性連接各次堆疊之金屬矽化物層。According to an embodiment, a method for fabricating a three-dimensional semiconductor device is provided, comprising: providing a substrate having an array region and a step region of an adjacent array region, wherein the step region includes N steps, and N is an integer greater than or equal to 1; Forming a multi-layered structure stacked on the substrate, and the multi-layer structure includes an active layer and an insulating layer staggered above the substrate, the stack comprising a plurality of sub-stacks formed on the substrate, and the N stacks and the step regions The steps are correspondingly arranged to respectively form contact regions, wherein an uppermost active layer layer stacked in each of the contact regions comprises a metal telluride layer; and the multilayer structure connector is respectively located in the corresponding contact region, and the multilayer structure connector system Extending downwardly to electrically connect the stacked metal halide layers.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式，作詳細說明如下：In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings
本揭露之實施例係提出一種三維半導體元件及其製造方法。根據實施例，藉由在三維半導體元件中形成金屬矽化物(silicide)的方式以大幅增加接觸降落窗口(contact landing windows)，無論三維半導體元件之OP層堆疊的層數有多少或是三維半導體元件尺寸是否縮小，都適合應用實施例。因此，根據實施例提出之具金屬矽化物之設計，可以提供應用之三維半導體元件有足夠寬的接觸降落窗口，進而增進應用元件的電子特性和性能表現。Embodiments of the present disclosure propose a three-dimensional semiconductor component and a method of fabricating the same. According to the embodiment, the contact landing windows are greatly increased by forming a metal silicide in the three-dimensional semiconductor element, regardless of the number of layers of the OP layer stack of the three-dimensional semiconductor element or the three-dimensional semiconductor element. Whether the size is reduced or not is suitable for the application embodiment. Therefore, the design of the metal halide according to the embodiment can provide a wide enough contact drop window for the applied three-dimensional semiconductor component, thereby enhancing the electronic characteristics and performance of the applied component.
本揭露可應用於許多具不同記憶胞陣列型態的三維半導體元件，例如垂直通道式(vertical-channel，VC)三維半導體元件和垂直閘極式(vertical-gate，VG)三維半導體元件，本揭露對於實施例之應用型態並沒有特別限制。第1圖係簡繪一三維半導體元件之立體圖。圖中係繪示一垂直通道式三維半導體元件為例作說明。一三維半導體元件包括一堆疊(stack)具有多層結構(multi-layers)疊置於一基板10上，基板10包括一陣列區域(array area)R A和鄰近陣列區域R A之一階梯區域(staircase area)R S，其中階梯區域R S包括N個梯級(N steps)，N為大於或等於1的整數。多層結構包括多層主動層112(i.e.記憶體層，例如是VC元件中包括了控制閘極)與絕緣層113交錯設置於基板10上方。三維半導體元件更包括複數條上方選擇線(upper selection lines)12U(上方選擇線可為共同源極線(Common Source Line)相互平行地位於主動層112(i.e.記憶體層)上方，複數條串列(strings)垂直於主動層112和上方選擇線12U，其中該些串列係電性連接至對應之上方選擇線12U。再者，三維半導體元件更包括複數條導線18(例如位元線BLs)位於上方選擇線12U上方，且該些導線18係相互平行並垂直於上方選擇線12U。複數個記憶胞係分別由串列、上方選擇線12 U和導線18定義，且記憶胞可排列為複數列(rows)及複數行(columns)以形成記憶體陣列。再者，複數個串列接觸(string contacts)17係垂直於主動層112和上方選擇線12U，且每串列接觸17之設置係對應於記憶胞之每串列，其中串列接觸17係電性連接至對應的上方選擇線12U和對應的導線18。三維半導體元件還包括其它元件，記憶體層下方更有下方選擇線(lower select lines)12L形成(下方選擇線可為反轉閘極(inversion gate, IG))。 The disclosure can be applied to a plurality of three-dimensional semiconductor components having different memory cell array types, such as vertical-channel (VC) three-dimensional semiconductor components and vertical-gate (VG) three-dimensional semiconductor components. There is no particular limitation on the application form of the embodiment. Figure 1 is a perspective view of a three-dimensional semiconductor component. The figure shows a vertical channel type three-dimensional semiconductor component as an example. A three-dimensional semiconductor device comprising a stack (Stack) has a multilayer structure (multi-layers) is stacked on a substrate 10, substrate 10 includes an array area (array area) R A and R A one array region adjacent the stepped regions (Staircase Area) R S , wherein the step region R S includes N steps, and N is an integer greater than or equal to 1. The multilayer structure includes a plurality of active layers 112 (ie, a memory layer, for example, a control gate included in the VC element) and an insulating layer 113 interleaved over the substrate 10. The three-dimensional semiconductor component further includes a plurality of upper selection lines 12U (the upper selection line may be a common source line (the Common Source Line) is located above the active layer 112 (ie memory layer) in parallel with each other, and the plurality of strings ( The strings are perpendicular to the active layer 112 and the upper select line 12U, wherein the series are electrically connected to the corresponding upper select line 12U. Further, the three-dimensional semiconductor component further includes a plurality of wires 18 (eg, bit lines BLs) located at The upper selection line 12U is above, and the wires 18 are parallel to each other and perpendicular to the upper selection line 12U. The plurality of memory cell systems are respectively defined by the series, the upper selection line 12 U and the wire 18, and the memory cells can be arranged in a plurality of columns. (rows) and complex rows (columns) to form a memory array. Further, a plurality of string contacts 17 are perpendicular to the active layer 112 and the upper selection line 12U, and the arrangement of each string of contacts 17 corresponds to In each column of the memory cell, the serial contact 17 is electrically connected to the corresponding upper selection line 12U and the corresponding wire 18. The three-dimensional semiconductor component further includes other components, and the memory layer has a lower selection below. The lower select lines 12L are formed (the lower selection line may be an inversion gate (IG)).
再者，實施例之堆疊包括複數個次堆疊(sub-stacks)形成於基板10上，且該些次堆疊與階梯區域R S之N個梯級對應設置以分別形成接觸區域(contact regions)R C。實施例之三維半導體元件更包括複數個多層結構連接器(multilayered connectors)(未繪示於第1圖。但可參照第2圖之多層結構連接器CT1-CT8)，分別位於對應的接觸區域R C。根據實施例，接觸區域R C中各個次堆疊的一最上層主動層(an uppermost active layer)係包括一金屬矽化物層(silicide layer)以覆蓋降落區域(ex: 一接觸墊，例如字元線接觸(word line pad))，且多層結構連接器係向下延伸以電性連接(例如直接接觸)各次堆疊之金屬矽化物層。於一實施例中，階梯區域R S中對應接觸區域R C之次堆疊的主動層係來自於陣列區域R A主動層(例如是做為字元線的多晶矽層)的延伸。以下係以在階梯區域R S中形成金屬矽化物之三維半導體元件之其中之一種態樣為例作實施例之三維半導體元件的說明，但本揭露並不僅限於此。 Furthermore, the stack of the embodiment includes a plurality of sub-stacks formed on the substrate 10, and the sub-stacks are disposed corresponding to the N steps of the step region R S to form contact regions R C , respectively. . The three-dimensional semiconductor device of the embodiment further includes a plurality of multilayered connectors (not shown in FIG. 1 but can refer to the multilayer structure connectors CT1 - CT8 of FIG. 2 ), respectively located in the corresponding contact regions R C. According to an embodiment, an uppermost active layer of each sub-stack in the contact region R C includes a metal silicide layer to cover the landing region (ex: a contact pad, such as a word line A word line pad, and the multilayer structure connector extends downwardly to electrically connect (eg, directly contact) each of the stacked metal halide layers. In one embodiment, the step corresponding to the region R S R C times the contact region of the active layer stacked array region R A system from the active layer (e.g., a polysilicon layer as a word line) which extends embodiment. Hereinafter, a description will be given of one of the three-dimensional semiconductor elements in which the metal germanide is formed in the step region R S as an example of the three-dimensional semiconductor device of the embodiment, but the disclosure is not limited thereto.
以下係參照所附圖式敘述本揭露提出之其中多個實施態樣，以描述相關構型與製造方法。相關的結構細節例如相關層別和空間配置等內容如下面實施例內容所述。然而，但本揭露並非僅限於所述態樣，本揭露並非顯示出所有可能的實施例。實施例中相同或類似的標號係用以標示相同或類似之部分。再者，未於本揭露提出的其他實施態樣也可能可以應用。相關領域者可在不脫離本揭露之精神和範圍內對實施例之結構加以變化與修飾，以符合實際應用所需。而圖式係已簡化以利清楚說明實施例之內容，圖式上的尺寸比例並非按照實際產品等比例繪製。因此，說明書和圖示內容僅作敘述實施例之用，而非作為限縮本揭露保護範圍之用。Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings to describe the related configurations and manufacturing methods. Relevant structural details such as related layers and spatial configurations are as described in the following examples. However, the disclosure is not limited to the description, and the disclosure does not show all possible embodiments. The same or similar reference numerals in the embodiments are used to designate the same or similar parts. Furthermore, other implementations not presented in this disclosure may also be applicable. Variations and modifications of the structure of the embodiments can be made in the relevant embodiments without departing from the spirit and scope of the disclosure. The drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to scale in terms of actual products. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.
再者，說明書與請求項中所使用的序數例如”第一”、”第二”、”第三”等之用詞，以修飾請求項之元件，其本身並不意含及代表該請求元件有任何之前的序數，也不代表某一請求元件與另一請求元件的順序、或是製造方法上的順序，該些序數的使用僅用來使具有某命名的一請求元件得以和另一具有相同命名的請求元件能作出清楚區分。Furthermore, the terms used in the specification and the claims, such as "first", "second", "third" and the like, are used to modify the elements of the claim, which are not intended to be Any previous ordinal does not represent the order of a request element and another request element, or the order of the manufacturing method. The use of these ordinals is only used to make one request element with a certain name the same as the other. Named request elements can make a clear distinction.
第2圖為本揭露一實施例之一三維半導體元件的階梯區域之剖面示意圖。第3A圖至第3L圖繪示根據一實施例於階梯區域中形成金屬矽化物的三維半導體元件之一種製造方法。在第2圖和第3A圖至第3L圖中，係以8對主動層和絕緣層以及8個接觸區域(P1-P8; N=8)為例做一實施例之說明。當然，接觸區域的數目以及主動層與絕緣層成對的數目可以依照實際應用之條件所需而改變。再者，為了達到能清楚呈現與說明實施例構型之目的，於第2圖和第3A圖至第3L圖中係省略了位於8對主動層和絕緣層下方一些已知層(例如：氧化層、選擇線層和基板)之繪製。FIG. 2 is a cross-sectional view showing a stepped region of a three-dimensional semiconductor device according to an embodiment of the present invention. 3A to 3L illustrate a method of fabricating a three-dimensional semiconductor device in which a metal telluride is formed in a step region according to an embodiment. In Fig. 2 and Figs. 3A to 3L, an embodiment is described by taking 8 pairs of active layers and insulating layers and 8 contact regions (P1-P8; N=8) as an example. Of course, the number of contact regions and the number of active layers in pairs with the insulating layer can be varied as required by the conditions of the actual application. Furthermore, for the purpose of clearly illustrating and illustrating the configuration of the embodiment, some known layers (for example, oxidation) located under 8 pairs of active layers and insulating layers are omitted in FIGS. 2 and 3A to 3L. Drawing of layers, selection line layers, and substrates).
如第2圖所示，實施例之堆疊包括形成於基板上方的數個次堆疊，且該些次堆疊設置於階梯區域(如第1圖所示之R S)中對應之接觸區域P1、P2、P3、P4、P5、P6、P7和P8(i.e. 8個梯級；N＝8)。其主動層(例如212-1、212-2、212-3、212-4、212-5、212-6、212-7)與絕緣層(如213-1、213-2、213-3、213-4、213-5、213-6、213-7)交錯設置於實施例三維半導體元件的階梯區域中。階梯區域中，實施例之三維半導體元件還包括多層結構連接器例如CT1、CT2、CT3、CT4、CT5、CT6、CT7和CT8分別位於對應的接觸區域P1- P8。再者，根據實施例，接觸區域中各次堆疊的一最上層主動層(an uppermost active layer)係包括一金屬矽化物層(silicide layer)；例如第2圖所示，金屬矽化物層24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8分別形成於接觸區域P1、P2、P3、P4、P5、P6、P7和P8。一實施例中，對於接觸區域的各個次堆疊，位於金屬矽化物層下方的主動層可皆為多晶矽層。多層結構連接器例如CT1、CT2、CT3、CT4、CT5、CT6、CT7和CT8係向下延伸以分別電性連接(例如直接接觸)各次堆疊之金屬矽化物層如24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8。 As shown in FIG. 2, the stack of the embodiment includes a plurality of sub-stacks formed over the substrate, and the sub-stacks are disposed in the corresponding contact regions P1, P2 in the step region (such as R S shown in FIG. 1). , P3, P4, P5, P6, P7 and P8 (ie 8 steps; N=8). Its active layers (such as 212-1, 212-2, 212-3, 212-4, 212-5, 212-6, 212-7) and insulating layers (such as 213-1, 213-2, 213-3, 213-4, 213-5, 213-6, 213-7) are alternately disposed in the stepped region of the three-dimensional semiconductor element of the embodiment. In the step region, the three-dimensional semiconductor device of the embodiment further includes a multilayer structure connector such as CT1, CT2, CT3, CT4, CT5, CT6, CT7 and CT8 respectively located in the corresponding contact regions P1 - P8. Moreover, according to an embodiment, an uppermost active layer of each of the stacked regions in the contact region includes a metal silicide layer; for example, as shown in FIG. 2, the metal halide layer 24- 1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7, and 24-8 are formed in the contact regions P1, P2, P3, P4, P5, P6, P7, and P8, respectively. In one embodiment, for each sub-stack of the contact regions, the active layers under the metal telluride layer may all be polycrystalline germanium layers. Multi-layered structural connectors such as CT1, CT2, CT3, CT4, CT5, CT6, CT7, and CT8 extend downwardly to electrically connect (eg, directly contact) each of the stacked metal halide layers, such as 24-1, 24-2. , 24-3, 24-4, 24-5, 24-6, 24-7, and 24-8.
值得注意的是，第2圖僅繪示其中一種實施態樣，亦即各個次堆疊之最上層主動層為24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8，其皆為金屬矽化物層，其中可利用在製程中將各個次堆疊之一最上層多晶矽層完全轉換而得到金屬矽化物層。然而，本揭露並不以此為限。於一些實施例中，各個次堆疊之最上層主動層亦可包括一多晶矽層和一金屬矽化物層形成於多晶矽層上方(例如藉由將各個次堆疊之一最上層多晶矽層部分轉換而得，其結構細節係於第4圖和相關段落中敘述)。It should be noted that FIG. 2 only shows one embodiment, that is, the uppermost active layers of each sub-stack are 24-1, 24-2, 24-3, 24-4, 24-5, 24- 6, 24-7 and 24-8, all of which are metal telluride layers, wherein a metal germanide layer can be obtained by completely converting one of the uppermost polycrystalline germanium layers of each sub-stack in the process. However, the disclosure is not limited thereto. In some embodiments, the uppermost active layer of each sub-stack may further include a polysilicon layer and a metal germanide layer formed over the polysilicon layer (for example, by converting a portion of the uppermost polycrystalline layer of each sub-stack, The structural details are described in Figure 4 and related paragraphs).
再者，三維半導體元件更包括一介電層26(如層間介電層(ILD))形成於該些接觸區域(ex: P1-P8)的次堆疊上。多層結構連接器(ex: CT1、CT2、CT3、CT4、CT5、CT6、CT7和CT8)係在介電層26中向下延伸，其中介電層26直接接觸各個次堆疊之金屬矽化物層24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8。如第2圖所示，於接觸區域(P1-P8)之各個次堆疊的金屬矽化物層24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8係做為各個次堆疊的降落區域，且所有降落區域(i.e.金屬矽化物層的上表面)除了被多層結構連接器CT1-CT8接觸的部分以外都被介電層26直接覆蓋。Furthermore, the three-dimensional semiconductor component further includes a dielectric layer 26 (such as an interlayer dielectric layer (ILD)) formed on the sub-stack of the contact regions (ex: P1-P8). The multilayer structure connectors (ex: CT1, CT2, CT3, CT4, CT5, CT6, CT7, and CT8) extend downwardly in the dielectric layer 26, wherein the dielectric layer 26 directly contacts the metal halide layer 24 of each sub-stack. -1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7 and 24-8. As shown in Fig. 2, the metal halide layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-4 are stacked in the contact regions (P1-P8). 7 and 24-8 are used as landing areas for each sub-stack, and all landing areas (the upper surface of the IE metallization layer) are directly covered by the dielectric layer 26 except for the portion that is contacted by the multilayer structure connectors CT1-CT8. .
再者，根據一實施例之三維半導體元件，於接觸區域(ex: P1-P8)中該些次堆疊的主動層212之側端(lateral ends of the active layers)包括金屬矽化物部份(silicide portions)。例如第2圖所示之分別對應接觸區域P3-P8中的金屬矽化物部份240-3、240-4、240-5、240-6、240-7和240-8。且介電層26直接接觸主動層的金屬矽化物部份240-3、240-4、240-5、240-6、240-7和 240-8。根據實施例，金屬矽化物層24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8與金屬矽化物部份240-3、240-4、240-5、240-6、240-7和 240-8包括相同材料。Furthermore, according to the three-dimensional semiconductor component of an embodiment, the lateral ends of the active layers of the sub-stacked active layers 212 in the contact regions (ex: P1-P8) include a metal halide portion (silicide) Portions). For example, the metal halide portions 240-3, 240-4, 240-5, 240-6, 240-7, and 240-8 in the contact regions P3-P8 are shown in Fig. 2, respectively. The dielectric layer 26 is in direct contact with the metal halide portions 240-3, 240-4, 240-5, 240-6, 240-7 and 240-8 of the active layer. According to an embodiment, the metal telluride layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7, and 24-8 and the metal telluride portions 240-3, 240 -4, 240-5, 240-6, 240-7, and 240-8 include the same material.
第3A圖至第3L圖繪示一種如第2圖所示於階梯區域中形成金屬矽化物的三維半導體元件之製造方法。第3A圖至第3F圖係例示如何形成N個梯級的其中一種應用程序(圖中N=8)。值得注意的是，於第3A圖至第3F圖所顯示之步驟僅是提供做示例之用，其他的蝕刻方法亦可應用以製得階梯區域的N個梯級之相應次堆疊。3A to 3L are views showing a method of manufacturing a three-dimensional semiconductor element in which a metal halide is formed in a step region as shown in Fig. 2. Figures 3A through 3F illustrate how one of the N steps can be formed (N = 8 in the figure). It should be noted that the steps shown in Figures 3A through 3F are provided for illustrative purposes only, and other etching methods may be applied to produce corresponding sub-stacks of N steps of the step region.
如第3A圖所示，一多層結構包括主動層(例如212-1、212-2、212-3、212-4、212-5、212-6、212-7和212-8)與絕緣層(如213-1、213-2、213-3、213-4、213-5、213-6、213-7和213-8)交錯設置於基板(未顯示)上方(例如是包括8對的多晶矽層和氧化層；及習稱之OP對)，且設置一第一圖案化光阻層(first patterned photo-resist layer)PR1於多層結構上並對應接觸區域P8、P6、P4和P2。接著，以第一圖案化光阻層PR1對主動層212-8和絕緣層213-8進行圖案化，以移除對應接觸區域P1、P3、P5和P7的主動層212-8和絕緣層213-8，如第3B圖所示。之後，移除第一圖案化光阻層PR1。As shown in FIG. 3A, a multilayer structure includes active layers (eg, 212-1, 212-2, 212-3, 212-4, 212-5, 212-6, 212-7, and 212-8) and insulation. The layers (such as 213-1, 213-2, 213-3, 213-4, 213-5, 213-6, 213-7, and 213-8) are staggered over the substrate (not shown) (for example, including 8 pairs) a polycrystalline germanium layer and an oxide layer; and a conventional OP pair), and a first patterned photo-resist layer PR1 is disposed on the multilayer structure and corresponds to the contact regions P8, P6, P4, and P2. Next, the active layer 212-8 and the insulating layer 213-8 are patterned with the first patterned photoresist layer PR1 to remove the active layer 212-8 and the insulating layer 213 of the corresponding contact regions P1, P3, P5, and P7. -8, as shown in Figure 3B. Thereafter, the first patterned photoresist layer PR1 is removed.
如第3C圖所示，設置一第二圖案化光阻層PR2於多層結構上並對應接觸區域P8、P4、P3和P7。接著，以第二圖案化光阻層PR2對第3C圖之多層結構進行圖案化，以移除對應接觸區域P6、P2、P1和P5的兩對主動層和絕緣層，如第3D圖所示。之後，移除第二圖案化光阻層PR2。As shown in FIG. 3C, a second patterned photoresist layer PR2 is disposed on the multilayer structure and corresponds to the contact regions P8, P4, P3, and P7. Next, the multilayer structure of the 3Cth layer is patterned by the second patterned photoresist layer PR2 to remove the two pairs of active layers and insulating layers corresponding to the contact regions P6, P2, P1, and P5, as shown in FIG. 3D. . Thereafter, the second patterned photoresist layer PR2 is removed.
如第3E圖所示，設置一第三圖案化光阻層PR3於多層結構上並對應接觸區域P8、P6、P5和P7。接著，以第三圖案化光阻層PR3對第3E圖之多層結構進行圖案化，以移除對應接觸區域P4、P2、P1 和P3的四對主動層和絕緣層，如第3F圖所示。之後，移除第三圖案化光阻層PR3。至此，已製得階梯區域中N個梯級(N=8)之次堆疊於相應之接觸區域中P1-P8。As shown in FIG. 3E, a third patterned photoresist layer PR3 is disposed on the multilayer structure and corresponds to the contact regions P8, P6, P5, and P7. Next, the multilayer structure of FIG. 3E is patterned by the third patterned photoresist layer PR3 to remove four pairs of active layers and insulating layers corresponding to the contact regions P4, P2, P1, and P3, as shown in FIG. 3F. . Thereafter, the third patterned photoresist layer PR3 is removed. So far, the N steps (N=8) in the stepped region have been produced and stacked in the corresponding contact regions P1-P8.
如第3G圖所示，完全移除接觸區域中P1-P8各個次堆疊的最上層絕緣層(例如氧化層)，例如是藉由蝕刻氧化物。亦即，分別位於接觸區域P8、P6、P4、P2、P1、P3、P5和P7 (第3F圖)中的最上層絕緣層213-8、213-6、213-4、213-2、213-1、213-3、213-5、213-7皆被完全移除，以暴露出最上層主動層。As shown in FIG. 3G, the uppermost insulating layer (for example, an oxide layer) of each of P1-P8 stacked in the contact region is completely removed, for example, by etching an oxide. That is, the uppermost insulating layers 213-8, 213-6, 213-4, 213-2, 213 located in the contact regions P8, P6, P4, P2, P1, P3, P5, and P7 (Fig. 3F), respectively. -1, 213-3, 213-5, 213-7 are all completely removed to expose the uppermost active layer.
如第3H圖所示，沈積一金屬層25於接觸區域P1-P8中各次堆疊的一最上層主動層上(例如多晶矽層)，且金屬層25亦沈積於次堆疊的裸露側壁(exposed sidewalls)上。因此，金屬層25是地毯式地覆蓋在第3H圖之接觸區域P1-P8的次堆疊上。一實施例中，金屬層25可包括鈷(Co)、鎳(Ni)、鈦(Ti)或其他適合之金屬材料。As shown in FIG. 3H, a metal layer 25 is deposited on an uppermost active layer (eg, a polysilicon layer) stacked in each of the contact regions P1-P8, and the metal layer 25 is also deposited on the exposed sidewalls of the sub-stack (exposed sidewalls). )on. Therefore, the metal layer 25 is carpet-covered on the secondary stack of the contact regions P1 - P8 of the 3H. In one embodiment, the metal layer 25 may comprise cobalt (Co), nickel (Ni), titanium (Ti), or other suitable metallic materials.
之後，如第3I圖所示，對結構進行熱退火處理(thermally annealing)以於接觸區域P1-P8之各次堆疊形成金屬矽化物層24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8；一應用例中，例如是(但不限制是)在高溫600°C -1000°C範圍之間進行熱退火處理。由於金屬層25也是沈積於次堆疊的裸露側壁上，在進行熱退火處理後係於次堆疊對應該些裸露側壁之主動層(例如212-2、212-3、212-4、212-5、212-6和212-7)的各個側端形成金屬矽化物部份(例如240-3、240-4、240-5、240-6、240-7和240-8)。Thereafter, as shown in FIG. 3I, the structure is thermally annealed to form metal telluride layers 24-1, 24-2, 24-3, 24-4 in each of the contact regions P1-P8. , 24-5, 24-6, 24-7, and 24-8; in an application example, for example, but not limited to, thermal annealing treatment is performed at a high temperature ranging from 600 ° C to 1000 ° C. Since the metal layer 25 is also deposited on the exposed sidewalls of the sub-stack, after being thermally annealed, it is attached to the active layer of the sub-stack corresponding to the exposed sidewalls (for example, 212-2, 212-3, 212-4, 212-5, The metal halide portions (e.g., 240-3, 240-4, 240-5, 240-6, 240-7, and 240-8) are formed at the respective side ends of 212-6 and 212-7).
於一實施例中，金屬矽化物層包括含鈷之矽化物、含鎳之矽化物、含鈦之矽化物、含鉬之矽化物和含鎢之矽化物至少其中之一。例如，金屬矽化物層可能包括矽化鈷(CoSi)、二矽化鈷(CoSi 2)、或包括兩者之混合物。於其他實施例，金屬矽化物層可能包括矽化鈦(TiSi)、二矽化鈦(TiSi 2)、或包括兩者之混合物。於其他實施例，金屬矽化物層可能包括矽化鎳(NiSi)、鎳矽化物(NiSi X，x≠1)、或包括兩者之混合物。例如，其他可應用之金屬矽化物層的材料還可包括二矽化鉬(Molybdenum disilicide，MoSi 2)、矽化鎢(tungsten silicide，WSi 2)。金屬矽化物層的材料係視實際應用時熱退火處理條件而改變，本揭露對此並不多做限制。實施例形成之金屬矽化物對於氧化物而言有高的蝕刻選擇比。 In one embodiment, the metal telluride layer comprises at least one of a cobalt-containing telluride, a nickel-containing telluride, a titanium-containing telluride, a molybdenum-containing telluride, and a tungsten-containing telluride. For example, the metal telluride layer may include cobalt telluride (CoSi), cobalt dichloride (CoSi 2 ), or a mixture of the two. In other embodiments, the metal telluride layer may include titanium telluride (TiSi), titanium dititanide (TiSi 2 ), or a mixture thereof. In other embodiments, the metal telluride layer may include nickel telluride (NiSi), nickel telluride (NiSi X , x≠1), or a mixture of the two. For example, materials of other applicable metal telluride layers may also include molybdenum disilicide (MoSi 2 ), tungsten tungsten silicide (WSi 2 ). The material of the metal telluride layer varies depending on the thermal annealing treatment conditions in practical use, and the present disclosure does not limit this. The metal halide formed in the examples has a high etching selectivity for the oxide.
如第3J圖所示，移除未反應之金屬層25(例如非矽化鈷的部分)以露出次堆疊之金屬矽化物層例如24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8，以及金屬矽化物部份例如240-3、240-4、240-5、240-6、240-7和240-8。As shown in FIG. 3J, the unreacted metal layer 25 (eg, a portion of non-deuterium cobalt) is removed to expose the sub-stacked metal halide layers such as 24-1, 24-2, 24-3, 24-4, 24 -5, 24-6, 24-7 and 24-8, and metal halide parts such as 240-3, 240-4, 240-5, 240-6, 240-7 and 240-8.
接著，沈積一絕緣層例如一層間介電層(ILD)於次堆疊上，並進行化學機械研磨(CMP)以形成介電層26，如第3K圖所示。介電層26直接接觸各次堆疊之金屬矽化物層24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8以及直接接觸金屬矽化物部份240-3、240-4、240-5、240-6、240-7和240-8。Next, an insulating layer such as an interlayer dielectric layer (ILD) is deposited on the sub-stack and subjected to chemical mechanical polishing (CMP) to form the dielectric layer 26, as shown in FIG. 3K. The dielectric layer 26 is in direct contact with each of the stacked metal halide layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7, and 24-8 and direct contact metal deuteration Object parts 240-3, 240-4, 240-5, 240-6, 240-7 and 240-8.
如第3L圖所示，形成多個多層結構連接器CT1、CT2、CT3、CT4、CT5、CT6、CT7和CT8在介電層26中向下延伸，以與各接觸區域P1-P8之金屬矽化物層24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8直接接觸。如第3L圖/第2圖所示，於一實施例中，各個次堆疊的一降落區域(landing area) 在沿一第一方向(ex：X方向),上具有一第一寬度(first width) d1，於接觸區域P1-P8中各次堆疊之金屬矽化物層24-1、24-2、24-3、24-4、24-5、24-6、24-7和24-8在沿第一方向上具有一第二寬度(second width)d2，其中第一寬度d1基本上等於第二寬度d2。根據實施例提出之三維半導體元件，由於在各接觸區域中的次堆疊之金屬矽化物層即做為降落區域之用，相較於傳統三維半導體元件，實施例之三維半導體元件會具有更大的接觸降落窗口(contact landing windows)，特別是對於在最底端只有一層主動層的接觸區域P1其接觸降落窗口增加的更多。As shown in FIG. 3L, a plurality of multilayer structure connectors CT1, CT2, CT3, CT4, CT5, CT6, CT7, and CT8 are formed to extend downward in the dielectric layer 26 to be deuterated with the metal of each of the contact regions P1-P8. The layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7 and 24-8 are in direct contact. As shown in FIG. 3L/FIG. 2, in an embodiment, a landing area of each sub-stack has a first width (first width) along a first direction (ex: X direction). D1, the metal halide layers 24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7 and 24-8 stacked in each of the contact regions P1-P8 are There is a second width d2 in the first direction, wherein the first width d1 is substantially equal to the second width d2. According to the three-dimensional semiconductor element proposed in the embodiment, since the sub-stacked metal telluride layer in each contact region is used as a landing region, the three-dimensional semiconductor device of the embodiment has a larger size than the conventional three-dimensional semiconductor device. Contact landing windows, in particular for the contact area P1 having only one active layer at the bottom end, the contact drop window is increased more.
第4圖為本揭露另一實施例之一三維半導體元件的階梯區域之剖面示意圖。前述第2圖和第3A-3L圖是繪示其中一種實施態樣，亦即各個次堆疊之最上層主動層(例如212-1、212-2、212-3、212-4、212-5、212-6、212-7和212-8)係皆為金屬矽化物層，其中可利用在熱退火處理步驟(如第3I圖所示之步驟) 中將各個次堆疊之最上層多晶矽層完全轉換而得到。但本揭露並不以此為限。第4圖即顯示各個次堆疊之最上層主動層包括了一多晶矽層(例如212-8/212-7/212-6/212-5/212-4/212-3/212-2/212-1)和一金屬矽化物層(例如24-1’/24-2’/24-3’/24-4’/24-5’/24-6’ /24-7’/24-8’)形成於多晶矽層上方。如第4圖所示，金屬矽化物層 24-1’、24-2’、24-3’、24-4’、24-5’、24-6’、24-7’和24-8’可藉由部分轉換各個次堆疊之最上層多晶矽層而得，而未被反應的多晶矽則位於金屬矽化物層下方。再者，各個次堆疊也形成有金屬矽化物部份240-3’、240-4’、240-5’、240-6’、240-7’和240-8’(請參照上述實施例之內容與第2圖和第3A-3L圖)。於一示例中(但非限制揭露範圍)，在熱退火處理步驟進行之前，最上層多晶矽層 係具有一厚度約300Å，進行熱退火處理之後，係產生厚度約200Å的金屬矽化物層 24-1’、24-2’、24-3’、24-4’、24-5’、24-6’、24-7’和24-8’，以及厚度約100Å的多晶矽層於金屬矽化物層下方。根據本揭露，可透過調整熱退火處理的參數而控制各個次堆疊之最上層多晶矽層是否被全部轉換、或是部分轉換為金屬矽化物，視實際應用時之需求而定。FIG. 4 is a cross-sectional view showing a stepped region of a three-dimensional semiconductor device according to another embodiment of the present disclosure. The foregoing FIG. 2 and FIG. 3A-3L are diagrams showing one embodiment, that is, the uppermost active layers of each sub-stack (for example, 212-1, 212-2, 212-3, 212-4, 212-5). , 212-6, 212-7 and 212-8) are all metal telluride layers, wherein the uppermost polycrystalline germanium layer of each sub-stack can be completely used in the thermal annealing treatment step (such as the step shown in FIG. 3I). Converted to get. However, this disclosure is not limited to this. Figure 4 shows that the top active layer of each sub-stack includes a polysilicon layer (for example, 212-8/212-7/212-6/212-5/212-4/212-3/212-2/212- 1) and a metal telluride layer (for example, 24-1'/24-2'/24-3'/24-4'/24-5'/24-6'/24-7'/24-8') Formed above the polysilicon layer. As shown in Fig. 4, metal telluride layers 24-1', 24-2', 24-3', 24-4', 24-5', 24-6', 24-7' and 24-8' It can be obtained by partially converting the uppermost polycrystalline germanium layer of each sub-stack, while the unreacted polycrystalline germanium is located below the metal germanide layer. Furthermore, the metal halide portions 240-3', 240-4', 240-5', 240-6', 240-7', and 240-8' are also formed in each sub-stack (refer to the above embodiment). Content and Figure 2 and Figure 3A-3L). In an example (but not limiting), the uppermost polysilicon layer has a thickness of about 300 Å before the thermal annealing process, and after thermal annealing, a metal telluride layer 24-1 having a thickness of about 200 Å is produced. ', 24-2', 24-3', 24-4', 24-5', 24-6', 24-7' and 24-8', and a polycrystalline layer of approximately 100 Å thick below the metal telluride layer . According to the disclosure, whether the uppermost polysilicon layer of each sub-stack is completely converted or partially converted into metal telluride can be controlled by adjusting the parameters of the thermal annealing process, depending on the requirements of the actual application.
根據上述實施例所揭露之內容，藉由在三維半導體元件中形成金屬矽化物(silicide)的方式可大幅增加接觸降落窗口。根據實施例，各接觸區域P1-P8的最上層主動層係包括金屬矽化物。例如在製程中，可對暴露出的主動層如多晶矽層進行熱退火處理以形成金屬矽化物層。根據實施例，於各接觸區域之各個次堆疊的金屬矽化物層係做為各個次堆疊的降落區域，且這些降落區域具有相同寬度(d1)以使多層結構連接器降落，相較於傳統三維半導體元件(i.e.採用氮化矽層做為一蝕刻停止層，以使對應各接觸區域的所有接觸孔能一致地停在蝕刻停止層上)，實施例之三維半導體元件具有更大的接觸降落窗口。再者，若傳統三維半導體元件需要的OP層堆疊層數越多，則所需的蝕刻停止層(ex: SiN)之厚度越厚，這會使接觸區域的接觸降落窗口變得更小，特別是對於在最底端只有一層主動層的接觸區域P1其接觸降落窗口會縮小的更多。但根據實施例提出的三維半導體元件，不需要形成蝕刻停止層來使所有接觸孔一致地停在上面，因此無論發展的三維半導體元件需要的OP層堆疊層數有多少、或是三維半導體元件尺寸是否縮小，各接觸區域的降落區域都具有足夠的寬度(例如第2/3L/4圖所示之寬度d1或d2)來使多層結構連接器降落。According to the disclosure of the above embodiments, the contact drop window can be greatly increased by forming a metal silicide in the three-dimensional semiconductor element. According to an embodiment, the uppermost active layer of each of the contact regions P1-P8 comprises a metal telluride. For example, in the process, the exposed active layer, such as a polysilicon layer, may be thermally annealed to form a metal telluride layer. According to an embodiment, each of the metal halide layers stacked in each contact region is used as a landing region of each sub-stack, and these landing regions have the same width (d1) to cause the multilayer structure connector to fall, compared to the conventional three-dimensional The semiconductor device (ie uses a tantalum nitride layer as an etch stop layer so that all contact holes corresponding to the respective contact regions can uniformly stop on the etch stop layer), and the three-dimensional semiconductor device of the embodiment has a larger contact drop window . Furthermore, if the number of OP layer stack layers required for the conventional three-dimensional semiconductor element is larger, the thicker the etching stop layer (ex: SiN) is required, which makes the contact drop window of the contact region smaller, especially For the contact area P1 having only one active layer at the bottom end, the contact drop window is shrunk more. However, according to the three-dimensional semiconductor element proposed in the embodiment, it is not necessary to form an etch stop layer to uniformly stop all the contact holes, so that the number of OP layer stack layers required for the developed three-dimensional semiconductor element, or the size of the three-dimensional semiconductor element Whether or not the reduction is made, the landing area of each contact area has a sufficient width (for example, the width d1 or d2 shown in Fig. 2/3L/4) to cause the multilayer structure connector to fall.
其他實施例，例如元件的已知構件有不同的設置與排列等，亦可能可以應用，係視應用時之實際需求與條件而可作適當的調整或變化。因此，說明書與圖式中所示之結構僅作說明之用，並非用以限制本揭露欲保護之範圍。另外，相關技藝者當知，實施例中構成部件的形狀和位置亦並不限於圖示所繪之態樣，亦是根據實際應用時之需求和/或製造步驟在不悖離本揭露之精神的情況下而可作相應調整。Other embodiments, such as known components of components, may have different arrangements and arrangements, and may be applied, depending on the actual needs and conditions of the application, and may be appropriately adjusted or changed. Therefore, the structures shown in the specification and drawings are for illustrative purposes only and are not intended to limit the scope of the disclosure. In addition, it is to be understood by those skilled in the art that the shapes and positions of the components in the embodiments are not limited to those illustrated in the drawings, and the requirements and/or manufacturing steps according to actual applications are not deviated from the spirit of the disclosure. In the case of the situation can be adjusted accordingly.
綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
10‧‧‧基板
RA‧‧‧陣列區域
RS‧‧‧階梯區域
RC、P1、P2、P3、P4、P5、P6、P7、P8‧‧‧接觸區域
12U‧‧‧上方選擇線
12L‧‧‧下方選擇線
17‧‧‧串列接觸
18‧‧‧導線
112、212-1、212-2、212-3、212-4、212-5、212-6、212-7、212-8‧‧‧主動層
113、213-1、213-2、213-3、213-4、213-5、213-6、213-7、213-8‧‧‧絕緣層
CT1、CT2、CT3、CT4、CT5、CT6、CT7、CT8‧‧‧多層結構連接器
24-1、24-2、24-3、24-4、24-5、24-6、24-7、24-8、24-1’、24-2’、24-3’、24-4’、24-5’、24-6’、24-7’、24-8’‧‧‧金屬矽化物層
240-3、240-4、240-5、240-6、240-7、240-8、240-3’、240-4’、240-5’、240-6’、240-7’、240-8’‧‧‧金屬矽化物部份
25‧‧‧金屬層
26‧‧‧介電層
PR1‧‧‧第一圖案化光阻層
PR2‧‧‧第二圖案化光阻層
PR3‧‧‧第三圖案化光阻層
d1‧‧‧第一寬度
d2‧‧‧第二寬度10‧‧‧Substrate
R A ‧‧‧Array area
R S ‧‧‧ ladder area
R C , P1 , P2 , P3 , P4 , P5 , P6 , P7 , P8‧‧‧ contact areas
12U‧‧‧ top selection line
12L‧‧‧ selection line below
17‧‧‧ Serial contact
18‧‧‧Wire
112, 212-1, 212-2, 212-3, 212-4, 212-5, 212-6, 212-7, 212-8‧‧‧ active layer
113, 213-1, 213-2, 213-3, 213-4, 213-5, 213-6, 213-7, 213-8‧‧‧ insulation
CT1, CT2, CT3, CT4, CT5, CT6, CT7, CT8‧‧‧ multilayer structure connectors
24-1, 24-2, 24-3, 24-4, 24-5, 24-6, 24-7, 24-8, 24-1', 24-2', 24-3', 24-4 ', 24-5', 24-6', 24-7', 24-8'‧‧‧ metal telluride layer
240-3, 240-4, 240-5, 240-6, 240-7, 240-8, 240-3', 240-4', 240-5', 240-6', 240-7', 240 -8'‧‧‧Metal Telluride Part
25‧‧‧metal layer
26‧‧‧Dielectric layer
PR1‧‧‧First patterned photoresist layer
PR2‧‧‧Second patterned photoresist layer
PR3‧‧‧The third patterned photoresist layer
D1‧‧‧first width
D2‧‧‧ second width
第1圖係簡繪一三維半導體元件之立體圖。 第2圖為本揭露一實施例之一三維半導體元件的階梯區域之剖面示意圖。 第3A圖至第3L圖繪示根據一實施例於階梯區域中形成金屬矽化物的三維半導體元件之一種製造方法。 第4圖為本揭露另一實施例之一三維半導體元件的階梯區域之剖面示意圖。Figure 1 is a perspective view of a three-dimensional semiconductor component. FIG. 2 is a cross-sectional view showing a stepped region of a three-dimensional semiconductor device according to an embodiment of the present invention. 3A to 3L illustrate a method of fabricating a three-dimensional semiconductor device in which a metal telluride is formed in a step region according to an embodiment. FIG. 4 is a cross-sectional view showing a stepped region of a three-dimensional semiconductor device according to another embodiment of the present disclosure.
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| TWI741710B (en) * | 2020-06-05 | 2021-10-01 | 大陸商長江存儲科技有限責任公司 | Contact pad structure of three-dimensional memory device and method of forming the same |
| TWI812579B (en) * | 2022-05-12 | 2023-08-11 | 旺宏電子股份有限公司 | 3d memory structure |
| TWI812216B (en) * | 2022-05-12 | 2023-08-11 | 旺宏電子股份有限公司 | Method of forming 3d memory structure |
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| Publication number | Publication date |
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| TW201834217A (en) | 2018-09-16 |
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