TWI628742B - Stacked package structure - Google Patents
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Abstract
一種堆疊式封裝結構，包含第一板狀結構與第二板狀結構。第一板狀結構具有相對之第一面與第二面。第一板狀結構包含第一介電層與第一電子元件。第一電子元件設置於第一介電層中，其中第一電子元件具有第一主動面，且第一主動面形成第二面的一部份。第二板狀結構具有相對之第三面與第四面。第三面面對第二面，且第三面固定於第二面。第二板狀結構包含第二介電層與至少一第二電子元件。第二電子元件設置於第二介電層中，其中第二電子元件具有第二主動面，且第二主動面形成第三面的一部份。 A stacked package structure includes a first plate-like structure and a second plate-like structure. The first plate-like structure has a first surface and a second surface opposite to each other. The first plate-like structure includes a first dielectric layer and a first electronic component. The first electronic component is disposed in the first dielectric layer, wherein the first electronic component has a first active surface, and the first active surface forms a part of the second surface. The second plate-like structure has a third surface and a fourth surface opposite to each other. The third surface faces the second surface, and the third surface is fixed to the second surface. The second plate-like structure includes a second dielectric layer and at least one second electronic component. The second electronic component is disposed in the second dielectric layer, wherein the second electronic component has a second active surface, and the second active surface forms a part of the third surface.
Description
本發明是有關於一種堆疊式封裝結構。 The invention relates to a stacked packaging structure.
隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功能、高性能的研發方向。為滿足半導體元件高積集度(Integration)以及微型化(Miniaturization)的要求，半導體封裝結構的各項要求亦越來越高。 With the vigorous development of the electronics industry, electronic products have gradually entered the multi-functional, high-performance research and development direction. In order to meet the requirements of high integration and miniaturization of semiconductor devices, the requirements of semiconductor packaging structures are also getting higher and higher.
為了進一步改善半導體封裝結構的各項特性，相關領域莫不費盡心思開發。如何能提供一種具有較佳特性的半導體封裝結構，實屬當前重要研發課題之一，亦成為當前相關領域亟需改進的目標。 In order to further improve various characteristics of the semiconductor package structure, the related fields are developed with great care. How to provide a semiconductor package structure with better characteristics is really one of the important R & D topics at present, and it has become an urgent need for improvement in related fields.
本發明之一技術態樣是在提供一種堆疊式封裝結構，以提升其運作效率。 One aspect of the present invention is to provide a stacked package structure to improve its operating efficiency.
根據本發明一實施方式，一種堆疊式封裝結構，包含第一板狀結構與第二板狀結構。第一板狀結構具有相對之第一面與第二面。第一板狀結構包含第一介電層與第一電子元件。第一電子元件設置於第一介電層中，其 中第一電子元件具有第一主動面，且第一主動面形成第二面的一部份。第二板狀結構具有相對之第三面與第四面。第三面面對第二面，且第三面固定於第二面。第二板狀結構包含第二介電層與至少一第二電子元件。第二電子元件設置於第二介電層中，其中第二電子元件具有第二主動面，且第二主動面形成第三面的一部份。 According to an embodiment of the present invention, a stacked package structure includes a first plate-like structure and a second plate-like structure. The first plate-like structure has a first surface and a second surface opposite to each other. The first plate-like structure includes a first dielectric layer and a first electronic component. The first electronic component is disposed in the first dielectric layer. The first electronic component has a first active surface, and the first active surface forms a part of the second surface. The second plate-like structure has a third surface and a fourth surface opposite to each other. The third surface faces the second surface, and the third surface is fixed to the second surface. The second plate-like structure includes a second dielectric layer and at least one second electronic component. The second electronic component is disposed in the second dielectric layer, wherein the second electronic component has a second active surface, and the second active surface forms a part of the third surface.
於本發明之一或多個實施方式中，第一板狀結構更包含第三電子元件。第三電子元件設置於第一介電層中，其中第三電子元件具有第三主動面，且第三主動面形成第二面的一部份。 In one or more embodiments of the present invention, the first plate-like structure further includes a third electronic component. The third electronic component is disposed in the first dielectric layer, wherein the third electronic component has a third active surface, and the third active surface forms a part of the second surface.
於本發明之一或多個實施方式中，第一電子元件為處理器(Processor)，第三電子元件為靜態隨機存取記憶體(Static Random-Access Memory，SRAM)。 In one or more embodiments of the present invention, the first electronic component is a processor, and the third electronic component is a static random-access memory (SRAM).
於本發明之一或多個實施方式中，第二電子元件為動態隨機存取記憶體(Dynamic Random-Access Memory，DRAM)。 In one or more embodiments of the present invention, the second electronic component is a dynamic random-access memory (Dynamic Random-Access Memory, DRAM).
於本發明之一或多個實施方式中，第一介電層之材質為封膠膠材(Molding Compound)。 In one or more embodiments of the present invention, a material of the first dielectric layer is a molding compound.
於本發明之一或多個實施方式中，第一板狀結構更包含複數個導電通孔。導電通孔設置於第一介電層中。 In one or more embodiments of the present invention, the first plate-like structure further includes a plurality of conductive vias. The conductive via is disposed in the first dielectric layer.
於本發明之一或多個實施方式中，堆疊式封裝結構更包含重分佈層。重分佈層設置於第一面上且電性連接導電通孔。 In one or more embodiments of the present invention, the stacked package structure further includes a redistribution layer. The redistribution layer is disposed on the first surface and is electrically connected to the conductive via.
於本發明之一或多個實施方式中，堆疊式封裝結構更包含複數個凸塊。凸塊設置於重分佈層上。 In one or more embodiments of the present invention, the stacked package structure further includes a plurality of bumps. The bumps are disposed on the redistribution layer.
於本發明之一或多個實施方式中，堆疊式封裝結構，更包含重分佈層。重分佈層設置於第二面上，其中重分佈層電性連接第一主動面與導電通孔。 In one or more embodiments of the present invention, the stacked package structure further includes a redistribution layer. The redistribution layer is disposed on the second surface, wherein the redistribution layer is electrically connected to the first active surface and the conductive via.
於本發明之一或多個實施方式中，堆疊式封裝結構更包含重分佈層、複數個第一凸塊以及複數個第二凸塊。重分佈層設置於第二面上，其中重分佈層電性連接第一主動面。第一凸塊設置於重分佈層與第三面之間，其中第一凸塊電性連接重分佈層與第二主動面。第二凸塊設置於第二面與第三面之間，其中第二凸塊電性連接第一電子元件與導電通孔。 In one or more embodiments of the present invention, the stacked package structure further includes a redistribution layer, a plurality of first bumps, and a plurality of second bumps. The redistribution layer is disposed on the second surface, wherein the redistribution layer is electrically connected to the first active surface. The first bump is disposed between the redistribution layer and the third surface, wherein the first bump is electrically connected to the redistribution layer and the second active surface. The second bump is disposed between the second surface and the third surface, wherein the second bump is electrically connected to the first electronic component and the conductive via.
於本發明之一或多個實施方式中，堆疊式封裝結構更包含複數個凸塊。凸塊設置於第二面與第三面之間。 In one or more embodiments of the present invention, the stacked package structure further includes a plurality of bumps. The bump is disposed between the second surface and the third surface.
於本發明之一或多個實施方式中，堆疊式封裝結構更包含至少一重分佈層。重分佈層設置於第二主動面與凸塊之間。 In one or more embodiments of the present invention, the stacked package structure further includes at least one redistribution layer. The redistribution layer is disposed between the second active surface and the bump.
於本發明之於本發明之一或多個實施方式中，堆疊式封裝結構更包含第三板狀結構。第三板狀結構具有相對之第五面與第六面，其中第五面面對第六面，且第五面固定於第四面。第三板狀結構包含第三介電層以及至少一第四電子元件。第四電子元件設置於第三介電層中，其中第四電子元件具有第四主動面，且第四主動面形成第五面的一部份。 In one or more embodiments of the present invention, the stacked package structure further includes a third plate-like structure. The third plate-like structure has opposite fifth and sixth faces, wherein the fifth face faces the sixth face, and the fifth face is fixed on the fourth face. The third plate-like structure includes a third dielectric layer and at least one fourth electronic component. The fourth electronic component is disposed in the third dielectric layer, wherein the fourth electronic component has a fourth active surface, and the fourth active surface forms a part of the fifth surface.
於本發明之一或多個實施方式中，第二電子元件包含本體與複數個導電通孔。導電通孔設置於本體中。 In one or more embodiments of the present invention, the second electronic component includes a body and a plurality of conductive vias. The conductive through hole is disposed in the body.
於本發明之一或多個實施方式中，堆疊式封裝結構更包含複數個凸塊。凸塊設置於第四面與第五面之間。 In one or more embodiments of the present invention, the stacked package structure further includes a plurality of bumps. The bump is disposed between the fourth surface and the fifth surface.
於本發明之一或多個實施方式中，堆疊式封裝結構更包含散熱件。散熱件設置於第一面上。 In one or more embodiments of the present invention, the stacked package structure further includes a heat sink. The heat sink is disposed on the first surface.
於本發明之一或多個實施方式中，第二介電層之材質為封膠膠材(Molding Compound)。 In one or more embodiments of the present invention, a material of the second dielectric layer is a molding compound.
於本發明之一或多個實施方式中，第二板狀結構更包含複數個導電通孔。導電通孔設置於第二介電層中。 In one or more embodiments of the present invention, the second plate-like structure further includes a plurality of conductive vias. The conductive via is disposed in the second dielectric layer.
於本發明之一或多個實施方式中，堆疊式封裝結構更包含重分佈層。重分佈層設置於第四面上且電性連接於導電通孔。 In one or more embodiments of the present invention, the stacked package structure further includes a redistribution layer. The redistribution layer is disposed on the fourth surface and is electrically connected to the conductive via.
於本發明之一或多個實施方式中，堆疊式封裝結構更包含複數個凸塊。凸塊設置於重分佈層上。 In one or more embodiments of the present invention, the stacked package structure further includes a plurality of bumps. The bumps are disposed on the redistribution layer.
因為第一板狀結構的第二面面對第二板狀結構的第三面，第一電子元件的第一主動面與第三電子元件的第三主動面面對第二電子元件的第二主動面。於是，第一電子元件、第二電子元件與第三電子元件之間的電子訊號傳遞路徑將不會太長，第一電子元件、第二電子元件與第三電子元件僅需要較短的時間便能互相溝通，於是堆疊式封裝結構的整體運作效率將能有效提升。 Because the second surface of the first plate-like structure faces the third surface of the second plate-like structure, the first active surface of the first electronic component and the third active surface of the third electronic component face the second of the second electronic component. Active side. Therefore, the electronic signal transmission path between the first electronic component, the second electronic component, and the third electronic component will not be too long. The first electronic component, the second electronic component, and the third electronic component only need a short time. Can communicate with each other, so the overall operating efficiency of the stacked package structure can be effectively improved.
100‧‧‧堆疊式封裝結構 100‧‧‧ stacked package structure
200‧‧‧第一板狀結構 200‧‧‧ the first plate-like structure
201‧‧‧第一面 201‧‧‧ the first side
202‧‧‧第二面 202‧‧‧Second Side
209、309‧‧‧板狀結構 209, 309‧‧‧plate structure
210‧‧‧第一介電層 210‧‧‧ first dielectric layer
220‧‧‧第一電子元件 220‧‧‧The first electronic component
221‧‧‧第一主動面 221‧‧‧First active face
230‧‧‧第三電子元件 230‧‧‧Third electronic component
240、323、330、523‧‧‧導電通孔 240, 323, 330, 523‧‧‧ conductive vias
231‧‧‧第三主動面 231‧‧‧ third active face
300‧‧‧第二板狀結構 300‧‧‧Second plate structure
301‧‧‧第三面 301‧‧‧ the third side
302‧‧‧第四面 302‧‧‧Fourth
310‧‧‧第二介電層 310‧‧‧Second dielectric layer
320‧‧‧第二電子元件 320‧‧‧Second electronic component
321‧‧‧第二主動面 321‧‧‧Second Active Face
322‧‧‧本體 322‧‧‧ Ontology
410、411、420、440、460、480、720‧‧‧重分佈層 410, 411, 420, 440, 460, 480, 720‧‧‧ redistribution layer
430、431、432、450、470、490、730‧‧‧凸塊 430, 431, 432, 450, 470, 490, 730‧‧‧ bumps
500‧‧‧第三板狀結構 500‧‧‧ Third plate structure
501‧‧‧第五面 501‧‧‧Fifth
502‧‧‧第六面 502‧‧‧ sixth side
510‧‧‧第三介電層 510‧‧‧Third dielectric layer
520‧‧‧第四電子元件 520‧‧‧Fourth electronic component
521‧‧‧第四主動面 521‧‧‧The fourth active face
522‧‧‧本體 522‧‧‧ Ontology
620‧‧‧第五電子元件 620‧‧‧Fifth electronic component
621‧‧‧第五主動面 621‧‧‧Fifth active face
710‧‧‧散熱件 710‧‧‧ heat sink
901、902、903、905‧‧‧承載基板 901, 902, 903, 905‧‧‧bearing substrate
904、906‧‧‧裁切膠帶 904, 906‧‧‧cut tape
第1圖繪示依照本發明一實施方式之堆疊式封裝結構的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a stacked package structure according to an embodiment of the present invention.
第2圖繪示依照本發明另一實施方式之堆疊式封裝結構的剖面示意圖。 FIG. 2 is a schematic cross-sectional view of a stacked package structure according to another embodiment of the present invention.
第3圖繪示依照本發明又一實施方式之堆疊式封裝結構的剖面示意圖。 FIG. 3 is a schematic cross-sectional view of a stacked package structure according to another embodiment of the present invention.
第4圖繪示依照本發明再一實施方式之堆疊式封裝結構的剖面示意圖。 FIG. 4 is a schematic cross-sectional view of a stacked package structure according to yet another embodiment of the present invention.
第5圖至第22圖繪示依照本發明一實施方式之堆疊式封裝結構的製程各步驟的剖面示意圖。 FIG. 5 to FIG. 22 are schematic cross-sectional views of steps in a manufacturing process of a stacked package structure according to an embodiment of the present invention.
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。 In the following, a plurality of embodiments of the present invention will be disclosed graphically. For the sake of clarity, many practical details will be described in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and components will be shown in the drawings in a simple and schematic manner.
第1圖繪示依照本發明一實施方式之堆疊式封裝結構100的剖面示意圖。本發明不同實施方式提供一種堆疊式封裝結構100。堆疊式封裝結構100可以藉由晶圓級封裝製程製造。 FIG. 1 is a schematic cross-sectional view of a stacked package structure 100 according to an embodiment of the present invention. Various embodiments of the present invention provide a stacked packaging structure 100. The stacked package structure 100 can be manufactured by a wafer-level packaging process.
如第1圖所繪示，堆疊式封裝結構100包含第一板狀結構200與第二板狀結構300。第一板狀結構200具有相對之第一面201與第二面202。第一板狀結構200包含第一介電層210與第一電子元件220。第一電子元件220設置於第一介電層210中，其中第一電子元件220具有第一主動面221，且第一主動面221形成第二面202的一部份。第二板狀結構300具有相對之第三面301與第四面302。第三面301面對第二面202，且第三面301固定於第二面202。第二板狀結構300包含第二介電層310與至少一第二電子元件320。第二電子元件320設置於第二介電層310中，其中第二電子元件320具有第二主動面321，且第二主動面321形成第三面301的一部份。 As shown in FIG. 1, the stacked package structure 100 includes a first plate-like structure 200 and a second plate-like structure 300. The first plate-like structure 200 has a first surface 201 and a second surface 202 opposite to each other. The first plate-like structure 200 includes a first dielectric layer 210 and a first electronic component 220. The first electronic component 220 is disposed in the first dielectric layer 210. The first electronic component 220 has a first active surface 221, and the first active surface 221 forms a part of the second surface 202. The second plate-like structure 300 has a third surface 301 and a fourth surface 302 opposite to each other. The third surface 301 faces the second surface 202, and the third surface 301 is fixed to the second surface 202. The second plate-like structure 300 includes a second dielectric layer 310 and at least one second electronic component 320. The second electronic component 320 is disposed in the second dielectric layer 310. The second electronic component 320 has a second active surface 321, and the second active surface 321 forms a part of the third surface 301.
具體而言，第一電子元件220可為處理器(Processor)。更具體地說，第一電子元件220可為中央處理器(Central Processing Unit，CPU)或應用處理器(application processor，AP)。應了解到，以上所舉之第一電子元件220的具體實施方式僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第一電子元件220的具體實施方式。 Specifically, the first electronic component 220 may be a processor. More specifically, the first electronic component 220 may be a central processing unit (CPU) or an application processor (AP). It should be understood that the specific implementation of the first electronic component 220 mentioned above is merely an example and is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should flexibly select the first electronic component according to actual needs. A specific embodiment of 220.
具體而言，第一板狀結構200更包含第三電子元件230。第三電子元件230設置於第一介電層210中，其中第三電子元件230具有第三主動面231，且第三主動面231形成第二面202的一部份。 Specifically, the first plate-like structure 200 further includes a third electronic component 230. The third electronic component 230 is disposed in the first dielectric layer 210. The third electronic component 230 has a third active surface 231, and the third active surface 231 forms a part of the second surface 202.
具體而言，第三電子元件230可為靜態隨機存取記憶體(Static Random-Access Memory，SRAM)。應了解到，以上所舉之第三電子元件230的具體實施方式僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第三電子元件230的具體實施方式。 Specifically, the third electronic component 230 may be a Static Random-Access Memory (SRAM). It should be understood that the specific implementation of the third electronic component 230 mentioned above is merely an example and is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should flexibly select the third electronic component according to actual needs. A specific embodiment of 230.
在一些實施方式中，第一板狀結構200可能沒有包含第三電子元件230，且第三電子元件230的功能可能會整合於第一電子元件220中。 In some embodiments, the first plate-like structure 200 may not include the third electronic component 230, and the functions of the third electronic component 230 may be integrated into the first electronic component 220.
具體而言，第二電子元件320可為動態隨機存取記憶體(Dynamic Random-Access Memory，DRAM)。應了解到，以上所舉之第二電子元件320的具體實施方式僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇第二電子元件320的具體實施方式。 Specifically, the second electronic component 320 may be a dynamic random-access memory (Dynamic Random-Access Memory, DRAM). It should be understood that the specific implementation of the second electronic component 320 mentioned above is merely an example and is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should flexibly select the second electronic component according to actual needs. A specific embodiment of 320.
具體而言，堆疊式封裝結構100更包含重分佈層410、至少一重分佈層420以及複數個凸塊430。重分佈層410設置於第二面202上且電性連接第一主動面221與第三主動面231。重分佈層420設置於第三面301且電性連接第二主動面321。凸塊430設置於第二面202與第三面301之間。換句話說，重分佈層420為設置於第二主動面321與凸塊430之間。凸塊430電性連接重分佈層410與重分佈層420。 Specifically, the stacked package structure 100 further includes a redistribution layer 410, at least one redistribution layer 420, and a plurality of bumps 430. The redistribution layer 410 is disposed on the second surface 202 and is electrically connected to the first active surface 221 and the third active surface 231. The redistribution layer 420 is disposed on the third surface 301 and is electrically connected to the second active surface 321. The bump 430 is disposed between the second surface 202 and the third surface 301. In other words, the redistribution layer 420 is disposed between the second active surface 321 and the bump 430. The bump 430 is electrically connected to the redistribution layer 410 and the redistribution layer 420.
因為第一板狀結構200的第二面202面對第二板狀結構300的第三面301，第一電子元件220的第一主動面 221與第三電子元件230的第三主動面231將會面對第二電子元件320的第二主動面321。換句話說，第一電子元件220藉由重分佈層410、凸塊430與重分佈層410電性連接第二電子元件320，第三電子元件230藉由重分佈層410、凸塊430與重分佈層420電性連接第二電子元件320，第一電子元件220藉由重分佈層410電性連接第三電子元件230。於是，第一電子元件220、第二電子元件320與第三電子元件230之間的電子訊號傳遞路徑將不會太長，第一電子元件220、第二電子元件320與第三電子元件230僅需要較短的時間便能互相溝通，於是堆疊式封裝結構100的整體運作效率將能有效提升。 Because the second surface 202 of the first plate-like structure 200 faces the third surface 301 of the second plate-like structure 300, the first active surface of the first electronic component 220 221 and the third active surface 231 of the third electronic component 230 will face the second active surface 321 of the second electronic component 320. In other words, the first electronic component 220 is electrically connected to the second electronic component 320 through the redistribution layer 410, the bump 430, and the redistribution layer 410, and the third electronic component 230 is connected to the second electronic component 320 via the redistribution layer 410, the bump 430, and the redistribution layer. The distribution layer 420 is electrically connected to the second electronic component 320, and the first electronic component 220 is electrically connected to the third electronic component 230 through the redistribution layer 410. Therefore, the electronic signal transmission path between the first electronic component 220, the second electronic component 320, and the third electronic component 230 will not be too long. The first electronic component 220, the second electronic component 320, and the third electronic component 230 are only It takes a short time to be able to communicate with each other, so the overall operating efficiency of the stacked package structure 100 can be effectively improved.
第一板狀結構200更包含複數個導電通孔240。導電通孔240設置於第一介電層210中且電性連接重分佈層410。堆疊式封裝結構100更包含重分佈層440與複數個凸塊450。重分佈層440設置於第一面201上且電性連接導電通孔240。凸塊450設置於重分佈層440上。 The first plate-like structure 200 further includes a plurality of conductive vias 240. The conductive via 240 is disposed in the first dielectric layer 210 and is electrically connected to the redistribution layer 410. The stacked package structure 100 further includes a redistribution layer 440 and a plurality of bumps 450. The redistribution layer 440 is disposed on the first surface 201 and is electrically connected to the conductive via 240. The bump 450 is disposed on the redistribution layer 440.
第一電子元件220、第二電子元件320與第三電子元件230藉由重分佈層410、導電通孔240與重分佈層440電性連接凸塊450。因為凸塊450可以電性連接外部的其他電子元件，第一電子元件220、第二電子元件320與第三電子元件230因此可以電性連接外部的其他電子元件。 The first electronic component 220, the second electronic component 320, and the third electronic component 230 are electrically connected to the bump 450 through the redistribution layer 410, the conductive via 240, and the redistribution layer 440. Because the bump 450 can be electrically connected to other external electronic components, the first electronic component 220, the second electronic component 320, and the third electronic component 230 can be electrically connected to other external electronic components.
具體而言，第一介電層210之材質為封膠膠材(Molding Compound)。於是，因為導電通孔240形成於封膠膠材中，所以導電通孔240的製造成本將會遠低於形成於矽基板中的導電通孔。 Specifically, the material of the first dielectric layer 210 is a molding compound. Therefore, because the conductive vias 240 are formed in the sealant, the manufacturing cost of the conductive vias 240 will be much lower than the conductive vias formed in the silicon substrate.
第2圖繪示依照本發明另一實施方式之堆疊式封裝結構100的剖面示意圖。本實施方式的堆疊式封裝結構100與第1圖的堆疊式封裝結構100大致相同，以下將描述兩者的主要差異。 FIG. 2 is a schematic cross-sectional view of a stacked package structure 100 according to another embodiment of the present invention. The stacked package structure 100 of this embodiment is substantially the same as the stacked package structure 100 of FIG. 1, and the main differences between the two will be described below.
如第2圖所繪示，堆疊式封裝結構100包含重分佈層411、複數個凸塊431以及複數個凸塊432。重分佈層411設置於第二面202上，且重分佈層411電性連接第一主動面221與第三主動面231。凸塊431設置於重分佈層411與第三面301之間，且凸塊431電性連接重分佈層411與第二電子元件320，凸塊432設置於第二面202與第三面301之間，且凸塊432電性連接第一電子元件220與導電通孔240。 As shown in FIG. 2, the stacked package structure 100 includes a redistribution layer 411, a plurality of bumps 431, and a plurality of bumps 432. The redistribution layer 411 is disposed on the second surface 202, and the redistribution layer 411 is electrically connected to the first active surface 221 and the third active surface 231. The bump 431 is disposed between the redistribution layer 411 and the third surface 301, and the bump 431 is electrically connected to the redistribution layer 411 and the second electronic component 320. The bump 432 is disposed between the second surface 202 and the third surface 301. The bump 432 is electrically connected to the first electronic component 220 and the conductive via 240.
具體而言，凸塊431為設置於重分佈層411與重分佈層420之間，且凸塊431電性連接重分佈層411與重分佈層420。凸塊432為設置於第二面202與重分佈層420之間，且凸塊432電性連接重分佈層420與導電通孔240。換句話說，重分佈層420電性連接第二電子元件320與凸塊431、432。 Specifically, the bump 431 is disposed between the redistribution layer 411 and the redistribution layer 420, and the bump 431 is electrically connected to the redistribution layer 411 and the redistribution layer 420. The bump 432 is disposed between the second surface 202 and the redistribution layer 420, and the bump 432 is electrically connected to the redistribution layer 420 and the conductive via 240. In other words, the redistribution layer 420 is electrically connected to the second electronic component 320 and the bumps 431 and 432.
於是，第二電子元件320藉由重分佈層420、導電通孔240與重分佈層440電性連接凸塊450。第一電子元件220與第三電子元件230藉由重分佈層411、凸塊431、重分佈層420、凸塊432、導電通孔240與重分佈層440電性連接凸塊450。因為凸塊450可以電性連接外部的其他電子元件，第一電子元件220、第二電子元件320與第三電子元件230因此可以電性連接於外部的其他電子元件。 Therefore, the second electronic component 320 is electrically connected to the bump 450 through the redistribution layer 420, the conductive via 240, and the redistribution layer 440. The first electronic component 220 and the third electronic component 230 are electrically connected to the bump 450 through the redistribution layer 411, the bump 431, the redistribution layer 420, the bump 432, the conductive via 240, and the redistribution layer 440. Because the bump 450 can be electrically connected to other external electronic components, the first electronic component 220, the second electronic component 320, and the third electronic component 230 can be electrically connected to other external electronic components.
第3圖繪示依照本發明又一實施方式之堆疊式封裝結構100的剖面示意圖。本實施方式的堆疊式封裝結構100與第1圖的堆疊式封裝結構100大致相同，以下將描述兩者的主要差異。 FIG. 3 is a schematic cross-sectional view of a stacked package structure 100 according to another embodiment of the present invention. The stacked package structure 100 of this embodiment is substantially the same as the stacked package structure 100 of FIG. 1, and the main differences between the two will be described below.
如第3圖所繪示，堆疊式封裝結構100更包含第三板狀結構500。第三板狀結構500具有相對之第五面501與第六面502。第五面501面對第四面302，且第五面501固定於第四面302。第三板狀結構500包含第三介電層510以及至少一第四電子元件520。第四電子元件520設置於第三介電層510中，其中第四電子元件520具有第四主動面521，且第四主動面521形成第五面501的一部份。 As shown in FIG. 3, the stacked package structure 100 further includes a third plate-like structure 500. The third plate-like structure 500 has a fifth surface 501 and a sixth surface 502 opposite to each other. The fifth surface 501 faces the fourth surface 302, and the fifth surface 501 is fixed to the fourth surface 302. The third plate-like structure 500 includes a third dielectric layer 510 and at least one fourth electronic component 520. The fourth electronic component 520 is disposed in the third dielectric layer 510. The fourth electronic component 520 has a fourth active surface 521, and the fourth active surface 521 forms a part of the fifth surface 501.
第二電子元件320包含本體322與複數個導電通孔323。導電通孔323設置於本體322中。堆疊式封裝結構100更包含至少一重分佈層460與複數個凸塊470。重分佈層460設置於第五面501上且電性連接第四主動面521。凸塊470設置於第四面302與第五面501之間。在本實施方式中，凸塊470設置於第四面302與重分佈層460之間。 The second electronic component 320 includes a body 322 and a plurality of conductive vias 323. The conductive via 323 is disposed in the body 322. The stacked package structure 100 further includes at least one redistribution layer 460 and a plurality of bumps 470. The redistribution layer 460 is disposed on the fifth surface 501 and is electrically connected to the fourth active surface 521. The bump 470 is disposed between the fourth surface 302 and the fifth surface 501. In this embodiment, the bump 470 is disposed between the fourth surface 302 and the redistribution layer 460.
於是，第二電子元件320藉由導電通孔323、凸塊470與重分佈層460電性連接第四電子元件520。 Therefore, the second electronic component 320 is electrically connected to the fourth electronic component 520 through the conductive via 323, the bump 470 and the redistribution layer 460.
堆疊式封裝結構100更可包含其他的板狀結構或電子元件。在本實施方式中，堆疊式封裝結構100更包含至少一第五電子元件620。第五電子元件620具有第五主動面621。堆疊式封裝結構100更包含至少一重分佈層480與複數個凸塊490。重分佈層480設置於第五主動面621上且電性連 接第五主動面621。凸塊490設置於重分佈層480與第六面502之間。 The stacked package structure 100 may further include other plate-like structures or electronic components. In this embodiment, the stacked package structure 100 further includes at least one fifth electronic component 620. The fifth electronic component 620 has a fifth active surface 621. The stacked package structure 100 further includes at least one redistribution layer 480 and a plurality of bumps 490. The redistribution layer 480 is disposed on the fifth active surface 621 and is electrically connected. 接 fifth active surface 621. The bump 490 is disposed between the redistribution layer 480 and the sixth surface 502.
第四電子元件520包含本體522與複數個導電通孔523。導電通孔523設置於本體522中。於是，第四電子元件520藉由導電通孔523、凸塊490與重分佈層480電性連接第五電子元件620。 The fourth electronic component 520 includes a body 522 and a plurality of conductive vias 523. The conductive through hole 523 is disposed in the body 522. Therefore, the fourth electronic component 520 is electrically connected to the fifth electronic component 620 through the conductive via 523, the bump 490 and the redistribution layer 480.
第4圖繪示依照本發明再一實施方式之堆疊式封裝結構100的剖面示意圖。本實施方式的堆疊式封裝結構100與第1圖的堆疊式封裝結構100大致相同，以下將描述兩者的主要差異。 FIG. 4 is a schematic cross-sectional view of a stacked package structure 100 according to yet another embodiment of the present invention. The stacked package structure 100 of this embodiment is substantially the same as the stacked package structure 100 of FIG. 1, and the main differences between the two will be described below.
如第4圖所繪示，堆疊式封裝結構100更包含散熱件710。散熱件710設置於第一面201上。因為散熱件710設置於第一面201上，散熱件710可以有效地耗散第一電子元件220與第三電子元件230所產生的熱。 As shown in FIG. 4, the stacked package structure 100 further includes a heat sink 710. The heat sink 710 is disposed on the first surface 201. Because the heat dissipating member 710 is disposed on the first surface 201, the heat dissipating member 710 can effectively dissipate the heat generated by the first electronic component 220 and the third electronic component 230.
具體而言，第二介電層310之材質為封膠膠材(Molding Compound)。第二板狀結構300更包含複數個導電通孔330。導電通孔330設置於第二介電層310中，且重分佈層410電性連接導電通孔330。堆疊式封裝結構100更包含重分佈層720與複數個凸塊730。重分佈層720設置於第四面302上且電性連接於導電通孔330。凸塊730設置於重分佈層720上。 Specifically, the material of the second dielectric layer 310 is a molding compound. The second plate-like structure 300 further includes a plurality of conductive vias 330. The conductive vias 330 are disposed in the second dielectric layer 310, and the redistribution layer 410 is electrically connected to the conductive vias 330. The stacked package structure 100 further includes a redistribution layer 720 and a plurality of bumps 730. The redistribution layer 720 is disposed on the fourth surface 302 and is electrically connected to the conductive vias 330. The bumps 730 are disposed on the redistribution layer 720.
第一電子元件220、第二電子元件320與第三電子元件230藉由重分佈層410、導電通孔330與重分佈層720電性連接凸塊730。因為凸塊730可以電性連些外部的其他電 子元件，第一電子元件220、第二電子元件320與第三電子元件230因此也可以電性連接外部的其他電子元件。 The first electronic component 220, the second electronic component 320, and the third electronic component 230 are electrically connected to the bump 730 through the redistribution layer 410, the conductive vias 330, and the redistribution layer 720. Because the bump 730 can be electrically connected to other external electrical The sub-components, the first electronic component 220, the second electronic component 320, and the third electronic component 230 can also be electrically connected to other external electronic components.
重分佈層410、411、420、440、460、480、720可為單層結構或者多層結構。換句話說，重分佈層410、411、420、440、460、480、720可以包含單一線路層或多個線路層。 The redistribution layers 410, 411, 420, 440, 460, 480, and 720 may have a single-layer structure or a multilayer structure. In other words, the redistribution layers 410, 411, 420, 440, 460, 480, 720 may include a single circuit layer or multiple circuit layers.
第5圖至第22圖繪示依照本發明一實施方式之堆疊式封裝結構100的製程各步驟的剖面示意圖。如第5圖所繪示，設置至少一第一電子元件220與至少一第三電子元件230於承載基板901上。進一步來說，一個第一電子元件220與一個相鄰於第一電子元件220的第三電子元件230形成一組第一電子元件220與第三電子元件230。承載基板901為晶圓級的基板。複數組第一電子元件220與第三電子元件230均勻地分佈於整片承載基板901上。 FIG. 5 to FIG. 22 are schematic cross-sectional views illustrating steps of a manufacturing process of the stacked package structure 100 according to an embodiment of the present invention. As shown in FIG. 5, at least one first electronic component 220 and at least one third electronic component 230 are disposed on the carrier substrate 901. Further, a first electronic component 220 and a third electronic component 230 adjacent to the first electronic component 220 form a group of the first electronic component 220 and the third electronic component 230. The carrier substrate 901 is a wafer-level substrate. The plurality of first electronic components 220 and the third electronic components 230 are evenly distributed on the entire carrier substrate 901.
因為第一電子元件220與第三電子元件230為分別在封裝前製造，因此損壞的第一電子元件220與第三電子元件230可以在封裝前先丟棄，因而得以有效提升堆疊式封裝結構100的製造良率。 Because the first electronic component 220 and the third electronic component 230 are manufactured before packaging, respectively, the damaged first electronic component 220 and the third electronic component 230 can be discarded before packaging, thereby effectively improving the stacking package structure 100. Manufacturing yield.
第一電子元件220的第一主動面221與第三電子元件230的第三主動面231面對承載基板901。 The first active surface 221 of the first electronic component 220 and the third active surface 231 of the third electronic component 230 face the carrier substrate 901.
具體而言，承載基板901之材質為矽或玻璃。應了解到，以上所舉之承載基板901之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇承載基板901之材質。 Specifically, the material of the carrier substrate 901 is silicon or glass. It should be understood that the material of the carrier substrate 901 mentioned above is merely an example and is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should elastically select the material of the carrier substrate 901 according to actual needs.
如第6圖所繪示，形成第一介電層210，於是第一電子元件220與第三電子元件230為設置於第一介電層210中，並且第一介電層210、第一電子元件220與第三電子元件230形成板狀結構209。板狀結構209為晶圓級的結構。 As shown in FIG. 6, a first dielectric layer 210 is formed, so that the first electronic component 220 and the third electronic component 230 are disposed in the first dielectric layer 210, and the first dielectric layer 210 and the first electron The element 220 and the third electronic element 230 form a plate-like structure 209. The plate-like structure 209 is a wafer-level structure.
如第7圖所繪示，形成一重分佈層440於第一介電層210、第一電子元件220與第三電子元件230上。換句話說，重分佈層440為形成於板狀結構209的第一面201上。然後，形成複數個凸塊450於重分佈層440上。 As shown in FIG. 7, a redistribution layer 440 is formed on the first dielectric layer 210, the first electronic component 220, and the third electronic component 230. In other words, the redistribution layer 440 is formed on the first surface 201 of the plate-like structure 209. Then, a plurality of bumps 450 are formed on the redistribution layer 440.
如第7圖與第8圖所繪示，設置承載基板902於板狀結構209相對於第二面202之一側。然後，移除承載基板901。於是，板狀結構209的第二面202未被覆蓋，因此第一主動面221與第三主動面231也未被覆蓋。承載基板902為晶圓級的基板。 As shown in FIGS. 7 and 8, a carrier substrate 902 is disposed on one side of the plate-like structure 209 opposite to the second surface 202. Then, the carrier substrate 901 is removed. Therefore, the second surface 202 of the plate-shaped structure 209 is not covered, so the first active surface 221 and the third active surface 231 are also not covered. The carrier substrate 902 is a wafer-level substrate.
具體而言，承載基板902之材質為矽或玻璃。應了解到，以上所舉之承載基板902之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇承載基板902之材質。 Specifically, the material of the carrier substrate 902 is silicon or glass. It should be understood that the material of the carrier substrate 902 mentioned above is merely an example and is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should elastically select the material of the carrier substrate 902 according to actual needs.
如第9圖所繪示，將板狀結構209與承載基板902翻轉180度。然後，形成複數個導電通孔240於第一介電層210中。 As shown in FIG. 9, the plate-like structure 209 and the carrier substrate 902 are turned 180 degrees. Then, a plurality of conductive vias 240 are formed in the first dielectric layer 210.
如第10圖所繪示，形成重分佈層410於板狀結構209的第二面202上，於是重分佈層410電性連接於導電通孔240、第一主動面221與第三主動面231。 As shown in FIG. 10, a redistribution layer 410 is formed on the second surface 202 of the plate-shaped structure 209, and thus the redistribution layer 410 is electrically connected to the conductive via 240, the first active surface 221, and the third active surface 231. .
如第11圖所繪示，設置複數個第二電子元件320承載基板903上。在本實施方式中，每三個第二電子元件320為互相相鄰設置，因而形成一組第二電子元件320。承載基板903為晶圓級的基板。複數組第二電子元件320均勻地分佈於整片承載基板903上。 As shown in FIG. 11, a plurality of second electronic components 320 are disposed on the carrier substrate 903. In this embodiment, every three second electronic components 320 are disposed adjacent to each other, so a group of second electronic components 320 is formed. The carrier substrate 903 is a wafer-level substrate. The plurality of second electronic components 320 are evenly distributed on the entire carrier substrate 903.
具體而言，承載基板903之材質為矽或玻璃。應了解到，以上所舉之承載基板903之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇承載基板903之材質。 Specifically, the material of the carrier substrate 903 is silicon or glass. It should be understood that the material of the carrier substrate 903 mentioned above is merely an example and is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should elastically select the material of the carrier substrate 903 according to actual needs.
因為第二電子元件320為在封裝前製造，因此損壞的第二電子元件320可以在封裝前先丟棄，因而得以有效提升堆疊式封裝結構100的製造良率。 Because the second electronic component 320 is manufactured before packaging, the damaged second electronic component 320 can be discarded before packaging, thereby effectively improving the manufacturing yield of the stacked package structure 100.
如第12圖所繪示，形成第二介電層310，於是第二電子元件320為設置於第二介電層310中，並且第二介電層310與第二電子元件320形成板狀結構309。板狀結構309為晶圓級的結構。第二電子元件320的第二主動面321沒有被第二介電層310覆蓋。 As shown in FIG. 12, a second dielectric layer 310 is formed, so that the second electronic component 320 is disposed in the second dielectric layer 310, and the second dielectric layer 310 and the second electronic component 320 form a plate structure. 309. The plate-like structure 309 is a wafer-level structure. The second active surface 321 of the second electronic component 320 is not covered by the second dielectric layer 310.
如第13圖所繪示，形成至少一重分佈層420於第二介電層310與第二電子元件320上，意即，形成重分佈層420於板狀結構309的第三面301上。然後，形成複數個凸塊430於重分佈層420上。 As shown in FIG. 13, at least one redistribution layer 420 is formed on the second dielectric layer 310 and the second electronic component 320, that is, a redistribution layer 420 is formed on the third surface 301 of the plate-like structure 309. Then, a plurality of bumps 430 are formed on the redistribution layer 420.
如第13圖與第14圖所繪示，將板狀結構309與承載基板903翻轉180度。然後，將板狀結構309相對於第四 面302的一側設置於裁切膠帶904上。然後，移除承載基板903。裁切膠帶904為晶圓級的膠帶。 As shown in FIGS. 13 and 14, the plate-shaped structure 309 and the carrier substrate 903 are turned 180 degrees. Then, the plate-like structure 309 is One side of the surface 302 is provided on the cutting tape 904. Then, the carrier substrate 903 is removed. The cutting tape 904 is a wafer-level tape.
如第14圖與第15圖所繪示，板狀結構309被裁切為多個不同部份。換句話說，板狀結構309被裁切為多個第二板狀結構300。在本實施方式中，三個第二電子元件320設置於一個第二板狀結構300中。 As shown in FIGS. 14 and 15, the plate-shaped structure 309 is cut into a plurality of different parts. In other words, the plate-like structure 309 is cut into a plurality of second plate-like structures 300. In this embodiment, three second electronic components 320 are disposed in one second plate-like structure 300.
如第16圖所繪示，使第二板狀結構300脫離裁切膠帶904。 As shown in FIG. 16, the second plate-like structure 300 is detached from the cutting tape 904.
如第17圖所繪示，各個第二板狀結構300分別對準於各組第一電子元件220與第三電子元件230。換句話說，各個板狀結構分別對準於板狀結構209的不同部份。 As shown in FIG. 17, each second plate-like structure 300 is aligned with each group of the first electronic component 220 and the third electronic component 230. In other words, the respective plate-like structures are respectively aligned with different portions of the plate-like structure 209.
如第18圖所繪示，將第二板狀結構300放置於板狀結構209上。於是各個第二電子元件320分別電性連接於第一電子元件220與第三電子元件230。 As shown in FIG. 18, the second plate-like structure 300 is placed on the plate-like structure 209. Therefore, each second electronic component 320 is electrically connected to the first electronic component 220 and the third electronic component 230, respectively.
如第18圖與第19圖所繪示，將承載基板905放置於第二板狀結構300相對於第三面301的一側。承載基板905為晶圓級的基板。然後，移除承載基板902。 As shown in FIG. 18 and FIG. 19, the carrier substrate 905 is placed on a side of the second plate-like structure 300 opposite to the third surface 301. The carrier substrate 905 is a wafer-level substrate. Then, the carrier substrate 902 is removed.
具體而言，承載基板905之材質為矽或玻璃。應了解到，以上所舉之承載基板905之材質僅為例示，並非用以限制本發明，本發明所屬技術領域中具有通常知識者，應視實際需要，彈性選擇承載基板905之材質。 Specifically, the material of the carrier substrate 905 is silicon or glass. It should be understood that the material of the carrier substrate 905 mentioned above is merely an example and is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should flexibly select the material of the carrier substrate 905 according to actual needs.
如第20圖所繪示，將板狀結構209相對於第二面202之一側放置於裁切膠帶906上。裁切膠帶906為晶圓級的膠帶。 As shown in FIG. 20, one side of the plate-like structure 209 opposite to the second surface 202 is placed on the cutting tape 906. The cutting tape 906 is a wafer-level tape.
如第20圖與第21圖所繪示，移除承載基板905。然後，將板狀結構209裁切為多個不同部份。換句話說，板狀結構209被裁切為多個第一板狀結構200。在本實施方式中，一個第一電子元件220與一個第三電子元件230為放置於一個第一板狀結構200中。 As shown in FIGS. 20 and 21, the carrier substrate 905 is removed. Then, the plate-like structure 209 is cut into a plurality of different parts. In other words, the plate-like structure 209 is cut into a plurality of first plate-like structures 200. In this embodiment, a first electronic component 220 and a third electronic component 230 are placed in a first plate-like structure 200.
如第22圖所繪示，使第一板狀結構200與第二板狀結構300脫離裁切膠帶906。 As shown in FIG. 22, the first plate-like structure 200 and the second plate-like structure 300 are separated from the cutting tape 906.
因為第一板狀結構200的第二面202面對第二板狀結構300的第三面301，第一電子元件220的第一主動面221與第三電子元件230的第三主動面231面對第二電子元件320的第二主動面321。換句話說，第一電子元件220藉由重分佈層410、凸塊430與重分佈層420電性連接第二電子元件320，第三電子元件230藉由重分佈層410、凸塊430與重分佈層420電性連接第二電子元件320，第一電子元件220藉由重分佈層410電性連接第三電子元件230。於是，第一電子元件220、第二電子元件320與第三電子元件230之間的電子訊號傳遞路徑將不會太長，第一電子元件220、第二電子元件320與第三電子元件230僅需要較短的時間便能互相溝通，於是堆疊式封裝結構100的整體運作效率將能有效提升。 Because the second surface 202 of the first plate-like structure 200 faces the third surface 301 of the second plate-like structure 300, the first active surface 221 of the first electronic component 220 and the third active surface 231 of the third electronic component 230 The second active surface 321 of the second electronic component 320. In other words, the first electronic component 220 is electrically connected to the second electronic component 320 through the redistribution layer 410, the bump 430, and the redistribution layer 420, and the third electronic component 230 is connected to the second electronic component 320 via the redistribution layer 410, the bump 430, and the redistribution layer. The distribution layer 420 is electrically connected to the second electronic component 320, and the first electronic component 220 is electrically connected to the third electronic component 230 through the redistribution layer 410. Therefore, the electronic signal transmission path between the first electronic component 220, the second electronic component 320, and the third electronic component 230 will not be too long. The first electronic component 220, the second electronic component 320, and the third electronic component 230 are only It takes a short time to be able to communicate with each other, so the overall operating efficiency of the stacked package structure 100 can be effectively improved.
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope shall be determined by the scope of the attached patent application.
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| US20140217610A1 (en) * | 2010-02-26 | 2014-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D Semiconductor Package Interposer with Die Cavity |
| US20150187607A1 (en) * | 2013-12-30 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Two step molding grinding for packaging applications |
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