TWI626722B - Electronic package and method for fabricating the same - Google Patents
Electronic package and method for fabricating the same Download PDFInfo
- Publication number
- TWI626722B TWI626722B TW106114961A TW106114961A TWI626722B TW I626722 B TWI626722 B TW I626722B TW 106114961 A TW106114961 A TW 106114961A TW 106114961 A TW106114961 A TW 106114961A TW I626722 B TWI626722 B TW I626722B
- Authority
- TW
- Taiwan
- Prior art keywords
- item
- patent application
- electronic package
- application scope
- electronic component
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 claims abstract description 40
- 230000001681 protective effect Effects 0.000 claims abstract description 35
- 238000005538 encapsulation Methods 0.000 claims abstract description 19
- 230000001012 protector Effects 0.000 claims description 30
- 239000000945 filler Substances 0.000 claims description 15
- 239000002019 doping agent Substances 0.000 claims description 13
- 239000002245 particle Substances 0.000 claims description 13
- 239000012530 fluid Substances 0.000 claims description 12
- 238000004806 packaging method and process Methods 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 28
- 239000004065 semiconductor Substances 0.000 description 15
- 239000000463 material Substances 0.000 description 8
- 239000000084 colloidal system Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000008393 encapsulating agent Substances 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 238000004880 explosion Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000001788 irregular Effects 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000012792 core layer Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一種電子封裝件及其製法，係於設有電子元件之承載件上藉由支撐件堆疊一具有貫穿開口之基板，以於該基板與該電子元件之間形成間隔，且經由該開口填入保護體於該電子元件上之間隔處，再以封裝層包覆該保護體與該支撐件，故當該承載件與該基板之間的空間有限時，該保護體仍可經由該開口填入而形成於該電子元件上，以達到保護該電子元件的功效。 An electronic package and a manufacturing method thereof, a substrate having a through opening is stacked on a carrier provided with an electronic component by a supporting member, so as to form a space between the substrate and the electronic component, and the protection is filled through the opening The body is spaced on the electronic component, and then the protective body and the supporting member are covered with an encapsulation layer, so when the space between the carrier and the substrate is limited, the protective body can still be filled in through the opening It is formed on the electronic component to achieve the effect of protecting the electronic component.
Description
本發明係有關一種半導體封裝結構，尤指一種適用於高密度訊號串接的電子封裝件及其製法。 The invention relates to a semiconductor packaging structure, in particular to an electronic packaging part suitable for serial connection of high-density signals and a manufacturing method thereof.
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂開發出不同的立體封裝技術，例如，封裝堆疊(Package on package，簡稱FO PoP)結構等，以將不同功能之積體電路整合於單一封裝結構，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。 With the evolution of semiconductor packaging technology, semiconductor devices (Semiconductor device) have developed different packaging types, and in order to improve electrical functions and save packaging space, they have developed different three-dimensional packaging technologies, such as package stacking (Package on package (FO PoP) structure, etc., to integrate integrated circuits of different functions into a single package structure. This packaging method can play the heterogeneous integration characteristics of system packaging (SiP), which can integrate electronic components with different functions, such as memory , Central processor, graphics processor, image application processor, etc., through the stack design to achieve system integration, suitable for various thin and light electronic products.
請參閱第1A至1B圖，係為習知PoP型半導體封裝件1之製法的剖面示意圖。如第1A圖所示，將上基板13藉由複數導電柱12堆疊於一設有半導體元件11之下基板10上，再如第1B圖所示，形成一封裝膠體15於該下基板10與該上基板13之間，以包覆該半導體元件11與該些導電 柱12。 Please refer to FIGS. 1A to 1B, which are schematic cross-sectional views of a conventional manufacturing method of a PoP type semiconductor package 1. As shown in FIG. 1A, the upper substrate 13 is stacked on a lower substrate 10 provided with semiconductor elements 11 through a plurality of conductive pillars 12, and then as shown in FIG. 1B, an encapsulant 15 is formed on the lower substrate 10 and Between the upper substrate 13 to cover the semiconductor element 11 and the conductive Column 12.
目前高密度訊號串接的封裝產品為了滿足市場需求，需不斷縮小其元件體積，故於習知半導體封裝件1中，該上、下基板13,10與半導體元件11之厚度越來越薄，且該上、下基板13,10之間的空間S亦設計成越來越窄。再者，該封裝膠體15係為一種熱固性膠體，且為了改善相關的物理化學性質，會在熱固性膠體中添加填充物(filler)14，以進行改質。 At present, in order to meet market demands, high-density signal tandem packaging products need to continuously reduce the size of their components. Therefore, in the conventional semiconductor package 1, the thicknesses of the upper and lower substrates 13, 10 and the semiconductor component 11 are getting thinner and thinner. And the space S between the upper and lower substrates 13, 10 is also designed to become narrower and narrower. Furthermore, the encapsulating colloid 15 is a thermosetting colloid, and in order to improve the relevant physical and chemical properties, a filler 14 is added to the thermosetting colloid for modification.
然而，由於製作成本或製造技術難度考量，該填充物14之寬度尺寸r通常為100至300微米(μm)，故當該上、下基板13,10之間的空間S太窄時，該填充物14無法正常流動，致使該封裝膠體15充填不均，容易造成該封裝膠體15無法達到保護該半導體元件11與該些導電柱12的功效。 However, due to manufacturing cost or manufacturing technical difficulty, the width r of the filler 14 is usually 100 to 300 micrometers (μm), so when the space S between the upper and lower substrates 13, 10 is too narrow, the filler The objects 14 cannot flow normally, resulting in uneven filling of the encapsulant 15, which may easily cause the encapsulant 15 to fail to protect the semiconductor device 11 and the conductive pillars 12.
再者，該半導體元件11頂面與該上基板13底面之間，更常發生該封裝膠體15沒有充填的空隙(void)，此種空隙(void)容易於高低溫衝擊時發生氣爆的問題。 Furthermore, between the top surface of the semiconductor element 11 and the bottom surface of the upper substrate 13, voids that are not filled by the encapsulant 15 are more common, and such voids are prone to gas explosion during high and low temperature impact .
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the above-mentioned problems of the conventional technology has become an urgent problem to be solved at present.
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：承載件；電子元件，係結合於該承載件上；基板，係透過至少一支撐件堆疊於該承載件上，且該基板係具有相對之第一表面與第二表面及至少一連通該第一表面與第二表面之開口，並於該基板之第一表面與該 電子元件之間形成間隔；保護體，係形成於該間隔中以接觸結合該電子元件；以及封裝層，係包覆該保護體與該支撐件。 In view of the above-mentioned defects of the prior art, the present invention provides an electronic package including: a carrier; an electronic component, which is coupled to the carrier; and a substrate, which is stacked on the carrier through at least one support, And the substrate has opposing first and second surfaces and at least one opening connecting the first and second surfaces, and the first surface of the substrate and the opening A space is formed between the electronic components; a protection body is formed in the space to contact and bond the electronic component; and an encapsulation layer is used to cover the protection body and the support.
本發明復提供一種電子封裝件之製法，係包括：提供一承載件，其上設有至少一電子元件；將一基板透過至少一支撐件堆疊於該承載件上，且該基板係具有相對之第一表面與第二表面及至少一連通該第一表面與第二表面之開口，並於該基板之第一表面與該電子元件之間形成間隔；經由該開口形成保護體於該間隔中，以令該保護體接觸結合該電子元件；以及以封裝層包覆該保護體與該支撐件。 The invention further provides a method for manufacturing an electronic package, comprising: providing a carrier on which at least one electronic component is arranged; stacking a substrate on the carrier through at least one support, and the substrate has opposite A first surface and a second surface and at least one opening connecting the first surface and the second surface, and forming a space between the first surface of the substrate and the electronic component; forming a protective body in the space through the opening, So that the protector contacts the electronic component; and the protector and the support are covered with an encapsulation layer.
前述之製法中，該保護體之製程係包括：將流體填充物經由該開口填入該開口中與該間隔中，以令該流體填充物接觸結合該電子元件；以及固化該流體填充物，以令該流體填充物成為該保護體。 In the aforementioned manufacturing method, the manufacturing process of the protective body includes: filling the fluid filling into the opening and the space through the opening to make the fluid filling contact with the electronic component; and curing the fluid filling, to Let the fluid filling be the protective body.
前述之電子封裝件及其製法中，該開口之位置對應該電子元件之位置。 In the aforementioned electronic package and its manufacturing method, the position of the opening corresponds to the position of the electronic component.
前述之電子封裝件及其製法中，該保護體與該封裝層之間具有交界面。 In the aforementioned electronic package and its manufacturing method, there is an interface between the protector and the encapsulation layer.
前述之電子封裝件及其製法中，該保護體係結合該電子元件之頂面。進一步，該保護體復結合該電子元件之側面。 In the aforementioned electronic package and its manufacturing method, the protection system incorporates the top surface of the electronic component. Further, the protective body is combined with the side of the electronic component.
前述之電子封裝件及其製法中，該保護體之摻雜物之粒徑尺寸係為該間隔之1/3至1/6。例如，該間隔之距離係為10至200微米。 In the aforementioned electronic package and its manufacturing method, the particle size of the dopant of the protective body is 1/3 to 1/6 of the interval. For example, the separation distance is 10 to 200 microns.
前述之電子封裝件及其製法中，該保護體之摻雜物之粒徑尺寸係小於15微米。 In the aforementioned electronic package and its manufacturing method, the particle size of the dopant of the protective body is less than 15 microns.
前述之電子封裝件及其製法中，該保護體復形成於該開口中。 In the aforementioned electronic package and its manufacturing method, the protective body is formed in the opening.
前述之電子封裝件及其製法中，該基板復形成有複數連通該第一表面與第二表面之穿孔。 In the aforementioned electronic package and its manufacturing method, the substrate is formed with a plurality of through holes connecting the first surface and the second surface.
前述之電子封裝件及其製法中，該基板之第二表面形成有凹部。 In the aforementioned electronic package and its manufacturing method, a concave portion is formed on the second surface of the substrate.
前述之電子封裝件及其製法中，該電子元件之周圍佈設有止擋件。 In the aforementioned electronic package and its manufacturing method, a stopper is arranged around the electronic component.
前述之電子封裝件及其製法中，該保護體係為薄膜膠材。 In the aforementioned electronic package and its manufacturing method, the protection system is a film adhesive.
由上可知，本發明之電子封裝件及其製法，主要藉由該基板上形成開口，使該保護體能經由該開口結合至該電子元件上，再形成該封裝層於該承載件與該基板之間的其它空間，故相較於習知技術，當該承載件與該基板之間的空間越來越窄時，該保護體仍可經由該開口填入而形成於該電子元件上，以達到保護該電子元件的功效，且該封裝層因不需填入習知填充物而能充填均勻，故可達到保護該支撐件的功效。 It can be seen from the above that the electronic package of the present invention and its manufacturing method mainly form an opening in the substrate to enable the protection body to be coupled to the electronic component through the opening, and then form the packaging layer on the carrier and the substrate Compared with the conventional technology, when the space between the carrier and the substrate becomes narrower and narrower, the protector can still be filled in through the opening and formed on the electronic component to achieve The effect of protecting the electronic component is protected, and the encapsulation layer can be filled evenly without filling the conventional filler, so the effect of protecting the support can be achieved.
1‧‧‧半導體封裝件 1‧‧‧Semiconductor package
10‧‧‧下基板 10‧‧‧Lower substrate
11‧‧‧半導體元件 11‧‧‧Semiconductor components
12‧‧‧導電柱 12‧‧‧Conducting column
13‧‧‧上基板 13‧‧‧Upper board
14‧‧‧填充物 14‧‧‧filler
15‧‧‧封裝膠體 15‧‧‧Packing colloid
2,3‧‧‧電子封裝件 2,3‧‧‧Electronic package
20‧‧‧承載件 20‧‧‧Carrier
20a‧‧‧第一側 20a‧‧‧First side
20b‧‧‧第二側 20b‧‧‧Second side
200,231‧‧‧線路層 200,231‧‧‧ line layer
201‧‧‧銲球 201‧‧‧solder ball
21‧‧‧電子元件 21‧‧‧Electronic components
21a‧‧‧頂面 21a‧‧‧Top
21c‧‧‧側面 21c‧‧‧Side
210‧‧‧導電凸塊 210‧‧‧conductive bump
211‧‧‧底膠 211‧‧‧ Primer
22‧‧‧支撐件 22‧‧‧Support
23‧‧‧基板 23‧‧‧ substrate
23a‧‧‧第一表面 23a‧‧‧First surface
23b‧‧‧第二表面 23b‧‧‧Second surface
230‧‧‧開口 230‧‧‧ opening
24,24’,24”‧‧‧保護體 24,24 ’, 24” ‧‧‧protector
240‧‧‧摻雜物 240‧‧‧Dopant
25‧‧‧封裝層 25‧‧‧Encapsulation layer
330‧‧‧穿孔 330‧‧‧Perforation
331‧‧‧凹部 331‧‧‧recess
36‧‧‧止擋件 36‧‧‧stop
d‧‧‧粒徑尺寸 d‧‧‧particle size
L,L’‧‧‧交界面 L, L’ ‧‧‧Intersection
r‧‧‧寬度尺寸 r‧‧‧Width
S‧‧‧空間 S‧‧‧Space
t‧‧‧間隔 t‧‧‧Interval
第1A至1B圖係為習知半導體封裝件之製法的剖面示意圖；第2A至2D圖係為本發明之電子封裝件之製法的剖面 示意圖；第2D’及2D”圖係為對應第2D圖之其它實施例的剖面示意圖；第3圖係為對應第2D圖之另一實施例的剖面示意圖；第3A圖係為對應第3圖之上視示意圖；以及第3B圖係為對應第3圖之另一態樣的局部放大剖面示意圖。 FIGS. 1A to 1B are schematic cross-sectional views of conventional semiconductor package manufacturing methods; FIGS. 2A to 2D are cross-sectional views of electronic package manufacturing methods of the present invention Schematic diagram; Figures 2D 'and 2D "are cross-sectional schematic diagrams of other embodiments corresponding to Figure 2D; Figure 3 is a cross-sectional schematic diagram of another embodiment corresponding to Figure 2D; Figure 3A is a corresponding diagram of Figure 3 The schematic view from above; and FIG. 3B is a partially enlarged schematic cross-sectional view corresponding to another aspect of FIG. 3.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following describes the implementation of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structure, ratio, size, etc. shown in the drawings of this specification are only used to match the contents disclosed in the specification, for those familiar with this skill to understand and read, not to limit the implementation of the present invention The limited conditions, so it does not have the technical significance, any modification of structure, change of proportional relationship or adjustment of size, should not fall within the scope of the invention without affecting the efficacy and the purpose of the invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "upper", "first", "second" and "one" cited in this specification are only for the convenience of description, not to limit the scope of the invention, The change or adjustment of the relative relationship shall be regarded as the scope of the invention without substantial changes in the technical content.
第2A至2D圖係為本發明之電子封裝件2之製法的剖面示意圖。 2A to 2D are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.
如第2A圖所示，提供一具有相對之第一側20a與第二側20b之承載件20，且該第一側20a上設有至少一電子元件21，而該第二側20b植設複數銲球201。 As shown in FIG. 2A, a carrier 20 having a first side 20a and a second side 20b opposite to each other is provided, and the first side 20a is provided with at least one electronic component 21, and the second side 20b is planted with a plurality of Solder ball 201.
於本實施例中，該承載件20係為具有核心層或無核心層(coreless)之線路結構，如封裝基板(substrate)，其具有線路層200，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)之線路配置。應可理解地，該承載件20亦可為其它承載晶片之板材，如導線架(leadframe)、晶圓(wafer)、或其它具有金屬佈線(routing)之載板等，並不限於上述。 In this embodiment, the carrier 20 is a circuit structure with a core layer or a coreless layer, such as a package substrate, which has a circuit layer 200, such as a fan-out type redistribution circuit Layer (redistribution layer, RDL) line configuration. It should be understood that the carrier 20 may also be other boards carrying chips, such as leadframes, wafers, or other carrier boards with metal routing, etc., which are not limited to the above.
再者，該電子元件21係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該電子元件21係藉由複數如銲錫材料之導電凸塊210以覆晶方式設於該承載件20之第一側20a上並電性連接該線路層200，再於該電子元件21與該承載件20之間形成包覆該導電凸塊210之底膠211；或者，該電子元件21可藉由複數銲線(圖略)以打線方式電性連接該承載件20；亦或，該電子元件21可直接接觸該承載件20之線路層200。然而，有關該電子元件21電性連接該承載件20之方式不限於上述。 Furthermore, the electronic device 21 is an active device, a passive device, or a combination of the two. The active device is, for example, a semiconductor chip, and the passive device is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 is flip-chip mounted on the first side 20a of the carrier 20 by a plurality of conductive bumps 210 such as solder material and electrically connected to the circuit layer 200, and then the electronic component 21 and A primer 211 covering the conductive bump 210 is formed between the carrier members 20; alternatively, the electronic component 21 can be electrically connected to the carrier member 20 by wire bonding through a plurality of bonding wires (not shown); or, the The electronic component 21 can directly contact the circuit layer 200 of the carrier 20. However, the manner in which the electronic component 21 is electrically connected to the carrier 20 is not limited to the above.
如第2B圖所示，將一基板23藉由複數支撐件22堆疊於該承載件20之第一側20a上，且該基板23係具有相對之第一表面23a與第二表面23b及至少一連通該第一與第二表面23a,23b之開口(aperture)230，並於該基板23之第一 表面23a與該電子元件21之間形成一間隔t。 As shown in FIG. 2B, a substrate 23 is stacked on the first side 20a of the carrier 20 by a plurality of support members 22, and the substrate 23 has opposing first and second surfaces 23a and 23b and at least one connection Through the opening 230 of the first and second surfaces 23a, 23b, and at the first of the substrate 23 An interval t is formed between the surface 23a and the electronic component 21.
於本實施例中，該基板23係為具有核心層或無核心層(coreless)之線路結構，如封裝基板，其具有線路層231，如扇出型重佈線路層之線路配置。應可理解地，該基板23亦可為其它承載晶片之板材，如矽中介板、封裝件、導線架、晶圓、或其它具有金屬佈線之載板等，並不限於上述。 In this embodiment, the substrate 23 is a circuit structure with a core layer or a coreless layer, such as a package substrate, which has a circuit layer 231, such as a fan-out type circuit layer circuit configuration. It should be understood that the substrate 23 may also be other boards carrying wafers, such as silicon interposers, packages, lead frames, wafers, or other carrier boards with metal wiring, etc., which are not limited to the above.
再者，該開口230之位置係對應該電子元件21之位置，例如，該開口230位於該電子元件21之上方。 Furthermore, the position of the opening 230 corresponds to the position of the electronic component 21, for example, the opening 230 is located above the electronic component 21.
又，該支撐件22係位於該電子元件21之外圍，且電性連接該些線路層200,231。具體地，該支撐件22係為球狀、柱狀或釘狀，如銅柱、銲球(solder ball)或具有核心銅球(Cu core ball)之銲錫塊等，但不限於上述。 In addition, the support 22 is located at the periphery of the electronic component 21 and is electrically connected to the circuit layers 200 and 231. Specifically, the support 22 is spherical, cylindrical or nail-shaped, such as a copper pillar, a solder ball, or a solder block with a core copper ball, but is not limited to the above.
另外，該間隔t之距離係為25至45微米(低於30微米)。 In addition, the distance t is 25 to 45 microns (less than 30 microns).
如第2C圖所示，經由該開口230形成一保護體24於該該間隔t中，以令該保護體24接觸結合該電子元件21與該基板23之第一表面23a。 As shown in FIG. 2C, a protective body 24 is formed in the interval t through the opening 230, so that the protective body 24 contacts the first surface 23 a of the electronic component 21 and the substrate 23.
於本實施例中，該保護體24係為絕緣材，其製程係先將流體填充物(filler)(如底膠之液態膠材)經由該開口230注射(inject)填入該間隔t中(可選擇性形成於該開口230中)，以令該流體填充物接觸結合該電子元件21之頂面21a與該基板23之第一表面23a，之後再固化(Curing)該流體填充物而成為該保護體24。具體地，可藉由注射裝置(injective device)之噴嘴(nozzle)***該開口230中以注射 該流體填充物。此外，該開口230的設計係具有洩壓作用，可以減少習知技術中之氣爆問題的發生。 In this embodiment, the protector 24 is an insulating material, and its manufacturing process first injects a fluid filler (such as a liquid glue material of the primer) through the opening 230 into the interval t ( Can be selectively formed in the opening 230), so that the fluid filler contacts the top surface 21a of the electronic component 21 and the first surface 23a of the substrate 23, and then cures the fluid filler to become the Protector 24. Specifically, the nozzle 230 of an injection device can be inserted into the opening 230 for injection The fluid fill. In addition, the design of the opening 230 has a pressure relief effect, which can reduce the occurrence of gas explosion problems in the conventional technology.
再者，該保護體24延伸結合接觸該電子元件21之局部側面21c或全部側面21c，以提高對該電子元件21之保護；應可理解地，若該保護體24延伸結合接觸該底膠211，可對該電子元件21提供更好之包覆性與保護性。 Furthermore, the protector 24 extends and contacts the partial side surface 21c or all the side surfaces 21c of the electronic component 21 to improve the protection of the electronic component 21; it should be understood that if the protector 24 extends and contacts the primer 211 , Can provide better coverage and protection for the electronic component 21.
又，該保護體24’,24”亦可為薄膜膠材(film adhesive)，如雙面膠(double side tape)，如第2D’及2D”圖所示。然而，相較於該薄膜膠材之型態，上述液態膠材因於固化前能流動填滿該承載件20與該基板23之間的預計空間而能避免產生氣室(voids)，故使用液態膠材作為該保護體24較佳。 In addition, the protectors 24 ', 24 "may also be film adhesives, such as double side tape, as shown in Figs. 2D' and 2D". However, compared with the type of the film adhesive, the liquid adhesive can avoid the formation of voids because it can flow to fill the expected space between the carrier 20 and the substrate 23 before curing. A liquid rubber material is preferred as the protective body 24.
另外，使用液態膠材作為該保護體24，其包含膠體與摻雜物(dopes)240，且該摻雜物240之粒徑尺寸d係小於15微米(μm)(較佳為1至5μm)、或小於填充物(如圖所示之不規則顆粒)之粒徑尺寸(或習知填充物14之寬度尺寸r)之1/2至1/5、或為該間隔t之1/3至1/6，明顯小於該間隔t之距離(10至200微米)，故該膠體與摻雜物240能均勻擴散於該電子元件21之頂面21a。具體地，該摻雜物240係例如二氧化矽粉、氧化鋁粉或其它適當材質(如高散熱傳導、高溫耐受性)等，以針對該保護體24進行改質，且該開口230之寬度需具有一定大小，例如，配合該摻雜物240之粒徑尺寸d。 In addition, a liquid glue material is used as the protective body 24, which includes colloid and dopes 240, and the particle size d of the dopants 240 is less than 15 microns (μm) (preferably 1 to 5 μm) , Or less than 1/2 to 1/5 of the particle size of the filler (irregular particles as shown) (or the width r of the conventional filler 14), or 1/3 to 1/3 of the interval t 1/6, which is significantly smaller than the distance t (10 to 200 microns), so the colloid and the dopant 240 can uniformly diffuse on the top surface 21a of the electronic component 21. Specifically, the dopant 240 is, for example, silicon dioxide powder, aluminum oxide powder, or other suitable materials (such as high heat dissipation conduction, high temperature resistance), etc., to modify the protective body 24, and the opening 230 The width needs to have a certain size, for example, to match the particle size d of the dopant 240.
如第2D圖所示，以一封裝層25包覆該保護體24與 該些支撐件22。 As shown in FIG. 2D, the protection body 24 and the protection body 24 are covered with an encapsulation layer 25 This some support 22.
於本實施例中，形成該封裝層25之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或模塑料(rmolding compound)等。 In this embodiment, the material for forming the encapsulation layer 25 is polyimide (PI), dry film, epoxy, or molding compound.
再者，由於該保護體24與該封裝層25係於不同製程先後製作，故於該保護體24與該封裝層25之間產生不規則交界面(irregular interface)L。或者，如第2D’圖所示，該保護體24’亦可僅接觸結合該電子元件21之頂面21a而未佔滿該間隔t，使該封裝層25之材質係些微形成於部分該間隔t中之保護體24’上，故該不規則交界面L’大致環繞於該電子元件21之周緣。 Furthermore, since the protective body 24 and the encapsulation layer 25 are manufactured in different processes, an irregular interface L is generated between the protective body 24 and the encapsulation layer 25. Alternatively, as shown in FIG. 2D ′, the protector 24 ′ may only contact the top surface 21 a of the electronic component 21 without filling the interval t, so that the material of the encapsulation layer 25 is slightly formed in part of the interval On the protector 24 'in t, the irregular interface L' roughly surrounds the periphery of the electronic component 21.
又，如第2D”圖所示，該保護體24”亦可僅形成於該間隔t中而未形成於該開口230中。 Furthermore, as shown in FIG. 2D ", the protector 24" may be formed only in the interval t and not in the opening 230.
因此，本發明之製法藉由該基板23上形成開口230，使該保護體24,24’,24”能經由該開口230流至該電子元件21之頂面21a(甚至其側面21c)，且待固化該保護體24,24’,24”後，再形成該封裝層25於該承載件20與該基板23之間的其它空間，故相較於習知技術，當該承載件20與該基板23之間的空間越來越窄時，該保護體24,24’,24”仍可經由該開口230填入而形成於該電子元件21上，以達到保護該電子元件21的功效，且該封裝層25因無需混充習知填充物(亦即不受習知填充物之影響)而能充填均勻，以達到保護該些支撐件22的功效。 Therefore, in the manufacturing method of the present invention, by forming an opening 230 in the substrate 23, the protectors 24, 24 ', 24 "can flow through the opening 230 to the top surface 21a (even the side surface 21c) of the electronic component 21, and After the protectors 24, 24 ', 24 "are cured, the encapsulation layer 25 is formed in other spaces between the carrier 20 and the substrate 23, so compared with the conventional technology, when the carrier 20 and the When the space between the substrates 23 becomes narrower and narrower, the protectors 24, 24 ', 24 "can still be filled in through the opening 230 and formed on the electronic component 21 to achieve the effect of protecting the electronic component 21, and Since the encapsulation layer 25 does not need to be filled with conventional fillers (that is, it is not affected by the conventional fillers), it can be filled uniformly, so as to achieve the effect of protecting the support members 22.
再者，如第3及3A圖所示之電子封裝件3，該基板 23亦可形成有複數連通該第一與第二表面23a,23b之穿孔330，以外露該保護體24，且於形成該保護體24之前(例如，堆疊該基板23之前)，可佈設至少一止擋件36於該電子元件21之周圍。 Furthermore, as in the electronic package 3 shown in FIGS. 3 and 3A, the substrate 23 may also be formed with a plurality of through holes 330 connecting the first and second surfaces 23a, 23b, exposing the protective body 24, and before forming the protective body 24 (eg, before stacking the substrate 23), at least one The stop 36 is around the electronic component 21.
於本實施例中，該穿孔330係作為排氣孔，使外露於該穿孔330之保護體24會接觸空氣，故當該電子封裝件3進行後續的高溫製程時，該保護體24中之溶劑於揮發後，便可經由該些穿孔330排出該保護體24外，而不會存留於該承載件20與該基板23之間，進而不會形成氣泡。此外，該穿孔330具有洩壓作用，也可以減少習知技術中之氣爆問題的發生。 In this embodiment, the through hole 330 is used as a vent hole, so that the protective body 24 exposed to the through hole 330 will contact with the air, so when the electronic package 3 is subjected to a subsequent high-temperature process, the solvent in the protective body 24 After volatilization, it can be discharged out of the protective body 24 through the perforations 330 without remaining between the carrier 20 and the substrate 23, so that no bubbles are formed. In addition, the perforation 330 has a pressure relief effect, which can also reduce the occurrence of gas explosion problems in the conventional technology.
再者，該止擋件36係為牆狀、環狀或其它合適形體，以環繞於該電子元件21之位置周圍，以於形成該保護體24時，該止擋件36能防止該保護體24溢流。 Furthermore, the stopper 36 is a wall, ring or other suitable body to surround the position of the electronic component 21 so that the stopper 36 can prevent the protector when forming the protector 24 24 overflow.
另外，如第3B圖所示，該基板23之第二表面23b亦可形成有凹部331，以於形成該保護體24時，能防止該保護體24溢流至該基板23之第二表面23b之線路區域而破壞線路之狀況。例如，該凹部331連通該開口230或穿孔330，以利於防止該保護體24溢流。 In addition, as shown in FIG. 3B, the second surface 23b of the substrate 23 may also be formed with a concave portion 331 to prevent the protection body 24 from overflowing to the second surface 23b of the substrate 23 when the protection body 24 is formed The condition of the line is damaged. For example, the concave portion 331 communicates with the opening 230 or the perforation 330 to help prevent the protection body 24 from overflowing.
本發明提供一種電子封裝件2,3，係包括：一承載件20、至少一電子元件21、一基板23、一保護體24,24’,24”以及一封裝層25。 The present invention provides an electronic package 2, 3, which includes: a carrier 20, at least one electronic component 21, a substrate 23, a protective body 24, 24 ', 24 "and a packaging layer 25.
所述之承載件20係具有相對之第一側20a與第二側20b，且該第二側20b形成有複數銲球201。 The carrier 20 has a first side 20a and a second side 20b opposite to each other, and a plurality of solder balls 201 are formed on the second side 20b.
所述之電子元件21係結合於該承載件20之第一側20a上。 The electronic component 21 is coupled to the first side 20a of the carrier 20.
所述之基板23係藉由複數支撐件22堆疊於該承載件20之第一側20a上，且該基板23係具有相對之第一表面23a與第二表面23b及至少一連通該第一與第二表面23a,23b之開口230，並於該基板23之第一表面23a與該電子元件21之間形成間隔t。 The substrate 23 is stacked on the first side 20a of the carrier 20 by a plurality of support members 22, and the substrate 23 has opposing first and second surfaces 23a and 23b and at least one communicating with the first and The opening 230 of the second surface 23a, 23b forms an interval t between the first surface 23a of the substrate 23 and the electronic component 21.
所述之保護體24,24’,24”係為絕緣材，其形成於該間隔t中以接觸保護該電子元件21。 The protective bodies 24, 24 ', 24 "are insulating materials formed in the interval t to protect the electronic component 21 in contact.
所述之封裝層25係形成於該基板23與該承載件20之第一側20a之間以包覆該保護體24,24’,24”與該些支撐件22。 The encapsulation layer 25 is formed between the substrate 23 and the first side 20a of the carrier 20 to cover the protectors 24, 24 ', 24 "and the support members 22.
於一實施例中，該開口230之位置係對應該電子元件21之位置。 In one embodiment, the position of the opening 230 corresponds to the position of the electronic component 21.
於一實施例中，該保護體24,24’,24”與該封裝層25之間產生交界面L,L’。 In one embodiment, an interface L, L 'is formed between the protective bodies 24, 24', 24 "and the encapsulation layer 25.
於一實施例中，該保護體24,24’,24”係接觸結合該電子元件21之頂面21a。進一步，該保護體24復接觸結合該電子元件21之側面21c。 In one embodiment, the protectors 24, 24 ', 24 "contact the top surface 21a of the electronic component 21. The protector 24 further contacts the side surface 21c of the electronic component 21.
於一實施例中，該保護體24,24’,24”之摻雜物240之粒徑尺寸d係為該間隔t之1/3至1/6。例如，該間隔t之距離係為10至200微米。 In one embodiment, the particle size d of the dopant 240 of the protectors 24, 24 ', 24 "is 1/3 to 1/6 of the interval t. For example, the distance of the interval t is 10 To 200 microns.
於一實施例中，該保護體24,24’,24”之摻雜物240之粒徑尺寸d係小於15微米。 In one embodiment, the particle size d of the dopant 240 of the protective bodies 24, 24 ', 24 "is less than 15 microns.
於一實施例中，該保護體24復形成於該開口230中。 In one embodiment, the protective body 24 is formed in the opening 230.
於一實施例中，該基板23復形成有複數連通該第一與第二表面23a,23b之穿孔330，以外露該保護體24。 In one embodiment, the substrate 23 is formed with a plurality of through holes 330 connecting the first and second surfaces 23a, 23b, and the protection body 24 is exposed.
於一實施例中，該基板23之第二表面23b係形成有對應該開口230及/或穿孔330之凹部331。 In one embodiment, the second surface 23b of the substrate 23 is formed with a concave portion 331 corresponding to the opening 230 and / or the through hole 330.
於一實施例中，該電子元件21之周圍佈設有至少一止擋件36。 In one embodiment, at least one stop 36 is disposed around the electronic component 21.
於一實施例中，該保護體24’,24”係為薄膜膠材。 In one embodiment, the protectors 24 ', 24 "are thin film adhesive materials.
綜上所述，本發明之電子封裝件及其製法，係藉由該基板具有開口之設計，即使該承載件與該基板之間的空間越來越窄，該保護體仍能經由該開口流至該電子元件上，以達到保護該電子元件的功效，且該封裝層因不受習知填充物之影響而能充填均勻，故能達到保護該些支撐件的功效。 In summary, the electronic package and its manufacturing method of the present invention are based on the design that the substrate has an opening, even if the space between the carrier and the substrate becomes narrower and narrower, the protector can still flow through the opening On the electronic component, the effect of protecting the electronic component is achieved, and the encapsulation layer can be filled uniformly without being affected by the conventional filler, so the effect of protecting the supporting members can be achieved.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are used to exemplify the principles and effects of the present invention, rather than to limit the present invention. Anyone who is familiar with this skill can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as listed in the scope of patent application mentioned later.
Claims (27)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106114961A TWI626722B (en) | 2017-05-05 | 2017-05-05 | Electronic package and method for fabricating the same |
| CN201710346871.2A CN108807288B (en) | 2017-05-05 | 2017-05-17 | Electronic package and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106114961A TWI626722B (en) | 2017-05-05 | 2017-05-05 | Electronic package and method for fabricating the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI626722B true TWI626722B (en) | 2018-06-11 |
| TW201843786A TW201843786A (en) | 2018-12-16 |
Family
ID=63256103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106114961A TWI626722B (en) | 2017-05-05 | 2017-05-05 | Electronic package and method for fabricating the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108807288B (en) |
| TW (1) | TWI626722B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI682521B (en) * | 2018-09-13 | 2020-01-11 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
| TWI736802B (en) * | 2018-10-23 | 2021-08-21 | 矽品精密工業股份有限公司 | Electronic package |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370322B (en) * | 2020-03-24 | 2022-04-01 | 江苏海莱新创医疗科技有限公司 | Method for hermetically fixing sheet-like or plate-like electronic component to substrate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200532872A (en) * | 2004-03-18 | 2005-10-01 | United Test Ct Inc | Method for fabricating window ball grid array semiconductor package |
| TW200845346A (en) * | 2007-05-10 | 2008-11-16 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor package structure and package substrate applicable thereto |
| US20140293563A1 (en) * | 2012-03-13 | 2014-10-02 | Howe Yin Loo | Microelectronic device attachment on a reverse microelectronic package |
| TW201709434A (en) * | 2015-08-20 | 2017-03-01 | 矽品精密工業股份有限公司 | Electronic package and method of manufacture thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5981312A (en) * | 1997-06-27 | 1999-11-09 | International Business Machines Corporation | Method for injection molded flip chip encapsulation |
| US7635914B2 (en) * | 2007-05-17 | 2009-12-22 | Texas Instruments Incorporated | Multi layer low cost cavity substrate fabrication for pop packages |
| US8273607B2 (en) * | 2010-06-18 | 2012-09-25 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereof |
| KR101934917B1 (en) * | 2012-08-06 | 2019-01-04 | 삼성전자주식회사 | Semiconductor Packages and Methods of Fabricating the Same |
| TW201519402A (en) * | 2013-11-05 | 2015-05-16 | 矽品精密工業股份有限公司 | Semiconductor package and manufacturing method thereof and substrate and packaged structure |
| TWI556402B (en) * | 2014-01-02 | 2016-11-01 | 矽品精密工業股份有限公司 | Package on package structure and manufacturing method thereof |
| TWI595603B (en) * | 2016-11-10 | 2017-08-11 | 矽品精密工業股份有限公司 | Package stack structure |
-
2017
- 2017-05-05 TW TW106114961A patent/TWI626722B/en active
- 2017-05-17 CN CN201710346871.2A patent/CN108807288B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200532872A (en) * | 2004-03-18 | 2005-10-01 | United Test Ct Inc | Method for fabricating window ball grid array semiconductor package |
| TW200845346A (en) * | 2007-05-10 | 2008-11-16 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor package structure and package substrate applicable thereto |
| US20140293563A1 (en) * | 2012-03-13 | 2014-10-02 | Howe Yin Loo | Microelectronic device attachment on a reverse microelectronic package |
| TW201709434A (en) * | 2015-08-20 | 2017-03-01 | 矽品精密工業股份有限公司 | Electronic package and method of manufacture thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI682521B (en) * | 2018-09-13 | 2020-01-11 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
| CN110896056A (en) * | 2018-09-13 | 2020-03-20 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| CN110896056B (en) * | 2018-09-13 | 2021-05-14 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| TWI736802B (en) * | 2018-10-23 | 2021-08-21 | 矽品精密工業股份有限公司 | Electronic package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108807288A (en) | 2018-11-13 |
| TW201843786A (en) | 2018-12-16 |
| CN108807288B (en) | 2020-04-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI692030B (en) | Semiconductor package and method of manufacturing the same | |
| TWI631676B (en) | Electronic package and method of manufacture | |
| US7339278B2 (en) | Cavity chip package | |
| TWI587412B (en) | Package structures and methods for fabricating the same | |
| EP3154083B1 (en) | Fan-out package structure having embedded package substrate | |
| TWI652787B (en) | Electronic package and its manufacturing method | |
| TWI614848B (en) | Electronic package and method of manufacture thereof | |
| TW201830606A (en) | A semiconductor package structure and method for forming the same | |
| US11908759B2 (en) | Semiconductor device | |
| JP2010165814A (en) | Semiconductor device and method of fabricating the same | |
| TWI626722B (en) | Electronic package and method for fabricating the same | |
| TW202129900A (en) | Package structure | |
| TWI732509B (en) | Electronic package | |
| TW202230711A (en) | Semiconductor package | |
| TWI765778B (en) | Electronic package and manufacturing method thereof | |
| TW201719841A (en) | Electronic package and method of manufacture | |
| TWI632603B (en) | A semiconductor package, a semiconductor device and a manufacturing method of a semiconductor package | |
| US20140099755A1 (en) | Fabrication method of stacked package structure | |
| TWI718801B (en) | Electronic package manufacturing method | |
| TWI676248B (en) | Semiconductor device | |
| TWI691041B (en) | Electronic package and package substrate thereof and method for manufacturing same | |
| TWM521807U (en) | Package structure and intermediate board thereof | |
| CN106469706B (en) | Electronic package and manufacturing method thereof | |
| TWI809787B (en) | Electronic package and manufacturing method thereof | |
| US20240249989A1 (en) | Selectively Dispensed Underfill and Edge Bond Patterns |