TWI626535B - Power management system and controller - Google Patents
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- G06F1/26—Power supply means, e.g. regulation thereof
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
本發明提供了一種電源管理系統。電源管理系統包括一處理器、一晶片組、一控制器以及一電源調節電路。晶片組電性連接處理器,且經由一增強串列周邊介面傳送一電源資訊給控制器。控制器藉由增強串列周邊介面電性連接至晶片組,經由增強串列周邊介面接收電源資訊,且解碼電源資訊以取得一狀態資訊。電源調節電路接收來自控制器之一控制信號,且根據控制信號,關閉、開啟或調整處理器之電源。 The invention provides a power management system. The power management system includes a processor, a chipset, a controller, and a power regulation circuit. The chipset is electrically connected to the processor, and transmits a power source information to the controller through an enhanced serial peripheral interface. The controller is electrically connected to the chipset through the enhanced serial peripheral interface, receives power information through the enhanced serial peripheral interface, and decodes the power information to obtain a status information. The power adjustment circuit receives a control signal from one of the controllers, and according to the control signal, turns off, turns on, or adjusts the power of the processor.
Description
本發明說明書主要係有關於一處理器電源管理技術,特別係有關於藉由增強串列周邊介面(Enhanced Serial Peripheral Interface,eSPI)連接晶片組和控制器,以直接藉由控制器來管理處理器電源之處理器電源管理技術。 The description of the present invention mainly relates to a processor power management technology, and particularly relates to connecting a chipset and a controller through an Enhanced Serial Peripheral Interface (eSPI) to directly manage the processor through the controller. Processor power management technology for power supply.
為了延長電腦裝置電池之續航力,在傳統之電腦裝置中會配置一電源邏輯電路來監看晶片組(chipset)之SLP_S0#接腳,以判斷電腦裝置是否進入或離開低耗電模式。電源邏輯電路會根據判斷結果,指示電壓調節模組(Voltage Regulator Module,VRM)關閉或開啟電腦之中央處理器(Central Processing Unit,CPU)之電源。 In order to extend the battery life of the computer device, a power logic circuit will be configured in the traditional computer device to monitor the SLP_S0 # pin of the chipset to determine whether the computer device enters or leaves the low power consumption mode. The power logic circuit instructs the Voltage Regulator Module (VRM) to turn off or turn on the power of the computer's Central Processing Unit (CPU) according to the judgment result.
也就是說,在傳統之電腦裝置中,嵌入控制器(Embedded Controller,EC)或超級輸入輸出(Super Input Output,SIO)晶片並不會參與處理器電源之管理。再者,當SLP_S0#接腳為低電位時,處理器之電源狀態通常會處於C10之狀態。此外,相較於傳統用來連接晶片組和嵌入控制器(或超級輸入輸出)之低接腳數匯流排(Low Pin Count Bus,LPC Bus),增強串列周邊介面(eSPI)可用來提供處理器之C10狀態資訊。 In other words, in traditional computer devices, embedded controller (EC) or super input output (SIO) chips do not participate in the management of processor power. Furthermore, when the SLP_S0 # pin is at a low level, the power state of the processor is usually in the C10 state. In addition, compared to the traditional Low Pin Count Bus (LPC Bus), which is used to connect the chipset and embedded controller (or Super I / O), the Enhanced Serial Peripheral Interface (eSPI) can be used to provide processing C10 status information.
因此,如何藉由電腦裝置中原先就配置之嵌入控制器或超級輸入輸出晶片來管理處理器之電源,將是值得討論之課題。 Therefore, how to manage the power of the processor by using the embedded controller or super I / O chip originally configured in the computer device will be a topic worthy of discussion.
有鑑於上述先前技術之問題,本發明提供了藉由增強串列周邊介面連接晶片組和控制器,以直接藉由控制器來管理處理器電源之電源管理系統。 In view of the foregoing problems of the prior art, the present invention provides a power management system for connecting a chipset and a controller through an enhanced serial peripheral interface to directly manage the power of a processor through the controller.
根據本發明之一實施例提供了一種電源管理系統。上述電源管理系統包括一處理器、一晶片組、一控制器以及一電源調節電路。晶片組電性連接上述處理器,且經由一增強串列周邊介面傳送一電源資訊給控制器。控制器電性連接上述增強串列周邊介面,經由上述增強串列周邊介面接收上述電源資訊,且解碼上述電源資訊以取得一狀態資訊。電源調節電路接收來自上述控制器之一控制信號,且根據上述控制信號,關閉、開啟或調整上述處理器之電源。 According to an embodiment of the present invention, a power management system is provided. The power management system includes a processor, a chipset, a controller, and a power adjustment circuit. The chipset is electrically connected to the processor, and transmits a power source information to the controller through an enhanced serial peripheral interface. The controller is electrically connected to the enhanced serial peripheral interface, receives the power source information through the enhanced serial peripheral interface, and decodes the power source information to obtain a status information. The power adjustment circuit receives a control signal from one of the controllers, and turns off, turns on, or adjusts the power of the processor according to the control signal.
根據本發明一些實施例,上述控制器包括一解碼電路,用以解碼上述電源資訊。根據本發明一些實施例,上述控制器根據上述狀態資訊,產生一控制信號,且將上述控制信號傳送給上述電源調節電路。 According to some embodiments of the present invention, the controller includes a decoding circuit for decoding the power information. According to some embodiments of the present invention, the controller generates a control signal according to the status information, and transmits the control signal to the power adjustment circuit.
根據本發明一些實施例,上述狀態資訊包括晶片組之一SLP_S0#接腳資訊,以及一處理器電源狀態資訊。根據本發明一些實施例,處理器電源狀態資訊包括一C10狀態資訊。 According to some embodiments of the present invention, the above-mentioned state information includes SLP_S0 # pin information of a chipset, and a processor power state information. According to some embodiments of the present invention, the processor power state information includes a C10 state information.
根據本發明之一實施例提供了一種控制器。上述 控制器包括一解碼電路。上述控制器經由一增強串列周邊介面連接至一晶片組,且經由上述增強串列周邊介面接收來自上述晶片組傳送之上述電源資訊。 According to an embodiment of the present invention, a controller is provided. Above The controller includes a decoding circuit. The controller is connected to a chipset via an enhanced serial peripheral interface, and receives the power supply information transmitted from the chipset via the enhanced serial peripheral interface.
根據本發明一些實施例,上述控制器更包括一控制電路。控制電路根據上述狀態資訊,產生一控制信號,且將上述控制信號傳送給一電源調節電路。 According to some embodiments of the present invention, the controller further includes a control circuit. The control circuit generates a control signal according to the state information, and transmits the control signal to a power regulating circuit.
關於本發明其他附加的特徵與優點,此領域之熟習技術人士,在不脫離本發明之精神和範圍內,當可根據本案實施方法中所揭露之執行聯繫程序之使用者裝置、系統,做些許的更動與潤飾而得到。 Regarding other additional features and advantages of the present invention, those skilled in the art can make some modifications based on the user device and system for performing the contact procedure disclosed in the implementation method of the present invention without departing from the spirit and scope of the present invention. Changes and retouching.
100‧‧‧電源管理系統 100‧‧‧Power Management System
110‧‧‧處理器 110‧‧‧ processor
120‧‧‧晶片組 120‧‧‧chipset
130‧‧‧控制器 130‧‧‧controller
131‧‧‧解碼電路 131‧‧‧ decoding circuit
132‧‧‧控制電路 132‧‧‧Control circuit
140‧‧‧電源調節電路 140‧‧‧Power Regulation Circuit
150‧‧‧增強串列周邊介面 150‧‧‧Enhanced serial peripheral interface
S1‧‧‧控制信號 S1‧‧‧Control signal
第1圖係顯示根據本發明之一實施例所述之電源管理系統之方塊圖。 FIG. 1 is a block diagram showing a power management system according to an embodiment of the present invention.
第2圖係顯示根據本發明之一實施例所述之控制器之方塊圖。 FIG. 2 is a block diagram of a controller according to an embodiment of the present invention.
本章節所敘述的是實施本發明之最佳方式,目的在於說明本發明之精神而非用以限定本發明之保護範圍,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 This section describes the best way to implement the present invention. The purpose is to explain the spirit of the present invention and not to limit the scope of protection of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application. .
第1圖係顯示根據本發明之一實施例所述之電源管理系統100之方塊圖。電源管理系統100可係一電腦主機、一筆記型電腦、一平板電腦或一行動裝置,但本發明不以此為限。如第1圖所示,電源管理系統100中可包括了一處理器 110、一晶片組120、一控制器130、一電源調節電路140以及一增強串列周邊介面(Enhanced Serial Peripheral Interface,eSPI)150。注意地是,在第1圖中之方塊圖,僅係為了方便說明本發明之實施例,但本發明並不以此為限。電源管理系統100亦可包括其他元件。 FIG. 1 is a block diagram of a power management system 100 according to an embodiment of the present invention. The power management system 100 can be a computer host, a notebook computer, a tablet computer, or a mobile device, but the invention is not limited thereto. As shown in FIG. 1, the power management system 100 may include a processor. 110. A chipset 120, a controller 130, a power adjustment circuit 140, and an enhanced serial peripheral interface (eSPI) 150. It should be noted that the block diagram in FIG. 1 is only for the convenience of describing the embodiments of the present invention, but the present invention is not limited thereto. The power management system 100 may also include other components.
根據本發明之一實施例,處理器110會分別電性連接至晶片組120以及電源調節電路140。在本發明之實施例中,控制器130係藉由增強串列周邊介面150電性連接至晶片組120。 According to an embodiment of the present invention, the processor 110 is electrically connected to the chipset 120 and the power adjustment circuit 140 respectively. In the embodiment of the present invention, the controller 130 is electrically connected to the chipset 120 through the enhanced serial peripheral interface 150.
根據本發明之一實施例,晶片組120可包括北橋晶片和南橋晶片。處理器110可藉由前端匯流排電性連接至晶片組120之北橋晶片,控制器130則可藉由增強串列周邊介面150電性連接至晶片組120之南橋晶片。在本發明一些實施例中,晶片組120可係一平台控制器(Platform Controller Hub,PCH)。 According to an embodiment of the present invention, the chip set 120 may include a north bridge wafer and a south bridge wafer. The processor 110 may be electrically connected to the northbridge chip of the chipset 120 through a front-end bus, and the controller 130 may be electrically connected to the southbridge chip of the chipset 120 through an enhanced serial peripheral interface 150. In some embodiments of the present invention, the chipset 120 may be a Platform Controller Hub (PCH).
根據本發明之一實施例,控制器130可係一嵌入控制器(Embedded Controller,EC)或一超級輸入輸出(Super Input Output,SIO)晶片,但本發明不以此為限。根據本發明之一實施例,控制器130會配置關於處理器110之電源狀態相關之控制或判斷電路(例如:控制電路132),以使得控制器130可解碼晶片組120藉由增強串列周邊介面150所提供之電源資訊中關於處理器110之電源狀態之資訊。 According to an embodiment of the present invention, the controller 130 may be an embedded controller (EC) or a super input output (SIO) chip, but the present invention is not limited thereto. According to an embodiment of the present invention, the controller 130 configures a control or judgment circuit related to the power state of the processor 110 (for example, the control circuit 132), so that the controller 130 can decode the chipset 120 by enhancing the serial peripheral Information about the power state of the processor 110 in the power information provided by the interface 150.
根據本發明之一實施例,電源調節電路140可係一電壓調節模組(Voltage Regulator Module,VRM)。在本發明 之實施例中,電源調節電路140可用以提供處理器110所需之電源,並根據控制器130之指示,適當調節提供給處理器110之電源,例如:關閉、開啟或調整處理器110之電源。 According to an embodiment of the present invention, the power regulation circuit 140 may be a voltage regulator module (VRM). In the present invention In an embodiment, the power regulating circuit 140 may be used to provide the power required by the processor 110 and appropriately adjust the power provided to the processor 110 according to an instruction of the controller 130, such as: turning off, turning on, or adjusting the power of the processor 110 .
第2圖係顯示根據本發明之一實施例所述之控制器130之方塊圖。如第2圖所示,根據本發明一實施例,控制器130可包含一解碼電路131以及一控制電路132。注意地是,在第2圖中之方塊圖,僅係為了方便說明本發明之實施例,但本發明並不以此為限。 FIG. 2 is a block diagram of the controller 130 according to an embodiment of the present invention. As shown in FIG. 2, according to an embodiment of the present invention, the controller 130 may include a decoding circuit 131 and a control circuit 132. It is noted that the block diagram in FIG. 2 is only for the convenience of describing the embodiment of the present invention, but the present invention is not limited thereto.
根據本發明之一實施例,控制器130會藉由增強串列周邊介面150取得晶片組120所提供之電源資訊。當控制器130取得晶片組120所提供之電源資訊後,控制器130之解碼電路131會解碼從增強串列周邊介面150所接收到之電源資訊,以取得一狀態資訊,並將狀態資訊傳送給控制器130之控制電路132。控制電路132根據狀態資訊,即可得知目前處理器110以及晶片組120之電源狀態(或操作狀態)。舉例來說,控制電路132根據狀態資訊,可得知目前處理器110以及晶片組120是否進入一低耗電狀態或一休眠狀態。 According to an embodiment of the present invention, the controller 130 obtains the power information provided by the chipset 120 through the enhanced serial peripheral interface 150. After the controller 130 obtains the power supply information provided by the chipset 120, the decoding circuit 131 of the controller 130 decodes the power supply information received from the enhanced serial peripheral interface 150 to obtain a status information and transmits the status information to The control circuit 132 of the controller 130. The control circuit 132 can obtain the current power status (or operation status) of the processor 110 and the chipset 120 according to the status information. For example, the control circuit 132 can know whether the current processor 110 and the chipset 120 enter a low power consumption state or a hibernation state according to the status information.
根據本發明一些實施例,解碼電路131解碼後產生之狀態資訊可包括晶片組120之一SLP_S0#接腳資訊,以及一處理器電源狀態資訊,但本發明並不以此為限。 According to some embodiments of the present invention, the state information generated by the decoding circuit 131 after decoding may include SLP_S0 # pin information of the chipset 120 and a processor power state information, but the present invention is not limited thereto.
SLP_S0#接腳資訊係表示晶片組120之南橋晶片(組)之SLP_S0#接腳所帶之電位值。SLP_S0#接腳所帶之電位值可用來表示電源管理系統100是否進入或離開一耗電模式。根據本發明之一實施例,當控制電路132取得SLP_S0#接腳資 訊後,控制電路132即可根據所解出之SLP_S0#接腳資訊得知SLP_S0#接腳目前所帶之電位值,並根據電位值判斷目前電源管理系統100是否進入或離開一耗電模式。舉例來說,當SLP_S0#接腳目前所帶之電位值是低電位,控制電路132就會判斷電源管理系統100進入一耗電模式,以及當SLP_S0#接腳目前所帶之電位值是高電位,控制電路132就會判斷電源管理系統100離開一耗電模式。 The SLP_S0 # pin information indicates the potential value of the SLP_S0 # pin of the south bridge chip (group) of the chipset 120. The potential value of the SLP_S0 # pin can be used to indicate whether the power management system 100 enters or leaves a power consumption mode. According to an embodiment of the present invention, when the control circuit 132 obtains SLP_S0 # pin information After the communication, the control circuit 132 can obtain the current potential value of the SLP_S0 # pin according to the extracted SLP_S0 # pin information, and determine whether the current power management system 100 enters or leaves a power consumption mode according to the potential value. For example, when the current potential of the SLP_S0 # pin is low, the control circuit 132 determines that the power management system 100 enters a power consumption mode, and when the current value of the SLP_S0 # pin is high The control circuit 132 determines that the power management system 100 leaves a power consumption mode.
根據本發明之一實施例,處理器電源狀態資訊係表示一C10狀態(C10 state)資訊。C-state係進階組態與電源介面(Advanced Configuration and Power Interface,ACPI)中用來制定處理器(CPU)之電源狀態之規範。在C-state之規範中,處理器(CPU)之電源狀態包含了C1~C10狀態,其中C10係表示處理器之外部電壓調整可降至0V或完全關閉。 According to an embodiment of the present invention, the processor power state information indicates a C10 state information. C-state is a standard used in the Advanced Configuration and Power Interface (ACPI) to formulate the power state of the processor (CPU). In the C-state specification, the power state of the processor (CPU) includes C1 ~ C10 states, where C10 indicates that the external voltage adjustment of the processor can be reduced to 0V or turned off completely.
根據本發明之一實施例,當控制器130之控制電路132取得C10狀態資訊時,控制電路132即可根據C10狀態資訊,得知處理器110目前是否處於C10之狀態。因此,根據C10狀態資訊,控制電路132就會產生一控制信號S1,且將控制信號S1傳送給電源調節電路140。當調節電路140接收到控制信號S1,電源調節電路140就會根據控制信號S1之指示,關閉、開啟或調整提供給處理器110之電源。 According to an embodiment of the present invention, when the control circuit 132 of the controller 130 obtains the C10 state information, the control circuit 132 can know whether the processor 110 is currently in the C10 state according to the C10 state information. Therefore, according to the C10 status information, the control circuit 132 generates a control signal S1 and transmits the control signal S1 to the power adjustment circuit 140. When the adjustment circuit 140 receives the control signal S1, the power adjustment circuit 140 turns off, turns on, or adjusts the power supplied to the processor 110 according to the instruction of the control signal S1.
根據本發明之一實施例,電源管理系統100可藉由控制器130之控制電路132,根據解碼電路131解碼後產生之狀態資訊,控制風扇以及狀態燈號之電源。 According to an embodiment of the present invention, the power management system 100 can control the power of the fan and the status light according to the status information generated by the decoding circuit 131 through the control circuit 132 of the controller 130.
根據本案實施例所提出之電源管理系統100,可使 得電腦裝置可直接藉由自身之控制器(例如:EC或SIO),解碼從增強串列周邊介面接收到之電源資訊,並根據解碼後產生之狀態資訊,來管理處理器之電源。因此,電腦裝置中不用再藉由配置額外之電源邏輯電路來監看晶片組之SLP_S0#接腳,以管理處理器之電源。 According to the power management system 100 proposed in the embodiment of this case, The computer device can directly use its own controller (such as EC or SIO) to decode the power information received from the enhanced serial peripheral interface, and manage the power of the processor based on the decoded state information. Therefore, there is no need to monitor the SLP_S0 # pin of the chipset by configuring additional power logic circuits in the computer device to manage the power of the processor.
本說明書中所提到的「一實施例」或「實施例」,表示與實施例有關之所述特定的特徵、結構、或特性是包含根據本發明的至少一實施例中,但並不表示它們存在於每一個實施例中。因此,在本說明書中不同地方出現的「在一實施例中」或「在實施例中」詞組並不必然表示本發明的相同實施例。 "One embodiment" or "an embodiment" mentioned in this specification indicates that the specific feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment according to the present invention, but does not mean that They exist in every embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places in this specification do not necessarily denote the same embodiment of the invention.
以上段落使用多種層面描述。顯然的,本文的教示可以多種方式實現,而在範例中揭露之任何特定架構或功能僅為一代表性之狀況。根據本文之教示,任何熟知此技藝之人士應理解在本文揭露之各層面可獨立實作或兩種以上之層面可以合併實作。 The above paragraphs are described at multiple levels. Obviously, the teachings of this article can be implemented in many ways, and any particular architecture or function disclosed in the examples is only a representative situation. According to the teachings of this article, anyone familiar with the art should understand that the aspects disclosed in this article can be implemented independently or that more than two levels can be combined and implemented.
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
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