TWI624860B - Oxygen-containing ceramic hard masks and associated wet-cleans - Google Patents
Oxygen-containing ceramic hard masks and associated wet-cleans Download PDFInfo
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Abstract
一種在半導體基板上形成含氧陶瓷硬遮罩薄膜的方法包含：在電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)處理腔室中接收半導體基板、及藉由PECVD在基板上沉積形成含氧陶瓷硬遮罩薄膜，此薄膜對低介電常數(低k)介電質及銅具蝕刻選擇性、對電漿乾式蝕刻具抗性、並能夠藉由濕式蝕刻移除。此方法可更包含：以濕式蝕刻將含氧陶瓷硬遮罩薄膜由基板移除。對應之薄膜及設備亦被提供。 A method for forming an oxygen-containing ceramic hard mask film on a semiconductor substrate comprises: receiving a semiconductor substrate in a plasma-enhanced chemical vapor deposition (PECVD) processing chamber, and on the substrate by PECVD The deposition forms an oxygen-containing ceramic hard mask film that is resistant to low dielectric constant (low-k) dielectric and copper etch selectivity, plasma dry etch, and capable of being removed by wet etching. The method can further include: removing the oxygen-containing ceramic hard mask film from the substrate by wet etching. Corresponding films and equipment are also available.
Description
本申請案主張美國臨時專利申請案第61/738,599號的優先權，該優先權基礎案申請於2012年12月18日，且名為「OXYGEN-CONTAINING CERAMIC HARD MASKS AND ASSOCIATED WET-CLEANS」，其藉由參考其整體內容而合併於本文中以供所有目的。 The present application claims priority to US Provisional Patent Application No. 61/738,599, filed on Dec. 18, 2012, entitled "OXYGEN-CONTAINING CERAMIC HARD MASKS AND ASSOCIATED WET-CLEANS", It is incorporated herein by reference for its entirety for all purposes.
本發明係關於用在半導體處理中的硬遮罩薄膜。本發明亦涉及用於形成及移除此種薄膜的方法與設備。 This invention relates to hard mask films for use in semiconductor processing. The invention also relates to methods and apparatus for forming and removing such films.
硬遮罩薄膜在微影圖案化期間，例如在鑲嵌(Damascene)製程中溝槽及/或貫孔之形成期間，一般係用來當作犧牲層。在鑲嵌製程中，通常係將硬遮罩薄膜沉積至需要被圖案化的介電質層上。將光阻層沉積於此硬遮罩薄膜上(具有被沉積於硬遮罩及光阻之間的可選抗反射層)，並依所需將此光阻圖案化。在此光阻被顯影後，將位於圖案下方的曝露之硬遮罩薄膜移除，並蝕刻曝露之介電質，俾以形成所需尺寸的凹陷特徵部。剩餘的硬遮罩用於保護需要在蝕刻製程期間被保留的那些部分的介電質。因此，硬遮罩材料必須具有相對於介電質良好的蝕刻選擇性。使用鹵素基(halogen-based)電漿化學物質的反應離子蝕刻(reactive ion etching,RIE)通常係用於介電質之蝕刻。 The hard mask film is typically used as a sacrificial layer during lithographic patterning, such as during the formation of trenches and/or vias in a damascene process. In the damascene process, a hard mask film is typically deposited onto the dielectric layer that needs to be patterned. A photoresist layer is deposited on the hard mask film (with an optional anti-reflective layer deposited between the hard mask and the photoresist) and patterned as needed. After the photoresist is developed, the exposed hard mask film underlying the pattern is removed and the exposed dielectric is etched to form recess features of the desired size. The remaining hard mask is used to protect the dielectric of those portions that need to be preserved during the etching process. Therefore, the hard mask material must have good etch selectivity with respect to the dielectric. Reactive ion etching (RIE) using halogen-based plasma chemistries is commonly used for dielectric etching.
所蝕刻的凹陷特徵部接著被導電材料(例如銅)填滿，而 形成積體電路的導電路徑。通常，在凹陷特徵部被填滿後，會將硬遮罩材料由此部分製造之半導體基板完全移除。 The etched recess features are then filled with a conductive material such as copper, and Forming a conductive path of the integrated circuit. Typically, the hard mask material is completely removed from the partially fabricated semiconductor substrate after the recess features are filled.
在前段製程(front-end-of-line,FEOL)與後段製程(back-end-of-line,BEOL)二者之圖案化方案中，硬遮罩層正變得愈加普遍。舉例來說，硬遮罩薄膜在BEOL之層間介電質(inter-level dielectric,ILD)材料的關鍵圖案化應用中，常用作輔助物。這些硬遮罩薄膜應具有相對於ILD材料高的蝕刻選擇性、相容於基本微影製程、及能夠在不損傷下方ILD層的情況下被移除。目前，在BEOL的低介電常數(低k)介電質應用中，常使用TiN作為硬遮罩，此乃由於其具有相對於低k介電質非常高的蝕刻選擇性，此有助於最後將其移除。然而，存有與此種金屬基(metal-based)硬遮罩相關的一些整合上問題：(a)在蝕刻製程期間，被形成以保護低k ILD之側壁的聚合物會與金屬基硬遮罩發生反應，而形成會造成缺陷問題的金屬聚合物殘留物；(b)與弱機械特性之低k介電質耦合的TiN中的高壓縮應力會導致屈曲(buckling)現象；及(c)需要有相對於底層不同的蝕刻平台供硬遮罩用，其會更增加成本。 In the patterning scheme of both front-end-of-line (FEOL) and back-end-of-line (BEOL), hard mask layers are becoming more common. For example, hard mask films are often used as an aid in key patterning applications for BEOL inter-level dielectric (ILD) materials. These hard mask films should have high etch selectivity with respect to the ILD material, be compatible with the basic lithography process, and be capable of being removed without damaging the underlying ILD layer. Currently, in low dielectric constant (low-k) dielectric applications of BEOL, TiN is often used as a hard mask because of its very high etch selectivity relative to low-k dielectrics, which helps Finally remove it. However, there are some integration problems associated with such metal-based hard masks: (a) during the etching process, the polymer formed to protect the sidewalls of the low-k ILD will be hard-masked with the metal-based The cover reacts to form a metal polymer residue that causes defects; (b) high compressive stress in the TiN coupled to the low-k dielectric of weak mechanical properties causes buckling; and (c) It is necessary to have a different etching platform relative to the bottom layer for the hard mask, which will increase the cost.
本發明提供具有經改善之特性的硬遮罩薄膜及其製造與移除方法。在微影應用中，需要具有低應力的硬遮罩材料，此乃由於具有高度壓縮或拉伸應力的材料會導致基板上之硬遮罩薄膜的屈曲(buckling)或剝離，且，因此，會導致微影中的劣質圖案對準。除了低應力外，為了充分保護下方材料，硬遮罩材料應具有高硬度及/或高楊氏模數，因為硬度與模數通常係與高蝕刻選擇性極其相關。 The present invention provides a hard mask film having improved properties and methods of making and removing same. In lithography applications, a hard mask material with low stress is required because materials with high compressive or tensile stress can cause buckling or peeling of the hard mask film on the substrate, and, therefore, Causes inferior pattern alignment in the lithography. In addition to low stress, in order to adequately protect the underlying material, the hard mask material should have a high hardness and/or a high Young's modulus, as hardness and modulus are often highly correlated with high etch selectivity.
基於PECVD的陶瓷硬遮罩係傾向為化學惰性，藉此可在濕式化學或化學機械研磨(chemical mechanical polishing,CMP)期間具有非常低的移除率。然而，某些陶瓷，除了非常硬之外，本性上可以係親水性的，且其組成可使濕式清潔及CMP化學有效。提供了使用PECVD沉積來形成、且在圖案轉移步驟後藉濕式清潔移除的含氧陶瓷硬遮罩材料。這些硬遮罩材料具有低應力及相對於低k介電質材料高的 蝕刻選擇性，這些特性使得先進圖案化變得可行，且在同一時間這些硬遮罩材料係可藉由濕式清潔化學來移除而不需要CMP，因此對這些薄膜的整合極有幫助。 Ceramic hard masks based on PECVD tend to be chemically inert, thereby providing very low removal rates during wet chemical or chemical mechanical polishing (CMP). However, certain ceramics, in addition to being very hard, may be hydrophilic in nature and their composition may be effective for wet cleaning and CMP chemistry. An oxygen-containing ceramic hard mask material formed using PECVD deposition and removed by wet cleaning after the pattern transfer step is provided. These hard mask materials have low stress and are high relative to low-k dielectric materials Etching selectivity, which makes advanced patterning feasible, and at the same time these hard mask materials can be removed by wet cleaning chemistry without the need for CMP, thus greatly facilitating the integration of these films.
在一實施態樣中，在半導體基板上形成含氧陶瓷硬遮罩薄膜的方法包含：在電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)處理腔室中接收半導體基板、及藉由PECVD在基板上沉積形成含氧陶瓷硬遮罩薄膜，此薄膜對低k介電質及銅具蝕刻選擇性、對電漿乾式蝕刻具抗性、並能夠藉由濕式蝕刻移除。此方法可更包含以濕式蝕刻將含氧陶瓷硬遮罩薄膜由基板移除。提供有特定之製程參數。 In one embodiment, a method of forming an oxygen-containing ceramic hard mask film on a semiconductor substrate includes: receiving a semiconductor substrate in a plasma-enhanced chemical vapor deposition (PECVD) processing chamber, and An oxygen-containing ceramic hard mask film is formed by deposition on a substrate by PECVD. The film is etch-selective to low-k dielectric and copper, resistant to plasma dry etching, and can be removed by wet etching. The method can further include removing the oxygen-containing ceramic hard mask film from the substrate by wet etching. Specific process parameters are provided.
在另一實施態樣中，部分製造的半導體元件包含半導體元件基板，及設置於基板上的含氧陶瓷硬遮罩薄膜，此薄膜對低k介電質及銅具蝕刻選擇性、對電漿乾式蝕刻具抗性、並能夠藉由濕式蝕刻移除。 In another embodiment, the partially fabricated semiconductor device includes a semiconductor device substrate, and an oxygen-containing ceramic hard mask film disposed on the substrate, the film is selective for low-k dielectric and copper etching, and is plasma-resistant. Dry etching is resistant and can be removed by wet etching.
在又一實施態樣中，用於處理半導體基板上之硬遮罩薄膜的設備包含電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)處理腔室、在處理腔室中的半導體晶圓基板的支撐物、及具有程式指令的控制器，該支撐物用於在硬遮罩沉積期間將晶圓基板托持於適當位置中。控制器的程式指令係用於下列處理：在電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)處理腔室中接收半導體晶圓基板、及藉由PECVD在基板上形成含氧陶瓷硬遮罩薄膜，此薄膜對低k介電質及銅具蝕刻選擇性、對電漿乾式蝕刻具抗性、並能夠藉由濕式蝕刻移除。此設備可更包含濕式蝕刻處理腔室、及具有用於下列處理之程式指令的控制器：接收具有含氧陶瓷硬遮罩薄膜形成於其上的半導體晶圓基板；及以濕式蝕刻將含氧陶瓷硬遮罩薄膜由基板移除。 In yet another embodiment, an apparatus for processing a hard mask film on a semiconductor substrate comprises a plasma-enhanced chemical vapor deposition (PECVD) processing chamber, a semiconductor in the processing chamber A support for the wafer substrate, and a controller having program instructions for holding the wafer substrate in place during hard mask deposition. The program instructions of the controller are used for receiving semiconductor wafer substrates in a plasma-enhanced chemical vapor deposition (PECVD) processing chamber and forming oxygen-containing ceramics on the substrate by PECVD. A hard mask film that is etch-selective for low-k dielectric and copper, resistant to plasma dry etching, and capable of being removed by wet etching. The apparatus may further comprise a wet etching processing chamber, and a controller having program instructions for: receiving a semiconductor wafer substrate having an oxygen-containing ceramic hard mask film formed thereon; and etching by wet etching The oxygen-containing ceramic hard mask film is removed from the substrate.
較佳地，在藉由濕式蝕刻化學來完成圖案化後，含氧陶瓷薄膜可輕易被移除，而不需要CMP。 Preferably, after patterning by wet etching chemistry, the oxygen-containing ceramic film can be easily removed without the need for CMP.
在某些實施例中，於後段處理中將含氧陶瓷硬遮罩薄膜(例如上述薄膜之任一者)沉積在低k介電質層上，此低k介電質例如為具 有小於約3之介電常數的介電質，例如小於約2.8者。光阻層通常係沉積於含氧陶瓷硬遮罩之上(但不一定要直接與此硬遮罩接觸，因為抗反射層可能被沉積於其間)。進行微影圖案化，其中，凹陷特徵部(貫孔及/或溝槽)被形成於介電質層中。在完成圖案化且以金屬填滿此特徵部後，藉由濕式蝕刻製程移除硬遮罩。在某些實施例中，關於用以蝕刻貫孔及/或溝槽的乾式蝕刻化學(其通常為RIE製程)，硬遮罩薄膜相對於介電質的蝕刻選擇性為至少約8：1。 In some embodiments, an oxygen-containing ceramic hard mask film (such as any of the above films) is deposited on the low-k dielectric layer in a post-processing, such as a low-k dielectric There are dielectrics having a dielectric constant less than about 3, such as less than about 2.8. The photoresist layer is typically deposited on the oxygen-containing ceramic hard mask (but does not necessarily have to be in direct contact with the hard mask because the anti-reflective layer may be deposited therebetween). A lithographic patterning is performed in which recess features (through holes and/or trenches) are formed in the dielectric layer. After the patterning is completed and the features are filled with metal, the hard mask is removed by a wet etch process. In some embodiments, with respect to dry etch chemistry (which is typically an RIE process) used to etch vias and/or trenches, the etch selectivity of the hard mask film relative to the dielectric is at least about 8:1.
在其他實施例中，在前段處理中硬遮罩薄膜(例如上述薄膜之任一者)係沉積於多晶矽層上，並用於在各種處理步驟期間保護多晶矽。在某些實施例中，硬遮罩材料未被移除而會留在所製造的元件中。 In other embodiments, a hard mask film (such as any of the above films) is deposited on the polysilicon layer during the previous processing and is used to protect the polysilicon during various processing steps. In some embodiments, the hard mask material is not removed and will remain in the fabricated component.
本發明之這些與其他的特徵及優點將參照相關圖式而在以下進行更詳細之說明。 These and other features and advantages of the present invention will be described in more detail below with reference to the accompanying drawings.
101‧‧‧金屬層(銅層) 101‧‧‧metal layer (copper layer)
103‧‧‧第一介電質層 103‧‧‧First dielectric layer
105‧‧‧擴散阻擋(材料)層 105‧‧‧Diffusion barrier (material) layer
107‧‧‧介電質擴散阻擋層 107‧‧‧Dielectric diffusion barrier
109‧‧‧第二介電質層 109‧‧‧Second dielectric layer
111‧‧‧(介電質)緩衝層 111‧‧‧(dielectric) buffer layer
113‧‧‧硬遮罩層 113‧‧‧hard mask layer
115‧‧‧第一光阻層 115‧‧‧First photoresist layer
117‧‧‧填料層 117‧‧‧Filling layer
119‧‧‧第二光阻層 119‧‧‧second photoresist layer
121‧‧‧金屬 121‧‧‧Metal
201‧‧‧單晶矽層 201‧‧‧ Single crystal layer
203‧‧‧氧化物層 203‧‧‧Oxide layer
205‧‧‧多晶矽層 205‧‧‧Polysilicon layer
207‧‧‧硬遮罩(材料)層 207‧‧‧hard mask (material) layer
209‧‧‧可灰化硬遮罩 209‧‧‧Able to harden the hard mask
211‧‧‧光阻層 211‧‧‧ photoresist layer
301~311‧‧‧步驟 301~311‧‧‧Steps
401~411‧‧‧步驟 401~411‧‧‧Steps
501~505‧‧‧步驟 501~505‧‧‧Steps
601~609‧‧‧步驟 601~609‧‧‧Steps
800‧‧‧反應器 800‧‧‧Reactor
802‧‧‧低頻射頻產生器 802‧‧‧Low Frequency RF Generator
804‧‧‧高頻射頻產生器 804‧‧‧High frequency RF generator
806‧‧‧匹配網路 806‧‧‧match network
808‧‧‧歧管 808‧‧‧Management
810‧‧‧來源氣體管線 810‧‧‧ source gas pipeline
812‧‧‧入口 812‧‧‧ entrance
814‧‧‧噴淋頭 814‧‧‧Sprinkler
816‧‧‧基板 816‧‧‧Substrate
818‧‧‧晶圓基座 818‧‧‧ Wafer pedestal
820‧‧‧加熱器區塊 820‧‧‧heater block
822‧‧‧出口 822‧‧‧Export
824‧‧‧處理腔室 824‧‧‧Processing chamber
826‧‧‧真空幫浦 826‧‧‧vacuum pump
830‧‧‧(系統)控制器 830‧‧‧(system) controller
901‧‧‧設備腔室 901‧‧‧ equipment room
903~909‧‧‧站 903~909‧‧‧ Station
911‧‧‧分度盤 911‧‧ ‧ indexing plate
1020a~1020d‧‧‧處理模組 1020a~1020d‧‧‧Processing Module
1022‧‧‧自動機器 1022‧‧‧Automatic machine
1024‧‧‧終端作用器 1024‧‧‧End effector
1026‧‧‧晶圓 1026‧‧‧ wafer
1028‧‧‧模組中心 1028‧‧‧Modular Center
1030‧‧‧空氣鎖室 1030‧‧‧Air lock room
1032‧‧‧前端自動機器 1032‧‧‧ front-end automatic machine
1034‧‧‧前開式晶圓傳送盒(FOUP) 1034‧‧‧Front open wafer transfer box (FOUP)
1036‧‧‧面部 1036‧‧‧Face
1038‧‧‧真空傳輸模組(VTM) 1038‧‧‧Vacuum Transmission Module (VTM)
1040‧‧‧大氣傳輸模組(ATM) 1040‧‧‧Atmospheric Transmission Module (ATM)
1042‧‧‧載入端口模組(LPM) 1042‧‧‧Load Port Module (LPM)
1044‧‧‧對準機 1044‧‧‧Aligning machine
1~18‧‧‧感測器 1~18‧‧‧ Sensor
t‧‧‧寬度 ‧‧‧Width
v‧‧‧寬度 v‧‧‧Width
圖1A-1K顯示使用本文中所提供之硬遮罩的元件結構的橫剖面圖，此元件結構係在半導體元件之製造中的說明性後段微影製程期間所產生。 1A-1K show cross-sectional views of an element structure using the hard mask provided herein, which is produced during an illustrative post-lithography process in the fabrication of semiconductor components.
圖2A-2E顯示使用本文中所提供之硬遮罩的元件結構的橫剖面圖，此元件結構係在半導體元件之製造中的說明性前段微影製程期間所產生。 2A-2E show cross-sectional views of an element structure using the hard mask provided herein, which is produced during an illustrative front lithography process in the fabrication of semiconductor components.
圖3係適合使用本文中所提供之硬遮罩的後段微影製程的製程流程圖。 3 is a process flow diagram of a back-end lithography process suitable for use with the hard masks provided herein.
圖4係適合使用本文中所提供之硬遮罩的前段微影製程的製程流程圖。 4 is a process flow diagram of a front lithography process suitable for use with the hard masks provided herein.
圖5係依據本文中所提供之實施例的沉積含氧陶瓷硬遮罩之方法的製程流程圖。 5 is a process flow diagram of a method of depositing an oxygen-containing ceramic hard mask in accordance with embodiments provided herein.
圖6係依據本文中所提供之實施例使用含氧陶瓷硬遮罩的範例性處理方法的製程流程圖。 6 is a process flow diagram of an exemplary processing method using an oxygen-containing ceramic hard mask in accordance with embodiments provided herein.
圖7係說明了以氧摻雜陶瓷薄膜作為硬遮罩之適當性的實驗圖。 Figure 7 is an experimental diagram illustrating the suitability of an oxygen doped ceramic film as a hard mask.
圖8係依據本發明之某些實施例之PECVD設備的示意圖，該PECVD設備能夠使用低頻(low frequency,LF)及高頻(high frequency,HF)射頻電漿來源，並能用於沉積硬遮罩薄膜。 8 is a schematic illustration of a PECVD apparatus capable of using low frequency (LF) and high frequency (HF) RF plasma sources and capable of depositing hard masks in accordance with certain embodiments of the present invention. Cover film.
圖9係依據本發明之某些實施例之多站PECVD設備的示意圖，此多站PECVD設備適合形成硬遮罩薄膜。 9 is a schematic illustration of a multi-station PECVD apparatus suitable for forming a hard mask film in accordance with certain embodiments of the present invention.
圖10描繪依據所揭露實施例之多站群集工具的實施例。 FIG. 10 depicts an embodiment of a multi-station clustering tool in accordance with the disclosed embodiments.
本發明提供用於後段及前段半導體處理應用的含氧陶瓷硬遮罩薄膜。所提供的陶瓷硬遮罩包含氧與例如為硼、磷、鍺、碳、矽、氮及氫之元素的混合物。依據本發明的硬遮罩本質通常係親水的。硼摻雜碳化物基(boron doped carbide-based)硬遮罩材料為本發明硬遮罩之一較佳物種。硼的三價本質(在其典型的鍵結狀態下帶有空的π-軌域)容易促進其網狀結構的氧化。在特定實施例中，依據本發明的含氧陶瓷硬遮罩材料至少具有5%的氧。在含氧硼摻雜碳化物基硬遮罩材料中，B：C的比例通常不超過1：1，且氧的濃度(百分比)通常受硼的濃度所限制。 The present invention provides oxygenated ceramic hard mask films for use in back and front segment semiconductor processing applications. The ceramic hard mask is provided comprising a mixture of oxygen and an element such as boron, phosphorus, ruthenium, carbon, ruthenium, nitrogen and hydrogen. The hard mask in accordance with the present invention is generally hydrophilic in nature. A boron doped carbide-based hard mask material is one of the preferred species of the hard mask of the present invention. The trivalent nature of boron (with its empty π-orbital domain in its typical bonding state) tends to promote oxidation of its network structure. In a particular embodiment, the oxygen-containing ceramic hard mask material in accordance with the present invention has at least 5% oxygen. In the oxygen-containing boron doped carbide-based hard masking material, the ratio of B:C usually does not exceed 1:1, and the concentration (percentage) of oxygen is usually limited by the concentration of boron.
可使用蝕刻化學品對含氧陶瓷硬遮罩進行濕式清潔，蝕刻化學品包含，例如，氧化劑與強酸或強鹼化合物、或水，此二者之任一者係與腐蝕抑制劑結合。相對於低k材料及銅，這些濕式清潔對於含氧陶瓷硬遮罩極具選擇性。 The oxygen-containing ceramic hard mask can be wet cleaned using an etch chemistry comprising, for example, an oxidizing agent and a strong acid or strong base compound, or water, either of which is combined with a corrosion inhibitor. These wet cleanings are extremely selective for oxygen-containing ceramic hard masks relative to low-k materials and copper.
合適的濕式清潔化學品可具有範圍由2到13的pH值，例如，某些合適的蝕刻化學品具有介於6及10之間的pH值。這些濕式清潔可在由約20℃至100℃的溫度下進行。 Suitable wet cleaning chemicals can have a pH ranging from 2 to 13, for example, some suitable etch chemistries have a pH between 6 and 10. These wet cleanings can be carried out at temperatures from about 20 ° C to 100 ° C.
氧化劑可為過氧化物來源，例如過氧化氫，其能夠在約5至50%的濃度下被使用。鹼性化合物可選自於，例如，氫氧化銨、氫 氧化四甲銨、氫氧化鉀、氫氧化鈉、羥胺類、胺類、四烷基銨氫氧化物。腐蝕抑制劑可選自於胺基酸族，其包含例如，甘胺酸或丙胺酸、***、硫醇基-***、及咪唑。 The oxidizing agent can be a source of peroxide, such as hydrogen peroxide, which can be used at a concentration of from about 5 to 50%. The basic compound may be selected from, for example, ammonium hydroxide, hydrogen Tetramethylammonium oxide, potassium hydroxide, sodium hydroxide, hydroxylamines, amines, tetraalkylammonium hydroxides. The corrosion inhibitor may be selected from the group of amino acids, which include, for example, glycine or alanine, triazole, thiol-triazole, and imidazole.
因此，本發明提供含氧陶瓷硬遮罩材料及濕式清潔，以幫助將陶瓷硬遮罩處理解決方案整合於邏輯與記憶體應用兩者之中。可修改硬遮罩的化學組成(即，將氧併入的程度)，以促進在特定之濕式蝕刻化學品中之選擇性移除，同時能保持所需之硬遮罩的薄膜特性。 Accordingly, the present invention provides oxygen-containing ceramic hard mask materials and wet cleaning to help integrate ceramic hard mask processing solutions into both logic and memory applications. The chemical composition of the hard mask (i.e., the extent to which oxygen is incorporated) can be modified to facilitate selective removal in a particular wet etch chemistry while maintaining the desired hard mask film properties.
所提供之薄膜在用於貫孔及/或溝槽蝕刻的化學品中，具有相對於介電質(例如相對於具有3.0以下，像是2.8以下、或2.4以下之介電常數的介電質)高的蝕刻選擇性。範例蝕刻化學包含使用形成於製程氣體中之電漿的反應離子蝕刻(reactive ion etching,RIE)，此製程氣體包含CxFy(例如，CF4)、惰性氣體(例如，Ar)及氧化劑(例如，O2)。可使用其他的乾式蝕刻，例如具有包含Cl2及N2之製程氣體的電漿蝕刻。在某些實施例中，可獲得至少約5：1的蝕刻選擇性，例如至少約8：1(即，硬遮罩材料的蝕刻比介電質慢至少8倍)。 The provided film has a dielectric relative to the dielectric (eg, relative to a dielectric having a dielectric constant of 3.0 or less, such as 2.8 or less, or 2.4 or less) in a chemical for via and/or trench etching. High etch selectivity. An example etch chemistry includes reactive ion etching (RIE) using a plasma formed in a process gas comprising C x F y (eg, CF 4 ), an inert gas (eg, Ar), and an oxidant ( For example, O 2 ). May use other dry etching, for example, a plasma etch comprising Cl 2 and N 2 of the process gas. In some embodiments, an etch selectivity of at least about 5:1 can be achieved, such as at least about 8: 1 (ie, the hard mask material is etched at least 8 times slower than the dielectric).
可在存有本文中所提供之曝露硬遮罩材料的情況下被蝕刻的介電質包含氧化矽、碳摻雜矽氧化物(SiCOH)、矽酸四乙酯(tetraethyl orthosilicate,TEOS)沉積的氧化物、各種矽酸鹽玻璃、氫半矽氧烷(hydrogen silsesquioxane,HSQ)、甲基半矽氧烷(methylsilsesquioxane,MSQ)、以及多孔及/或有機介電質，此多孔及/或有機介電質包括聚醯亞胺、聚降冰片烯(polynorbornenes)、苯並環丁烯(benzocyclobutene)等等。所提供之硬遮罩最有利係用於機械強度弱的有機及/或多孔介電質的圖案化，此有機及/或多孔介電質具有2.8以下(例如2.4以下)的介電常數。 The dielectric etched in the presence of the exposed hard mask material provided herein comprises yttrium oxide, carbon doped lanthanum oxide (SiCOH), tetraethyl orthosilicate (TEOS) deposited. Oxides, various tellurite glasses, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), and porous and/or organic dielectrics, porous and/or organic Electrolytes include polyimine, polynorbornenes, benzocyclobutene, and the like. The hard mask provided is most advantageously used for the patterning of organic and/or porous dielectrics having weak mechanical strength, the organic and/or porous dielectric having a dielectric constant of 2.8 or less (e.g., 2.4 or less).
通常可使用多種方法來沉積本文中所述的硬遮罩材料，該等方法包含基於化學氣相沉積(chemical vapor deposition,CVD)的方法及基於物理氣相沉積(physical vapor deposition,PVD)的方法。電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)為一種特別優良的沉積方法。合適的PECVD設備包含可由Lam Research Corporation,Fremont,CA取得的SEQUEL®及VECTOR®工 具。低頻射頻(radio frequency,RF)功率代表RF功率具有介於100kHz及2MHz之間的頻率。低頻(low frequency,LF)電漿源的典型頻率範圍係介於約100kHz到500kHz之間，例如，可使用400kHz的頻率。在硬遮罩層的沉積期間，LF功率密度的範圍通常為約0.001-1.3W/cm2，在特定實施例中，為約0.1-0.7W/cm2。高頻(high frequency,HF)功率的範圍通常為約0.001-1.3W/cm2，且在特定實施例中，為約0.2-0.28W/cm2。高頻功率代表RF功率具有大於2MHz的頻率。一般而言，HF RF頻率在約2MHz-30MHz之間的範圍內。一般所使用的HF RF值包含13.56MHz及27MHz。在某些實施例中，硬遮罩的沉積包含將LF/HF功率比設定為至少約1，像是至少約1.5者，例如，至少約2者。 A variety of methods are generally used to deposit the hard mask materials described herein, including chemical vapor deposition (CVD) based methods and physical vapor deposition (PVD) based methods. . Plasma-enhanced chemical vapor deposition (PECVD) is a particularly excellent deposition method. Suitable PECVD apparatus comprises by Lam Research Corporation, Fremont, CA, and the acquired SEQUEL ® VECTOR ® tool. The radio frequency (RF) power represents the RF power having a frequency between 100 kHz and 2 MHz. A typical low frequency (LF) plasma source has a frequency range between about 100 kHz and 500 kHz, for example, a frequency of 400 kHz can be used. During deposition of the hard mask layer, the LF power density typically ranges from about 0.001 to 1.3 W/cm 2 , and in particular embodiments from about 0.1 to 0.7 W/cm 2 . Frequency range (high frequency, HF) power is generally about 0.001-1.3W / cm 2, and, in certain embodiments, from about 0.2-0.28W / cm 2. The high frequency power represents an RF power having a frequency greater than 2 MHz. In general, the HF RF frequency is in the range of between about 2 MHz and 30 MHz. The HF RF values typically used include 13.56 MHz and 27 MHz. In some embodiments, the deposition of the hard mask comprises setting the LF/HF power ratio to at least about 1, such as at least about 1.5, for example, at least about two.
在PECVD沉積期間，一般會以範圍通常為由約1000sccm至約10000sccm的流率將反應物氣體或蒸氣供應至處理腔室，並使用範圍為由約20℃至約500℃的基板底座溫度，此基板底座溫度較佳為由約200℃至約450℃。在某些實施例中，低於約400℃(例如，由約200℃至約400℃)的溫度對於硬遮罩沉積係較佳的。壓力的範圍可為由約10mTorr至約100Torr，較佳為由約0.5Torr至5Torr。應當瞭解的是，前驅物的流率能夠根據基板及腔室尺寸的大小而改變。 During PECVD deposition, reactant gas or vapor is typically supplied to the processing chamber at a flow rate typically ranging from about 1000 sccm to about 10,000 sccm, and a substrate base temperature ranging from about 20 ° C to about 500 ° C is used, The substrate base temperature is preferably from about 200 ° C to about 450 ° C. In certain embodiments, temperatures below about 400 ° C (eg, from about 200 ° C to about 400 ° C) are preferred for hard mask deposition. The pressure may range from about 10 mTorr to about 100 Torr, preferably from about 0.5 Torr to 5 Torr. It will be appreciated that the flow rate of the precursor can vary depending on the size of the substrate and chamber.
可使用蝕刻化學品對含氧陶瓷硬遮罩進行濕式清潔，此蝕刻化學品包含，例如，氧化劑與強酸或強鹼化合物、或水，特別是熱水(例如，大於60℃，像是約100℃者)，此二者之任一者係與腐蝕抑制劑結合，腐蝕抑制劑例如為包含甘胺酸或丙胺酸、***、硫醇基-***、及咪唑的胺基酸。相對於低k材料及銅，這些濕式清潔對於含氧陶瓷硬遮罩極具選擇性。 The oxygen-containing ceramic hard mask may be wet cleaned using an etch chemistry comprising, for example, an oxidizing agent with a strong acid or a strong base compound, or water, particularly hot water (eg, greater than 60 ° C, like about Any one of 100 ° C) is combined with a corrosion inhibitor such as an amino acid containing glycine or alanine, triazole, thiol-triazole, and imidazole. These wet cleanings are extremely selective for oxygen-containing ceramic hard masks relative to low-k materials and copper.
所提供之薄膜可被用於多種硬遮罩應用中。後段處理中硬遮罩薄膜之示範用法，係藉由圖1A-1K中所示之結構及藉由圖3中所示之製程流程圖加以說明。參照圖3的說明性製程流程，此製程係藉由提供具有曝露介電質層的基板而始於操作301。基板通常為具有一或更多材料層(例如導體或介電質)的半導體(例如矽)晶圓，該等材料層係位 處於該半導體晶圓上。基板的曝露部分包含需要以貫孔及溝槽來圖案化的介電質層。本文中所提供的硬遮罩一般能用於將先前章節中所列出之多種介電質材料圖案化。使用所提供之用於將超低k(ultra low-k,ULK)介電質圖案化的硬遮罩材料係特別有利的，此ULK介電質具有2.8以下(例如2.4以下)的介電常數，並包含機械強度弱的多孔及有機介電質。如前面所說明，在許多實施例中，所提供之硬遮罩具有非常低的應力，並能顯著減少屈曲(buckling)及劣質圖案對準，其通常發生在當高應力硬遮罩材料被用來將弱機械強度的ULK介電質圖案化時。應當注意的是，在某些實施例中，機械強度較強之材料的緩衝層被用在脆弱的ULK介電質及硬遮罩之間。因此，在某些實施例中，所提供的基板具有位處於ULK材料層上的曝露緩衝層(例如機械強度較強的介電質)。例如，包含具有大於2.8之介電常數之介電質的緩衝層可位處於具有較低介電常數的機械強度較弱之介電質上。舉例來說，包含一材料的緩衝層可位處於多孔及/或有機介電質上，該材料係選自於由碳摻雜矽氧化物(SiCOH)、矽酸四乙酯(tetraethyl orthosilicate,TEOS)沉積的氧化物、各種矽酸鹽玻璃、氫半矽氧烷(hydrogen silsesquioxane,HSQ)、及甲基半矽氧烷(methylsilsesquioxane,MSQ)所組成之群組，此多孔及/或有機介電質可包含聚醯亞胺、聚降冰片烯(polynorbornenes)、苯並環丁烯(benzocyclobutene)等等。可藉由例如旋轉塗佈(spin-on)方法或PECVD來沉積ULK介電質及緩衝層介電質。在某些實施例中，係在相同的PECVD模組中沉積介電質及/或緩衝層，以及沉積於其上之硬遮罩層。對於需要用PVD模組來沉積的氮化鈦硬遮罩，這提供了額外的優勢。 The films provided can be used in a variety of hard mask applications. Exemplary use of the hard mask film in the post-processing is illustrated by the structure shown in Figures 1A-1K and by the process flow diagram shown in Figure 3. Referring to the illustrative process flow of FIG. 3, the process begins with operation 301 by providing a substrate having an exposed dielectric layer. The substrate is typically a semiconductor (eg, germanium) wafer having one or more layers of material (eg, conductors or dielectrics) that are layered On the semiconductor wafer. The exposed portion of the substrate includes a dielectric layer that needs to be patterned with vias and trenches. The hard masks provided herein can generally be used to pattern a variety of dielectric materials listed in the previous sections. It is particularly advantageous to use a hard mask material provided for patterning ultra low-k (ULK) dielectrics having a dielectric constant of 2.8 or less (eg, 2.4 or less). And contains porous and organic dielectrics with weak mechanical strength. As explained above, in many embodiments, the provided hard mask has very low stress and can significantly reduce buckling and poor pattern alignment, which typically occurs when high stress hard mask materials are used. To pattern a weak mechanical strength ULK dielectric. It should be noted that in certain embodiments, a buffer layer of a material of higher mechanical strength is used between the fragile ULK dielectric and the hard mask. Thus, in certain embodiments, the substrate provided has an exposure buffer layer (eg, a dielectric that is more mechanically strong) on the layer of ULK material. For example, a buffer layer comprising a dielectric having a dielectric constant greater than 2.8 can be on a dielectric having a lower dielectric constant and having a lower mechanical strength. For example, a buffer layer comprising a material may be on a porous and/or organic dielectric selected from the group consisting of carbon doped lanthanum oxide (SiCOH), tetraethyl orthosilicate (TEOS). a group of deposited oxides, various tellurite glasses, hydrogen silsesquioxane (HSQ), and methylsilsesquioxane (MSQ), the porous and/or organic dielectric The substance may comprise polyimine, polynorbornenes, benzocyclobutene, and the like. The ULK dielectric and the buffer layer dielectric can be deposited by, for example, a spin-on method or PECVD. In some embodiments, a dielectric and/or buffer layer is deposited in the same PECVD module, as well as a hard mask layer deposited thereon. This provides an additional advantage for a titanium nitride hard mask that needs to be deposited with a PVD module.
在操作303中，於PECVD處理腔室中，將含氧陶瓷硬遮罩材料沉積到介電質層上(或到緩衝層上，其通常亦為介電質)。接著，可選擇地沉積一或更多抗反射層，例如底部抗反射塗佈(bottom anti-reflective coating,BARC)，隨後，在操作305中將光阻沉積於硬遮罩上。應當注意的是，光阻並不一定要與硬遮罩材料直接接觸，因為通常一或更多抗反射層會位處於硬遮罩與光阻之間。接著，在操作307中，使用所沉積之硬遮罩及微影圖案化(lithographic patterning)在介電 質層中蝕刻貫孔及/或溝槽。合適之蝕刻包含先前章節中所述的RIE，其中，在存在具有蝕刻之高蝕刻選擇性的曝露硬遮罩的情況下，蝕刻介電質材料。 In operation 303, an oxygen-containing ceramic hard mask material is deposited onto the dielectric layer (or onto the buffer layer, which is also typically dielectric) in a PECVD processing chamber. Next, one or more anti-reflective layers, such as a bottom anti-reflective coating (BARC), are optionally deposited, and then, in operation 305, a photoresist is deposited on the hard mask. It should be noted that the photoresist does not have to be in direct contact with the hard mask material, as typically one or more of the anti-reflective layers will be positioned between the hard mask and the photoresist. Next, in operation 307, the deposited hard mask and lithographic patterning are used in the dielectric. Through holes and/or grooves are etched into the layer. Suitable etchings include the RIE described in the previous section, wherein the dielectric material is etched in the presence of an exposed hard mask having a high etch selectivity of etching.
可使用多種微影方案來形成所需之凹陷特徵部的圖案，該等微影方案可包含多個光阻層之沉積與移除、填料層之沉積等等。這些微影方案在所屬技術領域中係為人所熟知，且將不再詳細描述。使用先定義溝槽而接著形成局部貫孔的方案，如圖1A-1K中所繪示。然而，應當瞭解的是，後段處理可使用多種其他方案。在操作309中，於形成貫孔及/或溝槽後，以金屬(例如電沉積的銅或其合金)填滿貫孔及/或溝槽，而在操作311中，係藉由濕式蝕刻來移除硬遮罩薄膜。在某些實施例中，對於硬遮罩的移除，含有過氧化物(像是含有過氧化氫的酸性漿液，例如食人魚溶液(piranha solution))的濕式蝕刻化學品係較佳的。在其他實施例中，可以水，特別是熱水(例如，高於60℃者，例如約100℃者)進行濕式蝕刻。在任一情況下，濕式蝕刻化學品亦可以包含腐蝕抑制劑，以防止在操作311期間接觸到濕式蝕刻化學品的金屬(例如銅)被腐蝕。在某些情況下，以水作為濕式蝕刻劑係較佳的，因為腐蝕抑制劑不會被水降解到其能夠存在於更具活性之酸性或鹼性濕式蝕刻化學品中的程度。 A variety of lithography schemes can be used to form the desired pattern of recessed features, which can include deposition and removal of multiple photoresist layers, deposition of filler layers, and the like. These lithography solutions are well known in the art and will not be described in detail. A scheme of defining a trench first and then forming a local via is used, as illustrated in Figures 1A-1K. However, it should be understood that a variety of other approaches can be used for the post-processing. In operation 309, after the via holes and/or trenches are formed, the vias and/or trenches are filled with a metal (eg, electrodeposited copper or an alloy thereof), and in operation 311, by wet etching. To remove the hard mask film. In some embodiments, for the removal of the hard mask, a wet etch chemistry containing a peroxide such as an acidic slurry containing hydrogen peroxide, such as a piranha solution, is preferred. In other embodiments, the wet etching can be performed with water, particularly hot water (eg, those above 60 °C, such as about 100 °C). In either case, the wet etch chemistry can also include a corrosion inhibitor to prevent corrosion of the metal (eg, copper) that is exposed to the wet etch chemistry during operation 311. In some cases, the use of water as a wet etchant is preferred because the corrosion inhibitor is not degraded by water to the extent that it can be present in more active acidic or basic wet etch chemistries.
圖1A-1K依據一說明性處理方案顯示在後段處理期間的部分製造之半導體基板的橫剖面示意圖。圖1A顯示部分之半導體基板(下方的矽層及主動元件未顯示)，此部分之半導體基板具有嵌於第一介電質層103(例如ULK介電質)中的銅層101，其中，擴散阻擋層105(例如，包含Ta、Ti、W、TaNx、TiNx、WNx、或其組合)位處於介電質與銅之間的界面。介電質擴散阻擋層(亦稱為蝕刻停止層)107，例如氮化矽或氮摻雜矽碳化物層，係位在銅101及介電質103的頂部上。第二介電質層109(例如旋轉塗佈或以PECVD沉積的ULK介電質)位處於介電質擴散阻擋層107的頂部上。由於介電質層109可為弱機械強度者且在硬遮罩沉積期間會受到傷害，因此會將機械強度較強的介電質緩衝層111(例如，TEOS介電質或碳摻雜矽氧化物(SiCOH))沉積至該層109上。藉由PECVD將包含本文中所述之高硬度材料的硬遮罩層113沉積到緩 衝層111上。不同於介電質擴散阻擋層107，含氧陶瓷硬遮罩層113係沉積於不包含曝露金屬的表面上。光阻層115係藉由旋轉塗佈方法而沉積於硬遮罩113上。通常，一或更多抗反射層係被直接沉積在硬遮罩與光阻之間。這些層未被示出以保持圖面清晰。 1A-1K are schematic cross-sectional views showing a partially fabricated semiconductor substrate during post processing, in accordance with an illustrative processing scheme. 1A shows a portion of a semiconductor substrate (the underlying germanium layer and active components are not shown) having a copper layer 101 embedded in a first dielectric layer 103 (eg, a ULK dielectric), wherein diffusion position interface between dielectric layer 105 and the copper in the blocking (e.g., comprising Ta, Ti, W, TaN x , TiN x, WN x, or a combination thereof). A dielectric diffusion barrier layer (also referred to as an etch stop layer) 107, such as a tantalum nitride or nitrogen doped yttrium carbide layer, is on top of copper 101 and dielectric 103. A second dielectric layer 109 (eg, spin coated or ULCVD dielectric deposited by PECVD) is on top of the dielectric diffusion barrier layer 107. Since the dielectric layer 109 can be weakly mechanically strong and can be damaged during the deposition of the hard mask, the dielectric buffer layer 111 with strong mechanical strength (for example, TEOS dielectric or carbon doped yttrium oxide) A substance (SiCOH) is deposited onto the layer 109. A hard mask layer 113 comprising the high hardness material described herein is deposited onto the buffer layer 111 by PECVD. Unlike the dielectric diffusion barrier layer 107, the oxygen-containing ceramic hard mask layer 113 is deposited on a surface that does not contain exposed metal. The photoresist layer 115 is deposited on the hard mask 113 by a spin coating method. Typically, one or more anti-reflective layers are deposited directly between the hard mask and the photoresist. These layers are not shown to keep the picture clear.
在光阻115已沉積後，使用標準微影技術將其圖案化以形成具有寬度t的開口，此開口將用以形成之後的溝槽。具有圖案化之光阻層115的所得到之結構係顯示於圖1B中。接著，位處於已移除之光阻下方的硬遮罩層113被打開(蝕刻)而形成曝露介電質111的圖案，如圖1C中所示。剩下的硬遮罩將用於在光阻移除及後續介電質蝕刻的期間保護介電質。接著，將光阻層115由此結構移除(例如，藉由灰化)，而形成了具有曝露之圖案化硬遮罩113的結構。在此階段，用以形成貫孔的圖案化係開始進行。為了使貫孔圖案化，係將可包含易移除介電質(例如HSQ或MSQ)的填料層117沉積於此結構之表面上而填滿硬遮罩中的開口，如圖1E中所示。接著，將第二光阻層119沉積在填料層117之上(於其間具有可選的抗反射層)，以形成圖1F中所示之結構。接著將光阻119圖案化以形成具有寬度v的開口，此開口將用於貫孔之形成，如結構1G中所示。接著，將在圖案化之光阻下方的硬遮罩移除，並在介電質109中部份蝕刻出貫孔，例如，使用RIE。將光阻119以及填料層117移除，而形成具有經部分蝕刻之貫孔及經定義之溝槽的結構，如圖1H中所示。接著，持續蝕刻介電質層111及109直到貫孔到達蝕刻停止層107，此蝕刻停止層隨即被蝕穿，而使在此貫孔底部的金屬層101曝露出來，如圖1I中所示。接著藉由PVD來保形沉積擴散阻擋材料層105，以在凹陷特徵部內及場區中為基板形成內襯。緊接著，以金屬121(例如，電沉積的銅或其合金)將此凹陷特徵部填滿，其通常具有一些過覆蓋層(overburden)在場中，而提供了圖1J中所示的結構。接著，將金屬過覆蓋層、擴散阻擋材料105、硬遮罩層113、及介電質緩衝層111由此結構的場區移除，而形成具有位處於低k介電質層109中之金屬內連線(interconnect)的部分製造元件，如圖1K中所示。在其他處理方案中，將不會移除緩衝層111而使其保留於基板上。 After the photoresist 115 has been deposited, it is patterned using standard lithography techniques to form an opening having a width t that will be used to form the subsequent trench. The resulting structure with patterned photoresist layer 115 is shown in Figure 1B. Next, the hard mask layer 113 under the removed photoresist is opened (etched) to form a pattern of exposed dielectric 111, as shown in FIG. 1C. The remaining hard mask will be used to protect the dielectric during photoresist removal and subsequent dielectric etching. Next, the photoresist layer 115 is removed from the structure (eg, by ashing) to form a structure having the exposed patterned hard mask 113. At this stage, the patterning system used to form the through holes begins. To pattern the vias, a fill layer 117, which may include a removable dielectric (eg, HSQ or MSQ), is deposited on the surface of the structure to fill the openings in the hard mask, as shown in FIG. 1E. . Next, a second photoresist layer 119 is deposited over the filler layer 117 (with an optional anti-reflective layer therebetween) to form the structure shown in FIG. 1F. The photoresist 119 is then patterned to form an opening having a width v that will be used for the formation of the via, as shown in structure 1G. Next, the hard mask under the patterned photoresist is removed and the vias are partially etched in the dielectric 109, for example, using RIE. The photoresist 119 and the filler layer 117 are removed to form a structure having partially etched vias and defined trenches, as shown in FIG. 1H. Next, the dielectric layers 111 and 109 are continuously etched until the via reaches the etch stop layer 107, and the etch stop layer is then etched away, thereby exposing the metal layer 101 at the bottom of the via, as shown in FIG. The diffusion barrier material layer 105 is then conformally deposited by PVD to form a liner for the substrate within the recess features and in the field regions. Next, the recessed features are filled with metal 121 (e.g., electrodeposited copper or alloys thereof), which typically has some overburden in the field, providing the structure shown in Figure 1J. Next, the metal overburden layer, the diffusion barrier material 105, the hard mask layer 113, and the dielectric buffer layer 111 are removed from the field region of the structure to form a metal having a position in the low-k dielectric layer 109. Part of the manufacturing component of the interconnect, as shown in Figure 1K. In other processing schemes, the buffer layer 111 will not be removed and left on the substrate.
如下面的進一步描述，依據於本發明的含氧陶瓷硬遮罩 之移除係藉由濕式蝕刻來完成，而不需要化學機械研磨(chemical mechanical planarization,CMP)。 As described further below, an oxygen-containing ceramic hard mask in accordance with the present invention The removal is done by wet etching without the need for chemical mechanical planarization (CMP).
包含部分貫孔之形成的處理方案，如圖1A-1K中所示，說明了低k介電質的一種可能之圖案化方案。本文中所提供之硬遮罩材料可被用於多種其他處理方案中，這些其他處理方案包含先貫孔(via-first)及先溝槽(trench-first)方案二者。 A processing scheme involving the formation of partial vias, as shown in Figures 1A-1K, illustrates one possible patterning scheme for low-k dielectrics. The hard mask materials provided herein can be used in a variety of other processing schemes, including both via-first and trench-first schemes.
所提供之含氧陶瓷硬遮罩的另一說明性用法係在前段處理期間保護多晶矽。在主動元件(例如電晶體)的形成期間，多晶矽被廣泛用在半導體晶圓上。在某些實施例中，所提供之含氧陶瓷硬遮罩材料係被沉積至多晶矽上，並在用於主動元件製造中的各種處理操作期間，用以保護多晶矽。值得注意的是，在許多實施例中的前段處理中，所提供之硬遮罩層並未被犧牲而保留於最終元件中，且係與多晶矽相接觸。 Another illustrative use of the oxygen-containing ceramic hard mask provided is to protect the polysilicon during the pre-treatment. Polycrystalline germanium is widely used on semiconductor wafers during the formation of active components such as transistors. In certain embodiments, the provided oxygen-containing ceramic hard mask material is deposited onto the polysilicon and used to protect the polysilicon during various processing operations used in the fabrication of active components. It is noted that in the front-end processing of many embodiments, the provided hard mask layer is not sacrificed but remains in the final element and is in contact with the polysilicon.
說明性的前段處理方案係顯示於圖4之處理流程圖中，並藉由圖2A-2E中所示之部分製造結構的橫剖面示意圖作進一步說明。參照圖4，此製程起始於操作401，操作401提供基板，此基板具有位處於氧化物(例如氧化矽、氧化鉿等等)層上方的多晶矽之曝露層。在其他實施例中，多晶矽可位處於不同的主動層之上。氧化物通常係位處於單晶矽層上。為了將氧化物及多晶矽層圖案化，二硬遮罩層被沉積於多晶矽層上。將第一硬遮罩直接沉積至多晶矽層上，且此第一硬遮罩係乃如本文中所述的含氧陶瓷硬遮罩，如操作403中所示。藉由CVD技術來沉積硬遮罩，較佳係藉由PECVD來沉積，如本文中進一步所述。接著，在操作405中，將可灰化硬遮罩(例如，實質上由碳所組成的硬遮罩(具有可選擇存在的氫))沉積在第一硬遮罩上方。亦可藉由CVD技術，例如藉由使用烴前驅物的PECVD沉積，而將可灰化硬遮罩沉積。接著，將光阻層沉積在可灰化硬遮罩上，並依所需將光阻圖案化，如操作407中所示。可選擇將一或更多抗反射層沉積於可灰化硬遮罩及光阻之間，但該等抗反射層並未被顯示以保持圖面清晰。具有未 圖案化光阻的說明性結構係描繪於圖2A中，其中，層201為單晶矽層。位處於矽層201上的層203為氧化物層。位於氧化物層203之頂部上的層205為多晶矽層。本文中所述的硬遮罩材料207直接位在多晶矽205之頂部上，而可灰化硬遮罩(例如碳硬遮罩)209位處於第一硬遮罩層207之上。光阻層211位處於可灰化硬遮罩209之上(在其間的可選之抗反射層未被顯示)。在光阻圖案化後所得到的此結構係顯示於圖2B中，圖2B說明了二個位置的光阻被移除，而留下中間的部分。 An illustrative front stage treatment scheme is shown in the process flow diagram of Figure 4 and is further illustrated by a cross-sectional schematic view of a portion of the fabrication structure illustrated in Figures 2A-2E. Referring to Figure 4, the process begins at operation 401, which provides a substrate having an exposed layer of polycrystalline germanium over a layer of oxide (e.g., yttria, yttria, etc.). In other embodiments, the polysilicon can be positioned on top of different active layers. The oxide is usually in the order of a single crystal layer. In order to pattern the oxide and polysilicon layers, a two hard mask layer is deposited on the polysilicon layer. The first hard mask is deposited directly onto the polysilicon layer, and this first hard mask is an oxygen-containing ceramic hard mask as described herein, as shown in operation 403. The hard mask is deposited by CVD techniques, preferably by PECVD, as further described herein. Next, in operation 405, an ashable hard mask (eg, a hard mask consisting essentially of carbon (with optionally present hydrogen)) is deposited over the first hard mask. The ashable hard mask can also be deposited by CVD techniques, such as by PECVD deposition using a hydrocarbon precursor. Next, a photoresist layer is deposited over the ashable hard mask and the photoresist is patterned as desired, as shown in operation 407. One or more anti-reflective layers may optionally be deposited between the ashable hard mask and the photoresist, but the anti-reflective layers are not shown to keep the surface clear. Have not An illustrative structure of the patterned photoresist is depicted in Figure 2A, wherein layer 201 is a single crystal germanium layer. The layer 203 on the germanium layer 201 is an oxide layer. Layer 205 on top of oxide layer 203 is a polysilicon layer. The hard mask material 207 described herein is directly on top of the polysilicon 205, while the ashable hard mask (e.g., carbon hard mask) 209 is over the first hard mask layer 207. The photoresist layer 211 is over the ashable hard mask 209 (the optional anti-reflective layer therebetween is not shown). This structure obtained after photoresist patterning is shown in Fig. 2B, which illustrates that the photoresist at two locations is removed leaving the middle portion.
再參照圖4，接下來的操作409中的製程，係在多晶矽與氧化物層中使用圖案化用之可灰化硬遮罩來蝕刻所需圖案。此乃由結構2C-2E所描繪。在結構2C中，可灰化硬遮罩層209於光阻圖案化後曝露的部分被打開(蝕刻)。接著，將光阻211完全移除，且第一硬遮罩層207、多晶矽層205、及氧化物層203未被可灰化硬遮罩層209所保護的部分均被蝕刻，而提供圖2D中所示之結構。 Referring again to FIG. 4, the process in the next operation 409 is to etch the desired pattern using a patternable ashable hard mask in the polysilicon and oxide layers. This is depicted by structure 2C-2E. In structure 2C, the portion of the ashable hard mask layer 209 that is exposed after the photoresist patterning is opened (etched). Then, the photoresist 211 is completely removed, and the portions of the first hard mask layer 207, the polysilicon layer 205, and the oxide layer 203 that are not protected by the grayable hard mask layer 209 are all etched, and FIG. 2D is provided. The structure shown in .
再參照圖4，在操作411中，可例如藉由氧電漿處理將可灰化硬遮罩移除，同時在多晶矽層上留下第一含氧陶瓷硬遮罩層。所得到的結構係顯示於圖2E中。在後續的前段處理期間，可以保留硬遮罩層207，且此硬遮罩層207能用於在各種後續操作的期間(例如在將摻雜物植入到結晶矽中的期間)保護多晶矽。應當注意的是，在所述處理序列中的硬遮罩材料並不執行實際的遮蔽(其由可灰化硬遮罩209完成)，而主要係用於保護多晶矽。取決於整合方案，在後續的前段操作中，例如在清潔處理中的乾式或濕式蝕刻期間、或在被執行用來定義閘極的氧化物蝕刻期間，硬遮罩207可用於遮蔽。硬遮罩材料最後可由最終元件移除，或可保留在元件中，此乃取決於所使用之整合方案。 Referring again to FIG. 4, in operation 411, the ashable hard mask can be removed, for example, by oxygen plasma treatment while leaving a first oxygen-containing ceramic hard mask layer on the polysilicon layer. The resulting structure is shown in Figure 2E. During the subsequent front-end processing, the hard mask layer 207 may be retained, and this hard mask layer 207 can be used to protect the polysilicon during various subsequent operations, such as during implantation of dopants into the crystalline germanium. It should be noted that the hard mask material in the processing sequence does not perform the actual masking (which is done by the ashable hard mask 209), but is primarily used to protect the polysilicon. Depending on the integration scheme, the hard mask 207 can be used for shadowing in subsequent front-end operations, such as during dry or wet etching in a cleaning process, or during an oxide etch that is performed to define a gate. The hard mask material may ultimately be removed by the final component or may remain in the component, depending on the integration scheme used.
上述的後段與前段應用係供作示例性序列，且應當瞭解的是，所提供的材料可被用於需要高硬度材料來保護下方層的各種其他製程中。 The latter and previous applications are provided as exemplary sequences, and it should be understood that the materials provided can be used in a variety of other processes that require high hardness materials to protect the underlying layers.
現將詳細說明適當含氧陶瓷硬遮罩的沉積與移除。 The deposition and removal of a suitable oxygenated ceramic hard mask will now be described in detail.
在各種實施例中，係藉由使用PECVD設備的沉積處理來 提供含氧陶瓷硬遮罩薄膜。適當的沉積製程包含三種反應氣體：C2H2、CO2、及B2H6，以及載體氣體He。C2H2及B2H6形成硼碳化物薄膜。在示例性製程中，總反應物流量的數量級可為10000sccm，其大多為He。對於基材(未氧化薄膜)，相對於總流量的前驅物百分比可為：He/C2H2/CO2/B2H6=86.5/10.8/0.0/2.7。根據拉塞福背向散射質譜分析法(Rutherford Backscattering Spectrometry,RBS)的量測，此種薄膜具有C/H/B=47.7/32.7/19.6之組成、並具有1.21原子/cm3的密度。可修改基材薄膜以形成依據於本發明的含氧陶瓷硬遮罩薄膜。在特定實施例中，依據於本發明的含氧陶瓷硬遮罩材料具有至少5%的氧。在含氧之硼摻雜碳化物基硬遮罩材料中，B：C的比例通常不超過1：1，而氧的濃度(百分比)通常受硼的濃度所限制。 In various embodiments, an oxygen-containing ceramic hard mask film is provided by a deposition process using a PECVD apparatus. A suitable deposition process comprises three reactive gases: C 2 H 2 , CO 2 , and B 2 H 6 , and a carrier gas He. C 2 H 2 and B 2 H 6 form a boron carbide film. In an exemplary process, the total reactant flow rate can be on the order of 10,000 sccm, which is mostly He. For the substrate (unoxidized film), the percentage of precursor relative to the total flow rate can be: He/C 2 H 2 /CO 2 /B 2 H 6 =86.5/10.8/0.0/2.7. According to the measurement of Rutherford Backscattering Spectrometry (RBS), the film had a composition of C/H/B = 47.7/32.7/19.6 and had a density of 1.21 atoms/cm 3 . The substrate film can be modified to form an oxygen-containing ceramic hard mask film in accordance with the present invention. In a particular embodiment, the oxygen-containing ceramic hard mask material in accordance with the present invention has at least 5% oxygen. In oxygen-containing boron doped carbide-based hard mask materials, the ratio of B:C usually does not exceed 1:1, and the concentration (percentage) of oxygen is generally limited by the concentration of boron.
藉由將氧化劑(例如CO2)添加到製程氣體流來提供氧化作用。舉例來說，適當的製程氣體可包含相對於總製程氣體流的下列前驅物百分比：約He 80-83%/C2H2 10-11%/CO2 5-8%/B2H6 2-3%；例如，約He 82%/C2H2 10.5%/CO2 5%/B2H6 2.5%；或例如He 80%/C2H2 10%/CO2 7.5%/B2H6 2.5%。 By an oxidizing agent (e.g. CO 2) added to the process gas stream to provide oxidation. For example, appropriate process gas may comprise a percentage of the total of the following precursor process gas flow: about He 80-83% / C 2 H 2 10-11% / CO 2 5-8% / B 2 H 6 2 -3%; for example, about He 82% / C 2 H 2 10.5% / CO 2 5% / B 2 H 6 2.5%; or for example He 80% / C 2 H 2 10% / CO 2 7.5% / B 2 H 6 2.5%.
可使用蝕刻化學品對含氧陶瓷硬遮罩進行濕式清潔，蝕刻化學品包含，例如，氧化劑及強酸或強鹼化合物、或水，特別是熱水(例如，大於60℃，例如約100℃者)，此二者之任一者係與腐蝕抑制劑結合。在某些實施例中，含有過氧化物(像是含有過氧化氫的酸性漿液，例如食人魚溶液(piranha solution))的濕式蝕刻化學品對於硬遮罩之移除係較佳的。在其他實施例中，可以水來進行濕式蝕刻，特別是熱水(例如，大於60℃，例如約100℃者)。在任一種情況下，濕式蝕刻化學品亦可包含腐蝕抑制劑，以防止在操作311期間接觸到濕式蝕刻化學品的金屬(例如銅)被腐蝕。在某些情況下，以水作為濕式蝕刻劑係較佳的，因為腐蝕抑制劑不會被水降解到其能夠存在於更具活性之酸性或鹼性濕式蝕刻化學品中的程度。相對於低k材料及銅，這些濕式清潔對於含氧陶瓷硬遮罩極具選擇性。 The oxygen-containing ceramic hard mask may be wet cleaned using an etch chemistry comprising, for example, an oxidizing agent and a strong acid or strong base compound, or water, particularly hot water (eg, greater than 60 ° C, eg, about 100 ° C) Any one of them is combined with a corrosion inhibitor. In certain embodiments, a wet etch chemistry containing a peroxide such as an acidic slurry containing hydrogen peroxide, such as a piranha solution, is preferred for hard mask removal. In other embodiments, wet etching may be performed with water, particularly hot water (eg, greater than 60 ° C, such as about 100 ° C). In either case, the wet etch chemistry can also include a corrosion inhibitor to prevent corrosion of the metal (eg, copper) that is exposed to the wet etch chemistry during operation 311. In some cases, the use of water as a wet etchant is preferred because the corrosion inhibitor is not degraded by water to the extent that it can be present in more active acidic or basic wet etch chemistries. These wet cleanings are extremely selective for oxygen-containing ceramic hard masks relative to low-k materials and copper.
如下表中所示，隨著添加到製程之CO2的量增加，所產生之薄膜中氧的濃度增加，於在濕式化學品中蝕刻材料的方法中，存 有根本的改變。 As shown in Table, with the amount added to the process of CO 2 increases, the oxygen concentration in the film arising, in a wet chemical method of etching material, there is a fundamental change.
雖然本發明並不受限於任何特定的作用原理，但一般相信可以是下列機制： Although the invention is not limited to any particular mechanism of action, it is generally believed to be the following mechanism:
(1)CO2為一種弱氧化劑，其依據一般形式為：CO2→CO+½ O2的吸熱反應而在電漿中分解。 (1) CO 2 is a weak oxidant which decomposes in the plasma according to the endothermic reaction of the general form: CO 2 →CO+1⁄2 O 2 .
(2)在沉積製程期間，所產生的氧自由基會攻擊薄膜表面上的碳、硼、或氫活性位置。 (2) During the deposition process, the generated oxygen radicals attack the carbon, boron, or hydrogen active sites on the surface of the film.
(3)碳活性位置的氧化容易產生CO，其在大多數的業界用電漿系統中為非常穩定的氣體；因此，在所沉積薄膜中的一些碳將會被蝕刻掉。 (3) Oxidation of carbon active sites is prone to CO, which is a very stable gas in most industrial plasma systems; therefore, some of the carbon in the deposited film will be etched away.
(4)硼活性位置的氧化容易產生B-OH基團(如硼酸H3BO3或B(OH)3中所見者)，其係一種固體並將會保留在薄膜中。 (4) Oxidation of the boron active sites readily produces B-OH groups (as seen in boric acid H 3 BO 3 or B(OH) 3 ), which are a solid and will remain in the film.
(5)氫活性位置的氧化將產生不穩定的氫氧根或水，其可能會被離子化而進一步將其他的碳或硼活性位置氧化。 (5) Oxidation of the hydrogen active site will result in unstable hydroxide or water which may be ionized to further oxidize other carbon or boron active sites.
綜上所述，CO2容易將部分的碳及氫移除，而在同時將 硼氧化。對於給定的製程，添加更多CO2通常意味更多氧化將會發生，直到到達飽和。假設此製程遠低於飽和，一般相信，7.5%(中等氧摻雜)的製程應具有比5%(低氧摻雜)的製程還多的B-OH。在高溫下薄膜變得更加水溶性的觀測支持這個結論，應注意硼酸表現出了類似的行為。在硫酸/過氧化氫溶液中蝕刻速率的降低同樣意味著更多的硼活性位置被氧化，也因此，對強氧化劑的曝露具有有限效果。 As described above, CO 2 is easy to remove part of the carbon and hydrogen, while at the same time the boron oxide. For a given process, adding more CO 2 usually means that more oxidation will occur until saturation is reached. Assuming that this process is much lower than saturation, it is generally believed that a 7.5% (medium oxygen doping) process should have more B-OH than a 5% (low oxygen doping) process. Observations that the film becomes more water soluble at elevated temperatures support this conclusion, and it should be noted that boric acid exhibits similar behavior. A reduction in the etch rate in the sulfuric acid/hydrogen peroxide solution also means that more boron active sites are oxidized and, therefore, have a limited effect on the exposure of strong oxidizing agents.
含氧陶瓷硬遮罩薄膜之形成的示例性製程流程圖係顯示於圖5中。在操作501中，將半導體基板(例如，具有曝露之介電質層或曝露之多晶矽層的基板)提供至PECVD處理腔室中。PECVD處理腔室包含用於前驅物之引入的入口、及電漿產生器。在某些實施例中，可使用雙頻RF電漿產生器，其具有HF及LF產生器零件。 An exemplary process flow diagram for the formation of an oxygen-containing ceramic hard mask film is shown in FIG. In operation 501, a semiconductor substrate (eg, a substrate having an exposed dielectric layer or an exposed polysilicon layer) is provided into the PECVD processing chamber. The PECVD processing chamber contains an inlet for the introduction of the precursor, and a plasma generator. In some embodiments, a dual frequency RF plasma generator can be used with HF and LF generator parts.
將含氧硬遮罩薄膜形成於基板上，其中，沉積處理包含使製程氣體流至腔室中(操作503)並形成電漿。適當的製程氣體流包含使包括用於所產生之含氧陶瓷硬遮罩薄膜中元素之前驅物及載體氣體的製程氣體流入，所產生之含氧陶瓷硬遮罩薄膜對低k介電質及銅具蝕刻選擇性、對電漿乾式蝕刻具抗性、並能夠藉由濕式蝕刻移除。舉例來說，除了載體氣體外，製程氣體可包括含烴前驅物、含氧前驅物、含硼前驅物，像是C2H2/CO2/B2H6/He。形成電漿以將含氧陶瓷硬遮罩薄膜沉積於基板上(操作505)。在一範例中，使用HF RF頻率為約13.56MHz且LF RF頻率為約400kHz的雙頻電漿。在此範例中，HF功率密度為約0.04-0.2W/cm2，而LF功率密度為約0.17-0.6W/cm2。 An oxygen-containing hard mask film is formed on the substrate, wherein the depositing process includes flowing a process gas into the chamber (operation 503) and forming a plasma. A suitable process gas stream comprises flowing a process gas comprising element precursors and carrier gases for use in the resulting oxygen-containing ceramic hard mask film, resulting in an oxygen-containing ceramic hard mask film for low-k dielectrics and Copper is etch selective, resistant to plasma dry etching, and can be removed by wet etching. For example, in addition to the carrier gas, the process gas can include a hydrocarbon-containing precursor, an oxygen-containing precursor, a boron-containing precursor, such as C 2 H 2 /CO 2 /B 2 H 6 /He. A plasma is formed to deposit an oxygen-containing ceramic hard mask film on the substrate (operation 505). In one example, a dual frequency plasma having an HF RF frequency of about 13.56 MHz and a LF RF frequency of about 400 kHz is used. In this example, the HF power density is about 0.04-0.2 W/cm 2 and the LF power density is about 0.17-0.6 W/cm 2 .
參照圖6，其描述在後段處理中使用含氧陶瓷硬遮罩的示例性製程流程。此製程起始於操作601，在操作601中於PECVD處理腔室中提供包含曝露之介電質層的半導體基板。此介電質層可為，例如，超低k介電質層(例如，具有介電常數小於約2.8，像是小於約2.4者)或具有較高介電常數的緩衝介電質層。 Referring to Figure 6, an exemplary process flow for using an oxygen-containing ceramic hard mask in a post-stage process is described. The process begins at operation 601 where a semiconductor substrate comprising an exposed dielectric layer is provided in a PECVD processing chamber. The dielectric layer can be, for example, an ultra low k dielectric layer (e.g., having a dielectric constant less than about 2.8, such as less than about 2.4) or a buffered dielectric layer having a higher dielectric constant.
在操作603中，對低k介電質及銅具蝕刻選擇性、對電漿乾式蝕刻具抗性、並能夠藉由濕式蝕刻移除的含氧陶瓷硬遮罩薄膜被沉積於曝露之介電質上。藉由使包含適當前驅物的製程氣體流到處理腔室中並形成電漿來進行此沉積。在某些實施例中，當LF電漿的功率 密度大於HF電漿的功率密度時能得到特別好的薄膜參數，例如，在LF/HF功率比至少為約1.5時，像是至少為約2時。 In operation 603, an oxygen-containing ceramic hard mask film that is resistant to low-k dielectric and copper etch selectivity, resistant to plasma dry etching, and capable of being removed by wet etching is deposited on the exposure layer. Electrical quality. This deposition is carried out by flowing a process gas containing the appropriate precursor into the processing chamber and forming a plasma. In some embodiments, when the power of the LF plasma Particularly good film parameters are obtained when the density is greater than the power density of the HF plasma, for example, when the LF/HF power ratio is at least about 1.5, such as at least about 2.
在薄膜已被沉積後，於操作605中，將介電質圖案化以形成溝槽及/或貫孔，舉例來說，如參照圖1A-1K而描述者。含氧陶瓷硬遮罩薄膜在利用RIE的介電質之乾式蝕刻期間能用作硬遮罩。在貫孔及/或溝槽已於介電質中形成後，於操作607中以金屬將貫孔及/或溝槽填滿。接著，在操作609中係藉由濕式蝕刻來移除含氧陶瓷硬遮罩而無須CMP。 After the film has been deposited, in operation 605, the dielectric is patterned to form trenches and/or vias, for example, as described with reference to Figures 1A-1K. The oxygen-containing ceramic hard mask film can be used as a hard mask during dry etching of a dielectric using RIE. After the vias and/or trenches have been formed in the dielectric, the vias and/or trenches are filled with metal in operation 607. Next, in operation 609, the oxygen-containing ceramic hard mask is removed by wet etching without CMP.
通常可以在不同類型的設備中沉積本文中所述之硬遮罩材料，這些設備包含CVD及PVD設備。在一較佳實施例中，此設備係可包含HFRF及LFRF功率來源的PECVD設備。適當設備的範例包含SEQUEL®及VECTOR®工具，其可由Lam Research Corporation,Fremont,CA購得。 The hard mask materials described herein can typically be deposited in different types of equipment, including CVD and PVD equipment. In a preferred embodiment, the device is a PECVD device that can include HFRF and LFRF power sources. Examples of suitable apparatus include SEQUEL ® and VECTOR ® tool by Lam Research Corporation, Fremont, CA available.
一般而言，此設備會包含一或更多腔室或「反應器」(有時包括多個站)，其能容納一或更多晶圓並適合處理晶圓。每一腔室可容納一或更多晶圓以供處理。此一或更多腔室將晶圓保持在限定的一或多個位置中(在該位置內具有或不具有運動，例如，轉動、振動、或其他攪動)。在某些實施例中，會在硬遮罩層沉積期間，於反應器內將正在進行此製程的晶圓由一站轉移到另一站。當在製程中時，每一晶圓係被基座、晶圓夾盤及/或其他的晶圓托持設備托持於特定位置。對於會在其中加熱晶圓的操作，這些設備可包含加熱器，例如加熱盤。 In general, the device will contain one or more chambers or "reactors" (sometimes including multiple stations) that can accommodate one or more wafers and are suitable for processing wafers. Each chamber can hold one or more wafers for processing. The one or more chambers hold the wafer in a defined position (with or without motion, such as rotation, vibration, or other agitation). In some embodiments, wafers undergoing this process are transferred from one station to another within the reactor during deposition of the hard mask layer. Each wafer is held in a specific location by the susceptor, wafer chuck, and/or other wafer holding device while in the process. For operations in which the wafer will be heated, these devices may include a heater, such as a heating plate.
圖8提供描繪了適當的PECVD反應器之各種反應器零件的簡易方塊圖，此PECVD反應器係配置來實施本發明。如圖所示，反應器800包含處理腔室824，此處理腔室824將反應器的其他零件包圍起來，並用於容納由電容式系統所產生的電漿，此電容式系統包含與接地之加熱器區塊820協同運作的噴淋頭814。高頻RF產生器804及低頻RF產生器802係與匹配網路806相連接，而匹配網路806又與噴淋頭814相連接。 Figure 8 provides a simplified block diagram depicting various reactor components of a suitable PECVD reactor configured to practice the present invention. As shown, reactor 800 includes a processing chamber 824 that encloses other components of the reactor and is used to house the plasma generated by the capacitive system, which includes heating with ground. The block 820 cooperates with the showerhead 814. The high frequency RF generator 804 and the low frequency RF generator 802 are coupled to a matching network 806, which in turn is coupled to the showerhead 814.
在反應器內，晶圓基座818支撐基板816。此基座通常包含夾盤、叉、或升降銷，以在沉積反應期間及之間托持及運送基板。此夾盤可為靜電夾盤、機械夾盤、或各種其他類型的夾盤，如可用於工業及/或研究上之用途者。 Within the reactor, wafer base 818 supports substrate 816. The susceptor typically includes a chuck, fork, or lift pin to hold and transport the substrate during and between deposition reactions. The chuck can be an electrostatic chuck, a mechanical chuck, or various other types of chucks, such as those useful for industrial and/or research purposes.
製程氣體係經由入口812引入。多個來源氣體管線810係連接於歧管808。此氣體可以或不必被預混合。使用適當的閥調節及質量流量控制機構，以確保在製程之沉積及電漿處理階段期間，能輸送正確的氣體。在化學前驅物係以液體形式輸送的情況下，會使用液體流控制機構。接著，在被加熱至高於此液體汽化點的歧管中輸送此液體的期間並在到達沉積腔室前，將液體蒸發並與其他製程氣體混合。 The process gas system is introduced via inlet 812. A plurality of source gas lines 810 are coupled to manifold 808. This gas may or may not be pre-mixed. Proper valve conditioning and mass flow control mechanisms are used to ensure proper gas delivery during the deposition and plasma processing stages of the process. Where the chemical precursor is delivered in liquid form, a liquid flow control mechanism is used. Next, the liquid is vaporized and mixed with other process gases during delivery of the liquid in a manifold heated to above the vaporization point of the liquid and before reaching the deposition chamber.
製程氣體經由出口822離開腔室824。真空幫浦826(例如，一或二階段的機械乾式幫浦及/或渦輪分子幫浦)通常能將製程氣體汲取出來，並藉由閉迴路控制之流量限制裝置來維持反應器內的適當低壓，此流量限制裝置例如為節流閥或擺閥。 Process gas exits chamber 824 via outlet 822. A vacuum pump 826 (eg, a one or two stage mechanical dry pump and/or a turbo molecular pump) can typically purge the process gas and maintain a suitable low pressure in the reactor by a closed loop controlled flow restriction device. This flow restricting device is, for example, a throttle valve or a swing valve.
在某些實施例中，系統控制器830(其可包含一或更多實體或邏輯控制器)控制一些或全部的沉積腔室之操作。系統控制器830可包含一或更多記憶體裝置及一或更多處理器。處理器可包含中央處理單元(central processing unit,CPU)或電腦、類比及/或數位輸入/輸出連結、步進馬達控制器板、及其他類似零件。用於實施適當之控制操作的指令係在處理器上執行。這些指令可被儲存於與控制器830相關聯的記憶體裝置上，或者，其可透過網路提供。在某些實施例中，系統控制器830能執行系統控制軟體。 In some embodiments, system controller 830 (which may include one or more physical or logical controllers) controls the operation of some or all of the deposition chambers. System controller 830 can include one or more memory devices and one or more processors. The processor can include a central processing unit (CPU) or computer, analog and/or digital input/output connections, stepper motor controller boards, and the like. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored on a memory device associated with controller 830 or may be provided over a network. In some embodiments, system controller 830 can execute system control software.
系統控制軟體可包含用於控制應用之時序、及/或下列腔室操作條件之任何一或更多者之程度的指令，腔室操作條件為：氣體之混合物及/或組成、腔室壓力、腔室溫度、晶圓/晶圓支撐物的溫度、施加於晶圓的偏壓、施加於線圈或其他電漿產生元件的頻率及功率、晶圓位置、晶圓移動速度、以及由此工具執行之特定製程的其他參數。可以任何適當方式配置系統控制軟體。舉例來說，可撰寫各種處理工具元件的子程式或控制物件，以控制對實行各種處理工具之製程係必要的處理工具元件之操作。系統控制軟體可以任何適當的電腦可讀取 編程語言編寫而成。 The system control software can include instructions for controlling the timing of the application, and/or the extent of any one or more of the following chamber operating conditions, the chamber operating conditions being: gas mixture and/or composition, chamber pressure, Chamber temperature, wafer/wafer support temperature, bias applied to the wafer, frequency and power applied to the coil or other plasma generating component, wafer position, wafer movement speed, and thus tool execution Other parameters of the specific process. The system control software can be configured in any suitable way. For example, subroutines or control objects of various processing tool components can be written to control the operation of processing tool components necessary to implement the various processing tools. System control software can be read by any suitable computer Written in a programming language.
在某些實施例中，系統控制軟體包含用於控制上述各種參數的輸入/輸出控制(input/output control,IOC)定序指令。舉例來說，半導體製造過程的每一階段可包含一或更多由系統控制器830所執行的指令。例如，用於設定沉積操作之製程條件的指令可被包含於對應的沉積配方階段中。 In some embodiments, the system control software includes input/output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each stage of the semiconductor fabrication process may include one or more instructions executed by system controller 830. For example, instructions for setting process conditions for the deposition operation can be included in the corresponding deposition recipe stage.
在某些實施例中，可使用其他的電腦軟體及/或程式。用於此目的之程式或程式之區段的範例包含晶圓定位程式、製程氣體成分控制程式、壓力控制程式、加熱器控制程式、及RF電源供應器控制程式。 In some embodiments, other computer software and/or programs may be used. Examples of sections of programs or programs used for this purpose include wafer positioning programs, process gas composition control programs, pressure control programs, heater control programs, and RF power supply control programs.
在某些狀況下，控制器830控制氣體濃度、晶圓運動、及/或供應至加熱器區塊820及/或晶圓基座818的功率。控制器830可藉由以下方式來控制氣體濃度，例如，開啟及關閉相關的閥以產生一或更多輸入氣體流，其提供適當濃度的必須反應物。晶圓運動可藉由以下方式控制，例如，導引晶圓定位系統以視需求而移動。可控制供應至加熱器區塊820及/或晶圓基座818的功率，以提供特定的RF功率位準。 In some cases, controller 830 controls gas concentration, wafer motion, and/or power supplied to heater block 820 and/or wafer pedestal 818. Controller 830 can control the gas concentration by, for example, turning the associated valve on and off to produce one or more input gas streams that provide the necessary concentrations of the necessary reactants. Wafer motion can be controlled by, for example, guiding the wafer positioning system to move as needed. The power supplied to heater block 820 and/or wafer pedestal 818 can be controlled to provide a particular RF power level.
系統控制器830可基於感測器輸出(例如，當功率、電位、壓力等等達到某種程度的臨界值時)、操作之時序(例如，在製程中的某個時間打開閥)、或基於由使用者處接收之指令而控制這些及其他態樣。 System controller 830 can be based on sensor output (eg, when power, potential, pressure, etc. reaches a certain threshold), timing of operation (eg, opening a valve at some time during the process), or based on These and other aspects are controlled by instructions received by the user.
在某些實施例中，多站設備可用於沉積硬遮罩層。多站反應器允許吾人在一個腔室環境中同時進行相同或不同的製程，藉此提高晶圓處理的效率。此種設備的範例係描繪於圖9中。俯視圖的概略呈現被顯示出來。設備腔室901包含四個站903-909。一般而言，在多站設備的單一腔室內有任何數量的站均為可能的。站903係用於載入及卸載基板晶圓。站903-909可具有相同或不同的功能，且在某些實施例中，能夠在不同的製程條件下(例如，在不同的溫度狀況下)操作。 In some embodiments, a multi-station device can be used to deposit a hard mask layer. Multi-station reactors allow us to perform the same or different processes simultaneously in a single chamber environment, thereby increasing the efficiency of wafer processing. An example of such a device is depicted in Figure 9. A schematic representation of the top view is shown. The equipment chamber 901 contains four stations 903-909. In general, any number of stations are possible in a single chamber of a multi-station device. Station 903 is used to load and unload substrate wafers. Stations 903-909 can have the same or different functions, and in some embodiments, can operate under different process conditions (e.g., under different temperature conditions).
在某些實施例中，係在設備的一個站中沉積整個硬遮罩層。在其他實施例中，係在第一站中沉積硬遮罩層的第一部分，接著 將晶圓運送到第二站，並在第二站中沉積相同硬遮罩層的第二部分，以此類推，直到晶圓回到第一站並退出此設備。 In some embodiments, the entire hard mask layer is deposited in one station of the device. In other embodiments, the first portion of the hard mask layer is deposited in the first station, followed by The wafer is transported to the second station and a second portion of the same hard mask layer is deposited in the second station, and so on, until the wafer returns to the first station and exits the device.
在一實施例中，站903、905、907、及909全部用於硬遮罩層之沉積。分度盤911係用於將基板抬離基座，並將基板精確定位在下一個處理站。當晶圓基板在站903被載入後，將其依序分度定位(index)至站905、907、及909，其中，係在每一站沉積硬遮罩層的一部份。在站903卸載處理過之晶圓，並將新的晶圓裝入此模組。在正常操作期間，個別的基板佔據每一站，且每次要重複進行此製程時，將該等基板移動至新的站。因此，具有四個站903、905、907、及909的設備得以同時處理四個晶圓。 In one embodiment, stations 903, 905, 907, and 909 are all used for deposition of the hard mask layer. The indexing disk 911 is used to lift the substrate off the pedestal and accurately position the substrate at the next processing station. When the wafer substrate is loaded at station 903, it is indexed sequentially to stations 905, 907, and 909, where a portion of the hard mask layer is deposited at each station. The processed wafer is unloaded at station 903 and a new wafer is loaded into the module. During normal operation, individual substrates occupy each station, and each time the process is repeated, the substrates are moved to a new station. Therefore, a device having four stations 903, 905, 907, and 909 can process four wafers simultaneously.
可以下列工具進行含氧陶瓷硬遮罩的濕式蝕刻，例如，Lam SP系列，Da Vinci®、或DV-Prime®單晶圓清潔工具、或更常見的批量濕式工作台。濕式蝕刻設備可包含控制器，例如參照此沉積設備而描述者，此控制器包含控制系統軟體，以控制濕式蝕刻腔室的一些或全部操作。可將PECVD及濕式蝕刻設備結合於半導體製程工具中，以便晶圓基板的處理。 Wet etching of oxygenated ceramic hard masks can be performed with the following tools, such as the Lam SP series, Da Vinci®, or DV-Prime® single wafer cleaning tools, or more commonly used batch wet benches. The wet etch apparatus can include a controller, such as described with reference to the deposition apparatus, which includes control system software to control some or all of the operation of the wet etch chamber. PECVD and wet etching equipment can be incorporated into semiconductor process tools for wafer substrate processing.
圖10描繪了具有多種模組的半導體製程群集架構(cluster architecture)，該等模組與真空傳輸模組1038(vacuum transfer module,VTM)界接。用於在多個儲存設備及處理模組之間「傳輸」晶圓的傳輸模組之配置可被稱為「群集工具架構」系統。空氣鎖室1030(亦被稱為運載鎖室(loadlock)或傳輸模組)係顯示於具有四個處理模組1020a-1020d的VTM 1038中，可個別將此四個處理模組最佳化以進行各種製造處理。通過舉例之方式，此處理模組1020a-1020d可以被實現以進行基板蝕刻、沉積、離子佈植、晶圓清潔、濺鍍、及/或其他的半導體製程。基板蝕刻處理模組(1020a-1020d之任何者)之一或更多者可被實施為本文中所揭露者，即，用於藉由PECVD來沉積含氧陶瓷硬遮罩薄膜、及用於藉由濕式蝕刻來移除含氧陶瓷硬遮罩薄膜、以及依據於所揭露之實施例的其他適當功能。空氣鎖室1030及處理模組1020可被稱為「站」。每一站具有將站與VTM 1038接合的面部1036。在每一面部內，感測器1-18係用於當晶圓1026在個別的站之間移動時偵測其通 過。 FIG. 10 depicts a semiconductor process cluster architecture having a plurality of modules that interface with a vacuum transfer module (VTM). The configuration of a transport module for "transferring" a wafer between a plurality of storage devices and processing modules may be referred to as a "cluster tool architecture" system. The air lock chamber 1030 (also referred to as a load lock or transfer module) is shown in the VTM 1038 having four process modules 1020a-1020d, which can be optimized individually. Various manufacturing processes are performed. By way of example, the processing modules 1020a-1020d can be implemented for substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and/or other semiconductor processes. One or more of the substrate etch processing modules (any of 1020a-1020d) can be implemented as disclosed herein, i.e., for depositing an oxygen-containing ceramic hard mask film by PECVD, and for borrowing The oxygen-containing ceramic hard mask film is removed by wet etching, as well as other suitable functions in accordance with the disclosed embodiments. The air lock chamber 1030 and the processing module 1020 may be referred to as "station." Each station has a face 1036 that engages the station with the VTM 1038. Within each face, sensors 1-18 are used to detect when the wafer 1026 moves between individual stations. Over.
自動機器1022在站之間傳送晶圓1026。在一實施例中，自動機器1022具有一手臂，而在另一實施例中，自動機器1022具有二手臂，其中每一手臂具有終端作用器(end effector)1024，以拾取晶圓(例如晶圓1026)以供傳輸。在大氣傳輸模組(atmospheric transfer module,ATM)1040中的前端自動機器1032係用於將晶圓1026由載入端口模組(Load Port Module,LPM)1042中的卡匣(cassette)或前開式晶圓傳送盒(Front Opening Unified Pod,FOUP)1034運送至空氣鎖室1030。在處理模組1020內的模組中心1028係用於放置晶圓1026的一個位置。在ATM 1040中的對準機1044係用於對準晶圓。 Automated machine 1022 transports wafer 1026 between stations. In one embodiment, the automated machine 1022 has one arm, and in another embodiment, the automated machine 1022 has two arms, each arm having an end effector 1024 for picking up wafers (eg, wafers) 1026) for transmission. The front end automatic machine 1032 in an atmospheric transfer module (ATM) 1040 is used to mount the wafer 1026 from a cassette or front opening in a Load Port Module (LPM) 1042. A Front Opening Unified Pod (FOUP) 1034 is shipped to the air lock chamber 1030. The module center 1028 within the processing module 1020 is used to place a location of the wafer 1026. Alignment machine 1044 in ATM 1040 is used to align wafers.
在示例性的處理方法中，將晶圓放置於LPM 1042中的FOUPs 1034之一者內。前端自動機器1032將晶圓由FOUP 1034運送至對準機1044，此對準機1044允許晶圓1026在被蝕刻或處理前正確地置中。在經過對準後，藉由前端自動機器1032將晶圓1026移動至空氣鎖室1030中。由於空氣鎖室模組具有使ATM與VTM之間的環境相匹配的能力，因此晶圓1026能夠在不受損害的情況下於二種壓力環境之間移動。由空氣鎖室模組1030開始，藉由自動機器1022將晶圓1026經由VTM 1038而移動至處理模組1020a-1020d其中一者中。為達成此晶圓移動，自動機器1022在其手臂之每一者上使用終端作用器1024。一但晶圓1026已經經過處理，會藉由自動機器1022將晶圓1026由處理模組1020a-1020d移動至空氣鎖室模組1030。由此，可藉由前端自動機器1032將晶圓1026移動到FOUPs 1034其中一者或到對準機1044。 In an exemplary processing method, the wafer is placed in one of the FOUPs 1034 in the LPM 1042. The front end automated machine 1032 transports the wafer from the FOUP 1034 to the aligner 1044, which allows the wafer 1026 to be properly centered prior to being etched or processed. After alignment, wafer 1026 is moved into air lock chamber 1030 by front end automated machine 1032. Since the air lock chamber module has the ability to match the environment between the ATM and the VTM, the wafer 1026 can be moved between the two pressure environments without damage. Beginning with the air lock chamber module 1030, the wafer 1026 is moved by the robot 1022 via the VTM 1038 to one of the processing modules 1020a-1020d. To achieve this wafer movement, the automated machine 1022 uses the end effector 1024 on each of its arms. Once the wafer 1026 has been processed, the wafer 1026 is moved from the processing modules 1020a-1020d to the air lock chamber module 1030 by the automated machine 1022. Thus, wafer 1026 can be moved to one of FOUPs 1034 or to alignment machine 1044 by front end automated machine 1032.
如同沉積及濕式蝕刻設備，此群集工具可包含控制器，例如參照此沉積設備而描述者，此控制器包含控制系統軟體，以控制此群集工具及其元件模組的一些或全部操作。 Like deposition and wet etching equipment, the cluster tool can include a controller, such as described with reference to the deposition apparatus, which includes control system software to control some or all of the operation of the cluster tool and its component modules.
應當注意的是，控制晶圓移動的電腦對此群集結構可以是本地的、或可設於一生產車間(manufacturing floor)中此群集結構的外部、或位於遠端位置中並經由網路連接至此群集結構。 It should be noted that the computer controlling the movement of the wafer may be local to the cluster structure or may be located outside of the cluster structure in a manufacturing floor or in a remote location and connected to the network via the network. Cluster structure.
下列範例證明了依據於本發明的含氧薄膜對於半導體處理方案的適用性。 The following examples demonstrate the applicability of oxygen-containing films in accordance with the present invention to semiconductor processing schemes.
使用前驅物製程氣體總流量之0-50%為CO2的氣體流來製備氧摻雜硬遮罩。以下表格呈現了由0-7.5%的CO2流所形成之薄膜的數據：
此表格顯示當氧被添加到陶瓷硬遮罩時薄膜特性的改變。添加氧會使薄膜的折射係數(refractive index,RI)及壓縮應力增加，然而此氧摻雜陶瓷薄膜具有可相容於作為遮罩使用的特性。 This table shows the change in film properties when oxygen is added to the ceramic hard mask. The addition of oxygen increases the refractive index (RI) and compressive stress of the film, however, the oxygen doped ceramic film has characteristics compatible with being used as a mask.
這些氧摻雜陶瓷薄膜作為硬遮罩的適用性，係藉由在圖7中以作圖方式呈現的數據而更加得到證明。係在氮化物、多晶矽、及基於TEOS者的蝕刻中，測試表示於上面表格的硬遮罩薄膜之乾式蝕刻速率。為了增加對這些薄膜的選擇性，所需要的是，在這些蝕刻中的蝕刻速率要盡可能的低。如圖中所示，添加氧到陶瓷硬遮罩薄膜，對於氮化物、多晶矽、及基於TEOS者之蝕刻中的薄膜蝕刻速率僅具有微小的影響。換言之，當氧摻雜薄膜被用作硬遮罩時，其相對於未摻雜薄膜僅有微小的蝕刻選擇性差異。因此，此含氧薄膜係適合用於將包含氮化矽、氧化矽、及多晶矽薄膜的許多薄膜圖案化。 The applicability of these oxygen-doped ceramic films as hard masks is further demonstrated by the data presented graphically in Figure 7. The dry etch rate of the hard mask film shown in the above table was tested in nitride, polysilicon, and TEOS based etch. In order to increase the selectivity to these films, it is desirable that the etch rate in these etches be as low as possible. As shown in the figure, the addition of oxygen to the ceramic hard mask film has only a minor effect on the film etch rate in nitride, polysilicon, and TEOS based etching. In other words, when an oxygen doped film is used as a hard mask, it has only a slight difference in etching selectivity with respect to the undoped film. Therefore, the oxygen-containing film is suitable for patterning a plurality of films including tantalum nitride, yttria, and polycrystalline germanium films.
當結合此含氧薄膜能夠藉由濕式蝕刻而無須CMP來移除的特性，含氧陶瓷硬遮罩材料應有助於在邏輯及記憶體應用此兩者中的陶瓷硬遮罩處理解決方案之整合。 When combined with the ability of the oxygen-containing film to be removed by wet etching without CMP, the oxygen-containing ceramic hard mask material should contribute to the ceramic hard mask processing solution in both logic and memory applications. Integration.
應瞭解的是，本文中所述之範例及實施例僅用於說明之 目的，而依照其所作之各種修改或變化當能為熟悉本技藝者所聯想到。雖然為了清晰之目的而省略諸多細節，但各種設計替代方案仍可以被實施。因此，本範例應被視為說明性而非限制性者，且本發明並不受限於本文中所提供的細節，而可在隨附申請專利範圍的範疇內進行修改。應瞭解的是，在某些實施例中，硬遮罩薄膜可不一定是積極用於微影技術中的遮蔽，而可僅供作下方材料的硬保護層。 It should be understood that the examples and embodiments described herein are for illustrative purposes only. Aim, and various modifications or variations made in accordance with the teachings of the present invention can be Although many details are omitted for clarity, various design alternatives can still be implemented. Therefore, the present examples are to be considered as illustrative and not restrictive, and the invention is not limited to the details provided herein, but may be modified within the scope of the appended claims. It will be appreciated that in some embodiments, the hard mask film may not necessarily be actively used for shadowing in lithography, but may be used only as a hard protective layer for the underlying material.
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| US10211310B2 (en) | 2012-06-12 | 2019-02-19 | Novellus Systems, Inc. | Remote plasma based deposition of SiOC class of films |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20140175617A1 (en) | 2014-06-26 |
| TW201440123A (en) | 2014-10-16 |
| US9337068B2 (en) | 2016-05-10 |
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