TWI623047B - 電晶體裝置及其製造方法 - Google Patents

電晶體裝置及其製造方法 Download PDF

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Publication number
TWI623047B
TWI623047B TW106123709A TW106123709A TWI623047B TW I623047 B TWI623047 B TW I623047B TW 106123709 A TW106123709 A TW 106123709A TW 106123709 A TW106123709 A TW 106123709A TW I623047 B TWI623047 B TW I623047B
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Taiwan
Prior art keywords
hard mask
interlayer dielectric
gate
dielectric
metal gate
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TW106123709A
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English (en)
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TW201839863A (zh
Inventor
Kai Hsuan Lee
李凱璿
Bo Yu Lai
賴柏宇
Sheng Chen Wang
王聖禎
Sai-Hooi Yeong
楊世海
Yen Ming Chen
陳燕銘
Chi-On Chui
徐志安
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Taiwan Semiconductor Manufacturing Co., Ltd.
台灣積體電路製造股份有限公司
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Publication of TWI623047B publication Critical patent/TWI623047B/zh
Publication of TW201839863A publication Critical patent/TW201839863A/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一種方法包含形成金屬閘極在第一層間介電質內、在金屬閘極及第一層間介電質上進行處理、選擇性成長硬遮罩在金屬閘極上，且不從第一層間介電質成長硬遮罩、沉積第二層間介電質在硬遮罩及第一層間介電質上、平坦化第二層間介電質及硬遮罩，以及形成閘極接觸插塞穿過硬遮罩，以電性耦合金屬閘極。

Description

電晶體裝置及其製造方法
本揭露是關於一種電晶體及其製造方法，特別是關於一種電晶體的自對準閘極硬遮罩及其製造方法。
在鰭式場效電晶體之金屬閘極及各自的金屬接觸插塞的形成中，金屬閘極通常為內縮，且由於金屬閘極的凹陷而填充硬遮罩至凹陷內。接著，移除硬遮罩的一些部分，以形成接觸開口，穿過暴露的金屬閘極。形成閘極接觸插塞，以連接至金屬閘極。
硬遮罩的凹陷導致金屬閘極的流失，故須要形成高於最後高度的金屬閘極，以補償失去的高度。金屬閘極增加的高度導致用以形成金屬閘極之間隙填充的困難。再者，在硬遮罩的蝕刻中，硬遮罩的凹陷受到圖案負載效應的困擾，且圖案負載效應(pattern-loading effect)導致金屬閘極之一些部分較其他金屬閘極內縮。
本揭露之一態樣為一種方法，其係包含形成金 屬閘極在第一層間介電質內、在金屬閘極及第一層間介電質上進行處理、選擇性成長硬遮罩在金屬閘極上，且不從第一層間介電質成長硬遮罩、沉積第二層間介電質在硬遮罩及第一層間介電質上、平坦化第二層間介電質及硬遮罩，以及形成閘極接觸插塞穿過硬遮罩，以電性耦合金屬閘極。
本揭露之另一態樣為一種方法，其係包含形成金屬閘極在第一層間介電質內、內縮第一層間介電質，以使第一層間介電質之頂表面低於金屬閘極之頂表面、選擇性成長硬遮罩在金屬閘極上。硬遮罩包含向上成長之頂部部分，及水平成長之側壁部分。方法更包含沉積第二層間介電質在硬遮罩及第一層間介電質上、平坦化硬遮罩，使硬遮罩之底部部分維持在覆蓋金屬閘極。形成閘極接觸插塞穿過第二層間介電質，以電性耦合金屬閘極。
本揭露之再一態樣為一種裝置，其係包含第一層間介電質、具有在第一層間介電質內之金屬閘極的閘極堆疊、包含與閘極堆疊交疊之第一部分及與第一層間介電質之第一部分交疊之第二部分的硬遮罩。第二層間介電質具有與硬遮罩之側壁接觸的側壁。第二層間介電質與第一層間介電質之第二部分交疊。閘極接觸插塞，穿過硬遮罩，以與閘極堆疊接觸。
10‧‧‧晶圓
20‧‧‧基材
22‧‧‧隔離區域
22A‧‧‧頂表面
24‧‧‧半導體條
24’‧‧‧凸出鰭片
30‧‧‧虛擬閘極堆疊
32‧‧‧虛擬閘極介電質
34‧‧‧虛擬閘極電極
36‧‧‧硬遮罩層
38‧‧‧閘極間隙壁
40‧‧‧凹陷
41‧‧‧磊晶區域
42‧‧‧磊晶區域(源極/汲極區域)
46‧‧‧層間介電質
47‧‧‧接觸蝕刻中止層
48‧‧‧溝渠
52‧‧‧閘極介電層
54‧‧‧界面層
56‧‧‧高k介電層
58‧‧‧堆疊層
60‧‧‧金屬材料
62‧‧‧金屬閘極電極
63‧‧‧抑制層(薄膜)
64‧‧‧取代閘極堆疊
65‧‧‧箭頭
66‧‧‧硬遮罩
67A‧‧‧區域
67B‧‧‧區域
68‧‧‧層間介電質
70‧‧‧矽化物區域
72‧‧‧金屬層
74‧‧‧導電阻障層
76‧‧‧金屬區域
78‧‧‧源極/汲極接觸插塞
80‧‧‧蝕刻中止層
82‧‧‧層間介電質
83‧‧‧開口
84‧‧‧開口
86‧‧‧插塞/介層窗
88‧‧‧插塞/介層窗
90‧‧‧阻障層
92‧‧‧金屬材料
100‧‧‧鰭式場效電晶體
200‧‧‧方法
202‧‧‧形成半導體鰭片
204‧‧‧形成虛擬閘極堆疊在半導體鰭片上
206‧‧‧形成磊晶源極/汲極區域
208‧‧‧沉積接觸蝕刻中止層及第一層間介電質
210‧‧‧移除虛擬閘極堆疊
212‧‧‧前處理
214‧‧‧處理以形成抑制層
216‧‧‧選擇性地成長自對準硬遮罩在取代閘極堆疊上
218‧‧‧形成第二層間介電質，以覆蓋硬遮罩
220‧‧‧平坦化自對準硬遮罩
222‧‧‧形成源極/汲極矽化物區域及較低的源極/汲極接觸插塞
224‧‧‧形成閘極接觸插塞及較高的源極/汲極接觸插塞
D1‧‧‧深度
W1‧‧‧距離
W2‧‧‧寬度
T1‧‧‧厚度
根據以下詳細說明並配合附圖閱讀，使本揭露的態樣獲致較佳的理解。需注意的是，如同業界的標準作 法，許多特徵並不是按照比例繪示的。事實上，為了進行清楚討論，許多特徵的尺寸可以經過任意縮放。
[圖1]至[圖17]係繪示根據本揭露一些實施例之在電晶體的形成之中間階段的透視視圖及剖面視圖。
[圖18]係繪示根據本揭露一些實施例之形成電晶體及接觸插塞的流程圖。
以下揭露提供許多不同實施例或例示，以實施發明的不同特徵。以下敘述之成份和排列方式的特定例示是為了簡化本揭露。這些當然僅是做為例示，其目的不在構成限制。舉例而言，第一特徵形成在第二特徵之上或上方的描述包含第一特徵和第二特徵有直接接觸的實施例，也包含有其他特徵形成在第一特徵和第二特徵之間，以致第一特徵和第二特徵沒有直接接觸的實施例。許多特徵的尺寸可以不同比例繪示，以使其簡化且清晰。除此之外，本揭露在各種例示中會重複元件符號及/或字母。此重複的目的是為了簡化和明確，並不表示所討論的各種實施例及/或配置之間有任何關係。
再者，空間相對性用語，例如「下方(underlying)」、「在...之下(below)」、「低於(lower)」、「上方(overlying)」、「高於(upper)」等，是為了易於描述圖式中所繪示的元素或特徵和其他元素或特徵的關係。空間相對性用語除了圖式中所描繪的方向外，還包含元件在使 用或操作時的不同方向。裝置可以其他方式定向(旋轉90度或在其他方向)，而本文所用的空間相對性描述也可以如此解讀。
根據各種例示實施例提供電晶體及其製造方法。根據一些實施例繪示製造電晶體的中間階段。討論一些實施例的一些變化。透過各種視圖及說明的實施例，類似的參考數字係用於標示類似的元件。在繪示的例示實施例中，鰭式場效電晶體(Fin Field-Effect Transistors，FinFETs)係用以做為解釋本揭露之概念的具體例。平面電晶體也可採用本揭露的概念。
圖1至圖17係繪示根據本揭露一些實施例之在鰭式場效電晶體的形成之中間階段的剖面視圖及透視視圖。圖1至圖16所示之步驟也在圖18所示之流程圖200中以圖表式表現。
圖1繪示起始結構的透視視圖。起始結構包含晶圓10，其中晶圓10更包含基材20。基材20可為半導體基材，其可為矽基材、矽鍺基材或由其他半導體材料形成的基材。基材20可被p型雜質或n型雜質摻雜。形成例如淺溝渠隔離(Shallow Trench Isolation，STI)區域的隔離區域22，以自基材20之頂表面延伸至基材20內。在相鄰的淺溝渠隔離區域22之間的基材20之部分係當作半導體條24。根據一些例示實施例，半導體條24之頂表面及淺溝渠隔離區域22之頂表面係實質為與彼此在同一高度。根據本揭露一些實施例，半導體條24係原基材20之部分，因此，半導體 條24之材料係與基材20之材料相同。根據本揭露另一些實施例，半導體條24係藉由蝕刻在淺溝渠隔離區域22之間的基材20之部分，以形成凹陷，而形成的取代條，並進行磊晶，以在凹陷內再成長其他半導體材料。因此，半導體條24係由與基材20不同的半導體材料所形成。根據一些例示實施例，半導體條24係由矽鍺、碳化矽或III-V族化合物半導體材料所形成。
淺溝渠隔離區域22可包含襯氧化層(圖未繪示)，其中襯氧化層可為透過基材20之表面層的熱氧化所形成的熱氧化物。襯氧化層也可為沉積氧化矽層，其係利用例如原子層沉積(Atomic Layer Deposition，ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)或化學氣相沉積(Chemical Vapor Depostion，CVD)所形成。淺溝渠隔離區域22也可包含在襯氧化層上的介電材料，其中介電材料可為利用流動式化學氣相沉積(Flowable Chemical Vapor Deposition，FCVD)、旋轉塗佈(spin-on coating)或類似方式所形成。
請參閱圖2，淺溝渠隔離區域22係內縮，以使半導體條24之頂部部分凸出至高於淺溝渠隔離區域22之剩餘部分的頂表面22A，以形成凸出鰭片24’。相應的步驟係繪示於如圖18所示之流程圖200中的步驟202。可利用乾式蝕刻製程進行蝕刻，其中三氟化氮(NF3)及氨(NH3)係被使用為蝕刻氣體。在蝕刻製程中，可產生電漿。也可包含氬氣。 根據本揭露另一些實施例，利用濕式蝕刻製程進行淺溝渠隔離區域22的內縮。蝕刻化學品可包含例如氫氟酸。
請參閱圖3，形成虛擬閘極堆疊30在(凸出)鰭片24’之頂表面及側壁上。相應的步驟係繪示於如圖18所示之流程圖200中的步驟204。虛擬閘極堆疊30可包含虛擬閘極介電質32及在虛擬閘極介電質上的虛擬閘極電極34。可利用例如多晶矽及其他可使用的材料形成虛擬閘極電極34。每一個虛擬閘極堆疊30也可包含一個(或複數個)在虛擬閘極電極34上的硬遮罩層36。硬遮罩層36可由氮化矽、氮化矽、碳氮化矽或其中的多層所形成。虛擬閘極堆疊30可穿過單一個或複數個凸出鰭片24’及/或淺溝渠隔離區域22。虛擬閘極堆疊30亦具有垂直於凸出鰭片24’之縱向方向的縱向方向。
接著，形成閘極間隙壁38在虛擬閘極堆疊30之側壁上。根據本揭露一些實施例，閘極間隙壁38係由介電材料(例如氮化矽、碳氮化矽或類似物)所形成，且閘極間隙壁38可具有單一層結構或包含複數個介電層的多層結構。根據本揭露一些實施例，閘極間隙壁38之中係不具有氧原子。
然後，進行蝕刻步驟(之後表示為源極/汲極內縮步驟)，以蝕刻凸出鰭片24’之未被虛擬閘極堆疊30及閘極間隙壁38覆蓋的部分，以製得圖4所示之結構。內縮步驟可為非等向性蝕刻，因此，直接在鰭片24’之部分下方的虛擬閘極堆疊30及閘極間隙壁38係被保護而不被蝕刻。根據 一些實施例，內縮半導體條24之頂表面係低於淺溝渠隔離區域22之頂表面22A。因此，形成凹陷40在淺溝渠隔離區域22之間。凹陷40係位於虛擬閘極堆疊30的相反側上。
接著，磊晶區域(源極/汲極區域)42係藉由選擇性成長半導體材料在凹陷40內所形成，以製得圖5A所示之結構。相應的步驟係繪示於如圖18所示之流程圖200中的步驟206。根據一些例示實施例，磊晶區域42包含矽鍺或矽。根據製成之鰭式場效電晶體為p型鰭式場效電晶體或n型鰭式場效電晶體，可繼續進行磊晶，以原位摻雜p型雜質或n型雜質。舉例而言，當製成之鰭式場效電晶體為p型鰭式場效電晶體，可成長矽鍺硼(silicon germanium boron，SiGeB)。相反地，當製成之鰭式場效電晶體為n型鰭式場效電晶體，可成長磷化矽(silicon phosphorous，SiP)或碳磷化矽(silicon carbon phosphorous，SiCP)。根據本揭露另一些實施例，磊晶區域42係由III-V族化合物半導體(例如：GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、前述的組合或其中的多層)所形成。在磊晶區域42完全填充凹陷40後，磊晶區域42開始水平地膨脹，並形成晶面。
在磊晶步驟後，磊晶區域42可進一步佈植p型雜質或n型雜質，以形成源極及汲極區域，其可使用類似的數字42表示。根據本揭露另一些實施例，當磊晶區域42已在磊晶以形成源極/汲極區域時原位摻雜p型雜質或n型雜質，則可省略佈植步驟。磊晶源極/汲極區域42包含下部分 及上部分，其中下部分係形成在淺溝渠隔離區域22內，而上部分係形成在淺溝渠隔離區域22之頂表面上。
圖5B係繪示根據本揭露另一些實施例之源極/汲極區域42的形成。根據這些實施例，圖3所示之凸出鰭片24’並未內縮，且磊晶區域41係成長在凸出鰭片24’上。磊晶區域41之材料係與圖5A所示之磊晶半導體材料42之材料相似，其係取決於製成之鰭式場效電晶體為p型鰭式場效電晶體或n型鰭式場效電晶體。因此，源極/汲極區域42包含凸出鰭片24’及磊晶區域41。進行佈植，以佈植n型雜質或p型雜質。
圖6係繪示接觸蝕刻中止層(Contact Etch Stop Layer，CESL)47及層間介電質(Inter-Layer Dielectric，ILD)46形成後之結構的透視視圖。相應的步驟係繪示於如圖18所示之流程圖200中的步驟208。根據一些實施例，可省略接觸蝕刻中止層47，而當形成接觸蝕刻中止層47，其係由氮化矽、碳氮化矽或類似物所形成。根據本揭露一些實施例，接觸蝕刻中止層47之內係不具有氧。接觸蝕刻中止層47係利用共形沉積法(例如原子層沉積或化學氣相沉積)所形成。層間介電質46可包含介電材料，其係利用例如流動式化學氣相沉積、旋轉塗佈、化學氣相沉積或其他沉積方法所形成。層間介電質46也可由含氧介電材料形成，其中含氧介電材料可為以氧化矽為基礎的四乙氧基矽烷(tetraethyl orthosilicate，TEOS)氧化物、電漿輔助化學氣相沉積(Plasma-Enhanced CVD，PECVD)氧化 物(SiO2)、磷矽玻璃(Phospho-Silicate Glass，PSG)、硼矽玻璃(Boro-Silicate Glass，BSG)、硼摻雜磷矽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)或類似物。可進行例如化學機械研磨(Chemical Mechanical Polish，CMP)或機械研磨(mechanical grinding)的平坦化步驟，以使層間介電質46、虛擬閘極堆疊30及閘極間隙壁38之頂表面彼此在同一高度。
圖6所示之結構的剖面視圖係繪示於圖7，其中剖面視圖係從包含圖6中的線A-A之垂直面所獲得。
接著，如圖8及圖9所示，包含硬遮罩層36、虛擬閘極電極34及虛擬閘極介電質32的虛擬閘極堆疊係被包含金屬閘極及取代閘極介電質的取代閘極堆疊所取代。圖8及圖9示之剖面視圖及後續的剖面視圖係同樣從包含圖6中的線A-A之垂直面所獲得。在剖面視圖中，繪示淺溝渠隔離區域22之頂表面22A的高度，且半導體鰭片24’係在頂表面22A上。
當形成取代閘極堆疊，首先，以一或複數個蝕刻步驟移除如圖7所示之硬遮罩層36、虛擬閘極電極34及虛擬閘極介電質32，以形成圖8所示之溝渠/開口48。相應的步驟係繪示於如圖18所示之流程圖200中的步驟210。凸出半導體鰭片24’之頂表面及側壁係暴露至溝渠48。
接著，請參閱圖9，形成(取代)閘極介電層52，其係延伸至溝渠48(圖8)內。根據本揭露一些實施例，閘極介電層52係包含當作是下部分的界面層(Interfacial Layer，IL)54。界面層54係形成在凸出鰭片24’之暴露的表面上。界面層54可包含例如氧化矽層的氧化層，其係透過對凸出鰭片24’進行熱氧化、化學氧化製程或沉積製程所形成。閘極介電層52也可包含形成在界面層54上的高k介電層56。高k介電層56包含高k介電材料，例如二氧化鉿、氧化鑭、氧化鋁、二氧化鋯、氮化矽或類似物。高k介電材料的介電常數(k值)係高於3.9，且可高於7.0。高k介電層56係在界面層54之上，且可接觸界面層54。高k介電層56係形成為共形層，並延伸至凸出鰭片24’之側壁及閘極間隙壁38之側壁上。根據本揭露一些實施例，高k介電層56係利用原子層沉積或化學氣相沉積所形成。
請繼續參閱圖9，沉積堆疊層58。堆疊層58內的子層並未分開繪示，在現實狀況下，子層彼此係可分辨的。沉積係利用共形沉積法(例如原子層沉積或化學氣相沉積)進行，以使堆疊層58(及每一個子層)之垂直部分的厚度與水平部分的厚度係實質上與彼此相等。沉積的閘極介電層52及堆疊層58延伸至溝渠48(圖8)內，且係包含在層間介電質46上的一些部分。
堆疊層58可包含擴散阻障層及在擴散阻障層上的一個(或多個)功函數層。擴散阻障層係由氮化鈦(titanium nitride，TiN)所形成，其中氮化鈦可(或可不)被矽摻雜。功函數層決定閘極的功函數，且包含至少一層或由不同材料所形成的多層。功函數層的材料係根據對應之鰭式場效電晶體為n型鰭式場效電晶體或p型鰭式場效電晶體 以進行選擇。舉例而言，當鰭式場效電晶體為n型鰭式場效電晶體時，功函數層可包含氮化鉭(TaN)層及在氮化鉭層上的鈦鋁(TiAl)層。當鰭式場效電晶體為p型鰭式場效電晶體時，功函數層可包含氮化鉭層、在氮化鉭層上的氮化鈦層及在氮化鈦層上的鈦鋁層。在功函數層的沉積後，形成阻障層，其可為另外的氮化鈦層。
接著，沉積金屬材料60，金屬材料60可為由例如鎢或鈷所形成。金屬材料60完全填充剩餘的溝渠48(圖8)。在圖9所示之後續步驟中，進行如化學機械研磨或機械研磨的平坦化步驟，以移除在層間介電質46上的層56、堆疊層58及金屬材料60之部分。因此，形成金屬閘極電極62，其係包含堆疊層58及金屬材料60的剩餘部分。閘極介電層52、堆疊層58及金屬材料60之的剩餘部分在之後係當作取代閘極堆疊64。如圖9所示，金屬閘極電極62、閘極間隙壁38、接觸蝕刻中止層47及層間介電質46在此時為實質上共平面。
圖10至圖12A係繪示根據一些實施例之自對準硬遮罩的形成。層間介電質46之材料係與接觸蝕刻中止層47、閘極間隙壁38及金屬閘極電極62之材料不同。舉例而言，層間介電質46可為含氧介電質，例如氧化物，而接觸蝕刻中止層47、閘極間隙壁38及金屬閘極電極62係不具有氧。因此，在圖10至圖12A中，對層間介電質46、接觸蝕刻中止層47、閘極間隙壁38及金屬閘極電極62之表面進行處理，以使後續硬遮罩的選擇性沉積得以進行。
請參閱圖10，進行前處理，例如使用酸，其可為稀釋氫氟酸水溶液。相應的步驟係繪示於如圖18所示之流程圖200中的步驟212。前處理在圖中係利用箭頭65表示。前處理也可利用氨(NH3)及三氟化氮(NF3)的混合氣體進行。
根據一些實施例，前處理會影響蝕刻，其係造成層間介電質46的凹陷。凹陷深度D1可為約10奈米至約50奈米。因此，暴露出接觸蝕刻中止層47之側壁(或閘極間隙壁38之側壁，若沒有形成接觸蝕刻中止層47時)。
接著，如圖11所示，進一步處理晶圓10，且在層間介電質46之表面上產生的鍵結(在前處理時)係被終止，以產生抑制層63。相應的步驟係繪示於如圖18所示之流程圖200中的步驟214。舉例而言，可進行處理，以使在層間介電質46中與氧原子產生一些疏水性鍵結。根據一些實施例，連接至氧原子的鍵結可包含Si(CH3)3。連接鍵結的對應製程可包含矽烷化(silylation)製程，其中對應製程氣體可包含雙(三甲基矽基)胺[bis(trimethylsilyl)amine]、六甲基二矽氮烷(hexamethyldisilazane，HMDS)、四甲基二矽氮烷(tetramethyldisilazane，TMDS)、三甲基氯矽烷(trimethylchlorosilane，TMCS)、二甲基二氯矽烷(dimethyldichlorosilane，DMDCS)、甲基三氯矽烷(methyltrichlorosilane，MTCS)或類似物。根據其他實施例，因為層間介電質46之材料係與接觸蝕刻中止層47、 閘極間隙壁38及金屬閘極電極62之材料不同，可選擇性沉積有機薄膜(也可表示為薄膜63)在層間介電質46之表面上，但不在接觸蝕刻中止層47、閘極間隙壁38及金屬閘極電極62之暴露表面上。因此，無論是透過終止鍵結或透過選擇性沉積，層間介電質46之表面的性質係轉變成與接觸蝕刻中止層47、閘極間隙壁38及金屬閘極電極62的性質不同。
然後，如圖12A所示，選擇性沉積自對準硬遮罩66在取代閘極堆疊64上。相應的步驟係繪示於如圖18所示之流程圖200中的步驟216。硬遮罩66係當作自對準硬遮罩，由於其係自對準至接觸蝕刻中止層47、閘極間隙壁38及金屬閘極電極62的位置。硬遮罩66係由介電材料(例如氮化矽、碳氮化矽或類似物)所形成。在沉積中，由於層間介電質46之表面已被改變，難以在層間介電質46之表面上成核，因而硬遮罩66係不會從層間介電質46開始形成。另外，沉積硬遮罩66在接觸蝕刻中止層47、閘極間隙壁38及金屬閘極電極62之表面上。直接在金屬閘極電極62上的硬遮罩66之部分主要係向上成長，且從接觸蝕刻中止層47(或閘極間隙壁38，若接觸蝕刻中止層47沒有形成)之側壁成長的硬遮罩66之部分主要係水平地成長。
在閘極介電質56含有氧的實施例中，根據閘極介電質56的組成，硬遮罩66可或可不從閘極介電質56之頂表面成長。然而，由於閘極介電質56係薄的，且閘極介電質56之暴露表面係窄的，即使硬遮罩66未從閘極介電質56 成長地很好，從金屬閘極電極62及閘極間隙壁38成長的硬遮罩66之部分會彼此結合，以形成主體硬遮罩66。根據一些實施例，孔隙(圖未繪示)可(或可不)被形成在區域67A及/或區域67B，由於這些區域的成長不佳，且根據一些例示實施例，孔隙可造成硬遮罩66與層間介電質46及/或閘極介電質56些微地物理性分離。
圖12B係繪示如圖12A所示之晶圓10的透視視圖。圖12B係繪示硬遮罩66形成覆蓋金屬閘極電極62、閘極間隙壁38及接觸蝕刻中止層47的長條。如圖12A所示，硬遮罩66側向擴散至超出接觸蝕刻中止層47的外部邊緣，藉此硬遮罩66可具有寬度W2係大於距離W1，其中距離W1係在接觸蝕刻中止層47之相鄰的垂直部分的外部邊緣之間。硬遮罩66更具有圓形的(弧狀的)側壁及頂表面。根據本揭露的一些實施例，硬遮罩66之厚度T1係大於約10奈米，且厚度T1之範圍係介於為約10奈米至約100奈米。
在硬遮罩66的形成之後，進行後處理，以優化硬遮罩66的膜品質。根據一些例示實施例，透過溫度介於約800℃及約1200℃之間的快速熱退火(Rapid Thermal Anneal，RTA)進行後處理。根據另一些實施例，透過電漿處理進行後處理，其中電漿處理之製程氣體係包含例如氮氣、氫氣、氬氣、氦氣及/或類似物。後處理係移除硬遮罩66的懸浮鍵(dangling bond)，使其成為較少孔洞且較能抵抗後續的清洗製程。
根據後處理的方法及抑制膜63的組成，後處理 可或可不導致抑制膜63的移除。若抑制膜63未因為後處理而被移除，在硬遮罩66的形成之後，且在後處理之前或之後，進行額外的製程，以移除抑制膜63，使在層間介電質上方的沉積可進行。根據一些實施例，在蝕刻氣體或蝕刻溶液中移除抑制膜63，取決於抑制膜的類型。根據另一些實施例，利用電漿移除抑制膜，其中電漿可具有輕微的碰撞效應。
接著，如圖13所示，形成層間介電質68。相應的步驟係繪示於如圖18所示之流程圖200中的步驟218。形成層間介電質68的材料係選自於層間介電質46之候選材料的相同族群，且層間介電質68之材料可與層間介電質46之材料相同或不同。層間介電質68具有之頂表面係高於硬遮罩66之頂表面，以使硬遮罩66係埋入層間介電質68內。在層間介電質46及層間介電質68之間可具有或不具有可視的界面。
圖14A及圖14B係分別繪示晶圓10在平坦化步驟之後的剖面視圖及透視視圖，其中平坦化步驟可利用化學機械研磨或機械研磨來進行。圖14B係繪示圖14A所示之晶圓10的透視視圖。相應的步驟係繪示於如圖18所示之流程圖200中的步驟220。因為平坦化步驟，硬遮罩66之頂表面係被平坦化的，且硬遮罩66之頂表面係與層間介電質68之頂表面共平面。剩下的硬遮罩66仍具有與層間介電質68接觸的曲面側壁。
在平坦化之後，可進行額外的後處理，以更優 化硬遮罩66的膜品質。額外的後處理與在層間介電質68形成之前所進行之先前的後處理具有類似的功用，且可移除由於平坦化而暴露之硬遮罩66新暴露出的懸浮鍵，且更使硬遮罩66成為較少孔洞且較能抵抗後續的清洗製程。進行額外的後處理之方法係選自於與進行先前處理之候選材料及方法的相同族群。
圖15至圖17係繪示源極/汲極接觸插塞及閘極接觸插塞的形成。在繪示的例示實施例中，所示為三個源極/汲極區域42，且繪示的製程係顯示一個源極/汲極接觸插塞連接至最左邊的源極/汲極區域42的形成。在現實製程中，也形成源極/汲極接觸插塞，以連接至中心及最右邊的源極/汲極區域42。然而，這些源極/汲極插塞係形成在繪示的不同平面上，且未於繪示的平面中顯示。同樣地，雖然一個閘極接觸插塞係繪示為形成直接在圖式右側的取代閘極堆疊64上，也可形成閘極接觸插塞直接在左邊的取代閘極堆疊64上，其係與繪示的不同平面，且圖未繪示。
圖15繪示源極/汲極矽化物區域70、金屬層72、導電阻障層74及金屬區域76的形成。相應的步驟係繪示於如圖18所示之流程圖200中的步驟222。根據一些實施例，金屬層72(例如鈦金屬層)係沉積為毯覆層，接著在金屬層72之頂部部分上進行氮化製程，以形成金屬氮化物層(例如74)。金屬層72之底部部分係未被氮化。接著，進行退火(可為快速熱退火)，以使金屬層72與源極/汲極區域42之頂部部分反應，以形成矽化物區域70。在層間介電質46之側 壁上的金屬層72之部分未發生反應。然後，可留下先前形成之金屬氮化物層74，以做為繪示的導電阻障層74，或移除先前形成的金屬氮化物層74，再接著沉積新的金屬氮化物層(例如氮化鈦，亦利用參考數值74表示)，且其係較被移除的金屬氮化物層薄。然後，形成金屬區域76，其係例如藉由填充鎢、鈷或類似物，接著，進行平坦化，以移除多餘的材料，以製成較低的源極/汲極接觸插塞78。
請參閱圖16，根據本揭露的一些實施例，形成蝕刻中止層80。根據一些實施例，蝕刻中止層係由氮化矽(SiN)、碳氮化矽(SiCN)、碳化矽(SiC)、氮碳氧化矽(SiOCN)或其他介電材料所形成。蝕刻中止層80之厚度的範圍可為約2奈米至約4奈米。形成方法可包含電漿輔助化學氣相沉積、原子層沉積、化學氣相沉積或類似方法。接著，形成層間介電質82在蝕刻中止層80上。層間介電質82之材料係可選自於與形成層間介電質46及層間介電質68相同的候選材料(及方法)，且層間介電質46、層間介電質68及層間介電質82係由相同或不同的介電材料所形成。根據一些實施例，層間介電質82係使用電漿輔助化學氣相沉積、流動式化學氣相沉積、旋轉塗佈或類似方法所形成，且可包含氧化矽(SiO2)。層間介電質82之厚度的範圍係介於約700Å和約800Å之間。
蝕刻層間介電質82及蝕刻中止層80，以形成開口83及開口84。可利用例如反應性離子蝕刻(Reactive Ion Etch，RIE)進行蝕刻。在後續步驟中，如圖17所示，形成 插塞/介層窗86及插塞/介層窗88。相應的步驟係繪示於如圖18所示之流程圖200中的步驟224。根據本揭露的一些實施例，插塞/介層窗86及插塞/介層窗88包含阻障層90及在阻障層90上的含金屬材料92。根據本揭露的一些實施例，插塞/介層窗86及插塞/介層窗88的形成包含形成毯覆阻障層90及在毯覆阻障層90上的含金屬材料92，並進行平坦化，以移除毯覆阻障層90及含金屬材料92的多餘部分。阻障層90可由金屬氮化物(例如氮化鈦或氮化鉭)所形成。含金屬材料92可由鎢、鈷、銅或類似物所形成。
在最終鰭式場效電晶體100中，閘極接觸插塞88穿過對應的硬遮罩，剩下的硬遮罩66具有在閘極接觸插塞88之相反側上的部分。硬遮罩66側向延伸至超過對應的取代閘極堆疊64及接觸蝕刻中止層47，並具有與層間介電質68接觸的曲面(或可為圓形的)側壁。
本揭露的實施例具有一些優勢的特徵。藉由利用選擇性沉積在金屬閘極上，而非以內縮金屬閘極的方式形成硬遮罩，接著形成硬遮罩在凹陷內，金屬閘極不須在內縮製程時考量高度損失，且可不用形成較高的高度。因此，孔隙填充在金屬閘極的形成中變得較容易。也可減少金屬閘極內縮的圖案負載效應，其中圖案負載效應係造成最終金屬閘極具有不同高度。
根據本揭露的一些實施例，一種方法包含形成金屬閘極在第一層間介電質內、在金屬閘極及第一層間介電質上進行處理、選擇性成長硬遮罩在金屬閘極上，且不從第 一層間介電質成長硬遮罩、沉積第二層間介電質在硬遮罩及第一層間介電質上、平坦化第二層間介電質及硬遮罩，以及形成閘極接觸插塞穿過硬遮罩，以電性耦合金屬閘極。
在一實施例中，閘極間隙壁係在金屬閘極之側壁上，接觸蝕刻中止層之垂直部分係在閘極間隙壁之側壁上，且自接觸蝕刻中止層之垂直部分的側壁中再成長硬遮罩。
在一實施例中，硬遮罩係成長為具有曲面側壁及曲面頂表面。
在一實施例中，上述處理係包含以酸預處理金屬閘極及第一層間介電質，以及形成抑制膜在第一層間介電質之暴露表面上，而不形成抑制膜在金屬閘極上。
在一實施例中，上述方法更包含在選擇性成長硬遮罩之操作後，對硬遮罩進行後處理。
在一實施例中，後處理包含熱退火。
在一實施例中，在平坦化第二層間介電質及硬遮罩之操作後，對硬遮罩進行額外後處理。
根據本揭露的一些實施例，一種方法包含形成金屬閘極在第一層間介電質內、內縮第一層間介電質，以使第一層間介電質之頂表面低於金屬閘極之頂表面、選擇性成長硬遮罩在金屬閘極上。硬遮罩包含向上成長之頂部部分，及水平成長之側壁部分。方法更包含沉積第二層間介電質在硬遮罩及第一層間介電質上、平坦化硬遮罩，使硬遮罩之底部部分維持在覆蓋金屬閘極。形成閘極接觸插塞穿過第二層 間介電質，以電性耦合金屬閘極。
在一實施例中，閘極接觸插塞更穿過硬遮罩，且硬遮罩包含仍在閘極接觸插塞之一側上的部分。
在一實施例中，閘極間隙壁係在金屬閘極之側壁上，且自閘極間隙壁之側壁成長硬遮罩之側壁部分。
在一實施例中，硬遮罩係成長為具有曲面側壁及曲面頂表面。
在一實施例中，上述方法更包含以酸預處理金屬閘極及第一層間介電質，以及形成抑制膜在第一層間介電質之頂表面上，而不形成抑制膜在金屬閘極上。
在一實施例中，在選擇性成長硬遮罩之操作後，對硬遮罩進行後處理。
在一實施例中，後處理包含熱退火。
在一實施例中，後處理包含電漿處理。
根據本揭露的一些實施例，一種裝置包含第一層間介電質、具有在第一層間介電質內之金屬閘極的閘極堆疊、包含與閘極堆疊交疊之第一部分及與第一層間介電質之第一部分交疊之第二部分的硬遮罩。第二層間介電質具有與硬遮罩之側壁接觸的側壁。第二層間介電質與第一層間介電質之第二部分交疊。閘極接觸插塞係穿過硬遮罩，以與閘極堆疊接觸。
在一實施例中，硬遮罩之側壁為曲面。
在一實施例中，閘極堆疊包含閘極介電質，閘極介電質包含垂直部分，且裝置更包含孔隙，孔隙在閘極介 電質之垂直部分之頂部。
在一實施例中，第一層間介電質之頂表面係低於閘極堆疊之頂表面，且硬遮罩之第二部分係低於閘極堆疊之頂表面。
在一實施例中，上述裝置更包含接觸蝕刻中止層，接觸蝕刻中止層包含與第一層間介電質交疊之底部部分以及具有側壁且與第一層間介電質接觸之垂直部分，其中硬遮罩之第二部分更與接觸蝕刻中止層之垂直部分的側壁接觸。
上述摘要許多實施例的特徵，因此本領域具有通常知識者可更了解本揭露的態樣。本領域具有通常知識者應理解利用本揭露為基礎可以設計或修飾其他製程和結構以實現和所述實施例相同的目的及/或達成相同優勢。本領域具有通常知識者也應了解與此同等的架構並沒有偏離本揭露的精神和範圍，且可以在不偏離本揭露的精神和範圍下做出各種變化、交換和取代。

Claims (10)

  1. 一種電晶體裝置的製造方法，包含：形成一金屬閘極在一第一層間介電質內；在該金屬閘極及該第一層間介電質上進行一處理；選擇性成長一硬遮罩在該金屬閘極上，且不從該第一層間介電質成長該硬遮罩，其中該硬遮罩係成長為具有一曲面側壁及一曲面頂表面；沉積一第二層間介電質在該硬遮罩及該第一層間介電質上；平坦化該第二層間介電質及該硬遮罩；以及形成一閘極接觸插塞，其中該閘極接觸插塞穿過該硬遮罩，以電性耦合該金屬閘極。
  2. 如申請專利範圍第1項所述之方法，其中一閘極間隙壁係在該金屬閘極之一側壁上，一接觸蝕刻中止層之一垂直部分係在該閘極間隙壁之一側壁上，且自該接觸蝕刻中止層之該垂直部分的一側壁中再成長該硬遮罩。
  3. 如申請專利範圍第1項所述之方法，其中該處理包含：以一酸預處理該金屬閘極及該第一層間介電質；以及形成一抑制膜在該第一層間介電質之一暴露表面上，而不形成該抑制膜在該金屬閘極上。
  4. 如申請專利範圍第1項所述之方法，更包含，在該選擇性成長該硬遮罩之操作後，對該硬遮罩進行一後處理；以及在該平坦化該第二層間介電質及該硬遮罩之操作後，對該硬遮罩進行一額外後處理。
  5. 一種電晶體裝置的製造方法，包含：形成一金屬閘極在一第一層間介電質內；內縮該第一層間介電質，以使該第一層間介電質之一頂表面低於該金屬閘極之一頂表面；選擇性成長一硬遮罩在該金屬閘極上，其中該硬遮罩包含向上成長之一頂部部分，及水平成長之一側壁部分；沉積一第二層間介電質在該硬遮罩及該第一層間介電質上；平坦化該硬遮罩，使該硬遮罩之一底部部分仍覆蓋該金屬閘極；以及形成一閘極接觸插塞穿過該第二層間介電質，以電性耦合該金屬閘極。
  6. 如申請專利範圍第5項所述之方法，其中該閘極接觸插塞更穿過該硬遮罩，且該硬遮罩包含仍在該閘極接觸插塞之一側上的一部分。
  7. 如申請專利範圍第5項所述之方法，更包含，在該選擇性成長該硬遮罩之操作後，對該硬遮罩進行一後處理，且該後處理包含一熱退火或一電漿處理。
  8. 一種電晶體裝置，包含：一第一層間介電質；一閘極堆疊，包含在該第一層間介電質內的一金屬閘極；一硬遮罩，包含與該閘極堆疊交疊之一第一部分，及與該第一層間介電質之一第一部分交疊之一第二部分；一第二層間介電質，具有一側壁，該側壁與該硬遮罩之一側壁接觸，且該第二層間介電質與該第一層間介電質之一第二部分交疊；以及一閘極接觸插塞，穿過該硬遮罩，以接觸該閘極堆疊。
  9. 如申請專利範圍第8項所述之裝置，其中該閘極堆疊包含一閘極介電質，該閘極介電質包含一垂直部分，該裝置更包含一孔隙，該孔隙在該閘極介電質之該垂直部分之一頂部，該第一層間介電質之一頂表面係低於該閘極堆疊之一頂表面，該硬遮罩之該第二部分係低於該閘極堆疊之該頂表面，且該硬遮罩之該側壁為曲面。
  10. 如申請專利範圍第8項所述之裝置，更包含一接觸蝕刻中止層，該接觸蝕刻中止層包含與該第一層間介電質交疊之一底部部分以及具有一側壁且與該第一層間介電質接觸之一垂直部分，其中該硬遮罩之該第二部分更與該接觸蝕刻中止層之該垂直部分的該側壁接觸。
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US12009253B2 (en) 2018-09-27 2024-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with staggered selective growth

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US20190013400A1 (en) 2019-01-10
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US10062784B1 (en) 2018-08-28
US10686075B2 (en) 2020-06-16
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