TWI619335B - Rectifier circuit for various linear and nonlinear inputs and loads - Google Patents
Rectifier circuit for various linear and nonlinear inputs and loads Download PDFInfo
- Publication number
- TWI619335B TWI619335B TW105143840A TW105143840A TWI619335B TW I619335 B TWI619335 B TW I619335B TW 105143840 A TW105143840 A TW 105143840A TW 105143840 A TW105143840 A TW 105143840A TW I619335 B TWI619335 B TW I619335B
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit
- voltage
- linear
- rectifier circuit
- bridge rectifier
- Prior art date
Links
Landscapes
- Rectifiers (AREA)
- Dc-Dc Converters (AREA)
Abstract
本發明係一種應用於各種線性與非線性輸入及負載之整流電路，包括輸入電壓、橋式整流電路、負載電路、電壓準位維持驅動電路、電流相位時序偵測電路、高壓側及低壓側驅動電路、輸入電壓相位時序偵測電路、單穩態電路及電晶體導通控制電路。本發明藉由同時偵測輸入訊號的電壓導通相位以及總線路上電流的導通相位，決定橋式整流電路上開關元件的導通時間，因此可在達到高效率的同時，使橋式整流電路可運用在任意波形的輸入訊號以及線性或非線性電路的各種組合上，進一步提升電源使用效率以及減少電路設計的複雜度，亦可避免電路產生誤動作。 The invention relates to a rectifier circuit applied to various linear and non-linear inputs and loads, including an input voltage, a bridge rectifier circuit, a load circuit, a voltage level maintaining driving circuit, a current phase timing detecting circuit, a high voltage side and a low voltage side driving. Circuit, input voltage phase timing detection circuit, monostable circuit and transistor conduction control circuit. The invention determines the on-time of the switching element on the bridge rectifier circuit by simultaneously detecting the voltage conduction phase of the input signal and the conduction phase of the current on the bus line, so that the bridge rectifier circuit can be used while achieving high efficiency. The arbitrary waveform input signal and various combinations of linear or non-linear circuits further improve the power efficiency and reduce the complexity of the circuit design, and also avoid circuit malfunction.
Description
本發明係一種整流電路，特別是關於一種應用於各種線性與非線性輸入及負載之整流電路。 The present invention is a rectifying circuit, and more particularly to a rectifying circuit applied to various linear and non-linear inputs and loads.
提高整流電路的效率係為提升電路效率的重要方法之一。在電源轉換電路中，由於功率提高，因此，針對轉換效率的重要性則日益增加。電路的輸入訊號與負載係由線性與非線性的特性混合組成，傳統方式僅針對弦波的輸入訊號配合電阻式線性負載，並根據輸入電壓相位，導通相對應與整流二極體並聯的開關元件，然而，當負載為非線性或者輸入訊號為直流電時，與整流二極體並聯的開關元件會失效或無法使用。 Increasing the efficiency of the rectifier circuit is one of the important ways to improve the efficiency of the circuit. In power conversion circuits, the importance of conversion efficiency is increasing due to increased power. The input signal and load of the circuit are composed of linear and nonlinear characteristics. The traditional method only matches the input signal of the sine wave with the resistive linear load, and according to the phase of the input voltage, turns on the switching element corresponding to the rectifier diode. However, when the load is non-linear or the input signal is direct current, the switching element in parallel with the rectifying diode may be disabled or unusable.
進一步而言，在整流電路中使用的二極體整流器由於功率的消耗隨著通過電流的增加而加大，為了降低二極體的損耗，在兩端並聯開關元件，例如MOSFET，並於二極體順向導通時開啟MOSFET，以降低導通二極體的功率損耗。然而，習知的整流電路係以偵測輸入電壓的相位，決定開關元件的導通與否，若負載電路包括電容元件或者其它非電阻式的負載電路，而使得輸入電壓呈現非線性訊號時，負載電路將產生逆向電流，進一步造成短路問題，將使得整流電路失效；或者， 當輸入為極長週期的交流電或直流電訊號時，將使得浮接的自舉式電源失去電源供應的效果，使得控制電路失效。 Further, the diode rectifier used in the rectifier circuit increases in power consumption as the passing current increases. In order to reduce the loss of the diode, a switching element such as a MOSFET is connected in parallel at both ends, and the diode is The MOSFET is turned on when the body is turned on to reduce the power loss of the conducting diode. However, the conventional rectifier circuit determines the phase of the input voltage to determine whether the switching element is turned on or not. If the load circuit includes a capacitive element or other non-resistive load circuit, so that the input voltage exhibits a nonlinear signal, the load The circuit will generate a reverse current, further causing a short circuit problem that will cause the rectifier circuit to fail; or, When the input is an extremely long period of AC or DC signal, the floating bootstrap power supply will lose the power supply effect, making the control circuit ineffective.
鑑於上述問題，本發明揭露應用於各種線性與非線性輸入及負載之整流電路，包括一輸入電壓、一橋式整流電路、一負載電路、複數個電壓準位維持驅動電路、一電流相位時序偵測電路、複數個高壓側及低壓側驅動電路、複數個輸入電壓相位時序偵測電路、一單穩態電路以及一電晶體導通控制電路。橋式整流電路，接收輸入電壓。負載電路電性連接橋式整流電路。複數個電壓準位維持驅動電路電性連接橋式整流電路，以維持導通橋式整流電路之電壓準位。電流相位時序偵測電路電性連接負載電路及該橋式整流電路，以偵測總線路上之電流訊號。複數個高壓側及低壓側驅動電路電性連接複數個電壓準位維持驅動電路，並產生至少一驅動訊號至橋式整流電路，使橋式整流電路根據至少一驅動訊號作動。複數個輸入電壓相位時序偵測電路電性連接橋式整流電路及輸入電壓，以調整輸入電壓之峰值。單穩態電路接收一時脈訊號。電晶體導通控制電路接收複數個輸入電壓相位時序偵測電路、單穩態電路及電流相位時序偵測電路之輸出訊號，以產生至少一邏輯控制訊號，使複數個高壓側及低壓側驅動電路根據至少一邏輯控制訊號作動，其中橋式整流電路係根據複數個高壓側及低壓側驅動電路產生之複數個驅動訊號作動。 In view of the above problems, the present invention discloses a rectifier circuit applied to various linear and non-linear inputs and loads, including an input voltage, a bridge rectifier circuit, a load circuit, a plurality of voltage level sustain drive circuits, and a current phase timing detection. The circuit, the plurality of high-voltage side and low-voltage side driving circuits, the plurality of input voltage phase timing detecting circuits, a monostable circuit, and a transistor conduction control circuit. A bridge rectifier circuit that receives an input voltage. The load circuit is electrically connected to the bridge rectifier circuit. A plurality of voltage levels maintain the driving circuit electrically connected to the bridge rectifier circuit to maintain the voltage level of the conduction bridge rectifier circuit. The current phase timing detection circuit is electrically connected to the load circuit and the bridge rectifier circuit to detect the current signal on the bus line. The plurality of high-voltage side and low-voltage side driving circuits are electrically connected to the plurality of voltage level maintaining driving circuits, and generate at least one driving signal to the bridge rectifier circuit, so that the bridge rectifier circuit operates according to at least one driving signal. A plurality of input voltage phase timing detection circuits are electrically connected to the bridge rectifier circuit and the input voltage to adjust the peak value of the input voltage. The monostable circuit receives a clock signal. The transistor conduction control circuit receives the output signals of the plurality of input voltage phase timing detection circuits, the monostable circuit and the current phase timing detection circuit to generate at least one logic control signal, so that the plurality of high voltage side and low voltage side driving circuits are At least one logic control signal is actuated, wherein the bridge rectifier circuit is actuated according to a plurality of driving signals generated by the plurality of high side and low side driving circuits.
承上所述，本發明的應用於各種線性與非線性輸入及負載之整流電路藉由同時偵測輸入訊號的電壓導通相位以及總線路上電流的導通相位，決定橋式整流電路上開關元件的導通時間，因此可在達到高效率的同時，使橋式整流電路可運用在任意波形的輸入訊號以及線性或非線性電路的各種組合上，進一步提升電源使用效率以及減少電路設計的複雜度，亦可避免電路產生誤動作。此外，習知技術中的浮接式開關元件驅動電路必須額外提供電壓源作為驅動電源，但於本發明中係使用內建震盪電路或是外接輸入時脈訊號，經由單穩態電路調整工作週期驅動隔離變壓器，其並不需要外加供應電源，因此，即使在輸入訊號為極長週期的交流電、直流電或任意波形的情況下亦可正常作動。 As described above, the rectifier circuit of the present invention applied to various linear and non-linear inputs and loads determines the conduction of the switching elements on the bridge rectifier circuit by simultaneously detecting the voltage conduction phase of the input signal and the conduction phase of the current on the bus line. Time, so that the bridge rectifier circuit can be used in any waveform input signal and various combinations of linear or non-linear circuits to further improve power efficiency and reduce circuit design complexity. Avoid circuit malfunctions. In addition, the floating-type switching element driving circuit in the prior art must additionally provide a voltage source as a driving power source, but in the present invention, the built-in oscillation circuit or an external input clock signal is used to adjust the duty cycle through the monostable circuit. The isolation transformer is driven, which does not require an external power supply. Therefore, it can operate normally even when the input signal is an extremely long period of alternating current, direct current or arbitrary waveform.
1‧‧‧應用於各種線性與非線性輸入及負載之整流電路 1‧‧‧Rectifier circuits for various linear and non-linear inputs and loads
11‧‧‧電壓準位維持驅動電路 11‧‧‧Voltage level maintenance drive circuit
12‧‧‧電流相位時序偵測電路 12‧‧‧ Current phase timing detection circuit
13‧‧‧高壓側及低壓側驅動電路 13‧‧‧High-voltage side and low-voltage side drive circuits
14‧‧‧輸入電壓相位時序偵測電路 14‧‧‧Input voltage phase timing detection circuit
141‧‧‧第一輸入電壓相位時序偵測電路 141‧‧‧First input voltage phase timing detection circuit
142‧‧‧第二輸入電壓相位時序偵測電路 142‧‧‧Second input voltage phase timing detection circuit
15‧‧‧單穩態電路 15‧‧‧monostable circuit
16‧‧‧電晶體導通控制電路 16‧‧‧Transistor conduction control circuit
17‧‧‧負載電路 17‧‧‧Load circuit
18‧‧‧時脈訊號 18‧‧‧ clock signal
19‧‧‧禁能電路 19‧‧‧ disable circuit
Q1、Q2、Q3、Q4、Q5、Q6‧‧‧MOSFET電晶體 Q1, Q2, Q3, Q4, Q5, Q6‧‧‧ MOSFET transistors
Q7~Q11‧‧‧電晶體 Q7~Q11‧‧‧Optoelectronics
D1~D13‧‧‧二極體 D1~D13‧‧‧ diode
Vi‧‧‧輸入電壓 Vi‧‧‧ input voltage
V1、V2、V3、V4、V5‧‧‧定電壓 V1, V2, V3, V4, V5‧‧ ‧ constant voltage
Vs‧‧‧輸入端 Vs‧‧ input
Vgp、Vgn‧‧‧邏輯控制訊號 Vgp, Vgn‧‧‧ logic control signals
VgsQ1、VgsQ2、VgsQ3、VgsQ4‧‧‧電晶體Q1、Q2、Q3、Q4之閘極端電壓 Gate extreme voltage of VgsQ1, VgsQ2, VgsQ3, VgsQ4‧‧‧ transistors Q1, Q2, Q3, Q4
Viload‧‧‧輸出訊號 Viload‧‧‧ output signal
VRVDN、VRVDL‧‧‧輸出訊號 VRVDN, VRVDL‧‧‧ output signal
AC+、V+‧‧‧正電端 AC+, V+‧‧‧ positive terminal
AC-、V-‧‧‧負電端 AC-, V-‧‧‧ negative terminal
R1、R7、R8、R9、R10、R13、R14、R15、R17~R29、Rload‧‧‧電阻 R1, R7, R8, R9, R10, R13, R14, R15, R17~R29, Rload‧‧‧ resistance
U1‧‧‧放大器 U1‧‧Amplifier
U2‧‧‧比較器 U2‧‧‧ comparator
U3、U4、U5‧‧‧邏輯及閘 U3, U4, U5‧‧‧ logic and gate
Cload、C2~C7‧‧‧電容 Cload, C2~C7‧‧‧ capacitor
TR1、TR2‧‧‧轉換電路 TR1, TR2‧‧‧ conversion circuit
第1圖係為本發明應用於各種線性與非線性輸入及負載之整流電路的方塊示意圖；第2A圖係為輸入電壓相位時序偵測電路的電路圖；第2B圖及第2C圖係為輸入電壓及輸入電壓相位時序偵測電路輸出訊號的時序圖；第3A圖係為電流相位時序偵測電路的電路圖；第3B圖及第3C圖係為電流相位時序偵測電路的輸入訊號、輸出訊號以及輸入電壓的時序圖； 第4A圖係為電晶體導通控制電路的邏輯電路圖；第4B圖係為各個訊號的相位導通時序圖；第5A圖及第5B圖係為高壓側及低壓側驅動電路以及電壓準位維持驅動電路的電路圖及方塊示意圖；以及第5C圖係為邏輯控制訊號以及整流電路四個MOSFET電晶體之閘極端的導通時序圖。 1 is a block diagram of a rectifier circuit applied to various linear and non-linear inputs and loads; FIG. 2A is a circuit diagram of an input voltage phase timing detection circuit; and FIG. 2B and FIG. 2C are input voltages. And the timing diagram of the output voltage phase timing detection circuit output signal; the 3A diagram is the circuit diagram of the current phase timing detection circuit; the 3B diagram and the 3C diagram are the input signal and output signal of the current phase timing detection circuit and Timing diagram of the input voltage; 4A is a logic circuit diagram of the transistor conduction control circuit; FIG. 4B is a phase conduction timing diagram of each signal; 5A and 5B are high-voltage side and low-voltage side driving circuits and a voltage level maintaining driving circuit; The circuit diagram and block diagram; and the 5C diagram is the logic timing control and the conduction timing diagram of the gate terminals of the four MOSFET transistors of the rectifier circuit.
請參閱第1圖，其係為本發明應用於各種線性與非線性輸入及負載之整流電路的方塊示意圖。應用於各種線性與非線性輸入及負載之整流電路1包括一輸入電壓Vi、一橋式整流電路(由MOSFET電晶體Q1、Q2、Q3、Q4及二極體D1、D2、D3、D4組成)、一負載電路17、複數個電壓準位維持驅動電路11、一電流相位時序偵測電路12、複數個高壓側及低壓側驅動電路13、複數個輸入電壓相位時序偵測電路14、一單穩態電路15以及一電晶體導通控制電路16。橋式整流電路電性連接輸入電壓Vi，並接收輸入電壓Vi。負載電路17電性連接橋式整流電路。複數個電壓準位維持驅動電路11電性連接橋式整流電路，以維持導通橋式整流電路之電壓準位。電流相位時序偵測電路12電性連接負載電路17及橋式整流電路，以偵測總線路上之電流訊號。複數個高壓側及低壓側驅動電路13電性連接複數個電壓準位維持驅動電路11，並產生至少一驅動訊號至橋式整流電路，使橋式整流電路根據至少一驅動訊號作動。複數個輸入電 壓相位時序偵測電路14電性連接橋式整流電路及輸入電壓Vi，以調整輸入電壓Vi之峰值。單穩態電路15接收一時脈訊號18。電晶體導通控制電路16接收複數個輸入電壓相位時序偵測電路14、單穩態電路15及電流相位時序偵測電路12之輸出訊號，以產生至少一邏輯控制訊號Vgp、Vgn，使複數個高壓側及低壓側驅動電路13根據至少一邏輯控制訊號Vgp、Vgn作動，其中橋式整流電路係根據複數個高壓側及低壓側驅動電路13產生之複數個驅動訊號作動。 Please refer to FIG. 1 , which is a block diagram of a rectifier circuit applied to various linear and non-linear inputs and loads. The rectifier circuit 1 applied to various linear and non-linear inputs and loads includes an input voltage Vi, a bridge rectifier circuit (composed of MOSFET transistors Q1, Q2, Q3, Q4 and diodes D1, D2, D3, D4), a load circuit 17, a plurality of voltage level maintaining drive circuit 11, a current phase timing detecting circuit 12, a plurality of high side and low side driving circuits 13, a plurality of input voltage phase timing detecting circuits 14, a monostable Circuit 15 and a transistor turn-on control circuit 16. The bridge rectifier circuit is electrically connected to the input voltage Vi and receives the input voltage Vi. The load circuit 17 is electrically connected to the bridge rectifier circuit. A plurality of voltage levels maintain the driving circuit 11 electrically connected to the bridge rectifier circuit to maintain the voltage level of the conduction bridge rectifier circuit. The current phase timing detection circuit 12 is electrically connected to the load circuit 17 and the bridge rectifier circuit to detect the current signal on the bus line. The plurality of high-voltage side and low-voltage side driving circuits 13 are electrically connected to the plurality of voltage level maintaining driving circuits 11, and generate at least one driving signal to the bridge rectifier circuit, so that the bridge rectifier circuit operates according to at least one driving signal. Multiple input The voltage phase timing detecting circuit 14 is electrically connected to the bridge rectifier circuit and the input voltage Vi to adjust the peak value of the input voltage Vi. The monostable circuit 15 receives a clock signal 18. The transistor conduction control circuit 16 receives the output signals of the plurality of input voltage phase timing detection circuits 14, the monostable circuit 15 and the current phase timing detection circuit 12 to generate at least one logic control signal Vgp, Vgn to make a plurality of high voltages. The side and low side drive circuits 13 are actuated according to at least one of the logic control signals Vgp, Vgn, wherein the bridge rectifier circuit is actuated according to a plurality of drive signals generated by the plurality of high side and low side drive circuits 13.
橋式整流電路包括四個MOSFET以及與四個MOSFET並聯之二極體。負載電路17包括線性負載電路或非線性負載電路，其係以第2A圖中的電阻Rload及電容Cload作為示意。 The bridge rectifier circuit includes four MOSFETs and a diode connected in parallel with the four MOSFETs. The load circuit 17 includes a linear load circuit or a non-linear load circuit, which is illustrated by the resistor Rload and the capacitor Cload in FIG. 2A.
在習知技術的電路中，僅針對輸入電壓Vi的訊號進行偵測，然而，於本發明中係進一步針對總線路上的電流訊號進行偵測。電流相位時序偵測電路12偵測的電流訊號則連同複數個輸入電壓相位時序偵測電路14偵測的輸入電壓訊號以及單穩態電路15輸出的訊號，輸入至電晶體導通控制電路16，以產生邏輯控制訊號Vgp、Vgn。 In the circuit of the prior art, only the signal of the input voltage Vi is detected. However, in the present invention, the current signal on the bus line is further detected. The current signal detected by the current phase timing detecting circuit 12 is input to the transistor conduction control circuit 16 together with the input voltage signal detected by the plurality of input voltage phase timing detecting circuits 14 and the signal output from the monostable circuit 15. The logic control signals Vgp, Vgn are generated.
請參閱第幾2A圖，其係為輸入電壓相位時序偵測電路的電路圖。為了清楚了解輸入電壓相位時序偵測電路14與輸入電壓Vi及橋式整流電路的連接關係，第2A圖中左方係重新繪製輸入電壓Vi及橋式整流電路，且為了簡潔說明起見，係 省略第1圖中與各個MOSFET電晶體Q1、Q2、Q3、Q4併聯的齊納二極體，而第1圖中未繪製的電阻R1係顯示於第2A圖中。複數個輸入電壓相位時序偵測電路14的MOSFET閘極端連接一定電壓V3、V5，汲極端分別連接輸入電壓Vi的兩端，亦即，第一輸入電壓相位時序偵測電路141的汲極端連接輸入電壓Vi的負電端AC-，第二輸入電壓相位時序偵測電路142的汲極端連接輸入電壓Vi的正電端AC+。據此，在扣除掉MOSFET電晶體Q5、Q6的導通電壓之後，可由輸入電壓相位時序偵測電路14的源極端取出電壓，輸出至電晶體導通控制電路16。此外，輸入電壓相位時序偵測電路14係由源極端的分壓取出電壓輸出至電晶體導通控制電路16，但，其設計並不以必須分壓的設計為限，而是可根據實際電路的設計由電阻R7、R8、R9、R10的大小調整。再者，圖示中的電路僅作為示例，並非侷限輸入電壓相位時序偵測電路14的設計，而是可調整輸入電壓Vi峰值的任意電路均屬於輸入電壓相位時序偵測電路14的範疇，例如電壓位準移位電路(voltage level shifting circuit)。 Please refer to Figure 2A, which is a circuit diagram of the input voltage phase timing detection circuit. In order to clearly understand the connection relationship between the input voltage phase timing detection circuit 14 and the input voltage Vi and the bridge rectifier circuit, the left side of FIG. 2A redraws the input voltage Vi and the bridge rectifier circuit, and for the sake of brevity, The Zener diodes connected in parallel with the respective MOSFET transistors Q1, Q2, Q3, and Q4 in FIG. 1 are omitted, and the resistor R1 not shown in FIG. 1 is shown in FIG. 2A. The MOSFET gate terminals of the plurality of input voltage phase timing detecting circuits 14 are connected to a certain voltage V3, V5, and the 汲 terminals are respectively connected to the two ends of the input voltage Vi, that is, the 汲 terminal connection input of the first input voltage phase timing detecting circuit 141. The negative terminal AC- of the voltage Vi, the 汲 terminal of the second input voltage phase timing detecting circuit 142 is connected to the positive terminal AC+ of the input voltage Vi. Accordingly, after the turn-on voltages of the MOSFET transistors Q5 and Q6 are subtracted, the voltage can be taken out from the source terminal of the input voltage phase timing detecting circuit 14 and output to the transistor turn-on control circuit 16. In addition, the input voltage phase timing detecting circuit 14 outputs the voltage-divided voltage from the source terminal to the transistor conduction control circuit 16, but the design is not limited to the design that must be divided, but may be based on the actual circuit. The design is sized by resistors R7, R8, R9, and R10. Moreover, the circuit in the figure is only an example, and is not limited to the design of the input voltage phase timing detecting circuit 14, but any circuit that can adjust the peak value of the input voltage Vi belongs to the range of the input voltage phase timing detecting circuit 14, for example Voltage level shifting circuit.
請參閱第2B圖及第2C圖，其係為輸入電壓及輸入電壓相位時序偵測電路輸出訊號的時序圖。在經過輸入電壓相位時序偵測電路14調整過輸入電壓Vi的峰值後，可將輸入電壓Vi由高壓轉換為低壓。為了清楚波形的變化，於圖示中並未依照大小比例繪製。此外，由第2B圖可看出輸入電壓Vi並不限於線性或非線性的訊號，其包括線性或非線性之任意波形的電 壓。 Please refer to FIG. 2B and FIG. 2C, which are timing diagrams of input voltage and input voltage phase timing detection circuit output signals. After the input voltage phase timing detecting circuit 14 adjusts the peak value of the input voltage Vi, the input voltage Vi can be converted from a high voltage to a low voltage. In order to clarify the change of the waveform, it is not drawn according to the size ratio in the illustration. In addition, it can be seen from FIG. 2B that the input voltage Vi is not limited to a linear or non-linear signal, and includes a linear or non-linear arbitrary waveform of electricity. Pressure.
請參閱第3A圖，其係為電流相位時序偵測電路的電路圖，第3B圖及第3C圖係為電流相位時序偵測電路的輸入訊號、輸出訊號以及輸入電壓的時序圖。電流相位時序偵測電路12用於放大偵測的電流訊號，其輸入端Vs的訊號來自一般變壓器或電阻的感應器訊號，並連接橋式整流電路(參閱第2A圖)，經過放大器U1放大電流訊號後，由比較器U2及V2電壓比較後，由輸出端輸出電壓相位與導通時間的訊號至電晶體導通控制電路16。電流相位時序偵測電路12包括的電阻R13、R14、R15、R17、R18、電容C2及定電壓V1、V2、V4，其連接關係及詳細的作動原理於此並不詳述，其中V+及V-係為正、負電端。相似地，圖示中的電路僅作為示例，並非侷限電流相位時序偵測電路12的設計，而是可放大電流訊號的任意電路均屬於電流相位時序偵測電路12的範疇，例如電流偵測器。 Please refer to FIG. 3A, which is a circuit diagram of a current phase timing detection circuit, and FIG. 3B and FIG. 3C are timing diagrams of input signals, output signals, and input voltages of the current phase timing detection circuit. The current phase timing detecting circuit 12 is configured to amplify the detected current signal, and the signal of the input terminal Vs is from the sensor signal of the general transformer or the resistor, and is connected to the bridge rectifier circuit (refer to FIG. 2A), and the current is amplified by the amplifier U1. After the signal is compared, after the voltages of the comparators U2 and V2 are compared, the voltage phase and the on-time signal are output from the output terminal to the transistor conduction control circuit 16. The current phase timing detecting circuit 12 includes resistors R13, R14, R15, R17, and R18, a capacitor C2, and constant voltages V1, V2, and V4. The connection relationship and detailed operation principle are not described in detail herein, wherein V+ and V are - The system is positive and negative. Similarly, the circuit in the figure is only an example, and is not limited to the design of the current phase timing detecting circuit 12, but any circuit that can amplify the current signal belongs to the category of the current phase timing detecting circuit 12, such as a current detector. .
請參閱第4A圖，其係為電晶體導通控制電路的邏輯電路圖。電晶體導通控制電路16係由複數個邏輯及閘U3、U4組成，並接收輸入電壓相位時序偵測電路14的輸出訊號VRVDN、VRVDL、單穩態電路15的訊號以及電流相位時序偵測電路12的輸出訊號Viload，以產生邏輯控制訊號Vgp、Vgn至複數個高壓側及低壓側驅動電路13，使複數個高壓側及低壓側驅動電路13根據至少一邏輯控制訊號Vgp、Vgn作動。 Please refer to FIG. 4A, which is a logic circuit diagram of the transistor conduction control circuit. The transistor conduction control circuit 16 is composed of a plurality of logic and gates U3, U4, and receives the output signals VRVDN, VRVDL of the input voltage phase timing detecting circuit 14, the signal of the monostable circuit 15, and the current phase timing detecting circuit 12 The output signal Viload generates the logic control signals Vgp and Vgn to the plurality of high-voltage side and low-voltage side driving circuits 13, and activates the plurality of high-voltage side and low-voltage side driving circuits 13 according to the at least one logic control signals Vgp and Vgn.
第4B圖係為各個訊號的相位導通時序圖。輸入至 電晶體導通控制電路16的邏輯及閘U3、U4後，產生邏輯控制訊號Vgp、Vgn。此外，單穩態電路15係由一時脈訊號18輸入，相較於其它訊號的頻率(Hz)，其係為更高的一高頻訊號(KHz)，因此並未繪示於圖示中。時脈訊號18來自於方波震盪電路或者包含有PWM訊號的負載電路所產生的訊號。由於外部來源的訊號或是本身電路產生訊號的工作週期(duty cycle)並非固定不變，因此，利用單穩態電路15可以把訊號的工作週期調整為固定週期。 Figure 4B is a phase conduction timing diagram of each signal. Input to After the transistor turns on the logic of the control circuit 16 and the gates U3 and U4, logic control signals Vgp and Vgn are generated. In addition, the monostable circuit 15 is input by a clock signal 18, which is a higher frequency (KHz) than the frequency (Hz) of other signals, and thus is not shown in the drawing. The clock signal 18 is derived from a square wave oscillating circuit or a signal generated by a load circuit including a PWM signal. Since the external source signal or the duty cycle of the signal generated by the circuit itself is not fixed, the monostable circuit 15 can be used to adjust the duty cycle of the signal to a fixed period.
請參閱第5A圖及第5B圖，其係為高壓側及低壓側驅動電路以及電壓準位維持驅動電路的電路圖及方塊示意圖。高壓側及低壓側驅動電路13的輸入端接收電晶體導通控制電路16產生的邏輯控制訊號Vgp、Vgn，以根據邏輯控制訊號Vgp、Vgn的準位開啟或關閉。複數個電壓準位維持驅動電路11電性連接橋式整流電路四個MOSFET電晶體Q1、Q2、Q3、Q4之閘極端，其閘極端電壓分別為VgsQ1、VgsQ2、VgsQ3、VgsQ4，使四個MOSFET電晶體Q1、Q2、Q3、Q4分別根據複數個高壓側及低壓側驅動電路13產生的至少一驅動訊號作動。 Please refer to FIG. 5A and FIG. 5B , which are circuit diagrams and block diagrams of the high-voltage side and low-voltage side driving circuits and the voltage level maintaining driving circuit. The input terminals of the high-voltage side and low-voltage side driving circuit 13 receive the logic control signals Vgp, Vgn generated by the transistor conduction control circuit 16 to be turned on or off according to the levels of the logic control signals Vgp, Vgn. A plurality of voltage level sustaining driving circuits 11 are electrically connected to the gate terminals of the four MOSFET transistors Q1, Q2, Q3, and Q4 of the bridge rectifier circuit, and the gate voltages thereof are VgsQ1, VgsQ2, VgsQ3, and VgsQ4, respectively, so that four MOSFETs are provided. The transistors Q1, Q2, Q3, and Q4 are each actuated according to at least one driving signal generated by the plurality of high side and low side driving circuits 13.
進一步而言，在第5A圖的電路圖中，以邏輯控制訊號Vgp為高訊號準位為例，高壓側及低壓側驅動電路13係開啟作動，習知技藝者應可透過電路圖由各個元件(邏輯及閘U5、二極體D5~D13、電晶體Q7~Q11、電容C3~C7及電阻R19~R29)的連接關係推斷出高壓側及低壓側驅動電路13的作 動，於此不再贅述。電壓準位維持驅動電路11用於維持導通訊號的準位，使得各個電壓準位維持驅動電路11對應連接橋式整流電路的MOSFET電晶體Q1、Q2、Q3、Q4在需要導通時導通。例如，在輸入訊號Vi為正半週時，導通MOSFET電晶體Q1、Q4，輸入訊號Vi為負半週時，導通MOSFET電晶體Q2、Q3。 Further, in the circuit diagram of FIG. 5A, taking the logic control signal Vgp as the high signal level as an example, the high-voltage side and low-voltage side driving circuit 13 are activated, and the skilled artisan should be able to pass the circuit diagram from each component (logic The connection relationship between the gate U5, the diodes D5 to D13, the transistors Q7 to Q11, the capacitors C3 to C7, and the resistors R19 to R29) infers the operation of the high-voltage side and low-voltage side driver circuits 13. Move, no longer repeat here. The voltage level maintaining driving circuit 11 is configured to maintain the level of the conduction communication number, so that the respective voltage level maintaining driving circuit 11 is connected to the MOSFET transistors Q1, Q2, Q3, and Q4 connected to the bridge rectifier circuit when conduction is required. For example, when the input signal Vi is positive half cycle, the MOSFET transistors Q1 and Q4 are turned on, and when the input signal Vi is negative half cycle, the MOSFET transistors Q2 and Q3 are turned on.
第5C圖係為邏輯控制訊號Vgp、Vgn以及整流電路四個MOSFET電晶體Q1、Q2、Q3、Q4之閘極端電壓VgsQ1、VgsQ2、VgsQ3、VgsQ4的導通時序圖，由圖中可清楚了解橋式整流電路的MOSFET電晶體Q1、Q2、Q3、Q4僅在對應的邏輯控制訊號Vgp、Vgn導通時開啟。 Figure 5C shows the turn-on timing diagrams of the gate voltages VgsQ1, VgsQ2, VgsQ3, and VgsQ4 of the logic control signals Vgp, Vgn and the four MOSFET transistors Q1, Q2, Q3, and Q4 of the rectifier circuit. The MOSFET transistors Q1, Q2, Q3, and Q4 of the rectifier circuit are turned on only when the corresponding logic control signals Vgp, Vgn are turned on.
此外，高壓側及低壓側驅動電路13以及電壓準位維持驅動電路11之間係以例如變壓器的轉換電路TR1、TR2作為耦接，因此，並不需要在電路之外額外提供電源。進一步而言，以邏輯控制訊號Vgp為例，邏輯控制訊號Vgp在經過高壓側及低壓側驅動電路13之後，驅動轉換電路TR1，以自轉換電路TR1的N1側(高壓側及低壓側驅動電路13側)轉換訊號至N2側(電壓準位維持驅動電路11側)，並以此訊號準位驅動連接的橋式整流電路的MOSFET電晶體Q1，另一端未經過轉換電路TR1轉換的邏輯控制訊號Vgp則經由電壓準位維持驅動電路11之後驅動連接橋式整流電路的MOSFET電晶體Q4。因此，本發明並不需要使用浮動電源電路供電(floating voltage supply)作為驅動橋式整流電路的電源，亦即，不需要在電晶體Q1及 Q2側提供驅動電源。 Further, the high-voltage side and low-voltage side drive circuits 13 and the voltage level sustain drive circuit 11 are coupled by, for example, transformer conversion circuits TR1 and TR2, and therefore, it is not necessary to additionally provide power supply outside the circuit. Further, taking the logic control signal Vgp as an example, the logic control signal Vgp drives the conversion circuit TR1 after passing through the high-voltage side and low-voltage side drive circuit 13 to the N1 side of the self-conversion circuit TR1 (the high-voltage side and the low-voltage side drive circuit 13). The side is switched to the N2 side (the voltage level maintains the drive circuit 11 side), and the MOSFET transistor Q1 of the bridge rectifier circuit connected to the signal is driven by the signal level, and the logic control signal Vgp of the other end is not converted by the conversion circuit TR1. Then, the MOSFET transistor Q4 connected to the bridge rectifier circuit is driven after the drive circuit 11 is maintained via the voltage level. Therefore, the present invention does not need to use a floating power supply as a power source for driving the bridge rectifier circuit, that is, it does not need to be in the transistor Q1 and The Q2 side provides drive power.
再者，應用於各種線性與非線性輸入及負載之整流電路更包括一禁能(disable)電路19，電性連接複數個高壓側及低壓側驅動電路13，並接收電晶體導通控制電路16之至少一邏輯控制訊號Vgp、Vgn，以產生至少一禁能訊號，使複數個高壓側及低壓側驅動電路13根據至少一禁能訊號停止作動，因而可避免橋式整流電路的MOSFET電晶體Q1、Q2、Q3、Q4在受到外部的干擾訊號時，使不需要導通的MOSFET電晶體導通，亦即避免MOSFET電晶體Q1、Q3與MOSFET電晶體Q2、Q4發生短路。因此，禁能電路19係具有保護電路的功效。相似地，其準位訊號的作動，習知技藝者應可透過電路圖推斷出禁能電路19的作動，進一步判斷是否禁能其電性連接的高壓側及低壓側驅動電路11、13，於此不再贅述。 Furthermore, the rectifying circuit applied to various linear and non-linear inputs and loads further includes a disable circuit 19 electrically connected to the plurality of high-voltage side and low-voltage side driving circuits 13 and receiving the transistor conduction control circuit 16 The at least one logic control signal Vgp, Vgn is configured to generate at least one disable signal, so that the plurality of high-voltage side and low-voltage side driving circuits 13 stop operating according to the at least one disable signal, thereby avoiding the MOSFET transistor Q1 of the bridge rectifier circuit. When Q2, Q3, and Q4 are subjected to external interference signals, the MOSFET transistors that do not need to be turned on are turned on, that is, the short circuits of the MOSFET transistors Q1 and Q3 and the MOSFET transistors Q2 and Q4 are avoided. Therefore, the disable circuit 19 has the effect of protecting the circuit. Similarly, the operation of the level signal, the skilled artisan should be able to infer the operation of the disable circuit 19 through the circuit diagram, and further determine whether the high-voltage side and low-voltage side drive circuits 11, 13 are electrically disabled. No longer.
綜上所述，本發明的應用於各種線性與非線性輸入及負載之整流電路藉由同時偵測輸入訊號的電壓導通相位以及及總線路上電流的導通相位，決定橋式整流電路上開關元件的導通時間，因此可在達到高效率的同時，使橋式整流電路可運用在任意波形的輸入訊號以及線性或非線性電路的各種組合上，進一步提升電源使用效率以及減少電路設計的複雜度，亦可避免電路產生誤動作。此外，習知技術中的浮接式開關元件驅動電路必須額外提供電壓源作為驅動電源，但於本發明中係使用內建震盪電路或是外接輸入時脈訊號驅動，經單穩 態電路調整工作週期驅動隔離變壓器，其並不需要外加供應電源，因此，即使在輸入訊號為極長週期的交流電、直流電或任意波形的情況下亦可正常作動。 In summary, the rectifier circuit of the present invention applied to various linear and non-linear input and load determines the switching element of the bridge rectifier circuit by simultaneously detecting the voltage conduction phase of the input signal and the conduction phase of the current on the bus line. On-time, so that the bridge rectifier circuit can be used in any combination of arbitrary waveform input signals and linear or non-linear circuits while achieving high efficiency, further improving power supply efficiency and reducing circuit design complexity. Can avoid circuit malfunction. In addition, the floating-type switching element driving circuit in the prior art must additionally provide a voltage source as a driving power source, but in the present invention, the built-in oscillation circuit or an external input clock signal is used to drive the signal. The state circuit adjusts the duty cycle to drive the isolation transformer, which does not require an external power supply. Therefore, it can operate normally even when the input signal is an extremely long period of alternating current, direct current or arbitrary waveform.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105143840A TWI619335B (en) | 2016-12-29 | 2016-12-29 | Rectifier circuit for various linear and nonlinear inputs and loads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105143840A TWI619335B (en) | 2016-12-29 | 2016-12-29 | Rectifier circuit for various linear and nonlinear inputs and loads |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI619335B true TWI619335B (en) | 2018-03-21 |
| TW201824714A TW201824714A (en) | 2018-07-01 |
Family
ID=62189438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105143840A TWI619335B (en) | 2016-12-29 | 2016-12-29 | Rectifier circuit for various linear and nonlinear inputs and loads |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI619335B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI677179B (en) * | 2018-11-29 | 2019-11-11 | 國立中興大學 | A fully integrated active ac to dc rectifier |
| US10601302B1 (en) * | 2019-04-04 | 2020-03-24 | Navitas Semiconductor, Inc. | Bootstrap power supply circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060187686A1 (en) * | 2005-02-21 | 2006-08-24 | Chaoqun Sun | LLC series resonant converter and the driving method for the synchronous rectification power switches thereof |
| TW200919925A (en) * | 2007-10-16 | 2009-05-01 | Delta Electronics Inc | Resonant converter system having synchronous rectifier control circuit and controlling method thereof |
| TW201042897A (en) * | 2009-05-18 | 2010-12-01 | Silitek Electronic Guangzhou | Resonant converting apparatus and synchronous rectification circuit |
| CN204794688U (en) * | 2015-07-14 | 2015-11-18 | 成都铭庆电子科技有限公司 | DC power supply pulse load adapter |
-
2016
- 2016-12-29 TW TW105143840A patent/TWI619335B/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060187686A1 (en) * | 2005-02-21 | 2006-08-24 | Chaoqun Sun | LLC series resonant converter and the driving method for the synchronous rectification power switches thereof |
| TW200919925A (en) * | 2007-10-16 | 2009-05-01 | Delta Electronics Inc | Resonant converter system having synchronous rectifier control circuit and controlling method thereof |
| TW201042897A (en) * | 2009-05-18 | 2010-12-01 | Silitek Electronic Guangzhou | Resonant converting apparatus and synchronous rectification circuit |
| CN204794688U (en) * | 2015-07-14 | 2015-11-18 | 成都铭庆电子科技有限公司 | DC power supply pulse load adapter |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201824714A (en) | 2018-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9614448B2 (en) | Switching power-supply device | |
| JP4687958B2 (en) | DC-DC converter | |
| JP5991078B2 (en) | Switching power supply | |
| JP2013020931A (en) | Led lighting apparatus | |
| US10326356B2 (en) | Boost power factor correction circuit, driving circuit for light-emitting diode and lighting device | |
| KR101889108B1 (en) | Apparatus for power converter reducing the standby power consumption | |
| KR20070095234A (en) | High-efficiency electric power supply circuit and electronic device having the same | |
| KR101171042B1 (en) | Light emitting device driving circuit | |
| JP2014202632A (en) | Zero-crossing detection circuit | |
| JP5040268B2 (en) | Switching power supply | |
| TWI619335B (en) | Rectifier circuit for various linear and nonlinear inputs and loads | |
| KR20070110997A (en) | Switch driving device, half bridge converter using the switch driving device and the operating method of half bridge converter | |
| JP4788805B2 (en) | Semiconductor switching element drive circuit | |
| US9800173B1 (en) | Rectification circuit for using in all types of linear and nonlinear input and loading | |
| KR20140034065A (en) | Ionizer | |
| TWI657250B (en) | Current detection method | |
| CN104143905A (en) | Quick start control circuit of converter | |
| TWM496905U (en) | LED driving circuit with improved performance and utilization rate | |
| CN108336918B (en) | Rectifier circuit applied to various linear and nonlinear inputs and loads | |
| JP5823248B2 (en) | AC / DC inverter device and control method of AC / DC inverter device | |
| CN203289708U (en) | A multi-loop current-limiting power supply circuit | |
| CN111225478B (en) | Switch module protection circuit | |
| TW202106110A (en) | Driving device | |
| JP2010027406A (en) | Antiphase controller, and antiphase illumination control system using the same | |
| JP6282213B2 (en) | Power converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |