TWI619264B - Optoelectronic device and method for manufacturing the same - Google Patents

Abstract

一種製造一光電元件之方法，包含下列步驟：提供一成長基板；形成一過渡層於成長基板之上；形成一半導體疊層於過渡層之上；對半導體疊層及過渡層進行一第一蝕刻以形成至少一溝渠，其中溝渠將半導體疊層及過渡層分隔為複數個半導體島及複數個過渡層島，且裸露出部分成長基板；提供一承載基板連接些半導體島；以及進行一第二蝕刻以移除成長基板。 A method of fabricating a photovoltaic element, comprising the steps of: providing a growth substrate; forming a transition layer over the growth substrate; forming a semiconductor layer over the transition layer; and performing a first etch on the semiconductor stack and the transition layer Forming at least one trench, wherein the trench divides the semiconductor stack and the transition layer into a plurality of semiconductor islands and a plurality of transition layer islands, and exposes a portion of the grown substrate; providing a carrier substrate to connect the semiconductor islands; and performing a second etching To remove the growth substrate.

Description

光電元件及其製造方法 Photoelectric element and method of manufacturing same

本發明係關於一種光電元件，尤其是關於一種光電元件基板置換的方法。 The present invention relates to a photovoltaic element, and more particularly to a method of substrate replacement of a photovoltaic element.

發光二極體(light-emitting diode,LED)的發光原理是利用電子在n型半導體與p型半導體間移動的能量差，以光的形式將能量釋放，這樣的發光原理係有別於白熾燈發熱的發光原理，因此發光二極體被稱為冷光源。此外，發光二極體具有高耐久性、壽命長、輕巧、耗電量低等優點，因此現今的照明市場對於發光二極體寄予厚望，將其視為新一代的照明工具，已逐漸取代傳統光源，並且應用於各種領域，如交通號誌、背光模組、路燈照明、醫療設備等。 The principle of light-emitting diode (LED) is to use energy difference between the n-type semiconductor and the p-type semiconductor to release energy in the form of light. This principle of illumination is different from incandescent lamps. The principle of heat generation, so the light-emitting diode is called a cold light source. In addition, the light-emitting diode has the advantages of high durability, long life, light weight, low power consumption, etc., so the current lighting market has high hopes for the light-emitting diode, and it is gradually replaced as a new generation of lighting tools. Light source, and is used in various fields, such as traffic signs, backlight modules, street lighting, medical equipment, etc.

第1圖係習知之發光元件結構示意圖，如第1圖所示，習知之發光元件100，包含有一透明基板10、一位於透明基板10上之半導體疊層12，以及至少一電極14位於上述半導體疊層12上，其中上述之半導體疊層12由上而下至少包含一第一導電型半導體層120、一活性層122，以及一第二導電型半導體層124。 1 is a schematic view showing the structure of a conventional light-emitting element. As shown in FIG. 1, a conventional light-emitting element 100 includes a transparent substrate 10, a semiconductor laminate 12 on a transparent substrate 10, and at least one electrode 14 located in the semiconductor. On the stack 12, the semiconductor stack 12 includes at least a first conductive semiconductor layer 120, an active layer 122, and a second conductive semiconductor layer 124 from top to bottom.

此外，上述之發光元件100更可以進一步地與其他元件組合連接以形成一發光裝置(light-emitting apparatus)。第2圖為習知之發光裝置結構示意圖，如第2圖所示，一發光裝置200包含一具有至少一電路202之次載體(sub-mount)20；至少一焊料(solder)22位於上述次載體20上，藉由此焊料22將上述發光元件100黏結固定於次載體20上並使發光元件100之基板10與次載體20上之電路202形成電連接；以及，一電性連接結構24，以電性連接發光元件100之電極14與次載體20上之電路202；其中，上述次載 體20可以是導線架(lead frame)或大尺寸鑲嵌基底(mounting substrate)，以方便發光裝置200之電路規劃並提高其散熱效果。 In addition, the above-described light-emitting element 100 can be further combined with other elements to form a light-emitting apparatus. 2 is a schematic view showing the structure of a conventional light-emitting device. As shown in FIG. 2, a light-emitting device 200 includes a sub-mount 20 having at least one circuit 202; at least one solder 22 is located in the above-mentioned sub-carrier 20, the light-emitting element 100 is bonded and fixed to the secondary carrier 20 by the solder 22, and the substrate 10 of the light-emitting element 100 is electrically connected to the circuit 202 on the secondary carrier 20; and an electrical connection structure 24 is Electrically connecting the electrode 14 of the light-emitting element 100 with the circuit 202 on the secondary carrier 20; wherein, the second load The body 20 can be a lead frame or a large-sized mounting substrate to facilitate circuit planning of the light-emitting device 200 and improve its heat dissipation effect.

然而，如第1圖所示，於習知之發光元件100中，由於透明基板10之表面係一平整表面，且透明基板10之折射率與外部環境之折射率不同，因此活性層122所發出之光線A由基板進入外部環境時，容易形成全反射(Total Internal Reflection,TIR)，降低發光元件100之光摘出效率。 However, as shown in FIG. 1, in the conventional light-emitting element 100, since the surface of the transparent substrate 10 is a flat surface, and the refractive index of the transparent substrate 10 is different from the refractive index of the external environment, the active layer 122 is emitted. When the light A enters the external environment from the substrate, total internal reflection (TIR) is easily formed, and the light extraction efficiency of the light-emitting element 100 is lowered.

一種製造一光電元件之方法，包含下列步驟：提供一成長基板；形成一緩衝層於成長基板之上，其中緩衝層完整覆蓋成長基板；形成一半導體疊層於緩衝層之上；對半導體疊層及緩衝層進行一第一蝕刻以形成至少一溝渠，其中溝渠將半導體疊層及過渡層分隔為複數個半導體島及複數個過渡層島，且裸露出部分成長基板；提供一承載基板連接些半導體島；以及進行一第二蝕刻以移除成長基板。 A method of fabricating a photovoltaic element, comprising the steps of: providing a growth substrate; forming a buffer layer over the growth substrate, wherein the buffer layer completely covers the growth substrate; forming a semiconductor layer over the buffer layer; And the buffer layer performs a first etching to form at least one trench, wherein the trench divides the semiconductor stack and the transition layer into a plurality of semiconductor islands and a plurality of transition layer islands, and exposes a portion of the growth substrate; and provides a carrier substrate to connect the semiconductors Island; and performing a second etch to remove the grown substrate.

第1圖為一結構圖，顯示一習知發光二極體元件側視結構圖；第2圖為一示意圖，顯示一習知發光裝置結構示意圖；第3A-3J圖為本發明實施例製造流程結構示意圖；第4圖係顯示本發明設計之上視圖照片；第5A圖至第5C圖係繪示出一發光模組示意圖；第6A-6B圖係繪示出一光源產生裝置示意圖；及第7圖係繪示一燈泡示意圖。 1 is a structural view showing a side view of a conventional light-emitting diode element; FIG. 2 is a schematic view showing a structure of a conventional light-emitting device; and FIG. 3A-3J is a manufacturing process of an embodiment of the present invention; Figure 4 is a schematic view showing a top view of the design of the present invention; Figures 5A to 5C are schematic views showing a light-emitting module; and Figures 6A-6B are a schematic view showing a light source generating device; Figure 7 shows a schematic diagram of a light bulb.

本發明揭示一種發光元件及其製造方法，為了使本發明之敘述更加詳盡與完備，請參照下列描述並配合第3A圖至第7圖之圖示。 The present invention discloses a light-emitting element and a method of manufacturing the same. In order to make the description of the present invention more detailed and complete, please refer to the following description and cooperate with the drawings of FIGS. 3A to 7.

第3A圖至第3J圖為本發明實施例製造流程結構示意圖，如 第3A圖所示，提供一基板30，並形成一過渡層32於此基板30之上，接著形成一半導體磊晶疊層34於過渡層32上，其中半導體磊晶疊層34包含一第一導電型半導體層341、一活性層342，以及一第二導電型半導體層343。 3A to 3J are schematic diagrams showing the structure of a manufacturing process according to an embodiment of the present invention, such as As shown in FIG. 3A, a substrate 30 is provided and a transition layer 32 is formed over the substrate 30, followed by a semiconductor epitaxial layer 34 on the transition layer 32, wherein the semiconductor epitaxial layer 34 includes a first A conductive semiconductor layer 341, an active layer 342, and a second conductive semiconductor layer 343.

基板30係為一成長及/或承載基礎。候選材料可包含導電基板或不導電基板、透光基板或不透光基板。其中導電基板材料其一可為鍺(Ge)、砷化鎵(GaAs)、銦化磷(InP)、碳化矽(SiC)、矽(Si)、鋁酸鋰(LiAlO₂)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)、金屬。透光基板材料其一可為藍寶石(Sapphire)、鋁酸鋰(LiAlO₂)、氧化鋅(ZnO)、氮化鎵(GaN)、玻璃、鑽石、CVD鑽石、與類鑽碳(Diamond-Like Carbon；DLC)、尖晶石(spinel,MgAl₂O₄)、氧化矽(SiO_X)及鎵酸鋰(LiGaO₂)。過渡層32之材料可選自矽的氧化物或矽的氮化物。 The substrate 30 is a growth and/or carrier foundation. The candidate material may comprise a conductive substrate or a non-conductive substrate, a light transmissive substrate or an opaque substrate. One of the conductive substrate materials may be germanium (Ge), gallium arsenide (GaAs), indium phosphate (InP), tantalum carbide (SiC), germanium (Si), lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO). ), gallium nitride (GaN), aluminum nitride (AlN), metal. One of the transparent substrate materials may be sapphire, lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, and diamond-like carbon (Diamond-Like Carbon). ; DLC), spinel (MgAl ₂ O ₄ ), yttrium oxide (SiO _X ), and lithium gallate (LiGaO ₂ ). The material of the transition layer 32 may be selected from the group consisting of tantalum oxides or tantalum nitrides.

上述第一半導體層341、活性層342以及第二半導體層343之材料可包含一種或一種以上之元素選自鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)以及矽(Si)所構成群組。常用之材料係如磷化鋁鎵銦(AlGaInP)系列、氮化鋁鎵銦(AlGaInN)系列等III族氮化物、氧化鋅(ZnO)系列等。 The material of the first semiconductor layer 341, the active layer 342, and the second semiconductor layer 343 may include one or more elements selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), and phosphorus ( A group consisting of P), nitrogen (N), and bismuth (Si). Commonly used materials are such as Group III nitrides such as aluminum gallium indium phosphide (AlGaInP) series and aluminum gallium indium nitride (AlGaInN) series, and zinc oxide (ZnO) series.

如第3B~3C圖所示，形成第一電極36於半導體磊晶疊層34之第一表面34T之上。接著，形成一第一連接層38於上述第一金屬層36及半導體磊晶疊層34之上。在一實施例中，第一連接層38與部分半導體磊晶疊層34之第一表面34T直接接觸。 As shown in FIGS. 3B-3C, the first electrode 36 is formed over the first surface 34T of the semiconductor epitaxial stack 34. Next, a first connection layer 38 is formed over the first metal layer 36 and the semiconductor epitaxial laminate 34. In one embodiment, the first tie layer 38 is in direct contact with the first surface 34T of the portion of the semiconductor epitaxial stack 34.

接著，如第3D圖所示，對半導體疊層34及第一連接層38進行一第一蝕刻以形成至少一溝渠T，其中溝渠T將半導體疊層34及第一連接層38分隔為複數個半導體島34i及複數個第一連接層島38i。在一實施例中，每一半導體島34i之上表面具有一第一金屬層36。 Next, as shown in FIG. 3D, the semiconductor laminate 34 and the first connection layer 38 are first etched to form at least one trench T, wherein the trench T separates the semiconductor laminate 34 and the first connection layer 38 into a plurality of trenches T. The semiconductor island 34i and the plurality of first connection layer islands 38i. In one embodiment, each semiconductor island 34i has a first metal layer 36 on its upper surface.

接著，如第3E圖所示，從溝渠T對過渡層32繼續進行上述第一蝕刻，以在每個半導體島34i之下形成至少一個過渡層島32i，且裸露出部分基板30。在一實施例中，因為相較於半導體層34第一蝕刻對過渡層32有較強之蝕刻效率，因此上述過渡層島32i之兩邊緣相對半導體島34i之兩邊緣可具有一底切U形狀。在一實施例中，上述第一 蝕刻可為一化學蝕刻，且蝕刻液可選自氫氟酸(Hydrofluoric acid,HF)、緩衝式氧化物蝕刻液(Buffer Oxide Etcher,BOE)或二氧化矽蝕刻液(Surfactanated Buffered Oxide Etchants,SBOE)。在一實施例中，上述第一蝕刻之時間可為20-50分鐘，蝕刻液濃度可為30-60%。 Next, as shown in FIG. 3E, the first etching is continued from the trench T to the transition layer 32 to form at least one transition layer island 32i under each semiconductor island 34i, and a portion of the substrate 30 is exposed. In one embodiment, since the first etch has a higher etching efficiency to the transition layer 32 than the semiconductor layer 34, both edges of the transition layer island 32i may have an undercut U shape with respect to both edges of the semiconductor island 34i. . In an embodiment, the first The etching may be a chemical etching, and the etching solution may be selected from Hydrofluoric Acid (HF), Buffer Oxide Etcher (BOE) or Surfactanated Buffered Oxide Etchants (SBOE). . In one embodiment, the first etching time may be 20-50 minutes, and the etching solution concentration may be 30-60%.

之後，如第3F~3G圖所示，提供一承載基板40，並形成一第二連接層42於承載基板40之上。接下來，以上述第二連接層42及複數個第一連接層島38i進行一連接製程，使上述複數個半導體島34i連接至承載基板40。 Thereafter, as shown in FIGS. 3F to 3G, a carrier substrate 40 is provided, and a second connection layer 42 is formed on the carrier substrate 40. Next, a connection process is performed by the second connection layer 42 and the plurality of first connection layer islands 38i to connect the plurality of semiconductor islands 34i to the carrier substrate 40.

承載基板40之候選材料可包含導電基板或不導電基板、透光基板或不透光基板。其中導電基板材料其一可為鍺(Ge)、砷化鎵(GaAs)、銦化磷(InP)、碳化矽(SiC)、矽(Si)、鋁酸鋰(LiAlO₂)、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)、金屬。透光基板材料其一可為藍寶石(Sapphire)、鋁酸鋰(LiAlO₂)、氧化鋅(ZnO)、氮化鎵(GaN)、玻璃、鑽石、CVD鑽石、與類鑽碳(Diamond-Like Carbon；DLC)、尖晶石(spinel,MgAl₂O₄)、氧化矽(SiO_X)及鎵酸鋰(LiGaO₂)。在一實施例中，上述承載基板40可具有一完整表面，即不具有任何孔洞。 The candidate material of the carrier substrate 40 may include a conductive substrate or a non-conductive substrate, a light-transmitting substrate, or an opaque substrate. One of the conductive substrate materials may be germanium (Ge), gallium arsenide (GaAs), indium phosphate (InP), tantalum carbide (SiC), germanium (Si), lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO). ), gallium nitride (GaN), aluminum nitride (AlN), metal. One of the transparent substrate materials may be sapphire, lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, and diamond-like carbon (Diamond-Like Carbon). ; DLC), spinel (MgAl ₂ O ₄ ), yttrium oxide (SiO _X ), and lithium gallate (LiGaO ₂ ). In an embodiment, the carrier substrate 40 may have a complete surface, ie, without any holes.

之後，如第3H~3I圖所示，對過渡層島32i進行一第二蝕刻以移除此過渡層島32i及基板30，並裸露出半導體島34i之第一表面34B。之後，於上述半導體島34i之第一表面34B之上形成至少一第二電極44。在一實施例中，上述第二蝕刻可為一化學蝕刻，且蝕刻液可選自氫氟酸(Hydrofluoric acid,HF)、緩衝式氧化物蝕刻液(Buffer Oxide Etcher,BOE)或二氧化矽蝕刻液(Surfactanated Buffered Oxide Etchants,SBOE)。在一實施例中，上述第一蝕刻之時間可為20-50分鐘、或40-60分鐘、或60-90分鐘、或90-120分鐘、或120-150分鐘、或150-180分鐘、或180-240分鐘，蝕刻液濃度可為30-60%。藉由上述實施例揭露的溝渠T，可使得第二蝕刻所需要之時間由一天減少為數個小時，而可大幅的增加製程產出效率。 Thereafter, as shown in FIG. 3H to FIG. 3I, a second etching is performed on the transition layer island 32i to remove the transition layer island 32i and the substrate 30, and the first surface 34B of the semiconductor island 34i is exposed. Thereafter, at least one second electrode 44 is formed over the first surface 34B of the semiconductor island 34i. In one embodiment, the second etching may be a chemical etching, and the etching solution may be selected from the group consisting of hydrofluoric acid (HF), Buffer Oxide Etcher (BOE) or cerium oxide etching. Surfactanated Buffered Oxide Etchants (SBOE). In an embodiment, the first etching time may be 20-50 minutes, or 40-60 minutes, or 60-90 minutes, or 90-120 minutes, or 120-150 minutes, or 150-180 minutes, or The etchant concentration can be 30-60% for 180-240 minutes. With the trench T disclosed in the above embodiment, the time required for the second etching can be reduced from one day to several hours, and the process yield efficiency can be greatly increased.

在一實施例中，第一電極36或第二電極44之材料包含但不限於銅(Cu)、鋁(Al)、銦(In)、錫(Sn)、金(Au)、鉑(Pt)、鋅(Zn)、銀(Ag)、 鈦(Ti)、鎳(Ni)、鉛(Pb)、鈀(Pd)、鍺(Ge)、鉻(Cr)、鎘(Cd)、鈷(Co)、錳(Mn)、銻(Sb)、鉍(Bi)、鎵(Ga)、鉈(Tl)、釙(Po)、銥(Ir)、錸(Re)、銠(Rh)、鋨(Os)、鎢(W)、鋰(Li)、鈉(Na)、鉀(K)、鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)、鋇(Ba)、鋯(Zr)、鉬(Mo)、鈉(La)、銀-鈦(Ag-Ti)、銅-錫(Cu-Sn)、銅-鋅(Cu-Zn)、銅-鎘(Cu-Cd)、錫-鉛-銻(Sn-Pb-Sb)、錫-鉛-鋅(Sn-Pb-Zn)、鎳-錫(Ni-Sn)、鎳-鈷(Ni-Co)、金合金(Au alloy)、或鍺-金-鎳(Ge-Au-Ni)等金屬材料。 In an embodiment, the material of the first electrode 36 or the second electrode 44 includes, but is not limited to, copper (Cu), aluminum (Al), indium (In), tin (Sn), gold (Au), platinum (Pt). , zinc (Zn), silver (Ag), Titanium (Ti), nickel (Ni), lead (Pb), palladium (Pd), germanium (Ge), chromium (Cr), cadmium (Cd), cobalt (Co), manganese (Mn), antimony (Sb), Bi (Bi), gallium (Ga), thallium (Tl), antimony (Po), antimony (Ir), antimony (Re), antimony (Rh), antimony (Os), tungsten (W), lithium (Li), Sodium (Na), potassium (K), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zirconium (Zr), molybdenum (Mo), sodium (La), Silver-titanium (Ag-Ti), copper-tin (Cu-Sn), copper-zinc (Cu-Zn), copper-cadmium (Cu-Cd), tin-lead-bismuth (Sn-Pb-Sb), tin - lead-zinc (Sn-Pb-Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni-Co), gold alloy (Au alloy), or bismuth-gold-nickel (Ge-Au-Ni) Metal materials.

最後，如第3J圖所示，在一實施例中，可切割第二連接層42及承載基板40而完成依本發明製程所製作之光電元件300。 Finally, as shown in FIG. 3J, in one embodiment, the second connection layer 42 and the carrier substrate 40 can be diced to complete the photovoltaic device 300 fabricated in accordance with the process of the present invention.

第4圖係顯示本發明設計之上視圖照片，如照片所示，係顯示出依本發明製程所製作之光電元件300中的半導體島34i之部分第一表面34B為一粗糙表面M，此粗糙表面乃是一上述製程中對過渡層島32i進行一第二蝕刻而移過渡層島32i後所造成之粗糙面。在一實施例中，上述粗糙表面M係形成在半導體島34i之部分第一表面34B之幾何中心區域。 Figure 4 is a top view photo showing the design of the present invention. As shown in the photograph, a portion of the first surface 34B of the semiconductor island 34i in the photovoltaic element 300 fabricated in accordance with the process of the present invention is a rough surface M. The surface is a rough surface caused by a second etching of the transition layer island 32i and shifting the transition layer island 32i in the above process. In one embodiment, the rough surface M is formed in a geometric central region of a portion of the first surface 34B of the semiconductor island 34i.

第5A圖至第5C圖係繪示出一發光模組示意圖，第5A圖係顯示一發光模組外部透視圖，一發光模組500可包含一載體502，複數個透鏡504、506、508及510，及兩電源供應終端512及514。 5A to 5C are schematic views showing a light emitting module, and FIG. 5A is a perspective view showing an external light emitting module. The light emitting module 500 can include a carrier 502, a plurality of lenses 504, 506, and 508. 510, and two power supply terminals 512 and 514.

第5B-5C圖係顯示一發光模組剖面圖，其中第5C圖係第5B圖之E區的放大圖。載體502可包含一上載體503及下載體501，其中下載體501之一表面可與上載體503接觸。透鏡504及508形成在上載體503之上。上載體503可形成至少一通孔515，而依本發明實施例形成之發光元件300可形成在上述通孔515中並與下載體501接觸，且被膠材521包圍。膠材521之上具有一透鏡508。 Fig. 5B-5C shows a cross-sectional view of a light emitting module, wherein Fig. 5C is an enlarged view of the E area of Fig. 5B. The carrier 502 can include an upper carrier 503 and a download body 501, wherein a surface of the download body 501 can be in contact with the upper carrier 503. Lenses 504 and 508 are formed over upper carrier 503. The upper carrier 503 may form at least one through hole 515, and the light emitting element 300 formed according to the embodiment of the present invention may be formed in the through hole 515 and in contact with the download body 501, and surrounded by the rubber 521. There is a lens 508 above the glue 521.

如第5C圖所示，在一實施例中，通孔515之兩側壁之上可形成一反射層519以增加出光效率；下載體501之下表面可形成一金屬層517以增進散熱效率。 As shown in FIG. 5C, in one embodiment, a reflective layer 519 may be formed on both sidewalls of the via 515 to increase light extraction efficiency; a metal layer 517 may be formed on the lower surface of the download body 501 to improve heat dissipation efficiency.

第6A-6B圖係繪示出一光源產生裝置示意圖600，一光源產生裝置600可包含一發光模組500、一外殼540、一電源供應系統(未顯示)以供應發光模組600一電流、以及一控制元件(未顯示)，用以控制電源供應 系統(未顯示)。光源產生裝置600可以是一照明裝置，例如路燈、車燈或室內照明光源，也可以是交通號誌或一平面顯示器中背光模組的一背光光源。 6A-6B is a schematic diagram 600 of a light source generating device. A light source generating device 600 can include a light emitting module 500, a housing 540, and a power supply system (not shown) for supplying a current to the light emitting module 600. And a control element (not shown) for controlling the power supply System (not shown). The light source generating device 600 can be a lighting device, such as a street light, a car light or an indoor lighting source, or a backlight source of a traffic sign or a backlight module in a flat display.

第7圖係繪示一燈泡示意圖。燈泡900包括一個外殼921，一透鏡922，一照明模組924，一支架925，一散熱器926，一連接部927及一電連接器928。其中照明模組924係包括一載體923，並在載體923上包含至少一個上述實施例中的光電元件300。 Figure 7 is a schematic view of a light bulb. The light bulb 900 includes a housing 921, a lens 922, a lighting module 924, a bracket 925, a heat sink 926, a connecting portion 927 and an electrical connector 928. The illumination module 924 includes a carrier 923 and includes at least one of the photovoltaic elements 300 of the above embodiment on the carrier 923.

上述第一半導體層341及第二半導體層343係電性、極性或摻雜物相異，分別用以提供電子與電洞之半導體材料單層或多層結構(「多層」係指二層或二層以上，以下同。)其電性選擇可以為p型、n型、及i型中至少任意二者之組合。活性層342係位於上述二個部分之電性、極性或摻雜物相異、或者係分別用以提供電子與電洞之半導體材料之間，為電能與光能可能發生轉換或被誘發轉換之區域。電能轉變或誘發光能者係如發光二極體、液晶顯示器、有機發光二極體；光能轉變或誘發電能者係如太陽能電池、光電二極體。活性層342之結構係如：單異質結構(single heterostructure；SH)、雙異質結構(double heterostructure；DH)、雙側雙異質結構(double-side double heterostructure；DDH)、或多層量子井(multi-quantum well；MQW)結構。當光電元件300為一發光二極體，其發光頻譜可以藉由改變半導體單層或多層之物理或化學要素進行調整。再者，調整量子井之對數亦可以改變發光波長。 The first semiconductor layer 341 and the second semiconductor layer 343 are different in electrical conductivity, polarity or dopant, and are respectively used to provide a single or multi-layer structure of a semiconductor material of electrons and holes ("multilayer" means two or two layers. Above the layer, the following is the same.) The electrical selection may be a combination of at least any two of p-type, n-type, and i-type. The active layer 342 is located between the two portions of the electrical, polar or dopant, or between the semiconductor materials for providing electrons and holes, respectively, for the conversion of electrical energy and light energy or induced conversion. region. Those who convert or induce light energy are such as light-emitting diodes, liquid crystal displays, and organic light-emitting diodes; those that convert or induce light energy are such as solar cells and photodiodes. The structure of the active layer 342 is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-layer quantum well (multi- Quantum well; MQW) structure. When the photovoltaic element 300 is a light-emitting diode, its light-emitting spectrum can be adjusted by changing the physical or chemical elements of the semiconductor single layer or multiple layers. Furthermore, adjusting the logarithm of the quantum well can also change the wavelength of the illumination.

於本發明之一實施例中，半導體磊晶疊層34與基板30間尚可選擇性地包含一緩衝層(buffer layer，未顯示)。此緩衝層係介於二種材料系統之間，使基板之材料系統”過渡”至半導體系統之材料系統。對發光二極體之結構而言，一方面，緩衝層係用以降低二種材料間晶格不匹配之材料層。另一方面，緩衝層亦可以是用以結合二種材料或二個分離結構之單層、多層或結構，其可選用之材料係如：有機材料、無機材料、金屬、及半導體等；其可選用之結構係如：反射層、導熱層、導電層、歐姆接觸(ohmic contact)層、抗形變層、應力釋放(stress release)層、應力調整(stress adjustment)層、接合(bonding)層、波長轉換層、及機械固定構造等。 In an embodiment of the invention, the semiconductor epitaxial layer 34 and the substrate 30 may optionally include a buffer layer (not shown). The buffer layer is interposed between the two material systems to "transition" the material system of the substrate to the material system of the semiconductor system. For the structure of the light-emitting diode, on the one hand, the buffer layer is used to reduce the material layer of the lattice mismatch between the two materials. In another aspect, the buffer layer may also be a single layer, a plurality of layers or a structure for combining two materials or two separate structures, such as organic materials, inorganic materials, metals, and semiconductors; The selected structure is: reflective layer, thermally conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment (stress Adjustment) layer, bonding layer, wavelength conversion layer, mechanical fixing structure, and the like.

半導體磊晶疊層34上更可選擇性地形成一接觸層(未顯示)。接觸層係設置於半導體磊晶疊層34遠離基板30之一側。具體而言，接觸層可以為光學層、電學層、或其二者之組合。光學層係可以改變來自於或進入活性層的電磁輻射或光線。在此所稱之「改變」係指改變電磁輻射或光之至少一種光學特性，前述特性係包含但不限於頻率、波長、強度、通量、效率、色溫、演色性(rendering index)、光場(light field)、及可視角(angle of view)。電學層係可以使得接觸層之任一組相對側間之電壓、電阻、電流、電容中至少其一之數值、密度、分布發生變化或有發生變化之趨勢。接觸層之構成材料係包含氧化物、導電氧化物、透明氧化物、具有50%或以上穿透率之氧化物、金屬、相對透光金屬、具有50%或以上穿透率之金屬、有機質、無機質、螢光物、磷光物、陶瓷、半導體、摻雜之半導體、及無摻雜之半導體中至少其一。於某些應用中，接觸層之材料係為氧化銦錫、氧化鎘錫、氧化銻錫、氧化銦鋅、氧化鋅鋁、與氧化鋅錫中至少其一。若為相對透光金屬，其厚度較佳地約為0.005μm~0.6μm。在一實施例中，由於接觸層具有較佳的橫向電流擴散速率，可以用以協助電流均勻擴散到半導體磊晶疊層34之中。一般而言，根據接觸層摻混的雜質與製程的方式不同而有所變動，其能隙的寬度可介於0.5eV至5eV之間。 A contact layer (not shown) is more selectively formed on the semiconductor epitaxial laminate 34. The contact layer is disposed on one side of the semiconductor epitaxial layer 34 away from the substrate 30. In particular, the contact layer can be an optical layer, an electrical layer, or a combination of both. The optical layer can alter the electromagnetic radiation or light from or into the active layer. As used herein, "change" means changing at least one optical property of electromagnetic radiation or light, including but not limited to frequency, wavelength, intensity, flux, efficiency, color temperature, rendering index, light field. (light field), and angle of view. The electrical layer system may change or change the value, density, distribution of at least one of voltage, resistance, current, and capacitance between opposite sides of any one of the contact layers. The constituent material of the contact layer comprises an oxide, a conductive oxide, a transparent oxide, an oxide having a transmittance of 50% or more, a metal, a relatively light-transmissive metal, a metal having a transmittance of 50% or more, an organic substance, At least one of an inorganic substance, a phosphor, a phosphor, a ceramic, a semiconductor, a doped semiconductor, and an undoped semiconductor. In some applications, the material of the contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. In the case of a relatively light-transmitting metal, the thickness thereof is preferably about 0.005 μm to 0.6 μm. In one embodiment, the contact layer has a preferred lateral current spreading rate that can be used to assist in the uniform diffusion of current into the semiconductor epitaxial stack 34. Generally, the impurities blended according to the contact layer vary depending on the manner of the process, and the width of the energy gap may be between 0.5 eV and 5 eV.

以上各圖式與說明雖僅分別對應特定實施例，然而，各個實施例中所說明或揭露之元件、實施方式、設計準則、及技術原理除在彼此顯相衝突、矛盾、或難以共同實施之外，吾人當可依其所需任意參照、交換、搭配、協調、或合併。雖然本發明已說明如上，然其並非用以限制本發明之範圍、實施順序、或使用之材料與製程方法。對於本發明所作之各種修飾與變更，皆不脫本發明之精神與範圍。 The above figures and descriptions are only corresponding to specific embodiments, however, the elements, embodiments, design criteria, and technical principles described or disclosed in the various embodiments are inconsistent, contradictory, or difficult to implement together. In addition, we may use any reference, exchange, collocation, coordination, or merger as required. Although the invention has been described above, it is not intended to limit the scope of the invention, the order of implementation, or the materials and process methods used. Various modifications and variations of the present invention are possible without departing from the spirit and scope of the invention.

Claims (8)

一種製造一光電元件之方法，包含下列步驟：提供一成長基板；形成一過渡層於該成長基板之上；形成一半導體疊層於該過渡層之上；對該半導體疊層及該過渡層進行一第一蝕刻以形成至少一溝渠，其中該溝渠將該半導體疊層及該過渡層分隔為複數個半導體島及複數個過渡層島，且該溝渠裸露出部分該成長基板；提供一不導電基板連接該些半導體島；以及移除該成長基板。A method of fabricating a photovoltaic element, comprising the steps of: providing a growth substrate; forming a transition layer over the growth substrate; forming a semiconductor layer over the transition layer; performing the semiconductor stack and the transition layer a first etching to form at least one trench, wherein the trench separates the semiconductor stack and the transition layer into a plurality of semiconductor islands and a plurality of transition layer islands, and the trench exposes a portion of the growth substrate; providing a non-conductive substrate Connecting the semiconductor islands; and removing the growth substrate. 如請求項1所述之方法，更包含移除該複數個過渡層島，其中該複數個過渡層島係位於該複數個半導體島及該成長基板之間。The method of claim 1, further comprising removing the plurality of transition layer islands, wherein the plurality of transition layer islands are located between the plurality of semiconductor islands and the growth substrate. 如請求項1所述之方法，更包含形成一電極於該些半導體島之上。The method of claim 1, further comprising forming an electrode on the semiconductor islands. 如請求項1所述之方法，其中該第一蝕刻之蝕刻液選自氫氟酸(Hydrofluoric acid,HF)、緩衝式氧化物蝕刻液(Buffer Oxide Etcher,BOE)或二氧化矽蝕刻液(Surfactanated Buffered Oxide Etchants,SBOE)。The method of claim 1, wherein the first etching etchant is selected from the group consisting of hydrofluoric acid (HF), Buffer Oxide Etcher (BOE) or cerium oxide etching solution (Surfactanated). Buffered Oxide Etchants, SBOE). 如請求項1所述之方法，其中該過渡層之材料選自矽的氧化物或矽的氮化物。The method of claim 1, wherein the material of the transition layer is selected from the group consisting of an oxide of cerium or a nitride of cerium. 如請求項1所述之方法，更包含形成一第一連接層於該半導體疊層之上後再對該第一連接層、該半導體疊層及該過渡層進行一第一蝕刻以形成至少一溝渠，其中該溝渠將該第一連接層分隔為複數個第一連接層島，其中該第一連接層之材料為一導電材料。The method of claim 1, further comprising forming a first connection layer over the semiconductor layer and performing a first etching on the first connection layer, the semiconductor layer and the transition layer to form at least one a trench, wherein the trench separates the first connecting layer into a plurality of first connecting layer islands, wherein the material of the first connecting layer is a conductive material. 如請求項6所述之方法，更包含形成一第二連接層於該不導電基板之上後再與該些半導體島連接，其中該第二連接層之材料為一導電材料。The method of claim 6, further comprising forming a second connection layer on the non-conductive substrate and then connecting to the semiconductor islands, wherein the material of the second connection layer is a conductive material. 如請求項1所述之方法，其中該些過渡層島相對該些半導體島具有一底切(undercut)形狀。The method of claim 1, wherein the transitional islands have an undercut shape relative to the plurality of semiconductor islands.