TWI617008B - Memory structure, method of operating the same, and method of manufacturing the same - Google Patents
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Abstract
一種記憶結構，包括複數個堆疊、複數個記憶層、複數個通道層、複數個介電層、和複數個第一導線。該些堆疊各包括一組彼此交替的導電條和絕緣條。記憶層共形地設置在堆疊上。通道層共形地設置在記憶層上。介電層至少設置在通道層位在該些堆疊的第一側的部分和通道層位在該些堆疊的第二側的複數個部分上。第一導線沿著堆疊的側壁設置。第一導線由介電層與通道層隔絕。設置在一堆疊的第一側的一第一導線，與設置在相同堆疊的第二側的一第一導線隔絕，並與設置在一相鄰堆疊的第二側的一第一導線隔絕。 A memory structure includes a plurality of stacked layers, a plurality of memory layers, a plurality of channel layers, a plurality of dielectric layers, and a plurality of first wires. The stacks each include a set of alternating strips and strips that alternate with one another. The memory layer is conformally disposed on the stack. The channel layer is conformally disposed on the memory layer. The dielectric layer is disposed on at least a portion of the channel layer on the first side of the stack and a channel layer on a plurality of portions of the second side of the stack. The first wire is disposed along the sidewall of the stack. The first wire is separated from the channel layer by a dielectric layer. A first wire disposed on a first side of the stack is isolated from a first wire disposed on a second side of the same stack and is isolated from a first wire disposed on a second side of the adjacent stack.
Description
本揭露是關於一種半導體結構、其操作方法、和其製造方法。本揭露特別是關於一種記憶結構、其操作方法、和其製造方法。 The present disclosure relates to a semiconductor structure, a method of operating the same, and a method of fabricating the same. The present disclosure relates in particular to a memory structure, method of operation thereof, and method of making the same.
為了減少體積、降低重量、增加功率密度、和改善可攜帶性等理由，研究者與工程師們盡其努力地增加半導體裝置的密度。其中一種方法是使用3D結構取代傳統的2D結構。另一種方法是減少裝置中之元件和間隔的尺寸。這二種方法都有其技術瓶頸需要突破。 Researchers and engineers have tried their best to increase the density of semiconductor devices in order to reduce volume, reduce weight, increase power density, and improve portability. One such method is to replace the traditional 2D structure with a 3D structure. Another approach is to reduce the size of the components and spaces in the device. Both of these methods have their technical bottlenecks that need to be broken.
本揭露是關於記憶結構、以及其操作方法和製造方法，藉由其可提供具有實體上二位元記憶結構的記憶裝置。 The present disclosure relates to a memory structure, and a method of operation and a method of fabricating the same, by which a memory device having a physically two-dimensional memory structure can be provided.
根據一些實施例，一種記憶結構，包括一基板、複數個堆疊、複數個記憶層、複數個通道層、複數個介電層、和複數個第一導線。堆疊設置在基板上。該些堆疊各具有一第一側和一第二側。該些堆疊各包括一組彼此交替的複數個導電條和複數 個絕緣條。記憶層共形地設置在堆疊上。通道層共形地設置在記憶層上。介電層至少設置在通道層位在該些堆疊的該些第一側的複數個部分和通道層位在該些堆疊的該些第二側的複數個部分上。第一導線沿著堆疊的側壁設置。第一導線由介電層與通道層隔絕。第一導線包括設置在該些堆疊的該些第一側的一第一組第一導線和設置在該些堆疊的該些第二側的一第二組第一導線，設置在該些堆疊中之一堆疊的第一側的第一組第一導線中之一第一導線，與設置在相同堆疊的第二側的第二組第一導線中之一第一導線隔絕，並與設置在該些堆疊中之一相鄰堆疊的第二側的第二組第一導線中之一第一導線隔絕。 In accordance with some embodiments, a memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers, a plurality of dielectric layers, and a plurality of first wires. The stack is placed on the substrate. The stacks each have a first side and a second side. The stacks each include a plurality of alternating conductive strips and plurals alternating with each other Insulation strips. The memory layer is conformally disposed on the stack. The channel layer is conformally disposed on the memory layer. The dielectric layer is disposed at least on the plurality of portions of the channel layer on the first sides of the stack and the channel layer on a plurality of portions of the second sides of the stack. The first wire is disposed along the sidewall of the stack. The first wire is separated from the channel layer by a dielectric layer. The first wire includes a first set of first wires disposed on the first sides of the stacks and a second set of first wires disposed on the second sides of the stacks, disposed in the stacks One of the first wires of the first set of first wires of the stacked first side is isolated from the first wire of the second set of first wires disposed on the second side of the same stack, and is disposed at One of the stacks of one of the second sets of first conductors adjacent to the second side of the stack is isolated.
根據一些實施例，一種記憶結構(例如上述之記憶結構)的操作方法，包括藉由選擇對應之一或二個串列選擇線、對應之一位元線、和對應之一字元線，選擇一記憶胞。 According to some embodiments, a method of operating a memory structure, such as the memory structure described above, includes selecting by selecting one or two of a string selection line, a corresponding one of the bit lines, and a corresponding one of the word lines. A memory cell.
根據一些實施例，一種記憶結構的製造方法包括下列步驟。提供一基板。形成複數個堆疊在基板上。該些堆疊各具有一第一側和一第二側。該些堆疊各包括一組彼此交替的複數個導電條和複數個絕緣條。形成複數個記憶層共形地位在堆疊上。形成複數個通道層共形地位在記憶層上。形成複數個介電層在至少通道層位在該些堆疊的該些第一側的複數個部分和通道層位在該些堆疊的該些第二側的複數個部分上。形成複數個第一導線沿著堆疊的側壁。第一導線由介電層與通道層隔絕。第一導線包括形成在該些堆疊的該些第一側的一第一組第一導線和形成在該些堆疊的該些第二側的一第二組第一導線，形成在該些堆疊中之一堆疊的第一側的第一組第一導線中之一第一導線，與形成在 相同堆疊的第二側的第二組第一導線中之一第一導線隔絕，並與形成在該些堆疊中之一相鄰堆疊的第二側的第二組第一導線中之一第一導線隔絕。 According to some embodiments, a method of fabricating a memory structure includes the following steps. A substrate is provided. A plurality of stacked layers are formed on the substrate. The stacks each have a first side and a second side. The stacks each include a plurality of alternating conductive strips and a plurality of insulating strips alternating with one another. A plurality of memory layers are formed to conform to the stack. A plurality of channel layers are formed to conform to the memory layer. Forming a plurality of dielectric layers at a plurality of portions of the first side of the stack and channel layers at least at the channel level on a plurality of portions of the second sides of the stack. A plurality of first wires are formed along the sidewalls of the stack. The first wire is separated from the channel layer by a dielectric layer. The first wire includes a first set of first wires formed on the first sides of the stacks and a second set of first wires formed on the second sides of the stacks, formed in the stacks One of the first wires of the first set of first wires stacked on the first side, and formed in One of the first set of first conductors of the second side of the same stack is isolated and one of the first set of first conductors formed on the second side of the stack adjacent one of the stacks Wire isolated.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
100、200‧‧‧記憶結構 100,200‧‧‧ memory structure
102‧‧‧基板 102‧‧‧Substrate
104、204‧‧‧埋層 104, 204‧‧‧ buried layer
106‧‧‧源極線 106‧‧‧Source line
108‧‧‧堆疊 108‧‧‧Stacking
110、110(S)‧‧‧導電條 110,110(S)‧‧‧ Conductive strip
112‧‧‧絕緣條 112‧‧‧Insulation strip
114‧‧‧上部結構 114‧‧‧Superstructure
116‧‧‧第一絕緣層 116‧‧‧First insulation
118‧‧‧第二絕緣層 118‧‧‧Second insulation
120、220‧‧‧記憶層 120, 220‧‧‧ memory layer
122、222‧‧‧通道層 122, 222‧‧‧ channel layer
124‧‧‧絕緣材料 124‧‧‧Insulation materials
126‧‧‧氣隙 126‧‧‧ air gap
128‧‧‧介電層 128‧‧‧ dielectric layer
130‧‧‧第一導線 130‧‧‧First wire
132、132(S)‧‧‧第一導線 132, 132 (S) ‧ ‧ first wire
134、134(S)‧‧‧第一導線 134, 134 (S) ‧ ‧ first wire
136‧‧‧層間介電材料 136‧‧‧Interlayer dielectric materials
138、138(S)‧‧‧第二導線 138, 138 (S) ‧ ‧ second wire
140、240‧‧‧接觸元件 140, 240‧‧‧Contact elements
142、142(S)‧‧‧記憶胞 142, 142 (S) ‧ ‧ memory cells
308‧‧‧初始堆疊 308‧‧‧Initial stacking
310‧‧‧導電層 310‧‧‧ Conductive layer
312‧‧‧絕緣層 312‧‧‧Insulation
316‧‧‧絕緣層 316‧‧‧Insulation
318‧‧‧絕緣層 318‧‧‧Insulation
320‧‧‧初始記憶層 320‧‧‧ initial memory layer
321‧‧‧通道襯層 321‧‧‧channel lining
322‧‧‧初始通道層 322‧‧‧ initial channel layer
323‧‧‧第一絕緣材料 323‧‧‧First insulation material
325‧‧‧第二絕緣材料 325‧‧‧Second insulation material
352‧‧‧第一孔洞 352‧‧‧First hole
354‧‧‧第二孔洞 354‧‧‧Second hole
356‧‧‧第三絕緣材料 356‧‧‧ Third insulating material
358‧‧‧絕緣材料 358‧‧‧Insulation materials
360‧‧‧切割道 360‧‧‧ cutting road
S1‧‧‧第一側 S1‧‧‧ first side
S2‧‧‧第二側 S2‧‧‧ second side
第1圖繪示根據實施例的一種記憶結構。 FIG. 1 illustrates a memory structure in accordance with an embodiment.
第2圖繪示該種記憶結構的操作方法。 Figure 2 illustrates the operation of the memory structure.
第3圖繪示根據實施例的另一種記憶結構。 FIG. 3 illustrates another memory structure in accordance with an embodiment.
第4圖繪示該另一種記憶結構的操作方法。 Figure 4 illustrates the operation of the other memory structure.
第5A~19C圖繪示根據實施例的一種記憶結構的製造方法。 5A-19C illustrate a method of fabricating a memory structure in accordance with an embodiment.
以下將配合所附圖式對於各種不同的實施例進行更詳細的說明。所附圖式只用於描述目的，而不用於限制目的。為了清楚起見，在一些圖式中可能誇大一些元件。例如，在一組圖式中，一元件可能只在其中一個圖式中被誇大顯示。此外，可能從圖式中省略一些元件和/或元件符號。可以預期的是，一實施例中的元件和特徵，可以有利地納入於另一實施例中，而未再進一步地闡述。 Various embodiments will be described in more detail below in conjunction with the drawings. The drawings are for illustrative purposes only and are not intended to be limiting. For the sake of clarity, some elements may be exaggerated in some of the figures. For example, in a set of drawings, an element may only be exaggerated in one of the drawings. In addition, some elements and/or component symbols may be omitted from the drawings. It is contemplated that elements and features of one embodiment may be advantageously incorporated in another embodiment without further elaboration.
根據實施例的一記憶結構包括一基板、複數個堆疊、複數個記憶層、複數個通道層、複數個介電層、和複數個第一導線。堆疊設置在基板上。該些堆疊各具有一第一側和一第二 側。該些堆疊各包括一組彼此交替的複數個導電條和複數個絕緣條。記憶層共形地設置在堆疊上。通道層共形地設置在記憶層上。介電層至少設置在通道層位在該些堆疊的該些第一側的複數個部分和通道層位在該些堆疊的該些第二側的複數個部分上。第一導線沿著堆疊的側壁設置。第一導線由介電層與通道層隔絕。第一導線包括設置在該些堆疊的該些第一側的一第一組第一導線和設置在該些堆疊的該些第二側的一第二組第一導線，設置在該些堆疊中之一堆疊的第一側的第一組第一導線中之一第一導線，與設置在相同堆疊的第二側的第二組第一導線中之一第一導線隔絕，並與設置在該些堆疊中之一相鄰堆疊的第二側的第二組第一導線中之一第一導線隔絕。 A memory structure according to an embodiment includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers, a plurality of dielectric layers, and a plurality of first wires. The stack is placed on the substrate. The stacks each have a first side and a second side. The stacks each include a plurality of alternating conductive strips and a plurality of insulating strips alternating with one another. The memory layer is conformally disposed on the stack. The channel layer is conformally disposed on the memory layer. The dielectric layer is disposed at least on the plurality of portions of the channel layer on the first sides of the stack and the channel layer on a plurality of portions of the second sides of the stack. The first wire is disposed along the sidewall of the stack. The first wire is separated from the channel layer by a dielectric layer. The first wire includes a first set of first wires disposed on the first sides of the stacks and a second set of first wires disposed on the second sides of the stacks, disposed in the stacks One of the first wires of the first set of first wires of the stacked first side is isolated from the first wire of the second set of first wires disposed on the second side of the same stack, and is disposed at One of the stacks of one of the second sets of first conductors adjacent to the second side of the stack is isolated.
請參照第1圖，其繪示根據實施例的記憶結構100。記憶結構100被繪示成具有配置成I形串列之記憶胞的三維(3D)垂直通道反及(NAND)記憶結構。 Please refer to FIG. 1 , which illustrates a memory structure 100 in accordance with an embodiment. Memory structure 100 is depicted as a three-dimensional (3D) vertical channel inverse (NAND) memory structure having memory cells configured in an I-shaped array.
記憶結構100包括一基板102。基板102可包括形成在其中和/或其上的結構和元件等等。記憶結構100可選擇性地包括一埋層104，設置在基板102上。例如，在基板102提供電洞抹除功能的一些實施例中，記憶結構100可包括一薄的埋層104，或甚至沒有埋層。記憶結構100可包括一源極線106，設置在埋層104上。在一些實施例中，源極線106提供能帶間熱電洞抹除功能。 The memory structure 100 includes a substrate 102. Substrate 102 can include structures and elements, and the like formed therein and/or thereon. The memory structure 100 can optionally include a buried layer 104 disposed on the substrate 102. For example, in some embodiments in which the substrate 102 provides a hole erasing function, the memory structure 100 can include a thin buried layer 104, or even no buried layer. The memory structure 100 can include a source line 106 disposed on the buried layer 104. In some embodiments, source line 106 provides an inter-band thermal hole erase function.
記憶結構100包括複數個堆疊108，設置在基板102上。如第1圖所示，在具有配置成I形串列之記憶胞的3D垂直通道NAND記憶結構中，堆疊108可設置在源極線106上。堆疊 108及其組成元件(例如導電條110)在一第一方向上延伸，例如一X方向。堆疊108各具有一第一側S1和一第二側S2。堆疊108各包括一組彼此交替的複數個導電條110和複數個絕緣條112。堆疊108可各更包括一上部結構114，設置在該組導電條110和絕緣條112上。根據一些實施例，上部結構114可包括一第一絕緣層116和一第二絕緣層118。第一絕緣層116設置在該組導電條110和絕緣條112上。第二絕緣層118設置在第一絕緣層116上。 Memory structure 100 includes a plurality of stacks 108 disposed on substrate 102. As shown in FIG. 1, in a 3D vertical channel NAND memory structure having memory cells configured in an I-shaped string, the stack 108 can be disposed on the source line 106. Stacking 108 and its constituent elements (e.g., conductive strips 110) extend in a first direction, such as an X direction. The stacks 108 each have a first side S1 and a second side S2. The stacks 108 each include a plurality of alternating conductive strips 110 and a plurality of insulating strips 112 that alternate with one another. The stacks 108 can each further include an upper structure 114 disposed on the set of conductive strips 110 and the insulating strips 112. According to some embodiments, the upper structure 114 may include a first insulating layer 116 and a second insulating layer 118. The first insulating layer 116 is disposed on the set of conductive strips 110 and the insulating strips 112. The second insulating layer 118 is disposed on the first insulating layer 116.
記憶結構100包括複數個記憶層120，共形地設置在堆疊108上。根據一些實施例，記憶層120可具有阻障層-捕捉層-穿隧層結構，其中阻障層最靠近堆疊108，而穿隧層離堆疊108最遠。記憶結構100包括複數個通道層122，共形地設置在記憶層120上。沿著X方向，在該些堆疊108之各者上可設置有多於一個的通道層122。在一Y方向中，設置在相鄰堆疊108上的通道層122可彼此連接，如第1圖所示。 The memory structure 100 includes a plurality of memory layers 120 that are conformally disposed on the stack 108. According to some embodiments, the memory layer 120 can have a barrier layer-capture layer-tunnel layer structure with the barrier layer closest to the stack 108 and the tunneling layer being the furthest away from the stack 108. The memory structure 100 includes a plurality of channel layers 122 that are conformally disposed on the memory layer 120. In the X direction, more than one channel layer 122 may be disposed on each of the stacks 108. In a Y direction, the channel layers 122 disposed on adjacent stacks 108 can be connected to each other, as shown in FIG.
記憶結構100可包括一絕緣材料124，設置在堆疊108之間，對應至該些組導電條110和絕緣條112。在一些實施例中，氣隙126存在於絕緣材料124中。氣隙126有利於降低二個相鄰通道層122的耦合率(coupling rate)。 The memory structure 100 can include an insulating material 124 disposed between the stacks 108, corresponding to the set of conductive strips 110 and the insulating strips 112. In some embodiments, an air gap 126 is present in the insulating material 124. The air gap 126 facilitates reducing the coupling rate of the two adjacent channel layers 122.
記憶結構100包括複數個介電層128，至少設置在通道層122位在堆疊108的第一側S1的複數個部分和通道層122位在堆疊108的第二側S2的複數個部分上。在記憶結構100中，如第1圖所示，位在堆疊108的第一側S1的該些部分和通道層122位在堆疊108的第二側S2的該些部分對應至堆疊108的上部 結構114。在一些實施例中，介電層128包括一氧化物材料。在一些實施例中，介電層128包括一高介電係數材料。 Memory structure 100 includes a plurality of dielectric layers 128 disposed at least in a plurality of portions of channel layer 122 at a first side S1 of stack 108 and channel layer 122 at a plurality of portions of second side S2 of stack 108. In the memory structure 100, as shown in FIG. 1, the portions of the first side S1 of the stack 108 and the portions of the channel layer 122 at the second side S2 of the stack 108 correspond to the upper portion of the stack 108. Structure 114. In some embodiments, dielectric layer 128 includes an oxide material. In some embodiments, dielectric layer 128 comprises a high dielectric constant material.
記憶結構100包括複數個第一導線130，沿著堆疊108的側壁設置。亦即，第一導線130可實質上在所述第一方向(X方向)上延伸。第一導線130由介電層128與通道層122隔絕。如第1圖所示，介電層128和第一導線130可位在絕緣材料124上。由於絕緣材料124可對應至該些組導電條110和絕緣條112而設置，第一導線130可設置在高於該些組導電條110和絕緣條112的高度。第一導線130包括設置在堆疊108的第一側S1的一第一組第一導線(132)和設置在堆疊108的第二側S2的一第二組第一導線(134)。在敘述於此的實施例中，設置在一堆疊108的第一側S1的該第一組第一導線中之一第一導線132，與設置在相同堆疊108的第二側S2的該第二組第一導線中之一第一導線134隔絕，並與設置在一相鄰堆疊108的第二側S2的該第二組第一導線中之一第一導線134隔絕。如第1圖所示，該些第一導線130可具有複數個L形剖面。此外，第一組第一導線(132)的該些L形剖面與第二組第一導線(134)的該些L形剖面可呈鏡像對稱。在一些實施例中，第一導線130包括一基於多晶矽之材料，例如一摻雜多晶矽材料。在一些實施例中，第一導線130包括一金屬材料。 The memory structure 100 includes a plurality of first wires 130 disposed along sidewalls of the stack 108. That is, the first wire 130 may extend substantially in the first direction (X direction). The first wire 130 is isolated from the channel layer 122 by a dielectric layer 128. As shown in FIG. 1, dielectric layer 128 and first lead 130 may be positioned on insulating material 124. Since the insulating material 124 can be disposed corresponding to the set of conductive strips 110 and the insulating strips 112, the first conductive lines 130 can be disposed at a height higher than the set of the conductive strips 110 and the insulating strips 112. The first wire 130 includes a first set of first wires (132) disposed on a first side S1 of the stack 108 and a second set of first wires (134) disposed on a second side S2 of the stack 108. In the embodiment described herein, one of the first set of first conductors 132 of the first side S1 of the stack 108 is disposed, and the second of the second side S2 of the same stack 108 is disposed. One of the first wires of the set of first wires is isolated and isolated from one of the first wires 134 of the second set of first wires disposed on the second side S2 of the adjacent stack 108. As shown in FIG. 1, the first wires 130 may have a plurality of L-shaped cross sections. In addition, the L-shaped sections of the first set of first wires (132) and the L-shaped sections of the second set of first wires (134) may be mirror symmetrical. In some embodiments, the first wire 130 comprises a polysilicon based material, such as a doped polysilicon material. In some embodiments, the first wire 130 comprises a metallic material.
記憶結構100可包括複數個第二導線138，設置在第一導線130上方。更具體地說，記憶結構100可包括一層間介電材料136，其覆蓋以上所述的元件。層間介電材料136形成提供平坦上表面的一個層，第二導線138設置在該表面上。第二導線138在不同於所述第一方向的一第二方向上延伸，例如Y方 向。記憶結構100可包括複數個接觸元件140，將第二導線138連接到通道層122。 The memory structure 100 can include a plurality of second wires 138 disposed over the first wires 130. More specifically, memory structure 100 can include an interlevel dielectric material 136 that covers the elements described above. The interlayer dielectric material 136 forms a layer that provides a flat upper surface on which the second wire 138 is disposed. The second wire 138 extends in a second direction different from the first direction, such as the Y square to. The memory structure 100 can include a plurality of contact elements 140 that connect the second wire 138 to the channel layer 122.
請參照第2圖，其繪示記憶結構100的一種操作方法。一種記憶結構的操作方法，包括藉由選擇串列選擇線中對應之一或二個串列選擇線、位元線中對應之一位元線、和字元線中對應之一字元線，選擇記憶胞中之一記憶胞。根據一些實施例，在記憶結構100中，第一導線130為串列選擇線，第二導線138為位元線，導電條110為字元線。此外，複數個記憶胞142能夠被定義在導電條110(字元線)與通道層122的交點。在記憶結構100的操作例如編程、讀取、或抹除等之中，要進行操作的一記憶胞142(S)係藉由選擇對應的串列選擇線(第一導線132(S))、對應的位元線(第二導線138(S))、和對應的字元線(導電條110(S))而被選擇。在這樣的情況下，被選擇的串列選擇線(132(S))導通(turned on)，從而電流能夠從位元線(138(S))通過對應的通道層122到達底下的源極線106。在第2圖中，第二導線132(S)為對應的串列選擇線。然而在一些其他的實施例中，一第二導線134可為對應的串列選擇線。 Please refer to FIG. 2, which illustrates an operation method of the memory structure 100. A method for operating a memory structure includes selecting one or two of a string selection line, a corresponding one of the bit lines, and a corresponding one of the word lines in the string selection line. Select one of the memory cells in the memory cell. According to some embodiments, in the memory structure 100, the first wire 130 is a string selection line, the second wire 138 is a bit line, and the conductive strip 110 is a word line. In addition, a plurality of memory cells 142 can be defined at the intersection of the conductive strip 110 (word line) and the channel layer 122. In the operation of the memory structure 100, such as programming, reading, or erasing, etc., a memory cell 142(S) to be operated is selected by selecting a corresponding string selection line (first wire 132(S)), Corresponding bit lines (second wire 138(S)), and corresponding word lines (conductive strips 110(S)) are selected. In such a case, the selected string select line (132(S)) is turned on so that current can pass from the bit line (138(S)) through the corresponding channel layer 122 to the underlying source line. 106. In Fig. 2, the second wire 132(S) is a corresponding string selection line. In some other embodiments, however, a second wire 134 can be a corresponding string selection line.
請參照第3圖，其繪示根據另一實施例的記憶結構200。記憶結構200被繪示成具有配置成U形串列之記憶胞的3D垂直通道NAND記憶結構。不同於記憶結構100，記憶結構200中的堆疊108可直接設置在埋層204上，而記憶胞142的串列藉由接觸元件240連接到源極線(未繪示)。如第2圖所示，在Y方向中，設置在相鄰堆疊108上的通道層222彼此連接。在一些實施例中，於Y方向中，設置在相鄰堆疊108上的記憶層220可彼 此連接。 Please refer to FIG. 3, which illustrates a memory structure 200 in accordance with another embodiment. The memory structure 200 is depicted as a 3D vertical channel NAND memory structure having memory cells configured in a U-shaped array. Unlike the memory structure 100, the stack 108 in the memory structure 200 can be disposed directly on the buried layer 204, while the series of memory cells 142 are connected to the source lines (not shown) by contact elements 240. As shown in FIG. 2, in the Y direction, the channel layers 222 disposed on the adjacent stacks 108 are connected to each other. In some embodiments, in the Y direction, the memory layer 220 disposed on the adjacent stack 108 can be This connection.
請參照第4圖，其繪示記憶結構200的一種操作方法。與前述內容類似，在記憶結構200中，第一導線130可為串列選擇線，第二導線138可為位元線，導電條110可為字元線。此外，複數個記憶胞142能夠被定義在導電條110(字元線)與通道層122的交點。在記憶結構200的操作之中，要進行操作的一記憶胞142(S)係藉由選擇對應的串列選擇線(第一導線132(S)和134(S))、對應的位元線(138(S))、和對應的字元線(110(S))而被選擇。在這樣的情況下，被選擇的串列選擇線(132(S)和134(S))導通，從而電流能夠從位元線(138(S))通過對應的通道層122到達接觸元件240並從而到達源極線。 Please refer to FIG. 4, which illustrates an operation method of the memory structure 200. Similar to the foregoing, in the memory structure 200, the first wire 130 can be a string selection line, the second wire 138 can be a bit line, and the conductive strip 110 can be a word line. In addition, a plurality of memory cells 142 can be defined at the intersection of the conductive strip 110 (word line) and the channel layer 122. Among the operations of the memory structure 200, a memory cell 142(S) to be operated is selected by selecting corresponding serial string selection lines (first wires 132(S) and 134(S)), corresponding bit lines. (138(S)), and the corresponding word line (110(S)) are selected. In such a case, the selected string select lines (132(S) and 134(S)) are turned on so that current can pass from the bit line (138(S)) through the corresponding channel layer 122 to the contact element 240 and Thereby reaching the source line.
以下將說明繪示根據實施例的一種記憶結構的製造方法。這樣的方法包括下列步驟。首先，提供一基板。形成複數個堆疊在基板上。該些堆疊各具有一第一側和一第二側。該些堆疊各包括一組彼此交替的複數個導電條和複數個絕緣條。形成複數個記憶層共形地位在堆疊上。形成複數個通道層共形地位在記憶層上。形成複數個介電層在至少通道層位在該些堆疊的該些第一側的複數個部分和通道層位在該些堆疊的該些第二側的複數個部分上。形成複數個第一導線沿著堆疊的側壁。第一導線由介電層與通道層隔絕。第一導線包括形成在該些堆疊的該些第一側的一第一組第一導線和形成在該些堆疊的該些第二側的一第二組第一導線，形成在該些堆疊中之一堆疊的第一側的第一組第一導線中之一第一導線，與形成在相同堆疊的第二側的第二組第一導線中之一第一導線隔絕，並與形成在該些堆疊中之一相鄰堆疊 的第二側的第二組第一導線中之一第一導線隔絕。 A method of fabricating a memory structure in accordance with an embodiment will be described below. Such a method includes the following steps. First, a substrate is provided. A plurality of stacked layers are formed on the substrate. The stacks each have a first side and a second side. The stacks each include a plurality of alternating conductive strips and a plurality of insulating strips alternating with one another. A plurality of memory layers are formed to conform to the stack. A plurality of channel layers are formed to conform to the memory layer. Forming a plurality of dielectric layers at a plurality of portions of the first side of the stack and channel layers at least at the channel level on a plurality of portions of the second sides of the stack. A plurality of first wires are formed along the sidewalls of the stack. The first wire is separated from the channel layer by a dielectric layer. The first wire includes a first set of first wires formed on the first sides of the stacks and a second set of first wires formed on the second sides of the stacks, formed in the stacks One of the first wires of the first set of first wires of the stacked first side is isolated from the first wire of the second set of first wires formed on the second side of the same stack, and is formed at One of the stacks adjacent to the stack One of the first wires of the second set of first wires of the second side is isolated.
請參照第5A~19C圖，其繪示這樣的一方法。在此，為了易於理解，該方法被繪示成用於形成記憶結構100。以「B」和「C」所指示的圖式分別是取自由「A」所指示的圖式中的1-1’線和2-2’線的剖面圖。 Please refer to Figures 5A-19C for a method such as this. Here, for ease of understanding, the method is illustrated for forming the memory structure 100. The patterns indicated by "B" and "C" are the cross-sectional views taken from the lines 1-1' and 2-2' in the pattern indicated by "A".
請參照第5A~5B圖，提供一基板102。基板102可包括形成在其中和/或其上的結構和元件等等。例如，基板102可包括一p型井(未繪示)，對應至將在接下來的步驟中形成的堆疊108的位置。在一些實施例中，如第5B圖所示，形成一埋層104在基板102上。埋層104可由氧化物形成。形成一源極線106在埋層104上。源極線106可由重摻雜n型多晶矽形成。形成用於形成所述堆疊108的一初始堆疊308在基板102上。如第5B圖所示，初始堆疊308可形成在源極線106上。初始堆疊308包括一組彼此交替的複數個導電層310和複數個絕緣層312。初始堆疊308可包括另一絕緣層316，形成在該組交替的導電層310和絕緣層312上。初始堆疊308可選擇性地包括一絕緣層318，形成在絕緣層316上。導電層310可由摻雜多晶矽形成。絕緣層312可由氧化物形成。絕緣層316可由氧化物形成。絕緣層318可由氮化矽(SiN)形成。這樣的一SiN層能夠補償膜應力，並避免具有高深寬比的堆疊倒塌或彎曲。 Please refer to FIGS. 5A-5B to provide a substrate 102. Substrate 102 can include structures and elements, and the like formed therein and/or thereon. For example, substrate 102 can include a p-well (not shown) corresponding to the location of stack 108 that will be formed in the next step. In some embodiments, a buried layer 104 is formed on the substrate 102 as shown in FIG. 5B. The buried layer 104 may be formed of an oxide. A source line 106 is formed on the buried layer 104. Source line 106 can be formed from heavily doped n-type polysilicon. An initial stack 308 for forming the stack 108 is formed on the substrate 102. As shown in FIG. 5B, an initial stack 308 can be formed on the source line 106. The initial stack 308 includes a plurality of conductive layers 310 and a plurality of insulating layers 312 that alternate with one another. The initial stack 308 can include another insulating layer 316 formed over the set of alternating conductive layers 310 and insulating layers 312. The initial stack 308 can optionally include an insulating layer 318 formed over the insulating layer 316. The conductive layer 310 may be formed of doped polysilicon. The insulating layer 312 may be formed of an oxide. The insulating layer 316 may be formed of an oxide. The insulating layer 318 may be formed of tantalum nitride (SiN). Such a SiN layer can compensate for film stress and avoid stack collapse or bending with high aspect ratio.
請參照第6A~6B圖，藉由使用一圖案化製程分離初始堆疊308，複數個堆疊108形成在基板102上。該圖案化製程能夠停止於源極線106。堆疊108和其組成元件(例如導電條110)在一第一方向上延伸，例如一X方向。堆疊108各具有一第一側 S1和一第二側S2。堆疊108各包括一組彼此交替的複數個導電條110和複數個絕緣條112。堆疊108可各更包括一上部結構114，形成在該組導電條110和絕緣條112上。上部結構114可包括一第一絕緣層116和一第二絕緣層118。第一絕緣層116形成在該組導電條110和絕緣條112上。第二絕緣層118形成在第一絕緣層116上。 Referring to FIGS. 6A-6B, a plurality of stacks 108 are formed on the substrate 102 by separating the initial stack 308 using a patterning process. The patterning process can stop at the source line 106. Stack 108 and its constituent elements (e.g., conductive strips 110) extend in a first direction, such as an X direction. Stacks 108 each have a first side S1 and a second side S2. The stacks 108 each include a plurality of alternating conductive strips 110 and a plurality of insulating strips 112 that alternate with one another. The stacks 108 can each further include an upper structure 114 formed on the set of conductive strips 110 and the insulating strips 112. The upper structure 114 can include a first insulating layer 116 and a second insulating layer 118. A first insulating layer 116 is formed on the set of conductive strips 110 and the insulating strips 112. The second insulating layer 118 is formed on the first insulating layer 116.
請參照第7A~7B圖，形成一初始記憶層320。初始記憶層320共形地覆蓋堆疊108。初始記憶層320可具有阻障層-捕捉層-穿隧層結構，其中阻障層最靠近堆疊108，而穿隧層離堆疊108最遠。初始記憶層320可形成為ONO(氧化物-氮化物-氧化物)多層結構、ONONO(氧化物-氮化物-氧化物-氮化物-氧化物)多層結構、或ONONONO(氧化物-氮化物-氧化物-氮化物-氧化物-氮化物-氧化物)多層結構等等。形成一通道襯層321在初始記憶層320上。通道襯層321共形地覆蓋初始記憶層320。通道襯層321可由相同於用在通道層之材料形成，例如一未摻雜或輕摻雜之多晶矽材料或一矽鍺材料。 Referring to Figures 7A-7B, an initial memory layer 320 is formed. The initial memory layer 320 conformally covers the stack 108. The initial memory layer 320 can have a barrier layer-capture layer-tunnel layer structure with the barrier layer closest to the stack 108 and the tunneling layer being the furthest away from the stack 108. The initial memory layer 320 may be formed as an ONO (oxide-nitride-oxide) multilayer structure, an ONONO (oxide-nitride-oxide-nitride-oxide) multilayer structure, or ONONONO (oxide-nitride- Oxide-nitride-oxide-nitride-oxide) multilayer structure and the like. A channel liner 321 is formed on the initial memory layer 320. The channel liner 321 conformally covers the initial memory layer 320. The channel liner 321 can be formed of the same material as that used in the channel layer, such as an undoped or lightly doped polysilicon material or a germanium material.
請參照第8A~8B圖，藉由一非等向性蝕刻製程，移除通道襯層321和初始記憶層320形成在源極線106暴露之表面上的部份。如此一來，便形成複數個記憶層120共形地位在堆疊108上。接著，共形地形成一用於通道層之材料，例如是藉由沉積，從而形成一初始通道層322。初始通道層322包括通道襯層321的剩餘部分和在這個步驟中該用於通道層之材料。 Referring to FIGS. 8A-8B, a portion of the channel liner 321 and the initial memory layer 320 formed on the exposed surface of the source line 106 is removed by an anisotropic etching process. As a result, a plurality of memory layers 120 are formed conformally on the stack 108. Next, a material for the channel layer is conformally formed, for example, by deposition to form an initial channel layer 322. The initial channel layer 322 includes the remainder of the channel liner 321 and the material for the channel layer in this step.
請參照第9A~9B圖，以非共形方式，形成一第一絕緣材料323在第8A~8B圖的結構上。因此，該第一絕緣材料323 填充到堆疊108之間的間隔中。第一絕緣材料323可為氧化物。氣隙126可存在於第一絕緣材料323中。第一絕緣材料323中的氣隙126並不延伸到上部結構114的高度。 Referring to FIGS. 9A-9B, a first insulating material 323 is formed in a non-conformal manner on the structures of FIGS. 8A-8B. Therefore, the first insulating material 323 Filled into the space between the stacks 108. The first insulating material 323 may be an oxide. An air gap 126 may be present in the first insulating material 323. The air gap 126 in the first insulating material 323 does not extend to the height of the superstructure 114.
請參照第10A~10C圖，形成複數個第一孔洞352在第一絕緣材料323中，例如是藉由蝕刻。橢圓形的第一孔洞352沿著不同於堆疊108之延伸方向的方向排列，例如沿著一Y方向。第一孔洞352被第一絕緣材料323環繞，並貫穿第一絕緣材料323。在形成第一孔洞352時，部分的初始通道層322被移除。因此，初始通道層322並未存在於第一孔洞352中。在一些實施例中，如第10C圖所示，部分的記憶層120也可能被移除。在一些其他的實施例中，記憶層120可能並未由第一孔洞352的形成步驟移除。 Referring to FIGS. 10A-10C, a plurality of first holes 352 are formed in the first insulating material 323, for example, by etching. The elliptical first holes 352 are arranged in a direction different from the direction in which the stack 108 extends, for example along a Y direction. The first hole 352 is surrounded by the first insulating material 323 and penetrates through the first insulating material 323. When the first hole 352 is formed, a portion of the initial channel layer 322 is removed. Therefore, the initial channel layer 322 is not present in the first hole 352. In some embodiments, as shown in FIG. 10C, portions of the memory layer 120 may also be removed. In some other embodiments, memory layer 120 may not be removed by the forming step of first hole 352.
請參照第11A~11C圖，以非共形方式，形成一第二絕緣材料325在第10A~10C圖的結構上。因此，該第二絕緣材料325填充到第一孔洞352中，並形成沿著Y方向的橢圓島嶼列。第二絕緣材料325可為氧化物。氣隙126可存在於第二絕緣材料325中。與前述內容類似，第二絕緣材料325中的氣隙126並不延伸到上部結構114的高度。如果需要的話，可進行一平坦化製程，例如一化學機械平坦化(chemical-mechanical planarization,CMP)製程。 Referring to FIGS. 11A-11C, a second insulating material 325 is formed in a non-conformal manner on the structures of FIGS. 10A-10C. Therefore, the second insulating material 325 is filled into the first hole 352 and forms an elliptical island column along the Y direction. The second insulating material 325 can be an oxide. An air gap 126 may be present in the second insulating material 325. Similar to the foregoing, the air gap 126 in the second insulating material 325 does not extend to the height of the superstructure 114. If desired, a planarization process, such as a chemical-mechanical planarization (CMP) process, can be performed.
請參照第12A~12C圖，形成複數個第二孔洞354，例如是藉由一光刻圖案化製程。在這個步驟中，移除部分的初始通道層322，其是對應到由第一孔洞352的形成步驟移除的部份的位置。因此，初始通道層322在堆疊108(X方向)的延伸方向 上分離，從而形成複數個通道層122共形地位在記憶層120上。接著，如第13A~13C圖所示，填充一第三絕緣材料356到第二孔洞354中。第三絕緣材料356可為氮化矽(SiN)或氧化物。如果需要的話，可進行一平坦化製程，例如一CMP製程。 Referring to FIGS. 12A-12C, a plurality of second holes 354 are formed, for example, by a lithography patterning process. In this step, a portion of the initial channel layer 322 is removed, which corresponds to the portion of the portion removed by the forming step of the first hole 352. Thus, the initial channel layer 322 extends in the direction of the stack 108 (X direction) The upper layers are separated to form a plurality of channel layers 122 conformally positioned on the memory layer 120. Next, as shown in FIGS. 13A-13C, a third insulating material 356 is filled into the second holes 354. The third insulating material 356 can be tantalum nitride (SiN) or an oxide. If desired, a planarization process, such as a CMP process, can be performed.
請參照第14A~14C圖，進行一選擇性移除製程，例如對於多晶矽或通道層之材料具有高選擇性的一蝕刻製程。藉由這個步驟，第一絕緣材料323和第二絕緣材料325都只剩餘在堆疊108之間。第一絕緣材料323與第二絕緣材料325堆疊108的延伸方向(X方向)上彼此相鄰。第一絕緣材料323和第二絕緣材料325之剩餘部分的組合，相當於第1圖中形成在堆疊108之間並對應至該些組導電條110和絕緣條112的絕緣材料124。氣隙126並未被這個步驟暴露出來。 Referring to Figures 14A-14C, a selective removal process, such as an etching process with high selectivity for the material of the polysilicon or channel layer, is performed. By this step, both the first insulating material 323 and the second insulating material 325 remain only between the stacks 108. The first insulating material 323 and the second insulating material 325 stack 108 are adjacent to each other in the extending direction (X direction). The combination of the remaining portions of the first insulating material 323 and the second insulating material 325 corresponds to the insulating material 124 formed between the stacks 108 in FIG. 1 and corresponding to the set of conductive strips 110 and the insulating strips 112. The air gap 126 is not exposed by this step.
請參照第15A~15C圖，形成複數個介電層128在至少通道層122位在堆疊108的第一側S1的複數個部分和通道層122位在堆疊108的第二側S2的複數個部分上。例如，介電層128可包括一氧化物材料，並藉由氧化通道層122暴露之部分而形成，或藉由沉積該氧化物材料到該些部分上而形成。因此，所形成的介電層128位在高於第一絕緣材料323和第二絕緣材料325的高度。在一些實施例中，藉由氧化形成的介電層128可約為70A厚。在一些實施例中，取代所述氧化物材料，介電層128可包括一高介電係數材料。 Referring to FIGS. 15A-15C, a plurality of dielectric layers 128 are formed in at least a plurality of portions of the first side S1 of the stack 108 and at least a plurality of portions of the channel layer 122 at the second side S2 of the stack 108. on. For example, the dielectric layer 128 can comprise an oxide material and is formed by exposing portions of the oxidized via layer 122, or by depositing the oxide material onto the portions. Therefore, the dielectric layer 128 is formed at a higher level than the first insulating material 323 and the second insulating material 325. In some embodiments, the dielectric layer 128 formed by oxidation can be approximately 70 Å thick. In some embodiments, instead of the oxide material, the dielectric layer 128 can comprise a high dielectric constant material.
請參照第16A~16C圖，形成複數個第一導線130沿著堆疊108的側壁。例如，可形成用於形成第一導線130的一導電材料在由第一絕緣材料323和第二絕緣材料325暴露出的通道 層122上，例如是以共形方式。可填充一絕緣材料358(未示於第16A圖)到剩餘的空間中。接著，形成切割道360在堆疊108之間，例如是藉由一蝕刻製程。如此一來，便分離堆疊108之間的所述導電材料，從而形成第一導線130。這樣的製程為自對準製程。由這些步驟形成的第一導線130位在第一絕緣材料323和第二絕緣材料3254上。第一導線130由介電層128與通道層122隔絕。如第1圖所示，第一導線130第一導線130包括形成在堆疊108的第一側S1的一第一組第一導線(132)和形成在堆疊108的第二側S2的一第二組第一導線(134)，形成在一堆疊108的第一側S1的該第一組第一導線中之一第一導線132，與形成在相同堆疊108的第二側S2的該第二組第一導線中之一第一導線134隔絕，並與形成在一相鄰堆疊108的第二側S2的該第二組第一導線中之一第一導線134隔絕。如果需要的話，可進行一切割製程，以在堆疊108的末端部分分離對應至相同堆疊108的第一導線132和第一導線134。 Referring to FIGS. 16A-16C, a plurality of first wires 130 are formed along sidewalls of the stack 108. For example, a channel of a conductive material for forming the first conductive line 130 exposed by the first insulating material 323 and the second insulating material 325 may be formed. Layer 122 is, for example, in a conformal manner. An insulating material 358 (not shown in Figure 16A) may be filled into the remaining space. Next, a scribe line 360 is formed between the stacks 108, such as by an etch process. As such, the conductive material between the stacks 108 is separated to form the first wires 130. Such a process is a self-aligned process. The first wire 130 formed by these steps is positioned on the first insulating material 323 and the second insulating material 3254. The first wire 130 is isolated from the channel layer 122 by a dielectric layer 128. As shown in FIG. 1, the first wire 130 of the first wire 130 includes a first set of first wires (132) formed on the first side S1 of the stack 108 and a second formed on the second side S2 of the stack 108. a first set of wires (134) formed in one of the first set of first wires of a first side S1 of the stack 108, and a second set formed on a second side S2 of the same stack 108 One of the first wires 134 is isolated and isolated from one of the first wires 134 of the second set of first wires formed on the second side S2 of an adjacent stack 108. If desired, a cutting process can be performed to separate the first wire 132 and the first wire 134 corresponding to the same stack 108 at the end portions of the stack 108.
請參照第17A~17C圖，形成一層間介電材料136在第16A~16C圖的結構上，例如是藉由沉積。層間介電材料136可為氧化物。在一些實施例中，層間介電材料136相同於絕緣材料358。如果需要的話，可進行一平坦化製程，例如一CMP製程。 Referring to Figures 17A-17C, an inter-layer dielectric material 136 is formed on the structure of Figures 16A-16C, for example by deposition. The interlayer dielectric material 136 can be an oxide. In some embodiments, the interlayer dielectric material 136 is the same as the insulating material 358. If desired, a planarization process, such as a CMP process, can be performed.
請參照第18A~18C圖，形成複數個接觸元件140穿過層間介電材料136，例如是藉由一光刻圖案化製程，像是一蝕刻製程。接觸元件140用於把將在接下來的步驟中形成的第二導線138連接到通道層122。在一些實施例中，形成用於第一導線134的接觸元件(未繪示)在堆疊108的末端部分，例如是藉由相同 於形成接觸元件140的該製程。 Referring to FIGS. 18A-18C, a plurality of contact elements 140 are formed through the interlayer dielectric material 136, such as by a lithographic patterning process, such as an etch process. The contact element 140 is used to connect the second wire 138 to be formed in the next step to the channel layer 122. In some embodiments, a contact element (not shown) for the first wire 134 is formed at the end portion of the stack 108, for example by the same This process of forming contact element 140.
請參照第19A~19C圖，形成複數個第二導線138在第一導線130上方。如第19B圖所示，第二導線138可形成在層間介電材料136上，並藉由接觸元件140連接到通道層122。第二導線138在不同於所述第一方向的一第二方向上延伸，例如Y方向。 Referring to FIGS. 19A-19C, a plurality of second wires 138 are formed over the first wires 130. As shown in FIG. 19B, a second wire 138 can be formed over the interlayer dielectric material 136 and connected to the channel layer 122 by the contact element 140. The second wire 138 extends in a second direction different from the first direction, such as the Y direction.
根據實施例的記憶結構，具有在其中二個串列選擇線(132和134)對應到一個字元線堆疊(108)的構造型態。因此，一個通道層(122)能夠被分成分別由二個串列選擇線控制的二個部分。從而，提供一實體上二位元之結構。藉由這樣的構造型態，能夠將位元線(138)的密度降低到傳統記憶結構的一半。此外，由於串列選擇線(130)不是形成在堆疊(108)中，它們能夠由一金屬材料形成，伴隨著由一高介電係數材料形成的閘極介電層(128)。從而能夠降低串列選擇線的電阻，並改善其可控制性。 A memory structure according to an embodiment has a configuration in which two serial select lines (132 and 134) correspond to one word line stack (108). Thus, one channel layer (122) can be divided into two portions that are each controlled by two serial selection lines. Thus, a structure of two bits on an entity is provided. With such a configuration, the density of the bit line (138) can be reduced to half that of the conventional memory structure. Moreover, since the series select lines (130) are not formed in the stack (108), they can be formed of a metallic material accompanied by a gate dielectric layer (128) formed of a high dielectric constant material. Thereby, the resistance of the string selection line can be reduced and the controllability thereof can be improved.
可以理解的是，雖然前述的實施例是關於具有配置成I形和U形串列之記憶胞的3D垂直通道NAND記憶結構，所提供的在其中二個串列選擇線對應到一個堆疊的構造型態以及其操作和製造方法，在可能的情況下，能夠應用到其他類型的記憶結構。 It will be appreciated that while the foregoing embodiments are directed to a 3D vertical channel NAND memory structure having memory cells configured in an I-shaped and U-shaped string, a configuration is provided in which two string select lines correspond to one stack. The type and its operation and manufacturing methods can be applied to other types of memory structures where possible.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope of the appended claims. Prevail.
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| TW201635608A (en) * | 2015-03-24 | 2016-10-01 | 旺宏電子股份有限公司 | Memory device and manufacturing method of the same |
| TW201640614A (en) * | 2015-05-05 | 2016-11-16 | 旺宏電子股份有限公司 | Semiconductor device and manufacturing method thereof |
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| TW201635608A (en) * | 2015-03-24 | 2016-10-01 | 旺宏電子股份有限公司 | Memory device and manufacturing method of the same |
| TW201640614A (en) * | 2015-05-05 | 2016-11-16 | 旺宏電子股份有限公司 | Semiconductor device and manufacturing method thereof |
| TW201701793A (en) * | 2015-06-23 | 2017-01-16 | Ykk股份有限公司 | Button back and button |
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