TWI615979B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- TWI615979B TWI615979B TW105128279A TW105128279A TWI615979B TW I615979 B TWI615979 B TW I615979B TW 105128279 A TW105128279 A TW 105128279A TW 105128279 A TW105128279 A TW 105128279A TW I615979 B TWI615979 B TW I615979B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000002955 isolation Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 12
- 238000007667 floating Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000013461 design Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000015654 memory Effects 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical group 0.000 description 4
- 239000011295 pitch Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本發明提供一種半導體元件，其包括一基底、二摻雜區、一閘極以及一側壁子。基底包括一主動區，且摻雜區設置於基底之主動區內。閘極設置於基底表面並位於主動區內，在平行於基底表面之第一方向上，閘極位於兩摻雜區之間，且閘極內包括複數個開孔。一部分之側壁子覆蓋閘極之側壁，而另一部分之側壁子填入閘極之開孔中。The invention provides a semiconductor device, which includes a substrate, two doped regions, a gate, and a sidewall. The substrate includes an active region, and the doped region is disposed in the active region of the substrate. The gate is disposed on the surface of the substrate and is located in the active region. In a first direction parallel to the surface of the substrate, the gate is located between two doped regions, and the gate includes a plurality of openings. A part of the side wall covers the side wall of the gate electrode, and the other side wall is filled in the opening of the gate electrode.
Description
本發明係關於一種半導體元件，尤指一種閘極具有開孔的高壓(high voltage，HV)或中壓(MV)的半導體元件。The present invention relates to a semiconductor device, and more particularly to a high voltage (HV) or medium voltage (MV) semiconductor device having a gate electrode with an opening.
傳統的高壓電晶體一般具有較高的工作電壓，為了避免熱載子效應(Hot Electron Effect)所造成的問題，通常會將高壓電晶體設計成具有較長的通道長度(channel length)，又為了解決較長的通道長度造成電晶體的飽和電流(Idsat)變低之問題，另發展出將高壓電晶體的閘極寬度加寬以調大整體飽和電流。然而，在通道長度與寬度都加寬的設計下，即表示元件的整體面積都增加，使得元件的面積妥善利用指標變差。綜上，如何同時兼顧元件的面積妥善利用指標以及熱載子問題，實為業界目前努力之目標。Traditional high-voltage transistors generally have high operating voltages. In order to avoid problems caused by the Hot Electron Effect, high-voltage transistors are usually designed to have a longer channel length. In order to solve the problem that the transistor's saturation current (Idsat) becomes lower due to a longer channel length, another development has been made to widen the gate width of the high-voltage transistor to increase the overall saturation current. However, under the design that the length and width of the channel are widened, it means that the overall area of the component is increased, which makes the area's proper utilization index worse. In summary, how to take into account the proper use of the component area and the issue of hot carriers at the same time is the goal of the industry's current efforts.
本發明的目的之一在於提供一種半導體元件，其中本發明之半導體元件的閘極具有開孔，使得半導體元件能可在不增大主動區面積的情形下，維持熱載子的原本水準，並進一步提升飽和電流。另一方面，本發明亦能使得半導體元件在維持飽和電流的大小下將面積進一步縮小。It is an object of the present invention to provide a semiconductor element, wherein the gate of the semiconductor element of the present invention has an opening, so that the semiconductor element can maintain the original level of the hot carrier without increasing the active area area, Further increase the saturation current. On the other hand, the present invention can further reduce the area of the semiconductor element while maintaining the saturation current.
本發明之實施例提供一種半導體元件，其包括一基底、二摻雜區、一閘極以及一側壁子。其中，該基底包括一主動區，且該等摻雜區設置於該基底之主動區內。該閘極設置於該基底表面並位於該主動區內，在平行於該基底表面之一第一方向上，該閘極係位於該等摻雜區之間，且該閘極內包括複數個開孔。該側壁子之其中一部分覆蓋該閘極之側壁，而該側壁子之另一部分填入該閘極之該等開孔中。An embodiment of the present invention provides a semiconductor device including a substrate, two doped regions, a gate, and a sidewall. The substrate includes an active region, and the doped regions are disposed in the active region of the substrate. The gate is disposed on the surface of the substrate and is located in the active region. In a first direction parallel to the surface of the substrate, the gate is located between the doped regions, and the gate includes a plurality of openings. hole. A part of the side wall covers the side wall of the gate, and another part of the side wall fills the openings of the gate.
為使熟習本發明所屬技術領域之一般技藝者能更進一步瞭解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。In order to make a person skilled in the art who is familiar with the technical field of the present invention further understand the present invention, the preferred embodiments of the present invention are enumerated below, and in conjunction with the accompanying drawings, the constitutional content of the present invention and the effects to be achieved are described in detail. .
請參考第1圖與第2圖，其中第1圖為本發明半導體元件之第一實施例的俯視示意圖，而第2圖為第1圖所示半導體元件沿著剖面線1-1’的局部剖面示意圖。本實施例的半導體元件1A為金氧半導體電晶體，並且係以高壓金氧半導體電晶體為例，但不以此為限。如第1圖與第2圖所示，半導體元件1A包括一基底100、二摻雜區102、一閘極104以及一側壁子106，其中為使圖式簡單易讀，第1圖省略了半導體元件1A之部分元件，僅繪示出部分基底100、閘極104、側壁子106、當作源極/汲極的摻雜區102和開孔108。以下將依序介紹半導體元件1A之各元件。基底100可例如是矽基底、含矽基底（例如SiC）、矽覆絕緣(silicon-on-insulator, SOI)基底、含磊晶層之基底、三五族基底（例如GaN）、三五族覆矽基底(例如GaN-on-silicon)、石墨烯覆矽基底(graphene-on-silicon)或其他合適的半導體基底等，但不限於此。基底100表面定義有一主動區AA，且摻雜區102設置於主動區AA內。摻雜區102為具有P型摻質或N型摻質的區域，可分別作為半導體元件1A之源極與汲極。閘極104設置於基底100表面，並位於主動區AA內，其中部分的閘極104可延伸至主動區AA外，並且，在平行於基底100表面之一第一方向D1上，閘極104係位於兩摻雜區102之間。本實施例的閘極104在第一方向D1上之寬度W1係大於等於2.5微米，且閘極104可包括多晶矽或金屬材料，但不以此為限。閘極104與基底100的表面之間設置有一閘極介電層110，其可包括無機絕緣材料例如氧化矽、氮化矽或氮氧化矽等，也可包括有機絕緣材料或有機/無機混成絕緣材料，但不以此為限。側壁子106至少設置於閘極104的四周，並覆蓋閘極104的側壁。側壁子106可包括非導電之介電材料，例如氮化矽。本實施例的基底100舉例為具有P型之摻雜類型，而摻雜區102具有N型之摻雜類型，但不以此為限。在其他變化實施例中，基底可具有N型之摻雜類型，而摻雜區具有P型之摻雜類型。Please refer to FIG. 1 and FIG. 2, wherein FIG. 1 is a schematic plan view of a first embodiment of a semiconductor device of the present invention, and FIG. 2 is a part of the semiconductor device shown in FIG. 1 along a section line 1-1 ′ Schematic cross-section. The semiconductor element 1A of this embodiment is a metal oxide semiconductor transistor, and a high voltage metal oxide semiconductor transistor is taken as an example, but it is not limited thereto. As shown in FIGS. 1 and 2, the semiconductor device 1A includes a substrate 100, two doped regions 102, a gate 104, and a sidewall 106. In order to make the drawing simple and easy to read, the semiconductor is omitted in FIG. 1. For a part of the element 1A, only a part of the substrate 100, the gate 104, the side wall 106, the doped region 102 as the source / drain, and the opening 108 are shown. Hereinafter, each element of the semiconductor element 1A will be described in order. The substrate 100 may be, for example, a silicon substrate, a silicon-containing substrate (such as SiC), a silicon-on-insulator (SOI) substrate, a substrate including an epitaxial layer, a Group III or Five substrate (such as GaN), or a Group III or Five substrate. A silicon substrate (for example, GaN-on-silicon), a graphene-on-silicon substrate, or other suitable semiconductor substrate, and the like are not limited thereto. An active area AA is defined on the surface of the substrate 100, and the doped area 102 is disposed in the active area AA. The doped region 102 is a region having a P-type dopant or an N-type dopant, and can be used as a source and a drain of the semiconductor device 1A, respectively. The gate 104 is disposed on the surface of the substrate 100 and is located in the active area AA. A part of the gate 104 may extend outside the active area AA. In a first direction D1 parallel to the surface of the substrate 100, the gate 104 is Located between two doped regions 102. The width W1 of the gate 104 in the first direction D1 in this embodiment is greater than or equal to 2.5 μm, and the gate 104 may include polycrystalline silicon or a metal material, but is not limited thereto. A gate dielectric layer 110 is provided between the gate 104 and the surface of the substrate 100. The gate dielectric layer 110 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, or an organic insulating material or an organic / inorganic hybrid insulation Materials, but not limited to this. The sidewalls 106 are disposed at least around the gate electrode 104 and cover the sidewalls of the gate electrode 104. The sidewall spacers 106 may include a non-conductive dielectric material, such as silicon nitride. The substrate 100 in this embodiment is exemplified by a P-type doping type, and the doped region 102 is an N-type doping type, but not limited thereto. In other variations, the substrate may have an N-type doping type, and the doped region may have a P-type doping type.
本實施例的閘極104包括複數個開孔108，且開孔108設置於主動區AA內的閘極104中。開孔108在第一方向D1上係設置於閘極104之中央區域，但不以此為限。在開孔108中填入了側壁子106材料，換言之，側壁子106之其中一部分覆蓋了閘極104之側壁，而另一部分之側壁子106會填入閘極104之開孔108中。本實施例之開孔108沿一第二方向D2排列成一第一直行10與一第二直行20，其中第一方向D1與第二方向D2相交並具有90度的夾角，但不以此為限。第一直行10的開孔108與第二直行20的開孔108於第一方向D1上較佳不互相重疊，亦即兩直行中的開孔108呈現交錯排列。在本實施例中，開孔108之間在第一方向D1上之最小間距S1（直線距離）的範圍為約0.1微米至約0.2微米，換言之，第一直行10與第二直行20之間的間距為約0.1微米至約0.2微米。第一直行10或第二直行20兩端的開口108與摻雜區102邊緣（以摻雜區102邊緣沿著第一方向D1的延伸線為測量端）在第二方向D2上具有一最小間距S2，其中間距S2為約0.2微米。此外，各開孔108於第一方向D1上具有一寬度W2，且寬度W2小於等於0.2微米並大於等於0.1微米。另外，本實施例開孔108的形狀為正方形，亦即開孔108於第一方向D1及第二方向D2上的寬度皆為約0.2微米，但不以此為限。開孔108的形狀亦可為圓形或長方形等適合的形狀。需注意的是，上述本實施例所提及之各元件的尺寸、間距及形狀並非用來限制本發明，在不違背本發明之發明精神下，上述參數可依實際設計需要而調整。此外，在其他變化實施例中，開孔108可靠近摻雜區102設置，例如靠近第1圖中閘極104左側之摻雜區102設置或是靠近閘極104右側之摻雜區102設置。在此請況下，開孔108於第一方向D1上與閘極104邊緣的最小間距較佳為0.2微米。The gate 104 in this embodiment includes a plurality of openings 108, and the openings 108 are disposed in the gate 104 in the active area AA. The opening 108 is disposed in the central region of the gate electrode 104 in the first direction D1, but is not limited thereto. The openings 108 are filled with the material of the side wall 106, in other words, one part of the side wall 106 covers the side wall of the gate 104, and the other part of the side wall 106 is filled in the opening 108 of the gate 104. The openings 108 of this embodiment are arranged along a second direction D2 into a first straight line 10 and a second straight line 20, wherein the first direction D1 and the second direction D2 intersect and have an included angle of 90 degrees, but this is not the case. limit. The openings 108 in the first straight line 10 and the openings 108 in the second straight line 20 preferably do not overlap each other in the first direction D1, that is, the openings 108 in the two straight lines are staggered. In this embodiment, the minimum distance S1 (straight line distance) between the openings 108 in the first direction D1 ranges from about 0.1 micrometers to about 0.2 micrometers, in other words, between the first straight line 10 and the second straight line 20 The pitch is about 0.1 microns to about 0.2 microns. The opening 108 at both ends of the first straight line 10 or the second straight line 20 and the edge of the doped region 102 (using the extension line of the edge of the doped region 102 along the first direction D1 as the measurement end) have a minimum distance in the second direction D2 S2, wherein the distance S2 is about 0.2 microns. In addition, each of the openings 108 has a width W2 in the first direction D1, and the width W2 is 0.2 μm or less and 0.1 μm or more. In addition, the shape of the opening 108 in this embodiment is a square, that is, the width of the opening 108 in the first direction D1 and the second direction D2 is about 0.2 micrometers, but it is not limited thereto. The shape of the opening 108 may be a suitable shape such as a circle or a rectangle. It should be noted that the sizes, pitches and shapes of the elements mentioned in this embodiment are not intended to limit the present invention, and the above parameters can be adjusted according to actual design requirements without departing from the spirit of the present invention. In addition, in other modified embodiments, the opening 108 may be disposed near the doped region 102, for example, disposed near the doped region 102 on the left side of the gate 104 in FIG. 1 or disposed near the doped region 102 on the right side of the gate 104. In this case, the minimum distance between the opening 108 and the edge of the gate 104 in the first direction D1 is preferably 0.2 μm.
本發明在製作閘極104與側壁子106時，可先以用來定義閘極圖案的光罩同時定義出閘極104的圖案與開孔108的圖案，對閘極材料層進行蝕刻同時形成閘極104之結構和開孔108，然後在製作側壁子108時，先形成整層的側壁子材料，覆蓋閘極104的表面並填入開孔108中，然後再進行蝕刻製程以同時形成閘極104側壁表面的側壁子106與開孔108中的側壁子。為了使側壁子材料能有效地填入開孔108中，因此本實施例設計使開孔108的最大尺寸較佳為0.2微米，又為了滿足佈局圖設計之最小尺寸規則，故開孔108之尺寸較佳大於等於0.1微米，但本發明並不受限於上述尺寸，開孔108之尺寸可能隨著製程技術之進步或材料開發而有不同之設計。When the gate electrode 104 and the side wall 106 are manufactured in the present invention, the pattern of the gate electrode 104 and the pattern of the opening 108 can be simultaneously defined by a mask for defining the gate pattern, and the gate material layer is etched to form a gate. The structure of the electrode 104 and the opening 108. Then, when the sidewall 108 is fabricated, a whole layer of sidewall material is formed to cover the surface of the gate electrode 104 and fill the opening 108, and then an etching process is performed to form the gate electrode at the same time. The sidewalls 106 on the sidewall surface 104 and the sidewalls in the opening 108. In order to effectively fill the side wall material into the opening 108, this embodiment is designed so that the maximum size of the opening 108 is preferably 0.2 microns, and in order to meet the minimum size rule of the layout design, the size of the opening 108 It is preferably greater than or equal to 0.1 micron, but the present invention is not limited to the above-mentioned size, and the size of the opening 108 may have different designs as process technology advances or material development.
請參考第3圖，其為本實施例半導體元件1A與一對照實施例之半導體元件經實際量測的電流-電壓特性曲線圖，其中四條曲線I分別為本實施例半導體元件1A在四個不同的閘極電壓Vg1、Vg2、Vg3、Vg4下之汲極電壓Vd對汲極電流Id的特性曲線，四條曲線II分別為對照實施例之半導體元件在四個不同的閘極電壓Vg1、Vg2、Vg3、Vg4下之汲極電壓Vd對汲極電流Id的特性曲線，其中閘極電壓Vg1至閘極電壓Vg4之電壓值係依序增大。對照實施例之半導體元件為閘極不具有開孔之一高壓金氧半導體電晶體。另外，第3圖中汲極電壓Vd之數值1A至10A中之A代表一特定大小的電壓值，例如為1伏特、5伏特或10伏特。如第3圖中在閘極電壓Vg4下的曲線I與曲線II所示，本實施例之半導體元件1A在汲極電壓Vd為約8.5A時發生驟迴崩潰（snapback breakdown），而對照實施例之半導體元件則在汲極電壓Vd為約7.4A時發生驟迴崩潰，亦即本發明具有開孔108之半導體元件1A可承受較大的汲極電壓Vd，相較於對照實施例之閘極不具有開孔之高壓金氧半導體電晶體，半導體元件1A可多承受15%的汲極電壓Vd。由此可知，若在半導體元件1A的閘極104中設置開孔108，則可再將主動區AA的面積縮小，並還能承受原面積大小下所能承受的電壓，進而使得整體半導體元件1A的整體面積能夠縮小。Please refer to FIG. 3, which is a graph of actual measured current-voltage characteristics of the semiconductor device 1A of this embodiment and the semiconductor device of a comparative embodiment, in which four curves I are respectively different from the semiconductor device 1A of this embodiment in four different The characteristic curves of the drain voltage Vd versus the drain current Id at the gate voltages Vg1, Vg2, Vg3, and Vg4. The four curves II are the four different gate voltages Vg1, Vg2, and Vg3 of the semiconductor element of the comparative example. The characteristic curve of the drain voltage Vd versus the drain current Id under Vg4, wherein the voltage values of the gate voltage Vg1 to the gate voltage Vg4 are sequentially increased. The semiconductor device of the comparative example is a high-voltage metal-oxide-semiconductor transistor whose gate does not have an opening. In addition, A in the values 1A to 10A of the drain voltage Vd in FIG. 3 represents a voltage value of a specific magnitude, such as 1 volt, 5 volt, or 10 volt. As shown in the curve I and curve II under the gate voltage Vg4 in FIG. 3, the semiconductor element 1A of this embodiment has a snapback breakdown when the drain voltage Vd is about 8.5A, and the comparative example The semiconductor device suddenly collapses when the drain voltage Vd is about 7.4A. That is, the semiconductor device 1A with the opening 108 of the present invention can withstand a larger drain voltage Vd, compared with the gate electrode of the comparative example. For high-voltage metal-oxide semiconductor transistors without openings, the semiconductor element 1A can withstand an additional 15% of the drain voltage Vd. It can be seen from this that if an opening 108 is provided in the gate 104 of the semiconductor element 1A, the area of the active area AA can be reduced, and the voltage that can be withheld in the original area can be withstood, thereby making the overall semiconductor element 1A The overall area can be reduced.
根據本實施例，於半導體元件1A之閘極104設置多個交錯設置的開孔108可減少閘極電容，並使得電子的流動路徑變為曲折，進而改善熱載子問題，並使得半導體元件1A可承受較高的電壓，藉此可再將半導體元件1A的面積進一步微縮。According to this embodiment, providing a plurality of staggered openings 108 in the gate 104 of the semiconductor element 1A can reduce the gate capacitance and make the flow path of the electrons tortuous, thereby improving the problem of hot carriers and making the semiconductor element 1A Can withstand higher voltages, thereby further reducing the area of the semiconductor element 1A.
本發明之半導體元件並不以上述實施例為限。下文將繼續揭示本發明之其它實施例及變化實施例，然為了簡化說明並突顯各實施例之間的差異，下文中使用相同標號標注相同元件，並不再對重覆部分作贅述。The semiconductor device of the present invention is not limited to the above embodiments. The following will continue to disclose other embodiments and variations of the present invention, but in order to simplify the description and highlight the differences between the embodiments, the same elements are labeled with the same reference numerals in the following, and the repeated parts will not be repeated.
請參考第4圖，其為本發明半導體元件第一實施例之一變化實施例的俯視示意圖。如第4圖所示，本變化實施例與第一實施例不同的地方在於，半導體元件1B之閘極104僅包括兩個開孔108沿著第一方向D1並排。本實施例之開孔108的形狀為長條形，兩者相互平行設置。開孔108於第二方向D2上具有一長度L1，且長度L1小於或等於摻雜區102於第二方向D2上的長度，而開孔108於第一方向D1上的寬度W2為約0.2微米，但不以此為限。值得注意的是，由於本變化實施例中的開孔108為狹長形狀，因此其阻擋電子流動路徑的效果更為良好。本變化實施例之半導體元件1B中各元件的材料與其餘特徵可參考第一實施例，在此不再贅述。Please refer to FIG. 4, which is a schematic top view of a modified embodiment of the first embodiment of the semiconductor device of the present invention. As shown in FIG. 4, this modified embodiment is different from the first embodiment in that the gate 104 of the semiconductor element 1B includes only two openings 108 side by side along the first direction D1. The shape of the opening 108 in this embodiment is an elongated shape, and the two are arranged parallel to each other. The opening 108 has a length L1 in the second direction D2, and the length L1 is less than or equal to the length of the doped region 102 in the second direction D2. The width W2 of the opening 108 in the first direction D1 is about 0.2 micrometers. , But not limited to this. It is worth noting that, since the opening 108 in the present modified embodiment has a narrow shape, the effect of blocking the electron flow path is better. For the material and other features of each element in the semiconductor element 1B of this modified embodiment, reference may be made to the first embodiment, and details are not described herein again.
請參考第5圖，其為本發明半導體元件第一實施例之第二變化實施例的俯視示意圖。如第5圖所示，本變化實施例與第一實施例之不同處在於開孔108的形狀為長方形。在此設計下，開孔108於第一方向D1上的寬度W2仍維持約0.2微米，並在第二方向D2上具有大於寬度W2之一長度L2，且第一直行10與第二直行20中長方形的開孔108仍維持交錯排列。本變化實施例之半導體元件1C中各元件的材料與其餘特徵可參考第一實施例，在此不再贅述。Please refer to FIG. 5, which is a schematic top view of a second modified embodiment of the first embodiment of the semiconductor device of the present invention. As shown in FIG. 5, this modified embodiment is different from the first embodiment in that the shape of the opening 108 is rectangular. Under this design, the width W2 of the opening 108 in the first direction D1 remains about 0.2 microns, and has a length L2 that is greater than the width W2 in the second direction D2, and the first straight line 10 and the second straight line 20 The middle rectangular openings 108 are still staggered. For the materials and other features of the semiconductor device 1C in this modified embodiment, reference may be made to the first embodiment, and details are not described herein again.
請參考第6圖至第9圖，其中第6圖為本發明半導體元件之第二實施例的俯視示意圖，第7圖為第6圖所示半導體元件沿著剖面線2-2’的局部剖面示意圖，第8圖為第6圖所示半導體元件沿著剖面線3-3’的局部剖面示意圖，以及第9圖為第6圖所示半導體元件沿著剖面線4-4’的局部剖面示意圖。為使圖式簡單易讀，第6圖省略了半導體元件2之部分元件，僅繪示出部分基底100、閘極104、側壁子106、摻雜區102、開孔108、摻雜井112和接觸插塞114。本實施例的半導體元件2為運用於多次編程(multiple time programmable，MTP)記憶體之中壓（例如5至10伏）金氧半導體電晶體。如第6圖至第9圖所示，本實施例半導體元件2設置於基底100的摻雜井120中，且半導體元件2包括兩閘極104及三摻雜區102，並另包括一用來作為另一閘極之摻雜井112設於摻雜井120之上。在第一方向D1上，各閘極104分別設置於兩摻雜區102之間，其中位於兩閘極104之間的摻雜區102係作為共用源極，而另外兩個摻雜區102分別作為上汲極與下汲極，本實施例之閘極104包括多晶矽材料，但不以此為限。此外，本實施例的摻雜區102於第二方向D2上的寬度W3係大於等於0.5微米，而閘極104在第一方向D1上的寬度W4係大於等於0.5微米，且較佳為約0.5微米至約1微米。摻雜井112設置於基底100之主動區AA外，並具有與摻雜井120相反的摻雜類型。本實施例的摻雜井112例如為N型摻雜井，而摻雜井120例如為P型摻雜井，但不以此為限。閘極104從主動區AA延伸至摻雜井112上，且開孔108僅設置於主動區AA內之部分閘極104中。開孔108的形狀、排列方式及其餘特徵可參考第一實施例及其變化實施例。本實施例的摻雜井112係作為MTP記憶體之控制閘極(control gate，CG)，而閘極104係作為MTP記憶體之浮置閘極(floating gate，FG)。換言之，本實施例的開孔108係設置於浮置閘極中。Please refer to FIGS. 6 to 9, wherein FIG. 6 is a schematic plan view of a second embodiment of a semiconductor device according to the present invention, and FIG. 7 is a partial cross section of the semiconductor device shown in FIG. 6 along a section line 2-2 ′. 8 is a schematic partial cross-sectional view of the semiconductor device shown in FIG. 6 along the section line 3-3 ', and FIG. 9 is a partial cross-sectional schematic view of the semiconductor device shown in FIG. 6 along the section line 4-4' . In order to make the drawing simple and easy to read, FIG. 6 omits some elements of the semiconductor element 2 and only shows a part of the substrate 100, the gate 104, the side wall 106, the doped region 102, the opening 108, the doped well 112, and Contact plug 114. The semiconductor element 2 of this embodiment is a medium-voltage (for example, 5 to 10 volt) metal-oxide semiconductor transistor used in a multiple time programmable (MTP) memory. As shown in FIGS. 6 to 9, the semiconductor element 2 in this embodiment is disposed in the doped well 120 of the substrate 100, and the semiconductor element 2 includes two gates 104 and three doped regions 102, and further includes one for A doped well 112 as another gate is disposed on the doped well 120. In the first direction D1, each gate 104 is respectively disposed between two doped regions 102, wherein the doped region 102 located between the two gates 104 serves as a common source, and the other two doped regions 102 are respectively As the upper and lower drain electrodes, the gate 104 in this embodiment includes a polycrystalline silicon material, but is not limited thereto. In addition, the width W3 of the doped region 102 in the second direction D2 in this embodiment is 0.5 μm or more, and the width W4 of the gate electrode 104 in the first direction D1 is 0.5 μm or more, and preferably about 0.5 μm. Micrometer to about 1 micrometer. The doped well 112 is disposed outside the active area AA of the substrate 100 and has a doping type opposite to that of the doped well 120. The doped well 112 in this embodiment is, for example, an N-type doped well, and the doped well 120 is, for example, a P-type doped well, but is not limited thereto. The gate 104 extends from the active region AA to the doped well 112, and the opening 108 is only disposed in a part of the gate 104 in the active region AA. For the shape, arrangement, and other features of the openings 108, reference may be made to the first embodiment and its modified embodiments. The doped well 112 in this embodiment is used as a control gate (CG) of the MTP memory, and the gate 104 is used as a floating gate (FG) of the MTP memory. In other words, the opening 108 in this embodiment is provided in the floating gate.
本實施例之半導體元件2另包括閘極介電層110與三個接觸插塞114，其中閘極介電層110設於基底100的表面上，並位於閘極104與摻雜區102之間、閘極104與基底100之間以及閘極104與摻雜井112之間，而接觸插塞114分別與一個摻雜區102接觸並電性連接，本實施例的共用源極、上汲極與下汲極可分別藉由接觸插塞114而與半導體元件2中的內連線(圖未示)電性連接。接觸插塞114的材料可包括金屬或其他適合的導電材料。此外，半導體元件2另包括一層間介電層116設置於基板100上並覆蓋閘極104，層間介電層116可用以分離並隔絕接觸插塞114與基底100上的其他導電元件。此外，如第8圖所示，半導體元件2另可包括一隔離結構118（未示於第6圖）設置於摻雜井112與摻雜區102之間。隔離結構118可為淺溝隔離(shallow trench isolation, STI)或局部矽氧化絕緣層(local oxidation of silicon isolation layer, LOCOS)，用以避免摻雜井112與摻雜區102相接觸而發生短路。本實施例之半導體元件2中各元件的材料與其餘特徵可參考第一實施例，在此不再贅述。The semiconductor element 2 of this embodiment further includes a gate dielectric layer 110 and three contact plugs 114, wherein the gate dielectric layer 110 is disposed on the surface of the substrate 100 and is located between the gate 104 and the doped region 102. , Between the gate 104 and the substrate 100, and between the gate 104 and the doped well 112, and the contact plug 114 is in contact with and electrically connected to a doped region 102 respectively. The common source and the upper drain of this embodiment are common. The bottom drain electrode can be electrically connected to an interconnect (not shown) in the semiconductor device 2 through the contact plug 114, respectively. The material of the contact plug 114 may include metal or other suitable conductive materials. In addition, the semiconductor element 2 further includes an interlayer dielectric layer 116 disposed on the substrate 100 and covering the gate electrode 104. The interlayer dielectric layer 116 can be used to separate and isolate the contact plug 114 from other conductive elements on the substrate 100. In addition, as shown in FIG. 8, the semiconductor device 2 may further include an isolation structure 118 (not shown in FIG. 6) disposed between the doped well 112 and the doped region 102. The isolation structure 118 may be a shallow trench isolation (STI) or a local oxidation of silicon isolation layer (LOCOS), so as to avoid a short circuit between the doped well 112 and the doped region 102. For the materials and other features of the semiconductor elements 2 in this embodiment, reference may be made to the first embodiment, and details are not described herein again.
本實施例於主動區AA內之部分閘極104設置開孔108，可達到如第一實施例所述的功效。另由於本實施例的閘極104係作為MTP記憶體之浮置閘極，因此於浮置閘極設置開孔108可以減少浮置閘極的寄生電容，進而提高控制閘極與浮置閘極之間的閘極耦合值(gate coupling ratio，GCR)，改善元件效能。In this embodiment, an opening 108 is provided in a part of the gate electrode 104 in the active area AA to achieve the effect as described in the first embodiment. In addition, since the gate 104 of this embodiment is a floating gate of the MTP memory, providing an opening 108 in the floating gate can reduce the parasitic capacitance of the floating gate, thereby improving the control gate and the floating gate. The gate coupling ratio (GCR) between them improves the device performance.
綜上所述，本發明之半導體元件於閘極設置多個開孔，可以有效降低閘極的寄生電容，且開孔可為交錯排列而使得電子的流動路徑變為曲折，改善熱載子效應問題，並使得半導體元件在同樣尺寸下即可承受較高的電壓。藉此設計，本發明半導體元件僅需較短的通道長度就可承受較大的電壓並同時具有較大的飽和電流，或是在相同的電壓或飽和電流設計下，本發明半導體元件僅需較小的面積，因此可有效改善元件的面積妥善利用指標。此外，當本發明之半導體元件應用於多次編程記憶體時，於浮置閘極設置開孔可減少浮置閘極的寄生電容，藉此進一步提高控制閘極與浮置閘極之間的閘極耦合值，改善元件效能。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。In summary, the semiconductor device of the present invention is provided with a plurality of openings in the gate, which can effectively reduce the parasitic capacitance of the gate, and the openings can be staggered to make the flow path of the electrons tortuous and improve the hot carrier effect. Problems, and make semiconductor components can withstand higher voltage in the same size. With this design, the semiconductor element of the present invention can withstand a large voltage and have a large saturation current at the same time with only a short channel length, or under the same voltage or saturation current design, the semiconductor element of the present invention only needs Small area, so it can effectively improve the area of components and make good use of indicators. In addition, when the semiconductor device of the present invention is applied to multiple programming memories, providing an opening in the floating gate can reduce the parasitic capacitance of the floating gate, thereby further improving the relationship between the control gate and the floating gate. Gate coupling value to improve component performance. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.
1A、1B、1C、2‧‧‧半導體元件1A, 1B, 1C, 2‧‧‧ semiconductor devices
10‧‧‧第一直行10‧‧‧ first straight
20‧‧‧ 第二直行20‧‧‧ Second straight
100‧‧‧基底100‧‧‧ substrate
102‧‧‧摻雜區102‧‧‧ doped region
104‧‧‧ 閘極104‧‧‧ Gate
106‧‧‧側壁子106‧‧‧ side wall
108‧‧‧開孔108‧‧‧ opening
110‧‧‧閘極介電層110‧‧‧Gate dielectric layer
112、120‧‧‧摻雜井112, 120‧‧‧ doped wells
114‧‧‧接觸插塞114‧‧‧contact plug
116‧‧‧層間介電層116‧‧‧Interlayer dielectric layer
118‧‧‧隔離結構118‧‧‧Isolation Structure
AA‧‧‧主動區AA‧‧‧Active Zone
D1‧‧‧ 第一方向D1‧‧‧ first direction
D2‧‧‧第二方向D2‧‧‧ Second direction
Id‧‧‧ 汲極電流Id‧‧‧ Drain current
L1、L2‧‧‧長度L1, L2‧‧‧ length
S1、S2‧‧‧間距S1, S2‧‧‧ pitch
Vd‧‧‧汲極電壓Vd‧‧‧Drain voltage
Vg1、Vg2、Vg3、Vg4‧‧‧閘極電壓Vg1, Vg2, Vg3, Vg4‧‧‧Gate voltage
W1、W2、W3、W4‧‧‧寬度W1, W2, W3, W4‧‧‧Width
第1圖為本發明半導體元件之第一實施例的俯視示意圖。 第2圖為第1圖所示半導體元件沿著剖面線1-1’的局部剖面示意圖。 第3圖為本發明半導體元件之第一實施例的電流-電壓特性曲線示意圖。 第4圖為本發明半導體元件第一實施例之第一變化實施例的俯視示意圖。 第5圖為本發明半導體元件第一實施例之第二變化實施例的俯視示意圖。 第6圖為本發明半導體元件之第二實施例的俯視示意圖。 第7圖為第6圖所示半導體元件沿著剖面線2-2’的局部剖面示意圖。 第8圖為第6圖所示半導體元件沿著剖面線3-3’的局部剖面示意圖。 第9圖為第6圖所示半導體元件沿著剖面線4-4’的局部剖面示意圖。FIG. 1 is a schematic top view of a first embodiment of a semiconductor device according to the present invention. Fig. 2 is a schematic partial cross-sectional view of the semiconductor device shown in Fig. 1 along section line 1-1 '. FIG. 3 is a schematic diagram of a current-voltage characteristic curve of the first embodiment of the semiconductor device of the present invention. FIG. 4 is a schematic top view of a first modified embodiment of the first embodiment of the semiconductor device of the present invention. FIG. 5 is a schematic plan view of a second modified embodiment of the first embodiment of the semiconductor device of the present invention. FIG. 6 is a schematic top view of a second embodiment of a semiconductor device according to the present invention. Fig. 7 is a schematic partial cross-sectional view of the semiconductor device shown in Fig. 6 along a section line 2-2 '. Fig. 8 is a schematic partial cross-sectional view of the semiconductor device shown in Fig. 6 along a section line 3-3 '. Fig. 9 is a schematic partial cross-sectional view of the semiconductor device shown in Fig. 6 along a section line 4-4 '.
1A‧‧‧半導體元件 1A‧‧‧Semiconductor
10‧‧‧第一直行 10‧‧‧ first straight
20‧‧‧第二直行 20‧‧‧Second straight
100‧‧‧基底 100‧‧‧ substrate
102‧‧‧摻雜區 102‧‧‧ doped region
104‧‧‧閘極 104‧‧‧Gate
106‧‧‧側壁子 106‧‧‧ side wall
108‧‧‧開孔 108‧‧‧ opening
AA‧‧‧主動區 AA‧‧‧Active Zone
D1‧‧‧第一方向 D1‧‧‧ first direction
D2‧‧‧第二方向 D2‧‧‧ Second direction
S1、S2‧‧‧間距 S1, S2‧‧‧ pitch
W1、W2‧‧‧寬度 W1, W2‧‧‧Width
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