TWI615951B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI615951B
TWI615951B TW103111506A TW103111506A TWI615951B TW I615951 B TWI615951 B TW I615951B TW 103111506 A TW103111506 A TW 103111506A TW 103111506 A TW103111506 A TW 103111506A TW I615951 B TWI615951 B TW I615951B
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gate
insulating layer
semiconductor device
trench
inventive concept
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TW103111506A
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TW201445710A (zh
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金柱然
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三星電子股份有限公司
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract

本發明提供半導體裝置及其製造方法。所述半導體裝置包含：形成於基板中之場絕緣層；形成於所述場絕緣層上且包含暴露所述場絕緣層之至少一部分之溝槽的層間介電層；形成於所述溝槽中、將安置在所述場絕緣層上之沉積絕緣層；形成於所述溝槽中、將安置在所述沉積絕緣層上之閘極絕緣層；以及形成於所述溝槽中、在所述閘極絕緣層上之金屬閘極。

Description

半導體裝置及其製造方法
【相關申請案之交叉參考】
本申請案主張2013年5月31日在韓國智慧財產局申請的韓國專利申請案第10-2013-0062804號之優先權，以及自所述專利申請案產生之所有權利，所述專利申請案之內容以全文引用方式併入本文中。
本發明是有關於一種半導體裝置及其製造方法。
由於金屬氧化物半導體(metal oxide semiconductor；MOS)電晶體之特徵尺寸已減小，故閘極之長度以及形成於閘極下的通道之長度亦逐漸減小。因此，各種研究正在進行中以使閘極與通道之間的電容增加且改良MOS電晶體之操作特性。隨著主要用作閘極絕緣膜之氧化矽膜之厚度逐漸減小，氧化矽膜可經歷其電性質之物理性限制(physical limitations)。因此，為了替換習知氧化矽膜，正在積極進行對具有高介電常數之高介電常數膜 (high-k film)的研究。高介電常數膜在維持等效氧化物膜之小厚度之同時可使閘電極與通道區域之間的漏電流減小。
主要用作閘極材料之多晶矽可具有比大部分金屬高的電阻。因此，當前趨勢為用金屬閘電極替換多晶矽閘電極。
本發明概念之一些實施例提供使用沉積絕緣層來防止在製造程序期間產生殘餘物之半導體裝置。
本發明概念之一些實施例亦提供使用沉積絕緣層來防止在製造程序期間產生殘餘物之半導體裝置的製造方法。
本發明概念之此等以及其他目標將在實例實施例之以下描述中加以描述或自實例實施例之以下描述顯而易見。
根據本發明概念之一態樣，提供一種半導體裝置，其包含：形成於基板中之場絕緣層；形成於所述場絕緣層上且包含暴露所述場絕緣層之至少一部分之溝槽的層間介電層；形成於所述溝槽中、將安置在所述場絕緣層上之沉積絕緣層；形成於所述溝槽中、將安置在所述沉積絕緣層上之閘極絕緣層；以及形成於所述溝槽中、在所述閘極絕緣層上之金屬閘極。
根據本發明概念之另一態樣，提供一種半導體裝置，其包含：場絕緣層；形成於所述場絕緣層上且包含暴露所述場絕緣層之至少一部分之溝槽的層間介電層；接觸所述場絕緣層且形成於所述溝槽中之氧化物膜；以及形成於所述溝槽中、在所述氧化物膜上之金屬閘極。
根據本發明概念之又一態樣，提供一種半導體裝置之製 造方法，該製造方法包含：在基板中形成場絕緣層；在所述場絕緣層上形成層間介電層，所述層間介電層包含暴露所述場絕緣層之至少一部分之溝槽；在所述溝槽中形成將安置在所述場絕緣層上之沉積絕緣層；在所述溝槽中形成將安置在所述沉積絕緣層上之閘極絕緣層；以及在所述溝槽中形成將安置在所述閘極絕緣層上之金屬閘極。
根據本發明概念之再一態樣，提供一種半導體裝置之製造方法，該製造方法包含：在基板上形成包含第一溝槽以及第二溝槽之層間介電層；在所述第一溝槽之側壁及底面上、在所述第二溝槽之側壁及底面上且在所述層間介電層之頂面上形成沉積絕緣層；在所述第一溝槽以及所述第二溝槽中依序形成將安置在所述沉積絕緣層上之高介電常數材料層以及金屬層；以及平坦化所述金屬層、所述高介電常數材料層以及所述沉積絕緣層。
根據本發明概念之另一態樣，提供一種半導體裝置之製造方法，該製造方法包含：提供已界定有第一區域以及第二區域之基板；在所述第一區域中形成第一犧牲絕緣圖案以及第一犧牲閘極圖案且在所述第二區域中形成第二犧牲絕緣圖案以及第二犧牲閘極圖案；在所述第一犧牲絕緣圖案、所述第一犧牲閘極圖案、所述第二犧牲絕緣圖案以及所述第二犧牲閘極圖案附近形成層間介電層；移除所述第二犧牲絕緣圖案、所述第一犧牲閘極圖案以及所述第二犧牲閘極圖案；以及在所述第一溝槽中形成第一閘極絕緣層以及第一金屬閘極且在所述第二溝槽中形成第二閘極絕緣層以及第二金屬閘極，前述閘極絕緣層以及前述金屬閘極將安置在所述第一犧牲絕緣圖案上。
根據本發明概念之又一態樣，提供一種半導體裝置，其包含：在基板上縱向彼此平行地形成之第一鰭狀物以及第二鰭狀物；在所述基板上安置於所述第一鰭狀物與所述第二鰭狀物之間的場絕緣層；層間介電層，其形成於所述第一鰭狀物、所述第二鰭狀物以及所述場絕緣層上，且包含暴露所述第一鰭狀物之部分之第一溝槽以及暴露所述場絕緣層之部分之第二溝槽；形成於所述第一溝槽中之第一普通閘極；以及形成於所述第二溝槽中、將安置在所述場絕緣層上之沉積絕緣層；形成於所述第二溝槽中、將安置在所述沉積絕緣層上之閘極絕緣層；以及形成於所述第二溝槽中、將安置在所述閘極絕緣層上之虛設閘極。
請注意，可將關於一個實施例所描述的本發明概念之態樣併入不同實施例中，雖然未相對於所述不同實施例進行特定描述。亦即，所有實施例及/或任何實施例之特徵可以任何方式及/或組合進行組合。將在下文陳述之說明書中詳細地解釋本發明概念之此等以及其他目標及/或態樣。
1‧‧‧半導體裝置
2‧‧‧半導體裝置
3‧‧‧半導體裝置
4‧‧‧半導體裝置
5‧‧‧半導體裝置
6‧‧‧半導體裝置
7‧‧‧半導體裝置
8‧‧‧半導體裝置
9‧‧‧半導體裝置
10‧‧‧半導體裝置
11‧‧‧第一電晶體
11a‧‧‧第一電晶體
12‧‧‧半導體裝置
13‧‧‧第三電晶體
14‧‧‧第四電晶體
100‧‧‧基板
101‧‧‧基板
103‧‧‧主動區域
105‧‧‧場絕緣層
110‧‧‧層間介電層
111‧‧‧第一部分
112‧‧‧第一溝槽
119‧‧‧第一犧牲絕緣圖案
119a‧‧‧犧性絕緣層
120‧‧‧間隙壁
129‧‧‧第一犧牲閘極圖案
129a‧‧‧犧牲閘極層
130‧‧‧第一閘極絕緣層
135‧‧‧第一沉積絕緣層
135a‧‧‧第一沉積絕緣層
135b‧‧‧沉積絕緣層
161‧‧‧源極/汲極
170‧‧‧N型功函數控制膜
181‧‧‧第一黏接膜
190‧‧‧第一金屬閘極圖案
199‧‧‧第一金屬閘極
200‧‧‧基板
205‧‧‧場絕緣層
210‧‧‧層間介電層
212‧‧‧第二溝槽
220‧‧‧間隙壁
230‧‧‧第二閘極絕緣層
235‧‧‧第二沉積絕緣層
250‧‧‧P型功函數控制膜
270‧‧‧N型功函數控制膜
281‧‧‧第二黏接膜
290‧‧‧第二金屬閘極圖案
299‧‧‧第二金屬閘極
300‧‧‧基板
305‧‧‧場絕緣層
310‧‧‧層間介電層
312‧‧‧第三溝槽
319‧‧‧第三犧牲絕緣圖案
319a‧‧‧犧牲絕緣層
320‧‧‧間隙壁
329‧‧‧第三犧牲閘極圖案
329a‧‧‧犧牲閘極層
330‧‧‧第三閘極絕緣層
335b‧‧‧沉積絕緣層
370‧‧‧N型功函數控制膜
381‧‧‧第三黏接膜
390‧‧‧第三金屬閘極圖案
399‧‧‧第三金屬閘極
400‧‧‧基板
405‧‧‧場絕緣層
410‧‧‧層間介電層
412‧‧‧溝槽
420‧‧‧間隙壁
430‧‧‧第四閘極絕緣層
435‧‧‧第四沉積絕緣層
438‧‧‧第五沉積絕緣層
470‧‧‧N型功函數控制膜
481‧‧‧第四黏接膜
490‧‧‧第四金屬閘極圖案
499‧‧‧第四金屬閘極
512‧‧‧第二溝槽
521‧‧‧第一間隙壁
522‧‧‧第二間隙壁
530‧‧‧閘極絕緣層
535a‧‧‧沉積絕緣層
570‧‧‧功函數控制膜
581‧‧‧第一黏接膜
590‧‧‧金屬閘極圖案
599‧‧‧虛設閘極
610‧‧‧邏輯區域
611‧‧‧電晶體
612‧‧‧第一溝槽
620‧‧‧SRAM區域
621‧‧‧電晶體
623‧‧‧電晶體
624‧‧‧電晶體
630‧‧‧閘極絕緣層
635a‧‧‧沉積絕緣層
662‧‧‧第一升高源極/汲極
670‧‧‧功函數控制膜
681‧‧‧第一黏接膜
690‧‧‧金屬閘極圖案
699_1‧‧‧第一普通閘極
699_2‧‧‧普通閘極
998‧‧‧遮罩
999‧‧‧遮罩
1100‧‧‧電子系統
1110‧‧‧控制器
1120‧‧‧輸入/輸出裝置(I/O)
1130‧‧‧記憶體裝置
1140‧‧‧介面
1150‧‧‧匯流排
I‧‧‧第一區域
II‧‧‧第二區域
III‧‧‧第三區域
IV‧‧‧第四區域
F1‧‧‧鰭狀物
F2‧‧‧鰭狀物
K‧‧‧部分
H0、H1、H3、H4‧‧‧高度
W1‧‧‧距離
W2‧‧‧寬度
包含附圖以提供對本發明概念之進一步理解，且附圖被併入本說明書中且構成本說明書之部分。圖式說明本發明概念之一些實施例，且與描述一起用來解釋本發明概念之原理。
圖1為根據本發明概念之一些實施例之半導體裝置的佈局圖。
圖2為沿著圖1之線A-A截取的橫截面圖且圖3為沿著圖1之線B-B截取的橫截面圖。
圖4為根據本發明概念之一些實施例之半導體裝置的橫截面圖。
圖5為根據本發明概念之一些實施例之半導體裝置的橫截面圖。
圖6為根據本發明概念之一些實施例之半導體裝置的橫截面圖。
圖7為根據本發明概念之一些實施例之半導體裝置的橫截面圖。
圖8為根據本發明概念之一些實施例之半導體裝置的橫截面圖。
圖9為根據本發明概念之一些實施例之半導體裝置的橫截面圖。
圖10為根據本發明概念之第八實施例之半導體裝置的透視圖。
圖11為沿著圖10之線A-A截取的橫截面圖。
圖12為沿著圖10之線B-B截取的橫截面圖。
圖13A至圖13D說明根據本發明概念之一些實施例之半導體裝置。
圖14A及圖14B為說明根據本發明概念之一些實施例之半導體裝置的概念圖。
圖15為包含根據本發明概念之一些實施例的半導體裝置之電子系統的方塊圖。
圖16至圖21說明根據本發明概念之一些實施例之半導體裝置的製造方法中的中間程序步驟。
圖22說明根據本發明概念之一些實施例之半導體裝置的製造方法中的中間程序操作。
藉由參考實例實施例之以下詳細描述以及附圖可容易理解本發明概念以及實現本發明概念之方法的優點以及特徵。然而，本發明概念可以許多不同形式具體化且不應被解釋為限於本文中所陳述之實施例。實情為，提供此等實施例，使得揭露內容將是澈底且完整的且將向熟習此項技術者完整地傳達本發明概念 之概念，且本發明概念將僅由附加之申請專利範圍來界定。在圖 式中，為清楚起見，誇示層以及區域之厚度。
將理解，當元件或層被稱為「在」另一元件或層「上」或「連接至」另一元件或層時，所述元件可直接在另一元件或層上或直接連接至另一元件或層，或可存在介入元件或層。與之相比，當元件被稱為「直接在」另一元件或層「上」或「直接連接至」另一元件或層時，不存在介入元件或層。相同數字始終指代相同元件。如本文中所使用，術語「及/或」包含相關聯的所列項目中之一或多者之任一以及所有組合。
為了易於描述，諸如「在……下」、「在……下方」、「下部」、「在……上方」、「上部」以及其類似者的空間相對術語可在本文中用以描述如圖中所說明的一個元件或特徵與另一(多個)元件或特徵之關係。將理解，所述空間相對術語意欲除了圖中所描繪之定向外亦涵蓋裝置在使用中或操作中的不同定向。舉例而言，若翻轉圖中之裝置，則描述為在其他元件或特徵「下方」或 「之下」的元件將定向為在其他元件或特徵「上方」。因此，例示性術語「在……下方」可涵蓋「在……上方」以及「在……下方」兩個定向。裝置可以其他方式定向(旋轉90度或處於其他定向)，且相應地解譯本文中所使用之空間相對描述詞。
術語「一(a以及an)」及「所述」以及類似所指示物在描述本發明概念之上下文中(尤其在以下申請專利範圍之上下文中)的使用應被解釋為涵蓋單數以及複數兩者，除非本文中另有指示或明顯與上下文相矛盾。術語「包括」、「具有」、「包含」以及「含有」應被解釋為開放式術語(亦即，意味「包含，但不限於」)，除非另有說明。
將理解，雖然術語第一、第二等在本文中可用以描述各種元件，但此等元件不應受此等術語限制。此等術語僅用以區分一個元件與另一元件。因此，舉例而言，下文所論述之第一元件、第一組件或第一區段可被稱為第二元件、第二組件或第二區段而不脫離本發明概念之教示。
將參看透視圖、橫截面圖及/或平面圖描述本發明概念，在所述視圖中，展示了本發明概念之實例實施例。因此，例示性視圖之型態可根據製造技術及/或公差加以修改。亦即，本發明概念之實施例不欲限制本發明概念之範疇，而是涵蓋可由於製造製程之改變而產生的所有改變以及修改。因此，圖式所示之區域是以示意形式說明，且區域之形狀僅以說明方式呈現而非作為限制。
除非另外定義，否則本文中所使用的所有技術以及科學術語具有與一般熟習本發明概念所屬技術者通常所理解之意義相同的意義。請注意，本文中所提供之任何以及所有實例或例示性 術語之使用僅意欲更好地闡明本發明概念，而非對本發明概念之範疇的限制，除非另有規定。此外，除非另外定義，否則不可過度解譯在通常所用之辭典中所定義之所有術語。
圖1為根據本發明概念之一些實施例之半導體裝置的佈局圖，圖2為沿著圖1之線A-A截取的橫截面圖，且圖3為沿著圖1之線B-B截取的橫截面圖。此處，將N型電晶體之閘極結構例示為圖1所示之半導體裝置。
參看圖1至圖3，根據本發明概念之一些實施例之半導體裝置1包含基板100、場絕緣層105、包含第一溝槽112之層間介電層110、第一沉積絕緣層135、第一閘極絕緣層130以及第一金屬閘極199。第一金屬閘極199可包含N型功函數控制膜170、第一黏接膜181以及第一金屬閘極圖案190。第一金屬閘極199可藉由替換製程(replacement process)形成。
場絕緣層105(諸如，淺溝槽隔離(shallow trench isolation；STI)膜)可形成於基板100中以界定主動區域103。主動區域103可在第一方向上縱向地延伸，如圖1所示，但本發明概念之態樣不限於此。基板100可由選自由(例如)Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs以及InP組成之群組的一或多個半導體材料製成。在一些實施例中，基板100可為絕緣體上矽(silicon on insulator；SOI)基板。另外，基板100可為第三族至第五族基板。第一金屬閘極199之通道可包含SiGe通道。如稍後將描述，當基板100為第三族至第五族的或通道為SiGe通道而非Si通道時，可不使用氧化方法來形成氧化矽膜。在此情況下，與在本發明概念之一些實施例中相同，可使用沉積方法來形成氧化 矽膜。
層間介電層110形成於基板100上且可包含第一溝槽112。層間介電層110可藉由堆疊兩個或兩個以上絕緣層而形成。 如所示，第一溝槽112之側壁可接觸間隙壁120且第一溝槽112之底面可接觸基板100，但本發明概念之態樣不限於此。如圖1所示，第一溝槽112可在第二方向上縱向地延伸以橫過主動區域103，但本發明概念之態樣不限於此。因此，第一溝槽112可暴露場絕緣層105之至少一部分(參看圖2)或可暴露主動區域103之至少一部分(參看圖3)。
間隙壁120可由氮化物膜以及氮氧化物膜中之至少一者形成。
第一沉積絕緣層135可為藉由沉積方法形成之絕緣層。 沉積方法可包含化學氣相沉積(chemical vapor deposition；CVD)或原子層沉積(atomic layer deposition；ALD)，但本發明概念之態樣不限於此。第一沉積絕緣層135可包含氧化矽膜(例如，HTO)，但本發明概念之態樣不限於此。由於第一沉積絕緣層135是藉由沉積方法形成，故所述第一沉積絕緣層可形成於場絕緣層105上，如圖2所示。另外，由於第一沉積絕緣層135是在形成第一溝槽112之後藉由沉積方法形成(參見圖20)，故所述第一沉積絕緣層可沿著第一溝槽112之側壁以及底面以共形(conformally)方式形成。當氧化物膜是藉由不同於沉積方法之方法(諸如，熱處理、使用雙電漿之方法、使用UV電漿之方法或使用過氧化物之方法)形成時，氧化物膜可不形成於場絕緣層105上。在此情況下，氧化物膜亦可不形成於第一溝槽112之側壁上。第一沉積 絕緣層135以及場絕緣層105可經形成以彼此接觸。第一沉積絕緣層135可形成至(例如)近似50Å或更小(在近似5Å至近似50Å之範圍中)之厚度。舉例而言，第一沉積絕緣層135可形成至10Å之厚度。第一沉積絕緣層135用以改良高電壓電晶體之操作特性(亦即，使擊穿電壓增加)。如稍後將描述，藉由沉積方法形成之氧化物膜可比藉由不同於沉積方法之方法形成之氧化物膜較容易移除。換言之，藉由沉積方法形成之氧化物膜很少產生不剝離問題(unstrip issue)且留下很少殘餘物。另外，當基板100為第三族至第五族基板時，由於矽未包含於基板100中，故使用熱處理在基板100上形成矽絕緣層相當困難。因此，與在根據本發明概念之第一實施例之半導體裝置1中相同，使用沉積方法可容易地形成矽絕緣層。
第一閘極絕緣層130可沿著第一溝槽112之側壁以及底面以共形方式形成於第一沉積絕緣層135上。第一閘極絕緣層130以及第一沉積絕緣層135可以彼此接觸之方式安置。第一閘極絕緣層130可包含具有高於氧化矽膜之介電常數之高介電材料。舉例而言，第一閘極絕緣層130可包含選自由HfO2、ZrO2、Ta2O5、TiO2、SrTiO3以及(Ba,Sr)TiO3組成之群組的材料。第一閘極絕緣層130可根據待形成之裝置之類型而形成至適當厚度。舉例而言，當第一閘極絕緣層130包含HfO2時，所述第一閘極絕緣層130可形成至近似50Å或更小(亦即，在近似5Å至50Å之間的範圍中)之厚度。
雖然未圖示，但蝕刻終止膜可形成於第一閘極絕緣層130上。舉例而言，蝕刻終止膜可包含TiN以及TaN中之至少一者。 舉例而言，蝕刻終止膜可為TiN膜以及TaN膜之堆疊。蝕刻終止膜可用於移除N型功函數控制膜之一部分。
N型功函數控制膜170可在第一溝槽112中形成於第一閘極絕緣層130(或蝕刻終止膜)上。如所示，N型功函數控制膜170亦可沿著第一溝槽112之側壁及底面以共形方式形成。N型功函數控制膜170可藉由控制N型電晶體之功函數而控制N型電晶體之操作特性。N型功函數控制膜170可由選自由TiAl、TiAlC、TiAlN、TaC、TiC以及HfSi組成之群組的材料製成。舉例而言，N型功函數控制膜170可為TiAlC膜。
第一黏接膜181可在第一溝槽112中形成於N型功函數控制膜170上。第一黏接膜181可包含TiN以及Ti中之至少一者。 一些實施例規定第一黏接膜181可包含依序堆疊之TiN膜以及Ti膜。第一黏接膜181可使稍後將形成之第一金屬閘極圖案190之黏附性增加。舉例而言，當第一金屬閘極圖案190包含Al時，第一黏接膜181可為由Ti或TiN製成之單一膜。當第一金屬閘極圖案190包含W時，第一黏接膜181可為由TiN製成之單一膜。第一金屬閘極圖案190可在第一溝槽112中形成於第一黏接膜181上(或N型功函數控制膜170上)以填充第一溝槽112之一部分。 第一金屬閘極圖案190可包含選自由鋁(Al)、鎢(W)以及鈦(Ti)組成之群組的至少一者，但本發明概念之態樣不限於此。
同時，如圖2及圖3所示，在根據本發明概念之一些實施例之半導體裝置1中，形成於場絕緣層105上之閘極結構的多個功能層之堆疊次序與形成於主動區域103上之閘極結構的多個功能層之堆疊次序彼此相同。
換言之，如圖3所示，形成於場絕緣層105上之閘極結構包含依序堆疊之第一沉積絕緣層135、第一閘極絕緣層130以及第一金屬閘極199。如圖2所示，形成於主動區域103上之閘極結構亦可包含依序堆疊之第一沉積絕緣層135、第一閘極絕緣層130以及第一金屬閘極199。
圖4為根據本發明概念之一些實施例之半導體裝置的橫截面圖。為了解釋便利起見，以下描述將著重於當前實施例與圖1至圖3所示的本發明概念之先前所述實施例之間的不同之處。
參看圖4，在根據本發明概念之一些實施例之半導體裝置2中，第一沉積絕緣層135a可僅形成於第一溝槽112之底面上而不形成於第一溝槽112之側壁上。如稍後將描述，若第一沉積絕緣層135a是在形成第一溝槽112之前先形成，則所述第一沉積絕緣層135a可僅形成於第一溝槽112之底面上(參見圖22)。第一沉積絕緣層135a可以接觸場絕緣層105之方式形成。
第一閘極絕緣層130可沿著第一溝槽112之側壁及底面以共形方式形成於第一沉積絕緣層135a上。第一閘極絕緣層130之一部分可與第一沉積絕緣層135a接觸。如上所述，第一閘極絕緣層130可包含具有高於氧化矽膜之介電常數之高介電常數介電材料。
圖5為根據本發明概念之一些實施例之半導體裝置的橫截面圖。為了解釋便利起見，以下描述將著重於當前實施例與圖1至圖3所示的本發明概念之先前所述實施例之間的不同之處。此處，將P型電晶體之閘極結構例示為圖5所示之半導體裝置。
參看圖5，根據本發明概念之第三實施例之半導體裝置3 可包含基板200、包含第二溝槽212之層間介電層210、第二沉積絕緣層235、第二閘極絕緣層230、第二金屬閘極299以及間隙壁220。此處，第二金屬閘極299可包含P型功函數控制膜250、N型功函數控制膜270、第二黏接膜281以及第二金屬閘極圖案290。
第二沉積絕緣層235可沿著第二溝槽212之側壁及底面以共形方式形成。由於第二沉積絕緣層235是藉由沉積方法形成，故所述第二沉積絕緣層235亦可形成於場絕緣層205上。第二沉積絕緣層235以及場絕緣層205可被形成以彼此接觸。沉積方法可包含化學氣相沉積(CVD)或原子層沉積(ALD)，但本發明概念之態樣不限於此。第二沉積絕緣層235可包含氧化矽膜(例如，HTO)，但本發明概念之態樣不限於此。
同時，儘管未圖示，但第二沉積絕緣層235可僅形成於第二溝槽212之底面上而不形成於第二溝槽212之側壁上(參見圖4)。
第二閘極絕緣層230可沿著第二溝槽212之側壁及底面以共形方式形成於第二沉積絕緣層235上。第二閘極絕緣層230以及第二沉積絕緣層235可經形成以彼此接觸。
儘管未圖示，但蝕刻終止膜可形成於第二閘極絕緣層230上。
P型功函數控制膜250可在第二溝槽212中形成於第二閘極絕緣層230(或蝕刻終止膜)上。如所示，P型功函數控制膜250亦可沿著第二溝槽212之側壁及底面以共形方式形成。P型功函數控制膜250可藉由控制P型電晶體之功函數而控制P型電晶體之操作特性。舉例而言，P型功函數控制膜250可為TiN膜，但本 發明概念之態樣不限於此。
N型功函數控制膜270可在第二溝槽212中形成於P型功函數控制膜250上。若P型電晶體之操作特性未被嚴重阻礙，則N型功函數控制膜270未被移除，而是安置於P型電晶體中，如此做是為了使用減少光微影次數。
第二黏接膜281可在第二溝槽212中形成於N型功函數控制膜270上。
第二金屬閘極圖案290可形成於第二黏接膜281上以填充第二溝槽212。
圖6為根據本發明概念之一些實施例之半導體裝置的橫截面圖。
參看圖6，在根據本發明概念之一些實施例之半導體裝置4中，基板100及200可包含界定於其中之第一區域I及第二區域II。圖1至圖4所示之N型電晶體中之至少一者可形成於第一區域I中，且圖5所示之P型電晶體可形成於第二區域II中。舉例而言，圖2所示之N型電晶體可形成於第一區域I中，且圖5所示之P型電晶體可同時形成於第二區域II中。
圖7為根據本發明概念之一些實施例之半導體裝置的橫截面圖。
參看圖7，在根據本發明概念之一些實施例之半導體裝置5中，基板100及300可包含界定於其中之第一區域I以及第三區域III。具有第一操作電壓之第一電晶體11可形成於第一區域I中，且具有不同於第一操作電壓之第三操作電壓之第三電晶體13可形成於第三區域III中。第三操作電壓可小於第一操作電壓。舉 例而言，第一操作電壓可為高電壓且第三操作電壓可為常規電壓(regular voltage)，但本發明概念之態樣不限於此。舉例而言，第一操作電壓可在1.5V至1.8V之範圍中，且第三操作電壓可在0.8V至1.0V之範圍中。在所說明實施例中，第一電晶體11以及第三電晶體13為N型電晶體，但本發明概念之態樣不限於此。
在第一區域I中，第一電晶體11可包含第一沉積絕緣層135、形成於第一沉積絕緣層135上之第一閘極絕緣層130以及形成於第一閘極絕緣層130上之第一金屬閘極199。在第三區域III中，第三電晶體13可包含第三閘極絕緣層330以及形成於第三閘極絕緣層330上之第三金屬閘極399。換言之，沉積絕緣層不存在於第三閘極絕緣層330與基板300(或場絕緣層305)之間。
換言之，在第一電晶體11中，第一沉積絕緣層135以及第一閘極絕緣層130安置於第一金屬閘極199與基板100之間。 在第三電晶體13中，第三閘極絕緣層330安置於第三金屬閘極399與基板300之間。換言之，由於第一沉積絕緣層135以及第一閘極絕緣層130之厚度的總和相對較大，故第一電晶體11可在高電壓下操作。換言之，第一電晶體11之擊穿電壓可增加。然而，由於第三閘極絕緣層330之厚度相對較小，故第三電晶體13可在常規電壓下操作。第三電晶體13包括間隙壁320。
舉例而言，第一金屬閘極199可包含N型功函數控制膜170、第一黏接膜181以及第一金屬閘極圖案190，但本發明概念之態樣不限於此。舉例而言，第三金屬閘極399可包含N型功函數控制膜370、第三黏接膜381以及第三金屬閘極圖案390，但本發明概念之態樣不限於此。
圖8為根據本發明概念之一些實施例之半導體裝置的橫截面圖。為了解釋便利起見，以下描述將著重於當前實施例與圖7所示的本發明概念之先前實施例之間的不同之處。
參看圖8，在根據本發明概念之一些實施例之半導體裝置6中，第一電晶體11a形成於第一區域I中且第三電晶體13形成於第三區域III中。
第一電晶體11a之第一沉積絕緣層135a可僅形成於第一溝槽112之底面上而不形成於第一溝槽112之側壁上。若第一沉積絕緣層135a是在形成第一溝槽112之前先形成，則所述第一沉積絕緣層135a可僅形成於第一溝槽112之底面上(參見圖22)。 第一沉積絕緣層135a以及場絕緣層105可經形成以彼此接觸。
圖9為根據本發明概念之一些實施例之半導體裝置的橫截面圖。為了解釋便利起見，以下描述將著重於當前實施例與圖7所示的本發明概念之先前實施例之間的不同之處。
參看圖9，在根據本發明概念之一些實施例之半導體裝置7中，基板100、300及400可包含界定於其中之第一區域I、第三區域III以及第四區域IV。具有第一操作電壓之第一電晶體11可形成於第一區域I中，具有不同於第一操作電壓之第三操作電壓之113可形成於第三區域III中，且具有不同於第三操作電壓之第四操作電壓之第四電晶體14可形成於第四區域IV中。第四操作電壓可大於第一操作電壓且第一操作電壓可大於第三操作電壓。舉例而言，第四操作電壓可大於或等於3.0V，第一操作電壓可在1.5V至1.8V之範圍中，且第三操作電壓可在0.8V至1.0V之範圍中。在所說明實施例中，第一電晶體11、第三電晶體13以 及第四電晶體14為N型電晶體，但本發明概念之態樣不限於此。
在第一電晶體11中，第一沉積絕緣層135以及第一閘極絕緣層130可形成於第一金屬閘極199與基板100(或場絕緣層105)之間。
在第三電晶體13中，第三閘極絕緣層330可形成於第三金屬閘極399與基板300(或場絕緣層305)之間。換言之，沉積絕緣層可不存在於第三金屬閘極399與基板300之間。
在第四電晶體14中，第四沉積絕緣層435及第五沉積絕緣層438以及第四閘極絕緣層430可形成於第四金屬閘極499與基板400(或場絕緣層405)之間。因此，由於第四沉積絕緣層435及第五沉積絕緣層438以及第四閘極絕緣層430之厚度的總和相對較大，故第四電晶體14可在3.0V或更大之高電壓下操作。第四電晶體14包括層間介電層410、溝槽412以及間隙壁420。
同時，第一電晶體11之第一沉積絕緣層135可與第四電晶體14之第四沉積絕緣層435或第五沉積絕緣層438同時形成，但本發明概念之態樣不限於此。
舉例而言，第四金屬閘極499可包含N型功函數控制膜470、第四黏接膜481以及第四金屬閘極圖案490，但本發明概念之態樣不限於此。
接下來，將參看圖10至圖12描述根據本發明概念之一些實施例之半導體裝置。圖10為根據本發明概念之一些實施例之半導體裝置的透視圖，圖11為沿著圖10之線A-A截取的橫截面圖，且圖12為沿著圖10之線B-B截取的橫截面圖。圖10至圖12說明圖1所示之N型電晶體之閘極，所述閘極被應用於鰭型電 晶體(FinFET)。
參看圖10至圖12，根據本發明概念之一些實施例之半導體裝置8可包含鰭狀物F1、第一金屬閘極199以及源極/汲極161。
鰭狀物F1可在第二方向Y1上縱向地延伸。鰭狀物F1可為基板100之一部分且可包含自基板100生長之磊晶層。場絕緣層105可覆蓋鰭狀物F1之側表面。第一金屬閘極199可在第一方向X1上延伸。如所示，第一金屬閘極199可包含N型功函數控制膜170、第一黏接膜181以及第一金屬閘極圖案190。
源極/汲極161可安置於第一金屬閘極199之相對兩側處。源極/汲極161可為升高(elevated)的源極/汲極。換言之，源極/汲極161之頂面可比層間介電層110之底面高。另外，源極/汲極161以及第一金屬閘極199可藉由間隙壁120而彼此絕緣。
當根據本發明概念之一些實施例之半導體裝置8為N型電晶體時，源極/汲極161可包含張應力(tensile stress)材料。源極/汲極161可包含與基板100相同之材料或張應力材料。舉例而言，當基板100包含Si時，源極/汲極161可包含Si或具有小於Si之晶格常數之材料(例如，SiC)。
儘管未圖示，但一些實施例規定圖5所示之P型電晶體之閘極可應用於鰭型電晶體。
一些實施例規定，在將P型電晶體之閘極(例如，圖5所示之閘極)應用於鰭型電晶體之情況下，源極/汲極161可包含壓應力(compressive stress)材料。舉例而言，壓應力材料可為具有大於矽(Si)之晶格常數之材料，例如，SiGe。壓應力材料可藉由將壓應力施加至鰭狀物F1而改良通道區域之載子之移動率。
圖13A至圖13D說明根據本發明之一些實施例之半導體裝置。具體言之，圖13A及圖13B為根據本發明概念之第九實施例之半導體裝置的佈局圖以及概念透視圖，圖13C為沿著圖13A之線C-C截取的橫截面圖，且圖13D為說明不對準之發生的橫截面圖。
首先，參看圖13A及圖13B，多個鰭狀物F1及F2可縱向地延伸。鰭狀物F1及F2可為基板101之部分且可包含自基板101生長之磊晶層。
在所說明實施例中，鰭狀物F1及F2具有直角平行六面體(rectangular parallepiped)之形狀，但本發明概念之態樣不限於此。換言之，鰭狀物F1及F2可經倒角(chamfered)。換言之，鰭狀物F1及F2之拐角(corner)部分可經磨圓。由於鰭狀物F1及F2在縱向方向上形成，故所述鰭狀物可包含長邊以及短邊。即使鰭狀物F1及F2之拐角經磨圓，但對熟習此項技術者而言，可明確地彼此區分長邊與短邊亦為顯而易見的。
通道可沿著鰭狀物F1及F2之三個表面彼此連接。一些實施例規定所述通道可形成於鰭狀物F1及F2之對向表面(facing surface)上。
層間介電層110可包含具有不同高度之第一部分111以及第一溝槽112，可將第一溝槽112視為第二部分。第一溝槽112可具有高度H0且第一部分111可具有高度(H0+H1)。詳細地說，例如，第一部分111可經形成以接觸鰭狀物F1及F2之短邊，且第一溝槽112可經形成以接觸鰭狀物F1及F2之長邊。第一部分111可形成於虛設閘極599下，且第一溝槽112可形成於普通閘極 699_1及699_2下。換言之，層間介電層110之一部分(亦即，第一部分111)可定位於彼此面對之鰭狀物之間(例如，鰭狀物F1與鰭狀物F2之間)。
層間介電層110可為氧化物膜、氮化物膜、氮氧化物膜或其組合。
層間介電層110可形成於第一鰭狀物F1、第二鰭狀物F2以及場絕緣層105上。另外，層間介電層110可包含暴露第一鰭狀物F1之至少一部分之第一溝槽612以及暴露層間介電層110之至少一部分之第二溝槽512。
第一普通閘極699_1安置於第一溝槽612中。第一普通閘極699_1可與(例如)圖4所示之閘極結構實質上相同，但本發明概念之態樣不限於此。第一普通閘極699_1亦可與(例如)圖3所示之閘極結構實質上相同，其包括功函數控制膜670、第一黏接膜681以及金屬閘極圖案690。圖13C中繪示有閘極絕緣層630與沉積絕緣層635a。
形成於層間介電層110上之沉積絕緣層535a、形成於沉積絕緣層535a上之閘極絕緣層530以及形成於閘極絕緣層530上之虛設閘極599可安置於第二溝槽512中。虛設閘極599包括功函數控制膜570、第一黏接膜581以及金屬閘極圖案590。
同時，多個虛設閘極599可形成於層間介電層110之對應(corresponding)部分上(亦即，層間介電層110之第一部分111上)。詳言之，多個虛設閘極599中之每一者可形成於對應第一部分111上。由於虛設閘極599是逐個形成而非兩個或兩個以上虛設閘極599一起形成，故佈局尺寸可減小。
另外，如所示，層間介電層110之第一部分111之頂面可低於第一鰭狀物F1之頂面(或第二鰭狀物F2之頂面)。
另外，如所示，第一鰭狀物F1與第二鰭狀物F2之間的距離W1可大於虛設閘極599之寬度W2。因此，虛設閘極599可定位於第一鰭狀物F1與第二鰭狀物F2之間。詳言之，第一間隙壁521以及第二間隙壁522可安置於虛設閘極599之兩個側壁上。 此處，第一間隙壁521之側壁與第一鰭狀物F1之側壁可彼此間隔分開，且第二間隙壁522之側壁與第二鰭狀物F2之側壁可彼此間隔分開。
自第一鰭狀物F1之頂面至第一普通閘極699_1之頂面之範圍的高度H3可小於自層間介電層110(亦即，第一部分111)至第一鰭狀物F1之頂面之範圍的高度H4。
同時，形成於第一鰭狀物F1中之第一升高源極/汲極662可進一步形成於第一普通閘極699_1之相對兩側上。
當不對準(misalignment)發生時，虛設閘極599可以如圖13D所示之方式安置。
在此情況下，第二溝槽512不僅可暴露層間介電層110之一部分，而且可暴露第一鰭狀物F1之一部分。沉積絕緣層535a可形成於第二溝槽512中以安置於層間介電層110上且安置於第一鰭狀物F1之側壁上。閘極絕緣層530可形成於沉積絕緣層535a上。虛設閘極599可形成於閘極絕緣層530上以安置於層間介電層110上且安置於第一鰭狀物F1之側壁上。如所示，沉積絕緣層535a可經形成以向上延伸至第一鰭狀物F1之頂面。
詳言之，沉積絕緣層535a亦可形成於層間介電層110之 頂面上。沉積絕緣層535a可防止正常鰭型電晶體發生缺陷。詳細地說，虛設閘極599可藉由替換製程來形成。換言之，形成犧牲絕緣層(或沉積絕緣層)，形成包圍犧牲圖案之層間介電層，且接著移除犧性圖案以在層間介電層中形成溝槽。在移除犧性圖案時可使用蝕刻溶液(例如，氨水)。若犧牲絕緣層(沉積絕緣層)未覆蓋層間介電層110之頂面(具體言之，層間介電層110與第一鰭狀物F1之間的以「K」標記之部分)，則蝕刻溶液可滲透至層間介電層110與第一鰭狀物F1之間的部分K中，藉此移除第一鰭狀物F1之側壁以及升高的源極/汲極(例如，eSD)。然而，在根據本發明概念之第九實施例之半導體裝置9中，由於沉積絕緣層535a形成於層間介電層110之頂面上，故有可能防止缺陷產生。
圖14A及圖14B為說明根據本發明概念之一些不同各別實施例之半導體裝置的概念圖。
首先參看圖14A，在根據本發明概念之一些實施例之半導體裝置10中，不同電晶體621及611可形成於SRAM區域620以及邏輯區域610中。舉例而言，在電晶體621(參見圖7的形成於第三區域III中之第三電晶體13)中，沉積絕緣層可不存在於金屬閘極與基板(或場絕緣層)之間。在電晶體611(參見圖7的形成於第一區域I中之第一電晶體11)中，沉積絕緣層可存在於金屬閘極與基板(或場絕緣層)之間。電晶體621可為在常規電壓下操作之電晶體且電晶體611可為在高電壓下操作之電晶體。
參看圖14B，在根據本發明概念之一些實施例之半導體裝置12中，不同電晶體623及624可形成於邏輯區域610中。如上所述，電晶體623可為在常規電壓下操作之電晶體且電晶體624 可為在高電壓下操作之電晶體。
圖15為根據本發明概念之一些實施例的包含半導體裝置之電子系統的方塊圖。
參看圖15，電子系統1100可包含控制器1110、輸入/輸出裝置(I/O)1120、記憶體裝置1130、介面1140以及匯流排1150。 控制器1110、I/O 1120、記憶體裝置1130及/或介面1140可經由匯流排1150彼此連接。匯流排1150對應於資料移動通過之路徑。
根據本發明概念之一些實施例之半導體裝置可用於邏輯區塊中之至少一者中。
控制器1110可包含微處理器、數位信號處理器、微控制器以及能夠實現類似於此等元件之功能的功能之邏輯元件中之至少一者。I/O 1120可包含小鍵盤、鍵盤、顯示裝置等。記憶體裝置1130可儲存資料及/或指令。介面1140可執行將資料傳輸至通信網路及/或自通信網路接收資料之功能。介面1140可為有線或無線的。舉例而言，介面1140可包含天線及/或有線/無線收發器等。
儘管未圖示，但電子系統1100可更包含作為運作記憶體之高速DRAM及/或SRAM以用於改良控制器1110之操作。根據本發明概念之一些實施例之鰭式電場效應電晶體可設置於記憶體裝置1130中或可被設置作為控制器1110或I/O 1120之一些組件。
電子系統1100可應用於個人數位助理(personal digital assistant；PDA)、攜帶型電腦、網路平板電腦(web tablet)、無線電話、行動電話、數位音樂播放器、記憶卡及/或能夠在無線環境中傳輸及/或接收資訊的任何類型之電子裝置。
在下文中，將參看圖16至圖21以及圖7描述根據本發 明概念之一些實施例之半導體裝置之製造方法。
圖16至圖21說明如圖7中所說明的根據本發明概念之一些實施例之半導體裝置之製造方法中的中間程序步驟。
首先參看圖16，基板100及300可包含界定於其中之第一區域I以及第三區域III。換言之，藉由在基板100及300中形成場絕緣層105及305來界定主動區域。
接下來，在具有場絕緣層105及305之基板100及300上形成犧牲絕緣層119a及319a。此處，犧牲絕緣層119a及319a可為藉由沉積方法形成之絕緣層。沉積方法可包含化學氣相沉積(CVD)及/或原子層沉積(ALD)，但本發明概念之態樣不限於此。
接下來，在犧牲絕緣層119a及319a上形成犧牲閘極層129a及329a。犧牲閘極層129a及329a可由(例如)多晶矽製成，但本發明概念之態樣不限於此。
參看圖17，圖案化犧牲閘極層129a及329a以及犧牲絕緣層119a及319a，藉此在第一區域I中形成第一犧牲閘極圖案129以及第一犧牲絕緣圖案119且在第三區域III中形成第三犧牲閘極圖案329以及第三犧牲絕緣圖案319。
接下來，形成層間介電層110及310以充分包圍第一犧牲閘極圖案129、第一犧牲絕緣圖案119、第三犧牲閘極圖案329以及第三犧牲絕緣圖案319。接下來，平坦化層間介電層110及310以暴露第一犧牲閘極圖案129之頂面以及第三犧牲閘極圖案329之頂面。
參看圖18，移除第一犧牲閘極圖案129以及第三犧牲閘極圖案329以暴露第一犧牲絕緣圖案119以及第三犧牲絕緣圖案 319。
參看圖19，移除第一犧牲絕緣圖案119以及第三犧牲絕緣圖案319以暴露場絕緣層105及305之頂面且形成第一溝槽112以及第三溝槽312。此處，可藉由(例如)濕式蝕刻來執行移除第一犧牲絕緣圖案119以及第三犧牲絕緣圖案319。由於第一犧牲絕緣圖案119以及第三犧性絕緣圖案319是藉由沉積形成，故可容易地移除所述犧牲絕緣圖案而無殘餘物。當移除藉由不同於沉積方法之方法(諸如，熱處理、使用雙電漿之方法、使用UV電漿之方法或使用過氧化物之方法)形成之絕緣圖案時，可產生殘餘物。殘餘物可變為後續程序中之缺陷且可使半導體裝置的操作特性劣化。
參看圖20，沿著層間介電層110及310之頂面、第一溝槽112之側壁以及底面以及第三溝槽312之側壁以及底面以共形方式形成沉積絕緣層135b及335b。沉積方法可包含化學氣相沉積(CVD)或原子層沉積(ALD)，但本發明概念之態樣不限於此。
參看圖21，形成遮罩999，所述遮罩999在暴露第三區域III的同時覆蓋第一區域I，且移除形成於第三區域III中之沉積絕緣層335b。可藉由(例如)濕式蝕刻來執行沉積絕緣層335b之移除。由於沉積絕緣層335b是藉由沉積方法形成，故可容易地移除所述沉積絕緣層而無殘餘物。當移除藉由不同於沉積方法之方法(諸如，熱處理、使用雙電漿之方法、使用UV電漿之方法或使用過氧化物之方法)形成之絕緣圖案時，可產生殘餘物。接下來，移除遮罩999。
返回參看圖7，在圖21所示之所得產品上依序形成高介 電常數材料層、用於形成N型功函數控制膜之金屬層、用於形成黏接膜之金屬層及/或用於形成金屬閘極圖案之金屬層，且對所述層執行平坦化以暴露層間介電層110及310之頂面。結果，第一金屬閘極圖案190、第一黏接膜181、N型功函數控制膜170以及第一閘極絕緣層130形成於第一區域I中，且第三金屬閘極圖案390、第三黏接膜381、N型功函數控制膜370以及第三閘極絕緣層330形成於第三區域III中。
圖22說明如圖8中所說明的根據本發明概念之一些實施例之半導體裝置之製造方法中的中間程序步驟。為了解釋便利起見，以下描述將著重於根據圖7及圖8所說明之實施例的製造方法之間的不同之處。詳言之，在根據本發明概念之第六實施例之半導體裝置的製造方法中，圖16至圖18所示之中間程序步驟與根據對應於圖7中所說明之實施例之半導體裝置的半導電裝置之製造方法中的中間程序步驟相同。
如圖16所示，在基板100及300上形成犧牲絕緣層119a及319a以及犧牲閘極層129a及329a。
接下來，如圖17所示，執行蝕刻製程以形成第一犧牲閘極圖案129、第一犧牲絕緣圖案119、第三犧牲閘極圖案329以及第三犧牲絕緣圖案319。在第一犧牲閘極圖案129、第一犧牲絕緣圖案119、第三犧牲閘極圖案329以及第三犧牲絕緣圖案319附近形成層間介電層110及310。
接下來，如圖18所示，移除第一犧牲閘極圖案129以及第三犧牲閘極圖案329。
參看圖22，形成遮罩998，所述遮罩998在暴露第三區 域III的同時覆蓋第一區域I，且移除形成於第三區域III中之第三犧牲絕緣圖案319。可藉由(例如)濕式蝕刻來執行第三犧牲絕緣圖案319之移除。由於第三犧牲絕緣圖案319是藉由沉積方法形成，故可容易地移除所述犧性絕緣圖案而無殘餘物。當移除藉由不同於沉積方法之方法(諸如，熱處理、使用雙電漿之方法、使用UV電漿之方法或使用過氧化物之方法)形成之絕緣圖案時，可產生殘餘物。第一犧牲絕緣圖案119保留在第一區域I中。使用第一犧牲絕緣圖案119作為參照圖8所描述之第一沉積絕緣層135a。
接下來，參看圖8，在圖22所示之所得產品上依序形成高介電常數材料層、用於形成N型功函數控制膜之金屬層、用於形成黏接膜之金屬層以及用於形成金屬閘極圖案之金屬層，且對所述層執行平坦化以暴露層間介電層110及310之頂面。如此一來，第一金屬閘極圖案190、第一黏接膜181、N型功函數控制膜170以及第一閘極絕緣層130形成於第一區域I中，且第三金屬閘極圖案390、第三黏接膜381、N型功函數控制膜370以及第三閘極絕緣層330形成於第三區域III中。
雖然已參考本發明概念之例示性實施例特定地展示以及描述本發明概念，但一般熟習此項技術者將理解，在不脫離如以下申請專利範圍所界定的本發明概念之精神以及範疇之情況下，可在其中進行形式以及細節上的各種改變。因此需要在各個方面將本發明實施例視為對附加申請專利範圍而非前述描述的說明性而非限制性參考，以指示本發明概念之範疇。
1‧‧‧半導體裝置
100‧‧‧基板
105‧‧‧場絕緣層
110‧‧‧層間介電層
112‧‧‧第一溝槽
120‧‧‧間隙壁
130‧‧‧第一閘極絕緣層
135‧‧‧第一沉積絕緣層
170‧‧‧N型功函數控制膜
181‧‧‧第一黏接膜
190‧‧‧第一金屬閘極圖案
199‧‧‧第一金屬閘極

Claims (12)

  1. 一種半導體裝置，其包括：鰭狀物，突出於基板；場絕緣層，配置於所述基板上；第一閘極，配置於所述鰭狀物上；源極/汲極區，位於所述第一閘極與所述場絕緣層之間；以及第二閘極，配置於所述場絕緣層上，其中所述第二閘極的底面低於所述第一閘極的底面，其中所述源極/汲極區的底面與所述源極/汲極區的頂面之間的第一距離大於所述場絕緣層的頂面與所述鰭狀物的頂面之間的第二距離，且所述第二距離大於所述源極/汲極區的所述頂面與所述第一閘極的頂面之間的第三距離。
  2. 如申請專利範圍第1項所述之半導體裝置，其中所述第一閘極包括金屬閘極圖案與至少覆蓋所述金屬閘極圖案的底部與相對兩側的功函數控制膜。
  3. 如申請專利範圍第2項所述之半導體裝置，更包括閘極絕緣層，配置於所述功函數控制膜與所述鰭狀物的所述頂面之間。
  4. 如申請專利範圍第1項所述之半導體裝置，其中所述基板為第三族至第五族基板。
  5. 如申請專利範圍第1項所述之半導體裝置，其中所述源極/汲極區包括SiGe。
  6. 如申請專利範圍第1項所述之半導體裝置，其中所述第一閘極為普通閘極，且所述第二閘極為虛設閘極。
  7. 一種半導體裝置，其包括： 鰭狀物，突出於基板；場絕緣層，配置於所述基板上；第一閘極，配置於所述鰭狀物上；源極/汲極區，位於所述第一閘極與所述場絕緣層之間；以及第二閘極，配置於所述場絕緣層上，其中所述第二閘極的底面低於所述第一閘極的底面，其中所述源極/汲極區的底面與所述源極/汲極區的頂面之間的第一距離大於所述源極/汲極區的所述底面與所述鰭狀物的頂面之間的第二距離，且所述第二距離大於所述第一閘極的所述底面至所述第一閘極的頂面之間的第三距離。
  8. 如申請專利範圍第7項所述之半導體裝置，其中所述第一閘極包括金屬閘極圖案與至少覆蓋所述金屬閘極圖案的底部與相對兩側的功函數控制膜。
  9. 如申請專利範圍第8項所述之半導體裝置，更包括閘極絕緣層，配置於所述功函數控制膜與所述鰭狀物的所述頂面之間。
  10. 如申請專利範圍第7項所述之半導體裝置，其中所述基板為第三族至第五族基板。
  11. 如申請專利範圍第7項所述之半導體裝置，其中所述源極/汲極區包括SiGe。
  12. 如申請專利範圍第7項所述之半導體裝置，其中所述第一閘極為普通閘極，且所述第二閘極為虛設閘極。
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US20170110547A1 (en) 2017-04-20
US9536878B2 (en) 2017-01-03
US10497788B2 (en) 2019-12-03
US9954066B2 (en) 2018-04-24
US20140353719A1 (en) 2014-12-04
CN104218085B (zh) 2019-01-22
KR102078187B1 (ko) 2020-02-17
CN104218085A (zh) 2014-12-17

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