TWI615851B - Sensing circuit and method for non-volatile memory device - Google Patents
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Abstract
一種非揮發性記憶裝置的感測電路，包括偏壓產生電路以及第一感測放大器。偏壓產生電路包括以參考電流偏壓的驅動電路以及運算放大器。運算放大器的非反向輸入端接收參考電壓，反向輸入端藉由負回授路徑產生輸出電壓，負回授路徑包括驅動電路。第一感測放大器包括第一複製電路以及第一電流感測電路。第一複製電路用以複製輸出電壓至第一位元線，第一位元線耦接第一記憶胞。第一電流感測電路用以感測第一電流差以決定第一記憶胞的第一記憶狀態，其中第一電流差係參考電流經縮放後與第一記憶胞的第一記憶胞電流之間的差值。A sensing circuit for a non-volatile memory device includes a bias generating circuit and a first sense amplifier. The bias generating circuit includes a driving circuit biased with a reference current and an operational amplifier. The non-inverting input of the operational amplifier receives the reference voltage, the inverting input generates an output voltage through a negative feedback path, and the negative feedback path includes a driving circuit. The first sense amplifier includes a first replica circuit and a first current sense circuit. The first replica circuit is configured to copy the output voltage to the first bit line, and the first bit line is coupled to the first memory cell. The first current sensing circuit is configured to sense the first current difference to determine a first memory state of the first memory cell, wherein the first current difference is between the reference current and the first memory cell current of the first memory cell The difference.
Description
本揭露是關於非揮發性記憶裝置，尤其是一種用於非揮發性記憶裝置的感測電路及方法。The present disclosure relates to non-volatile memory devices, and more particularly to a sensing circuit and method for a non-volatile memory device.
非揮發性記憶裝置(Non-Volatile Memory Device)在即使失去電源時仍然能夠保持其儲存的資料，非揮發性記憶體的範例包括有NAND快閃記憶體、NOR快閃記憶體、相變化記憶體(Phase Change Memory, PCM)、可變電阻式記憶體(Resistive Random Access Memory, RRAM)。非揮發性記憶體中所儲存的不同資料可對應到不同的臨界電壓(Vt)或是記憶胞不同的電阻值，因此可藉由感測流過記憶胞的電流以偵測記憶體狀態。隨著記憶體晶片內的記憶胞數量增加，如何設計可靠且符合成本效益的感測電路及方法，乃目前業界所致力的課題之一。Non-Volatile Memory Device can maintain its stored data even when power is lost. Examples of non-volatile memory include NAND flash memory, NOR flash memory, phase change memory. (Phase Change Memory, PCM), Resistive Random Access Memory (RRAM). The different data stored in the non-volatile memory can correspond to different threshold voltages (Vt) or different resistance values of the memory cells, so the state of the memory can be detected by sensing the current flowing through the memory cells. As the number of memory cells in a memory chip increases, how to design a reliable and cost-effective sensing circuit and method is one of the current topics in the industry.
本揭露係關於非揮發性記憶裝置的感測電路及感測方法。The disclosure relates to a sensing circuit and a sensing method for a non-volatile memory device.
依據本揭露之一實施例，提供一種非揮發性記憶裝置的感測電路。感測電路包括偏壓產生電路以及第一感測放大器。偏壓產生電路包括驅動電路以及運算放大器。驅動電路以參考電流偏壓。運算放大器的非反向輸入端接收參考電壓。運算放大器的反向輸入端藉由負回授路徑產生輸出電壓，負回授路徑包括驅動電路。第一感測放大器包括第一複製電路以及第一電流感測電路。第一複製電路耦接偏壓產生電路，用以複製輸出電壓至第一位元線，第一位元線耦接第一記憶胞。第一電流感測電路耦接第一複製電路，用以感測第一電流差以決定第一記憶胞的第一記憶狀態，其中第一電流差係參考電流經縮放後與第一記憶胞的第一記憶胞電流之間的差值。In accordance with an embodiment of the present disclosure, a sensing circuit for a non-volatile memory device is provided. The sensing circuit includes a bias generating circuit and a first sense amplifier. The bias generating circuit includes a driving circuit and an operational amplifier. The drive circuit is biased with a reference current. The non-inverting input of the operational amplifier receives the reference voltage. The inverting input of the operational amplifier generates an output voltage through a negative feedback path, and the negative feedback path includes a driving circuit. The first sense amplifier includes a first replica circuit and a first current sense circuit. The first replica circuit is coupled to the bias generating circuit for replicating the output voltage to the first bit line, and the first bit line is coupled to the first memory cell. The first current sensing circuit is coupled to the first replica circuit for sensing the first current difference to determine a first memory state of the first memory cell, wherein the first current difference is compared with the first memory cell after the reference current is scaled The difference between the first memory cell currents.
依據本揭露之一實施例，提供一種非揮發性記憶裝置的感測方法，感測方法包括下列步驟。以參考電流偏壓驅動電路；以運算放大器的非反向輸入端接收參考電壓；於運算放大器的反向輸入端藉由負回授路徑產生輸出電壓，負回授路徑包括驅動電路；複製輸出電壓至第一位元線，第一位元線耦接第一記憶胞；以及感測第一電流差以決定第一記憶胞的第一記憶狀態，其中第一電流差係參考電流經縮放後與第一記憶胞的第一記憶胞電流之間的差值。According to an embodiment of the present disclosure, a sensing method of a non-volatile memory device is provided, and the sensing method includes the following steps. Driving the circuit with a reference current bias; receiving the reference voltage at the non-inverting input of the operational amplifier; generating an output voltage through the negative feedback path at the inverting input of the operational amplifier, the negative feedback path including the driving circuit; copying the output voltage Up to the first bit line, the first bit line is coupled to the first memory cell; and sensing the first current difference to determine a first memory state of the first memory cell, wherein the first current difference is after the reference current is scaled The difference between the first memory cell currents of the first memory cells.
第1圖繪示一種用於非揮發性記憶體的範例箝制感測電路。此圖中電流I_Cell代表流過記憶胞的電流，位元線電壓VBL被提供至位元線，接著藉由感測此位元線的電壓或電流，以偵測目標記憶胞的狀態。然而如第1圖所示的電路可能會碰到一些問題，舉例而言，當此感測電路用於RRAM，位元線電壓VBL變得會受到記憶胞電流I_Cell影響，對於低電阻記憶胞，會有較大的記憶胞電流I_Cell，而降低了位元線電壓VBL (與高電阻記憶胞比較)，如此不穩定的位元線電壓VBL可能造成讀取窗損耗，造成資料讀取錯誤。此外，電路中若是位元線電壓VBL因某些原因而過充電(overcharge)，例如是受到擾動或是信號干擾，則唯一的放電路徑是藉由記憶胞電流I_Cell，由於記憶胞電流I_Cell是奈安培(nA)等級，如此的放電速度很慢，且在記憶體陣列結構中，感測的記憶胞可能距離感測電路很遠，更使得放電速度變慢。而在另一範例中，當此感測電路用於NOR快閃記憶體，軟程式化效應(soft program effect)會變得更加嚴重。具體而言，當讀取NOR快閃記憶體時，同時也會輕微對其產生程式化操作，而當讀取低Vt記憶胞時，由於記憶胞被輕微程式化而使得臨界電壓上升，上升的臨界電壓會導致記憶胞電流I_Cell下降，如此又造成位元線電壓VBL上升，而更加強了程式化操作的效果，使得臨界電壓被上升更多。如此造成正回授的軟程式化效應，可能使得一個低Vt記憶胞在讀取操作時變成高Vt記憶胞。由於上述所提及的問題，於感測非揮發性記憶胞裝置時，有必要提供一個穩定的位元線電壓VBL。Figure 1 illustrates an example clamp sensing circuit for non-volatile memory. In the figure, the current I_Cell represents the current flowing through the memory cell, and the bit line voltage VBL is supplied to the bit line, and then the state of the target memory cell is detected by sensing the voltage or current of the bit line. However, the circuit shown in Figure 1 may encounter some problems. For example, when the sensing circuit is used for RRAM, the bit line voltage VBL becomes affected by the memory cell current I_Cell. For low-resistance memory cells, There will be a large memory cell current I_Cell, and the bit line voltage VBL (compared to the high resistance memory cell) is lowered. Such an unstable bit line voltage VBL may cause a reading window loss, resulting in a data reading error. In addition, if the bit line voltage VBL is overcharged for some reason in the circuit, for example, by disturbance or signal interference, the only discharge path is by the memory cell current I_Cell, since the memory cell current I_Cell is Ampere (nA) grade, such a discharge speed is very slow, and in the memory array structure, the sensed memory cell may be far away from the sensing circuit, and the discharge speed is slowed down. In another example, when the sensing circuit is used in NOR flash memory, the soft program effect becomes more serious. Specifically, when the NOR flash memory is read, the programmatic operation is also slightly generated at the same time, and when the low Vt memory cell is read, the threshold voltage rises due to the slight stylization of the memory cell, and rises. The threshold voltage causes the memory cell current I_Cell to drop, which in turn causes the bit line voltage VBL to rise, which further enhances the effect of the stylized operation, causing the threshold voltage to rise more. This causes a soft stylization effect of positive feedback, which may cause a low Vt memory cell to become a high Vt memory cell during a read operation. Due to the problems mentioned above, it is necessary to provide a stable bit line voltage VBL when sensing a non-volatile memory cell device.
第2圖繪示依據本發明一實施例感測電路架構的方塊圖。感測電路1包括偏壓產生電路100以及多個感測放大器(Sense Amplifier, SA)110、120、130、…、190。每一個感測放大器110-190可耦接到記憶體陣列結構中的其中一個位元線，以讀取該些位元線上的記憶胞資料。偏壓產生電路100可提供至少一偏壓電壓至所有的感測放大器110-190。在感測電路1中，由於所有的感測放大器110-190共享同一個偏壓產生電路100，因此可以節省用於產生偏壓的電路面積。2 is a block diagram of a sensing circuit architecture in accordance with an embodiment of the present invention. The sensing circuit 1 includes a bias generating circuit 100 and a plurality of sense amplifiers (SAs) 110, 120, 130, ..., 190. Each of the sense amplifiers 110-190 can be coupled to one of the bit lines in the memory array structure to read the memory cell data on the bit lines. The bias generating circuit 100 can provide at least one bias voltage to all of the sense amplifiers 110-190. In the sensing circuit 1, since all of the sense amplifiers 110-190 share the same bias generating circuit 100, the circuit area for generating a bias can be saved.
第3圖繪示依據本發明一實施例感測電路的示意圖。於第3圖中繪示單一個感測放大器以簡化圖示說明，並且用以表示本揭露的感測電路亦可以僅使用單一個感測放大器。於此實施例中，感測電路1包括偏壓產生電路100以及第一感測放大器110。偏壓產生電路100包括驅動電路102以及運算放大器104。驅動電路102以參考電流I REF偏壓(bias)。運算放大器104的非反向輸入端接收參考電壓V REF。運算放大器104的反向輸入端藉由負回授路徑產生輸出電壓V OUT，負回授路徑包括驅動電路102。第一感測放大器110包括第一複製電路112以及第一電流感測電路114。第一複製電路112耦接偏壓產生電路100，用以複製輸出電壓V OUT至第一位元線BL1，第一位元線BL1耦接第一記憶胞210。第一電流感測電路114耦接第一複製電路112，用以感測第一電流差以決定第一記憶胞210的第一記憶狀態，其中第一電流差係參考電流I REF經縮放後與第一記憶胞210的第一記憶胞電流之間的差值。 FIG. 3 is a schematic diagram of a sensing circuit according to an embodiment of the invention. A single sense amplifier is illustrated in FIG. 3 to simplify the illustration, and the sensing circuit used to represent the present disclosure may also use only a single sense amplifier. In this embodiment, the sensing circuit 1 includes a bias generating circuit 100 and a first sense amplifier 110. The bias voltage generating circuit 100 includes a driving circuit 102 and an operational amplifier 104. The drive circuit 102 is biased with a reference current I REF . The non-inverting input of operational amplifier 104 receives a reference voltage V REF . The inverting input of operational amplifier 104 produces an output voltage V OUT through a negative feedback path that includes drive circuit 102. The first sense amplifier 110 includes a first replica circuit 112 and a first current sense circuit 114. The first replica circuit 112 is coupled to the bias generating circuit 100 for replicating the output voltage V OUT to the first bit line BL1. The first bit line BL1 is coupled to the first memory cell 210. The first current sensing circuit 114 is coupled to the first replica circuit 112 for sensing the first current difference to determine a first memory state of the first memory cell 210, wherein the first current difference is compared with the reference current I REF and The difference between the first memory cell currents of the first memory cell 210.
用於第3圖所示的感測電路的感測方法可參考第8圖，其繪示依據本發明一實施例用於非揮發性記憶體的感測方法流程圖，包括下列步驟。步驟S400：以參考電流偏壓驅動電路。步驟S402：以運算放大器的非反向輸入端接收參考電壓。步驟S404：於運算放大器的反向輸入端藉由負回授路徑產生輸出電壓，負回授路徑包括驅動電路。步驟S406：複製輸出電壓至第一位元線，第一位元線耦接第一記憶胞。步驟S408：感測第一電流差以決定第一記憶胞的第一記憶狀態，其中第一電流差係參考電流經縮放後與第一記憶胞的第一記憶胞電流之間的差值。The sensing method for the sensing circuit shown in FIG. 3 can be referred to FIG. 8 , which illustrates a flow chart of a sensing method for non-volatile memory according to an embodiment of the invention, including the following steps. Step S400: biasing the driving circuit with a reference current. Step S402: receiving the reference voltage by the non-inverting input terminal of the operational amplifier. Step S404: The output voltage is generated by the negative feedback path at the inverting input terminal of the operational amplifier, and the negative feedback path includes the driving circuit. Step S406: Copy the output voltage to the first bit line, and the first bit line is coupled to the first memory cell. Step S408: Sensing the first current difference to determine a first memory state of the first memory cell, wherein the first current difference is a difference between the reference current and the first memory cell current of the first memory cell after being scaled.
在偏壓產生電路100中，運算放大器104接收的參考電壓V REF可以由能帶隙(Bandgap)參考電壓電路所提供，能帶隙參考電壓電路能夠提供固定電壓輸出，不受到電源供應變異、溫度改變、或電路負載影響。驅動電路102以及運算放大器104可組成負回授路徑，由於運算放大器104在輸入端之間的虛擬短路特性，在運算放大器104反向輸入端的輸出電壓V OUT實質等同於非反向輸入端的參考電壓V REF。而第一複製電路112複製輸出電壓V OUT至第一位元線BL1，因此能夠成功提供一個穩定的位元線電壓至讀取記憶胞的位元線。 In the bias generating circuit 100, the reference voltage V REF received by the operational amplifier 104 can be provided by a Bandgap reference voltage circuit, and the bandgap reference voltage circuit can provide a fixed voltage output without being subjected to power supply variations and temperatures. Change, or circuit load impact. The drive circuit 102 and the operational amplifier 104 can form a negative feedback path. The output voltage V OUT at the inverting input of the operational amplifier 104 is substantially equivalent to the reference voltage of the non-inverting input due to the virtual short-circuit characteristic between the input terminals of the operational amplifier 104. V REF . The first replica circuit 112 copies the output voltage V OUT to the first bit line BL1, so that a stable bit line voltage can be successfully supplied to the bit line of the read memory cell.
為了讀取第一記憶胞210所儲存的內容，感測第一記憶胞210的第一記憶胞電流，接著，感測到的第一記憶胞電流與縮放後的參考電流I REF比較，由第一電流感測電路114感測縮放後的參考電流I REF與第一記憶胞210的第一記憶胞電流之間的第一電流差。可以藉由適當地縮放參考電流I REF，而使得第一電流差為第一記憶胞210狀態的一個清楚指示。舉例而言，參考電流I REF可以依據電路實作而被縮放為1/2、2/3、3/4倍或其他倍率。在一實施例中，第一電流差可由縮放後的參考電流I REF減去第一記憶胞電流而獲得。當第一電流差大於0時，第一記憶胞210被判定為高Vt記憶胞；當第一電流差小於0時，第一記憶胞210被判定為低Vt記憶胞。此處僅為例示性的表示縮放倍率以及電流比較操作，本發明並不限定於此。 In order to read the content stored by the first memory cell 210, the first memory cell current of the first memory cell 210 is sensed, and then the sensed first memory cell current is compared with the scaled reference current I REF by A current sensing circuit 114 senses a first current difference between the scaled reference current I REF and the first memory cell current of the first memory cell 210. The first current difference can be made a clear indication of the state of the first memory cell 210 by appropriately scaling the reference current I REF . For example, the reference current I REF can be scaled to 1/2, 2/3, 3/4 times, or other magnification depending on the implementation of the circuit. In an embodiment, the first current difference is obtained by subtracting the first memory cell current from the scaled reference current I REF . When the first current difference is greater than 0, the first memory cell 210 is determined to be a high Vt memory cell; when the first current difference is less than 0, the first memory cell 210 is determined to be a low Vt memory cell. Here, the zoom magnification and the current comparison operation are merely exemplarily shown, and the present invention is not limited thereto.
如第2圖所示，感測電路1可能包括多於一個感測放大器，第4圖繪示依據本發明一實施例包括兩個感測放大器的感測電路示意圖。如第4圖所示的感測電路包括偏壓產生電路100、第一感測放大器110、以及第二感測放大器120。第二感測放大器120結構上可以與第一感測放大器110相同。第二感測放大器120包括第二複製電路122以及第二電流感測電路124。第二複製電路122耦接偏壓產生電路100，用以複製輸出電壓V OUT至第二位元線BL2，第二位元線BL2耦接第二記憶胞220。第二電流感測電路124耦接第二複製電路122，用以感測第二電流差以決定第二記憶胞220的第二記憶狀態，其中第二電流差係參考電流I REF經縮放後與第二記憶胞220的第二記憶胞電流之間的差值。 As shown in FIG. 2, the sensing circuit 1 may include more than one sense amplifier, and FIG. 4 is a schematic diagram of a sensing circuit including two sense amplifiers according to an embodiment of the invention. The sensing circuit as shown in FIG. 4 includes a bias generating circuit 100, a first sense amplifier 110, and a second sense amplifier 120. The second sense amplifier 120 can be structurally identical to the first sense amplifier 110. The second sense amplifier 120 includes a second replica circuit 122 and a second current sense circuit 124. The second replica circuit 122 is coupled to the bias generating circuit 100 for replicating the output voltage V OUT to the second bit line BL2, and the second bit line BL2 is coupled to the second memory cell 220. The second current sensing circuit 124 is coupled to the second replica circuit 122 for sensing the second current difference to determine a second memory state of the second memory cell 220, wherein the second current difference is the reference current I REF is scaled and The difference between the second memory cell currents of the second memory cell 220.
第二記憶胞220可經由字元線(word line)耦接至第一記憶胞210，並且可鄰近於第一記憶胞210，亦即，於記憶體陣列結構中第二位元線BL2可以鄰近於第一位元線BL1。第一感測放大器110以及第二感測放大器120共用同樣的偏壓產生電路100，因此能夠降低硬體成本。舉例而言，對於具有上百條或是上千條位元線的記憶裝置，雖然需要有對應數量的感測放大器，使用本揭露的感測電路僅需要共用一個偏壓產生電路即可。在一實施例中，偏壓產生電路100提供至少一偏壓電壓至第一感測放大器110以及第二感測放大器120，使得能有穩定的位元線電壓提供至第一位元線BL1以及第二位元線BL2。關於第二感測放大器120的操作，由於類似於第一感測放大器100，於此不再贅述。The second memory cell 220 can be coupled to the first memory cell 210 via a word line and can be adjacent to the first memory cell 210, that is, the second bit line BL2 can be adjacent in the memory array structure. On the first bit line BL1. The first sense amplifier 110 and the second sense amplifier 120 share the same bias generation circuit 100, and thus the hardware cost can be reduced. For example, for a memory device having hundreds or thousands of bit lines, although a corresponding number of sense amplifiers are required, the sensing circuit of the present disclosure only needs to share one bias generating circuit. In an embodiment, the bias generating circuit 100 provides at least one bias voltage to the first sense amplifier 110 and the second sense amplifier 120 such that a stable bit line voltage can be supplied to the first bit line BL1 and The second bit line BL2. Regarding the operation of the second sense amplifier 120, since it is similar to the first sense amplifier 100, it will not be described herein.
用於第4圖所示的感測電路的感測方法可參考第9圖，其繪示依據本發明一實施例用於非揮發性記憶體的感測方法流程圖。與第8圖流程圖相較，第9圖更包括步驟S416及步驟S418。步驟S416：複製輸出電壓至第二位元線，第二位元線耦接第二記憶胞。步驟S418：感測第二電流差以決定第二記憶胞的第二記憶狀態，其中第二電流差係參考電流經縮放後與第二記憶胞的第二記憶胞電流之間的差值。步驟S416可由第二複製電路122執行，而步驟S418可由第二電流感測電路124執行。A sensing method for the sensing circuit shown in FIG. 4 can be referred to FIG. 9, which illustrates a flow chart of a sensing method for non-volatile memory according to an embodiment of the present invention. Compared with the flowchart of FIG. 8, FIG. 9 further includes step S416 and step S418. Step S416: Copy the output voltage to the second bit line, and the second bit line is coupled to the second memory cell. Step S418: Sensing the second current difference to determine a second memory state of the second memory cell, wherein the second current difference is a difference between the reference current and the second memory cell current of the second memory cell. Step S416 can be performed by the second replica circuit 122, and step S418 can be performed by the second current sensing circuit 124.
第一複製電路112可以有多種電路實現方式。於一實施例中，第一複製電路112包括第一電流鏡(Current Mirror)，用以鏡射參考電流I REF。第一電流鏡可產生與參考電流I REF相同的電流，使得第一複製電路112產生的電壓可相等於輸出電壓V OUT。第一電流鏡可由雙極電晶體(BJT)或金氧半場效電晶體(MOSFET)實作，而第二複製電路122亦可同樣採用電流鏡的電路實現方式。 The first replica circuit 112 can have a variety of circuit implementations. In an embodiment, the first replica circuit 112 includes a first current mirror (Mirror Mirror) for mirroring the reference current I REF . The first current mirror can generate the same current as the reference current I REF such that the voltage generated by the first replica circuit 112 can be equal to the output voltage V OUT . The first current mirror can be implemented by a bipolar transistor (BJT) or a gold oxide half field effect transistor (MOSFET), and the second replica circuit 122 can also be implemented by a circuit of a current mirror.
第一電流感測電路114亦可以多種電路結構實現，第5圖繪示依據本發明一實施例第一電流感測電路的示意圖。第一電流感測電路114包括感測電晶體Ms、感測電流鏡140、縮放參考電流鏡142、以及電流比較器144。感測電晶體Ms用以偵測第一記憶胞電流，感測電晶體Ms可耦接第一位元線BL1並可由NMOS電晶體實作。在第5圖中感測電晶體Ms繪示為NMOS電晶體，然而於實作中，感測電晶體Ms亦可以是PMOS電晶體。感測電流鏡140用以鏡射流經感測電晶體Ms的電流。縮放參考電流鏡142用以鏡射縮放後的參考電流I REF。電流比較器144用以比較感測電流鏡140的電流以及縮放參考電流鏡142的電流，以決定第一記憶胞210的第一記憶狀態。 The first current sensing circuit 114 can also be implemented in various circuit configurations. FIG. 5 is a schematic diagram of a first current sensing circuit according to an embodiment of the invention. The first current sensing circuit 114 includes a sensing transistor Ms, a sensing current mirror 140, a scaling reference current mirror 142, and a current comparator 144. The sensing transistor Ms is configured to detect the first memory cell current, and the sensing transistor Ms can be coupled to the first bit line BL1 and can be implemented by the NMOS transistor. In FIG. 5, the sensing transistor Ms is illustrated as an NMOS transistor, but in practice, the sensing transistor Ms may also be a PMOS transistor. The sense current mirror 140 is used to mirror the current flowing through the sense transistor Ms. The scaled reference current mirror 142 is used to mirror the scaled reference current I REF . The current comparator 144 is configured to compare the current of the current mirror 140 and the current of the reference current mirror 142 to determine a first memory state of the first memory cell 210.
如前所述，參考電流I REF可經由適當縮放以利於感測操作，在一實施例中，其縮放倍率可由電晶體尺寸控制。根據如第5圖所示的電路結構，感測電流鏡140獲得第一記憶胞210的電流資訊，縮放參考電流鏡142獲得縮放後的參考電流，電流比較器144可藉由比較這兩個電流而決定記憶體狀態。舉例而言，電流比較器144可包括一個輸出閂鎖器及/或負載電容，當縮放後的參考電流大於記憶胞電流時，可對負載電容充電以輸出高邏輯位準，代表高Vt記憶胞；反之，當縮放後的參考電流小於記憶胞電流時，可對負載電容放電以輸出低邏輯位準，代表低Vt記憶胞。此處僅為例示性說明，而非用以限定本發明，電流比較器144亦可使用不同的電路實作 (例如在一實施例中電流比較器輸出高邏輯位準可用以代表低Vt記憶胞)。而第5圖所繪示的為功能方塊示意圖，是用以清楚表示第一電流感測電路114的操作原理，第5圖當中不同的功能方塊於電路實現中可以具有相同的電路元件。 As previously mentioned, the reference current I REF can be scaled appropriately to facilitate sensing operations, and in one embodiment, its zoom ratio can be controlled by the transistor size. According to the circuit structure as shown in FIG. 5, the sense current mirror 140 obtains current information of the first memory cell 210, the scaled reference current mirror 142 obtains the scaled reference current, and the current comparator 144 can compare the two currents. And determine the state of the memory. For example, the current comparator 144 can include an output latch and/or a load capacitor. When the scaled reference current is greater than the memory current, the load capacitor can be charged to output a high logic level, representing a high Vt memory cell. Conversely, when the scaled reference current is less than the memory cell current, the load capacitor can be discharged to output a low logic level, representing a low Vt memory cell. The current comparator 144 can also be implemented using different circuits (for example, in one embodiment, the current comparator output high logic level can be used to represent the low Vt memory cell, for illustrative purposes only, and not to limit the invention. ). FIG. 5 is a functional block diagram for clearly illustrating the operation principle of the first current sensing circuit 114. The different functional blocks in FIG. 5 may have the same circuit components in the circuit implementation.
用於第5圖所示第一電流感測電路114的方法可參考第10圖，其繪示依據本發明一實施例偵測第一電流差異步驟的流程圖，其中第一電流差異為第一記憶胞電流及縮放後參考電流的差異，此方法包括下列步驟。步驟S430：以感測電晶體偵測第一記憶胞電流。步驟S432：致能感測電流鏡以鏡射流經感測電晶體的電流。步驟S434：致能縮放參考電流鏡以鏡射縮放後的參考電流，其縮放倍率例如可以是1/2、2/3、3/4等等。步驟S436：比較感測電流鏡的電流以及縮放參考電流鏡的電流，以決定第一記憶胞的第一記憶狀態。For the method of the first current sensing circuit 114 shown in FIG. 5, reference may be made to FIG. 10, which is a flowchart of a step of detecting a first current difference according to an embodiment of the present invention, wherein the first current difference is first. The difference between the memory cell current and the scaled reference current, the method includes the following steps. Step S430: detecting the first memory cell current by the sensing transistor. Step S432: Assisting the current mirror to mirror the current flowing through the sensing transistor. Step S434: The reference current mirror is enabled to be scaled to mirror the scaled reference current, and the zoom ratio may be, for example, 1/2, 2/3, 3/4, or the like. Step S436: Comparing the current of the sensing current mirror and the current of the scaling reference current mirror to determine the first memory state of the first memory cell.
以下提出一個電晶體層級的實作方式實施例，於此實施例中使用MOSFET電晶體作為例子說明。第6圖繪示依據本發明一實施例偏壓產生電路的示意圖。驅動電路102包括第一PMOS電晶體MP1以及第一NMOS電晶體MN1。第一PMOS電晶體MP1具有源極、汲極、以及閘極，源極耦接供應電壓VDD，閘極耦接汲極以提供第一偏壓電壓PBIAS。第一NMOS電晶體MN1具有源極耦接運算放大器104的反向輸入端、汲極耦接第一PMOS電晶體MP1的汲極、以及閘極耦接運算放大器104的輸出端以提供第二偏壓電壓NBIAS。在此實施例中，偏壓產生電路100提供兩個偏壓電壓至第一感測放大器110 (以及第二感測放大器120)，兩個偏壓電壓包括PBIAS以及NBIAS。第一PMOS電晶體MP1以及第一NMOS電晶體MN1是以參考電流I REF偏壓。 An embodiment of a transistor level implementation is presented below, and a MOSFET transistor is used as an example in this embodiment. 6 is a schematic diagram of a bias generating circuit in accordance with an embodiment of the present invention. The driving circuit 102 includes a first PMOS transistor MP1 and a first NMOS transistor MN1. The first PMOS transistor MP1 has a source, a drain, and a gate. The source is coupled to the supply voltage VDD, and the gate is coupled to the drain to provide a first bias voltage PBIAS. The first NMOS transistor MN1 has a source coupled to the inverting input of the operational amplifier 104, a drain coupled to the drain of the first PMOS transistor MP1, and a gate coupled to the output of the operational amplifier 104 to provide a second bias. The voltage is NBIAS. In this embodiment, the bias generation circuit 100 provides two bias voltages to the first sense amplifier 110 (and the second sense amplifier 120), the two bias voltages including PBIAS and NBIAS. The first PMOS transistor MP1 and the first NMOS transistor MN1 are biased with a reference current I REF .
第7圖繪示依據本發明一實施例第一感測放大器的示意圖。第一複製電路112包括第二PMOS電晶體MP2以及第二NMOS電晶體MN2。第二PMOS電晶體MP2具有源極、汲極、以及閘極，閘極耦接第一偏壓電壓PBIAS。第二NMOS電晶體MN2具有源極耦接第一位元線BL1、汲極耦接第二PMOS電晶體MP2的汲極、以及閘極耦接第二偏壓電壓NBIAS。FIG. 7 is a schematic diagram of a first sense amplifier according to an embodiment of the invention. The first replica circuit 112 includes a second PMOS transistor MP2 and a second NMOS transistor MN2. The second PMOS transistor MP2 has a source, a drain, and a gate, and the gate is coupled to the first bias voltage PBIAS. The second NMOS transistor MN2 has a source coupled to the first bit line BL1, a drain coupled to the drain of the second PMOS transistor MP2, and a gate coupled to the second bias voltage NBIAS.
在一實施例中，第一PMOS電晶體MP1與第二PMOS電晶體MP2可形成匹配對，此外，第一NMOS電晶體MN1與第二NMOS電晶體MN2亦可形成匹配對，如此可形成電流鏡結構。在一實施例中，第一PMOS電晶體MP1以及第二PMOS電晶體MP2尺寸相同，第一NMOS電晶體MN1以及第二NMOS電晶體MN2尺寸相同，因此流經第二PMOS電晶體MP2與第二NMOS電晶體MN2的電流，實質相等於參考電流I REF。如此一來，驅動電路102以及第一複製電路112在相同的偏壓條件下，在第二NMOS電晶體源極的位元線電壓實質相等於輸出電壓V OUT，因此可將穩定的位元線電壓成功提供至第一位元線BL1。 In an embodiment, the first PMOS transistor MP1 and the second PMOS transistor MP2 can form a matching pair. In addition, the first NMOS transistor MN1 and the second NMOS transistor MN2 can also form a matching pair, so that a current mirror can be formed. structure. In an embodiment, the first PMOS transistor MP1 and the second PMOS transistor MP2 are the same size, and the first NMOS transistor MN1 and the second NMOS transistor MN2 are the same size, and thus flow through the second PMOS transistor MP2 and the second The current of the NMOS transistor MN2 is substantially equal to the reference current I REF . In this way, the driving circuit 102 and the first replica circuit 112 have the bit line voltage at the source of the second NMOS transistor substantially equal to the output voltage V OUT under the same bias condition, so that stable bit lines can be used. The voltage is successfully supplied to the first bit line BL1.
第一電流感測電路114包括第三NMOS電晶體MN3、第三PMOS電晶體MP3、以及第四NMOS電晶體MN4。第三NMOS電晶體MN3具有源極、汲極耦接第一位元線BL1、以及閘極耦接第二NMOS電晶體MN2的汲極。第三PMOS電晶體MP3具有源極、汲極、以及閘極耦接第一偏壓電壓PBIAS。第四NMOS電晶體MN4具有源極、汲極耦接第三PMOS電晶體MP3的汲極、以及閘極耦接第三NMOS電晶體MN3的閘極。The first current sensing circuit 114 includes a third NMOS transistor MN3, a third PMOS transistor MP3, and a fourth NMOS transistor MN4. The third NMOS transistor MN3 has a source, a drain coupled to the first bit line BL1, and a gate coupled to the drain of the second NMOS transistor MN2. The third PMOS transistor MP3 has a source, a drain, and a gate coupled to the first bias voltage PBIAS. The fourth NMOS transistor MN4 has a source, a drain coupled to the drain of the third PMOS transistor MP3, and a gate coupled to the gate of the third NMOS transistor MN3.
如第7圖所示，流經第三NMOS電晶體MN3的電流是參考電流I REF與第一記憶胞210的記憶胞電流I_Cell之間的差值 (I MN3= I REF- I_Cell)。換言之，第三NMOS電晶體MN3相當於感測了第一記憶胞210的記憶胞電流 (參考第5圖所示的感測電晶體Ms)。在一實施例中，第三NMOS電晶體MN3與第四NMOS電晶體MN4尺寸相同，形成電流鏡結構，流經第四NMOS電晶體MN4的電流實質相等於流經第三NMOS電晶體MN3的電流 (I MN4= I MN3= I REF- I_Cell)，第三NMOS電晶體MN3與第四NMOS電晶體MN4可組成第5圖所示的感測電流鏡140。 As shown in FIG. 7, the current flowing through the third NMOS transistor MN3 is the difference (I MN3 = I REF - I_Cell) between the reference current I REF and the memory cell current I_Cell of the first memory cell 210. In other words, the third NMOS transistor MN3 is equivalent to sensing the memory cell current of the first memory cell 210 (refer to the sensing transistor Ms shown in FIG. 5). In one embodiment, the third NMOS transistor MN3 is the same size as the fourth NMOS transistor MN4, forming a current mirror structure, and the current flowing through the fourth NMOS transistor MN4 is substantially equal to the current flowing through the third NMOS transistor MN3. (I MN4 = I MN3 = I REF - I_Cell), the third NMOS transistor MN3 and the fourth NMOS transistor MN4 may constitute the sensing current mirror 140 shown in FIG.
第一PMOS電晶體MP1與第三PMOS電晶體MP3亦可形成電流鏡 (參考第5圖所示的縮放參考電流鏡142)。第三PMOS電晶體MP3的尺寸是k倍於第一PMOS電晶體MP1的尺寸，此比例k可以適當地被設定而鏡射縮放後的參考電流(k×I REF)。第7圖所示的輸出節點SAout可以耦接至負載電容及/或閂鎖器以產生感測結果。從輸出節點SAout流出的電流為第一電流差 (I MP3- I MN4) = k×I REF- (I REF- I_Cell) = I_Cell - (1-k)×I REF。第三PMOS電晶體MP3與第四NMOS電晶體MN4組成電流比較器，用以比較縮放後的參考電流以及記憶胞電流 (參考第5圖所示的電流比較器144)。 The first PMOS transistor MP1 and the third PMOS transistor MP3 may also form a current mirror (refer to the scaled reference current mirror 142 shown in FIG. 5). The size of the third PMOS transistor MP3 is k times the size of the first PMOS transistor MP1, and this ratio k can be appropriately set to mirror the scaled reference current (k×I REF ). The output node SAout shown in FIG. 7 can be coupled to a load capacitor and/or a latch to generate a sensing result. The current flowing from the output node SAout is the first current difference (I MP3 - I MN4 ) = k × I REF - (I REF - I_Cell) = I_Cell - (1-k) × I REF . The third PMOS transistor MP3 and the fourth NMOS transistor MN4 form a current comparator for comparing the scaled reference current and the memory cell current (refer to the current comparator 144 shown in FIG. 5).
為了使得感測放大器電路單純，且為了使第一電流差能夠成為第一記憶胞210狀態的一個清楚指示，第一電流差可設定為依據第一記憶胞210不同狀態而具有不同極性。因此，數值(1-k)×I REF可設定為相等於「參考記憶胞」的電流。參考記憶胞是一個特殊類型的記憶胞，其臨界電壓界於高Vt以及低Vt之間，使得參考記憶胞的電流可作為一個判斷的臨界點，用以根據感測到的一般記憶胞電流而判斷記憶胞狀態。於以下說明中，參考記憶胞的電流以Ir表示。 In order to make the sense amplifier circuit simple, and in order for the first current difference to be a clear indication of the state of the first memory cell 210, the first current difference can be set to have different polarities depending on the different states of the first memory cell 210. Therefore, the value (1-k) × I REF can be set to be equal to the current of the "reference memory cell". The reference memory cell is a special type of memory cell whose threshold voltage is between high Vt and low Vt, so that the current of the reference memory cell can be used as a critical point for judging according to the sensed general memory cell current. Determine the state of the memory cell. In the following description, the current of the reference memory cell is represented by Ir.
將數值(1-k)×I REF設定為等於Ir，則第一電流差為(I MP3- I MN4) = (I_Cell - Ir)，此數值在記憶胞狀態不同時具有不同極性，如此可使得記憶胞儲存資料容易被取得。有多種設計選擇可滿足式子(1-k)×I REF= Ir，在一實施例中，參考電流I REF是兩倍於參考記憶胞的電流Ir (I REF= 2×Ir)，且第一PMOS電晶體MP1尺寸是第三PMOS電晶體MP3尺寸的兩倍 (比例k=1/2)。當然亦有其他可能的參數設定，舉例而言，可設定I REF= 3×Ir以及k=2/3，其他參數亦可類推得到。而第3圖中所示的參考電流I REF，可以藉由電流鏡實現，此電流鏡用以鏡射縮放後(例如放大為2倍)的參考記憶胞的電流Ir。 Setting the value (1-k)×I REF equal to Ir, the first current difference is (I MP3 - I MN4 ) = (I_Cell - Ir), and this value has different polarities when the state of the memory cell is different, so that Memory cell storage data is easily obtained. There are a variety of design choices to satisfy the equation (1-k) × I REF = Ir. In one embodiment, the reference current I REF is twice the current Ir of the reference memory cell (I REF = 2 × Ir), and A PMOS transistor MP1 is twice the size of the third PMOS transistor MP3 (ratio k = 1/2). Of course, there are other possible parameter settings. For example, I REF = 3 × Ir and k = 2 / 3 can be set, and other parameters can be analogized. The reference current I REF shown in FIG. 3 can be realized by a current mirror for mirroring the current Ir of the reference memory cell after scaling (for example, 2 times magnification).
而第7圖當中的第一位元線BL1不僅可經由記憶胞電流I_Cell放電，同時亦可經由第三NMOS電晶體MN3放電。若是位元線電壓因某些原因而過充電，由於提供了額外的放電路徑，放電速度可獲得改善 (相較於僅經由記憶胞放電)。因此本揭露的電路結構亦可克服位元線過充電問題。The first bit line BL1 in FIG. 7 can be discharged not only via the memory cell current I_Cell but also via the third NMOS transistor MN3. If the bit line voltage is overcharged for some reason, the discharge rate can be improved by providing an additional discharge path (compared to memory cell discharge only). Therefore, the circuit structure of the present disclosure can also overcome the problem of bit line overcharge.
第7圖所示的第一感測放大器110還可以選擇性地包含時序控制電路，例如第一感測放大器110還可包括第四PMOS電晶體MP4以及第五NMOS電晶體MN5。第四PMOS電晶體MP4的源極耦接供應電壓VDD、閘極耦接致能信號EN、汲極耦接第二PMOS電晶體MP2的源極。第五NMOS電晶體MP5的閘極耦接致能信號EN、汲極耦接第四NMOS電晶體MN4的閘極。藉由控制致能信號EN，控制第一感測放大器110的操作時序。在一實施例中，第一感測放大器110可以回應於致能信號EN，而致能或禁能電流感測操作。當致能信號EN為低邏輯位準時(例如0V)，則第一感測放大器110執行如前所述的電流感測操作；而當致能信號EN為高邏輯位準時(例如VDD)，則第一感測放大器110相當於停止作用，不進行電流感測操作。The first sense amplifier 110 shown in FIG. 7 can also optionally include a timing control circuit. For example, the first sense amplifier 110 can further include a fourth PMOS transistor MP4 and a fifth NMOS transistor MN5. The source of the fourth PMOS transistor MP4 is coupled to the supply voltage VDD, the gate coupling enable signal EN, and the drain to the source of the second PMOS transistor MP2. The gate of the fifth NMOS transistor MP5 is coupled to the enable signal EN and the drain is coupled to the gate of the fourth NMOS transistor MN4. The operation timing of the first sense amplifier 110 is controlled by controlling the enable signal EN. In an embodiment, the first sense amplifier 110 can enable or disable the current sensing operation in response to the enable signal EN. When the enable signal EN is at a low logic level (eg, 0V), the first sense amplifier 110 performs the current sensing operation as described above; and when the enable signal EN is at a high logic level (eg, VDD), then The first sense amplifier 110 corresponds to a stop action and does not perform a current sensing operation.
如第6圖及第7圖所繪示的電晶體層級電路實現僅為示例性說明，並非用以限定本發明，對於第6圖及第7圖所示的實施例，可以有多種可能的電路修改方式。舉例而言，圖中所示的單顆MOS電晶體可以取代為疊接(cascode)的MOS結構以增進電路效能、電流鏡的實作可以改變為使用本領域熟知的不同電流鏡架構、亦可以採用不同的電晶體尺寸選擇方針。The transistor level circuit implementations as shown in FIGS. 6 and 7 are merely illustrative and are not intended to limit the present invention. For the embodiments shown in FIGS. 6 and 7, there may be multiple possible circuits. Modification method. For example, the single MOS transistor shown in the figure can be replaced by a cascode MOS structure to improve circuit performance. The implementation of the current mirror can be changed to use different current mirror architectures well known in the art. Different transistor size selection guidelines are used.
根據本揭露所提出的感測電路以及感測方法，能夠提供穩定的位元線電壓至每個位元線，以達成可靠的記憶體讀取操作。而由於用以提供偏壓電壓的偏壓產生電路是由多個感測放大器所共用，在各個感測放大器中無需使用運算放大器，不僅可以節省電路硬體面積，亦能降低功率消耗。此外，藉由適當設定參考電流的大小以及縮放比例，記憶胞的電流資訊能夠容易取得，可藉由簡單的感測放大器電路成功偵測記憶胞狀態。而本揭露的感測電路更能夠克服位元線過充電的問題。According to the sensing circuit and the sensing method proposed by the present disclosure, it is possible to provide a stable bit line voltage to each bit line to achieve a reliable memory reading operation. Since the bias generating circuit for supplying the bias voltage is shared by a plurality of sensing amplifiers, it is not necessary to use an operational amplifier in each sensing amplifier, which not only saves the circuit hardware area but also reduces power consumption. In addition, by appropriately setting the magnitude of the reference current and the scaling ratio, the current information of the memory cell can be easily obtained, and the state of the memory cell can be successfully detected by a simple sense amplifier circuit. The sensing circuit of the present disclosure is more capable of overcoming the problem of bit line overcharging.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
1‧‧‧感測電路
100‧‧‧偏壓產生電路
102‧‧‧驅動電路
104‧‧‧運算放大器
110‧‧‧第一感測放大器
112‧‧‧第一複製電路
114‧‧‧第一電流感測電路
120‧‧‧第二感測放大器
122‧‧‧第二複製電路
124‧‧‧第二電流感測電路
130、190‧‧‧感測放大器
140‧‧‧感測電流鏡
142‧‧‧縮放參考電流鏡
144‧‧‧電流比較器
210‧‧‧第一記憶胞
220‧‧‧第二記憶胞
BL1‧‧‧第一位元線
BL2‧‧‧第二位元線
EN‧‧‧致能信號
I_Cell‧‧‧記憶胞電流
IREF‧‧‧參考電流
MN1、MN2、MN3、MN4、MN5‧‧‧NMOS電晶體
MP1、MP2、MP3、MP4‧‧‧PMOS電晶體
NBIAS‧‧‧第二偏壓電壓
PBIAS‧‧‧第一偏壓電壓
Res‧‧‧電阻
S400‧‧‧以參考電流偏壓驅動電路
S402‧‧‧以運算放大器的非反向輸入端接收參考電壓
S404‧‧‧於運算放大器的反向輸入端藉由負回授路徑產生輸出電壓，負回授路徑包括驅動電路
S406‧‧‧複製輸出電壓至第一位元線，第一位元線耦接第一記憶胞
S408‧‧‧感測第一電流差以決定第一記憶胞的第一記憶狀態，其中第一電流差係參考電流經縮放後與第一記憶胞的第一記憶胞電流之間的差值
S416‧‧‧複製輸出電壓至第二位元線，第二位元線耦接第二記憶胞
S418‧‧‧感測第二電流差以決定第二記憶胞的第二記憶狀態，其中第二電流差係參考電流經縮放後與第二記憶胞的第二記憶胞電流之間的差值
S430‧‧‧以感測電晶體偵測第一記憶胞電流
S432‧‧‧致能感測電流鏡以鏡射流經感測電晶體的電流
S434‧‧‧致能縮放參考電流鏡以鏡射縮放後的參考電流
S436‧‧‧比較感測電流鏡的電流以及縮放參考電流鏡的電流，以決定第一記憶胞的第一記憶狀態
SAout‧‧‧輸出節點
V_Clamp‧‧‧箝制電壓
VBL‧‧‧位元線電壓
VDD‧‧‧供應電壓
VOUT‧‧‧輸出電壓
VREF‧‧‧參考電壓1‧‧‧Sensor circuit
100‧‧‧ bias generation circuit
102‧‧‧ drive circuit
104‧‧‧Operational Amplifier
110‧‧‧First sense amplifier
112‧‧‧First copy circuit
114‧‧‧First current sensing circuit
120‧‧‧Second sense amplifier
122‧‧‧Second copy circuit
124‧‧‧Second current sensing circuit
130, 190‧‧ ‧ sense amplifier
140‧‧‧Sensing current mirror
142‧‧‧Zoom reference current mirror
144‧‧‧current comparator
210‧‧‧First memory cell
220‧‧‧Second memory cell
BL1‧‧‧ first bit line
BL2‧‧‧ second bit line
EN‧‧‧Enable signal
I_Cell‧‧‧ memory cell current
I REF ‧‧‧Reference current
MN1, MN2, MN3, MN4, MN5‧‧‧ NMOS transistor
MP1, MP2, MP3, MP4‧‧‧ PMOS transistors
NBIAS‧‧‧second bias voltage
PBIAS‧‧‧First bias voltage
Res‧‧‧Resistance
S400‧‧‧ reference current bias drive circuit
S402‧‧‧ Receives the reference voltage at the non-inverting input of the operational amplifier
S404‧‧‧ The output voltage is generated by the negative feedback path at the inverting input of the operational amplifier, and the negative feedback path includes the driving circuit
S406‧‧‧Copy the output voltage to the first bit line, the first bit line is coupled to the first memory cell
S408‧‧ ‧ sensing a first current difference to determine a first memory state of the first memory cell, wherein the first current difference is a difference between the reference current and the first memory cell current of the first memory cell
S416‧‧‧Copy the output voltage to the second bit line, and the second bit line is coupled to the second memory cell
S418‧‧ senses a second current difference to determine a second memory state of the second memory cell, wherein the second current difference is a difference between the reference current and the second memory cell current of the second memory cell
S430‧‧‧Detecting the first memory cell current with the sensing transistor
S432‧‧‧Enable current sensing mirror current flowing through the sensing transistor
S434‧‧‧Enable zoom reference current mirror to mirror the scaled reference current
S436‧‧‧ compares the current of the current mirror and the current of the scaled current mirror to determine the first memory state of the first memory cell
SAout‧‧‧ output node
V_Clamp‧‧‧ clamping voltage
VBL‧‧‧ bit line voltage
VDD‧‧‧ supply voltage
V OUT ‧‧‧ output voltage
V REF ‧‧‧reference voltage
第1圖繪示一種用於非揮發性記憶體的範例箝制感測電路。 第2圖繪示依據本發明一實施例感測電路架構的方塊圖。 第3圖繪示依據本發明一實施例感測電路的示意圖。 第4圖繪示依據本發明一實施例感測電路的示意圖。 第5圖繪示依據本發明一實施例第一電流感測電路的示意圖。 第6圖繪示依據本發明一實施例偏壓產生電路的示意圖。 第7圖繪示依據本發明一實施例第一感測放大器的示意圖。 第8圖繪示依據本發明一實施例用於非揮發性記憶體的感測方法流程圖。 第9圖繪示依據本發明一實施例用於非揮發性記憶體的感測方法流程圖。 第10圖繪示依據本發明一實施例偵測第一電流差異步驟的流程圖，其中第一電流差異為第一記憶胞電流及縮放後參考電流的差異。Figure 1 illustrates an example clamp sensing circuit for non-volatile memory. 2 is a block diagram of a sensing circuit architecture in accordance with an embodiment of the present invention. FIG. 3 is a schematic diagram of a sensing circuit according to an embodiment of the invention. 4 is a schematic diagram of a sensing circuit in accordance with an embodiment of the present invention. FIG. 5 is a schematic diagram of a first current sensing circuit according to an embodiment of the invention. 6 is a schematic diagram of a bias generating circuit in accordance with an embodiment of the present invention. FIG. 7 is a schematic diagram of a first sense amplifier according to an embodiment of the invention. FIG. 8 is a flow chart showing a sensing method for non-volatile memory according to an embodiment of the invention. FIG. 9 is a flow chart showing a sensing method for non-volatile memory according to an embodiment of the invention. FIG. 10 is a flow chart showing a step of detecting a first current difference according to an embodiment of the invention, wherein the first current difference is a difference between the first memory cell current and the scaled reference current.
100‧‧‧偏壓產生電路 100‧‧‧ bias generation circuit
102‧‧‧驅動電路 102‧‧‧ drive circuit
104‧‧‧運算放大器 104‧‧‧Operational Amplifier
110‧‧‧第一感測放大器 110‧‧‧First sense amplifier
112‧‧‧第一複製電路 112‧‧‧First copy circuit
114‧‧‧第一電流感測電路 114‧‧‧First current sensing circuit
210‧‧‧第一記憶胞 210‧‧‧First memory cell
BL1‧‧‧第一位元線 BL1‧‧‧ first bit line
IREF‧‧‧參考電流 I REF ‧‧‧Reference current
VOUT‧‧‧輸出電壓 V OUT ‧‧‧ output voltage
VREF‧‧‧參考電壓 V REF ‧‧‧reference voltage
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