TWI614864B - Assembling method - Google Patents
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Abstract
一種組裝方法，包含以下步驟。形成至少一第一導電結構於一基板上。形成至少一第二導電結構於一半導體元件上。壓合基板與半導體元件，其中在壓合的前段過程中，第一導電結構與第二導電結構係局部地接觸而形成一應力集中區。 An assembly method comprising the following steps. Forming at least one first conductive structure on a substrate. Forming at least one second conductive structure on a semiconductor component. The substrate and the semiconductor component are laminated, wherein the first conductive structure and the second conductive structure are in partial contact to form a stress concentration region during the pre-pressing process.
Description
本發明係關於一種組裝方法，特別是有關於導電結構接合的組裝方法。 The present invention relates to an assembly method, and more particularly to an assembly method for conductive structure bonding.
近年來，隨著電子產業的蓬勃發展，電子產品之外型趨向輕薄短小，在功能上則逐漸邁入高性能、高功能、高速度化的研發方向。一般而言，高效電子元件具有高密度的連接腳位，往往係利用焊錫球(solder balls)或是金屬凸塊(metal bumps)來達到彼此之間電性和機械性連接的目的。舉例來說，半導體元件通常是利用焊錫球與金屬凸塊與一封裝基板相連接，此種連接技術又稱為覆晶接合(flip-chip)。 In recent years, with the rapid development of the electronics industry, the appearance of electronic products has become light and thin, and the function has gradually entered the research and development direction of high performance, high function and high speed. In general, high-efficiency electronic components have high-density connection pins, often using solder balls or metal bumps to achieve electrical and mechanical connections between each other. For example, a semiconductor component is typically connected to a package substrate by solder balls and metal bumps. This bonding technique is also known as flip-chip bonding.
在現行覆晶技術中，焊錫球須經由迴焊製程或其他高溫製程而將焊錫球轉變為融熔狀態，以利於後續連接金屬凸塊。 In the current flip chip technology, the solder ball needs to be converted into a molten state by a reflow process or other high temperature process to facilitate subsequent connection of the metal bumps.
本發明係關於一種組裝方法，其可利於降低基板與半導體元件的組裝過程之所需溫度。 The present invention relates to an assembly method that can facilitate lowering the temperature required for the assembly process of the substrate and the semiconductor component.
依據本發明之部分實施方式，一種組裝方法包含 以下步驟。形成至少一第一導電結構於一基板上，且形成至少一第二導電結構於一半導體元件上。接著，壓合基板與半導體元件，其中在壓合的前段過程中，第一導電結構與第二導電結構係局部地接觸而形成一應力集中區。 According to some embodiments of the present invention, an assembly method includes The following steps. Forming at least one first conductive structure on a substrate, and forming at least one second conductive structure on a semiconductor component. Next, the substrate and the semiconductor component are laminated, wherein during the pre-pressing process, the first conductive structure and the second conductive structure are in partial contact to form a stress concentration region.
在上述實施方式中，於壓合基板與半導體元件的前段過程中，由於第一導電結構與第二導電結構係局部接觸而形成應力集中區，故可利於第一導電結構與第二導電結構的接合，因而可降低第一導電結構與第二導電結構的接合過程之所需溫度。此外，由於第一導電結構與第二導電結構的接合所需溫度被降低，故可進一步地降低基板與半導體元件受熱所產生的翹曲量。 In the above embodiment, during the process of laminating the substrate and the semiconductor device, since the first conductive structure and the second conductive structure are in partial contact to form a stress concentration region, the first conductive structure and the second conductive structure may be beneficial. Bonding, thereby reducing the temperature required for the bonding process of the first conductive structure and the second conductive structure. In addition, since the temperature required for the bonding of the first conductive structure and the second conductive structure is lowered, the amount of warpage caused by the heat of the substrate and the semiconductor element can be further reduced.
依據本發明之部分實施方式，一種組裝方法包含以下步驟。形成至少一第一銅結構於基板上，第一銅結構具有一第一接合面。形成至少一第二銅結構於半導體元件上，第二銅結構具有一第二接合面，且第一接合面與第二接合面的形狀不匹配。接著，壓合基板與半導體元件，使得第一接合面與第二接合面接合。 According to some embodiments of the present invention, an assembly method includes the following steps. Forming at least one first copper structure on the substrate, the first copper structure having a first bonding surface. Forming at least one second copper structure on the semiconductor element, the second copper structure has a second bonding surface, and the first bonding surface does not match the shape of the second bonding surface. Next, the substrate and the semiconductor element are laminated such that the first bonding surface and the second bonding surface are bonded.
在上述實施方式中，由於第一銅結構的第一接合面與第二銅結構的第二接合面的形狀不匹配，因此第一接合面與第二接合面在壓合的前段過程中係局部接觸的，故可利於第一銅結構與第二銅結構的接合，因而可降低第一銅結構與第二銅結構的接合過程之所需溫度。此外，由於第一銅結構與第二銅結構的接合所需溫度被降低，故可進一步地降低基板與半導體元件受熱所產生的翹曲量。 In the above embodiment, since the shape of the first joint surface of the first copper structure and the second joint surface of the second copper structure do not match, the first joint surface and the second joint surface are partially in the process of the front portion of the press fit. Contacted, thereby facilitating the bonding of the first copper structure to the second copper structure, thereby reducing the temperature required for the bonding process of the first copper structure and the second copper structure. Further, since the temperature required for the bonding of the first copper structure and the second copper structure is lowered, the amount of warpage caused by the heat of the substrate and the semiconductor element can be further reduced.
以上所述僅係用以闡述本發明所欲解決的問題、解決問題的技術手段、及其產生的功效等等，本發明之具體細節將在下文的實施方式及相關圖式中詳細介紹。 The above description is only for explaining the problems to be solved by the present invention, the technical means for solving the problems, the effects thereof, and the like, and the specific details of the present invention will be described in detail in the following embodiments and related drawings.
100‧‧‧基板 100‧‧‧Substrate
110‧‧‧剝離層 110‧‧‧ peeling layer
120‧‧‧金屬層 120‧‧‧metal layer
130‧‧‧重分布層 130‧‧‧ redistribution layer
132‧‧‧導電層 132‧‧‧ Conductive layer
140‧‧‧介電層 140‧‧‧Dielectric layer
142‧‧‧開孔 142‧‧‧ openings
144‧‧‧上表面 144‧‧‧ upper surface
146‧‧‧層間介電層 146‧‧‧Interlayer dielectric layer
200a、200b、200c‧‧‧第一導電結構 200a, 200b, 200c‧‧‧ first conductive structure
210a、210b、210c‧‧‧埋入部 210a, 210b, 210c‧‧‧ buried section
220a、220b、220c‧‧‧接合部 220a, 220b, 220c‧‧‧ joints
222a、222b、222c‧‧‧第一接合面 222a, 222b, 222c‧‧‧ first joint
2222b、2222c‧‧‧突起部 2222b, 2222c‧‧‧ protrusion
2224b、2224c‧‧‧基底部 2224b, 2224c‧‧‧ base
300‧‧‧半導體元件 300‧‧‧Semiconductor components
310‧‧‧承載板 310‧‧‧ carrying board
312‧‧‧表面 312‧‧‧ surface
314‧‧‧表面 314‧‧‧ surface
320‧‧‧晶片 320‧‧‧ wafer
400a、400b、400c‧‧‧第二導電結構 400a, 400b, 400c‧‧‧ second conductive structure
422a、422b、422c‧‧‧第二接合面 422a, 422b, 422c‧‧‧ second joint
4222a、4222c‧‧‧突起部 4222a, 4222c‧‧‧ protrusion
4224a、4224c‧‧‧基底部 4224a, 4224c‧‧‧ base
500‧‧‧抗氧化層 500‧‧‧Antioxidant layer
A、B、C‧‧‧局部區域 A, B, C‧‧‧ local areas
A’、B’、C’‧‧‧區段 A’, B’, C’‧‧‧ Section
A”、B”、C”‧‧‧區段 A", B", C" ‧ ‧ section
st1、st2、st3‧‧‧應力集中區 St1, st2, st3‧‧‧ stress concentration area
c1、c2、c3‧‧‧接觸區 C1, c2, c3‧‧‧ contact area
IL‧‧‧內增層結構 IL‧‧‧Incremental structure
閱讀以下詳細敘述並搭配對應之圖式，可了解本發明之多個樣態。需留意的是，圖式中的多個特徵並未依照該業界領域之標準作法繪製實際比例。事實上，所述之特徵的尺寸可以任意的增加或減少以利於討論的清晰性。 A number of aspects of the present invention can be understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the various features in the drawings do not draw actual proportions in accordance with standard practice in the industry. In fact, the dimensions of the features described can be arbitrarily increased or decreased to facilitate clarity of discussion.
第1至8圖繪示本發明之部分實施方式於不同步驟組裝基板與半導體元件的剖面示意圖。 1 to 8 are schematic cross-sectional views showing a part of an embodiment of the present invention in which a substrate and a semiconductor element are assembled in different steps.
第2A圖為第2圖之另一實施方式。 Fig. 2A is another embodiment of Fig. 2.
第7A圖為第7圖之局部區域A的放大示意圖。 Fig. 7A is an enlarged schematic view of a partial area A of Fig. 7.
第7B圖為第7圖之局部區域B的放大示意圖。 Fig. 7B is an enlarged schematic view of a partial region B of Fig. 7.
第7C圖為第7圖之局部區域C的放大示意圖。 Fig. 7C is an enlarged schematic view of a partial region C of Fig. 7.
第9圖為依據本發明之另一實施方式之基板與半導體元件於壓合前的剖面示意圖。 Fig. 9 is a schematic cross-sectional view showing a substrate and a semiconductor element before being pressed according to another embodiment of the present invention.
以下將以圖式及詳細說明清楚說明本發明之精神，任何所屬技術領域中具有通常知識者在瞭解本發明之實施例後，當可由本發明所教示之技術，加以改變及修飾，其並不脫離本發明之精神與範圍。 The spirit and scope of the present invention will be apparent from the following description of the embodiments of the present invention. It is within the spirit and scope of the invention.
此外，方位相對詞彙，如「在...之下」、「下面」、 「下」、「上方」或「上」或類似詞彙，在本文中為用來便於描述繪示於圖式中的一個元件或特徵至另外的元件或特徵之關係。方位相對詞彙除了用來描述裝置在圖式中的方位外，其包含裝置於使用或操作下之不同的方位。當裝置被另外設置(旋轉90度或者其他面向的方位)，本文所用的方位相對詞彙同樣可相應地進行解釋。 In addition, azimuth-relative vocabulary, such as "under", "below", "Bottom", "above" or "upper" or similar terms are used herein to facilitate the description of one element or feature in the drawings to the other elements or features. Azimuthally relative terms are used to describe different orientations of the device in use or operation, except to describe the orientation of the device in the drawings. When the device is otherwise set (rotated 90 degrees or other oriented orientation), the orientation relative vocabulary used herein can also be interpreted accordingly.
第1至8圖繪示本發明之部分實施方式於不同步驟組裝基板與半導體元件的剖面示意圖。參照第1圖。提供一基板100。於部分實施方式中，基板100的材料可為有機聚合材料，例如：雙順丁烯二酸醯亞胺/三氮阱(Bismaleimide triazine；BT)、或基板100的材料可為金屬，例如：鋁、銅或不銹鋼，但本發明不以此為限。或者，基板100可為可撓性基板，例如：聚醯亞胺(polyimide；PI)、聚乙烯對苯二甲酸酯(polyethylene terephthalate；PET)、聚醚(polyethersulfone；PES)或聚間苯二甲酸乙二酯(polyethylene naphthalate；PEN)等，但本發明不以此為限。 1 to 8 are schematic cross-sectional views showing a part of an embodiment of the present invention in which a substrate and a semiconductor element are assembled in different steps. Refer to Figure 1. A substrate 100 is provided. In some embodiments, the material of the substrate 100 may be an organic polymeric material, such as: Bismetimide triazine (BT), or the material of the substrate 100 may be a metal, such as aluminum. , copper or stainless steel, but the invention is not limited thereto. Alternatively, the substrate 100 may be a flexible substrate such as polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES) or poly(diphenylene). Polyethylene naphthalate (PEN), etc., but the invention is not limited thereto.
隨後，形成一剝離層(release layer)110於基板100上，且形成一金屬層120於剝離層110上。於部分實施方式中，剝離層110可為感壓膠(pressure sensitive adhesive；PSA)，例如：矽氧烷(siloxane)、矽樹脂(silicone)或壓克力，但本發明不以此為限。於部分實施方式中，剝離層110可為有機材料，例如：離型膜(release film)；剝離層110可為金屬材料，例如鎳；或者剝離層110可為無機材料，例如氧化鎳，但本發明不以此為限。於部分實施方式中，金屬層120係設置於 剝離層110上，且金屬層120可為銅或其他適合的材料，但本發明不以此為限。 Subsequently, a release layer 110 is formed on the substrate 100, and a metal layer 120 is formed on the lift-off layer 110. In some embodiments, the release layer 110 may be a pressure sensitive adhesive (PSA), such as siloxane, silicone, or acryl, but the invention is not limited thereto. In some embodiments, the release layer 110 may be an organic material, such as a release film; the release layer 110 may be a metal material such as nickel; or the release layer 110 may be an inorganic material such as nickel oxide, but The invention is not limited to this. In some embodiments, the metal layer 120 is disposed on The metal layer 120 may be copper or other suitable material, but the invention is not limited thereto.
於部分實施方式中，剝離層110與基板100的結合力大於剝離層110與金屬層120的結合力，或者剝離層110與金屬層120之間僅存在暫時性的結合力，以利於在後段製程中分離基板100與金屬層120，從而降低整體封裝元件的厚度，但本發明不以此為限。於其他實施方式中，剝離層110與基板100的結合力亦可約等於剝離層110與金屬層120的結合力，亦即，基板100與金屬層120可藉由剝離層110黏著而不分離。 In some embodiments, the bonding force of the peeling layer 110 and the substrate 100 is greater than the bonding force of the peeling layer 110 and the metal layer 120, or there is only a temporary bonding force between the peeling layer 110 and the metal layer 120, so as to facilitate the process in the back stage. The substrate 100 and the metal layer 120 are separated to reduce the thickness of the overall package component, but the invention is not limited thereto. In other embodiments, the bonding force of the peeling layer 110 and the substrate 100 can also be approximately equal to the bonding force of the peeling layer 110 and the metal layer 120, that is, the substrate 100 and the metal layer 120 can be adhered by the peeling layer 110 without being separated.
參照第2圖，形成一重分布層(Redistribution Layer；RDL)130於基板100之金屬層120上，且重分布層130可藉由圖案化製程，例如：微影製程與蝕刻製程，而形成多條金屬走線。接著，形成介電層140以覆蓋重分布層130，且介電層140具有開孔142以暴露部分的重分布層130。於其他實施方式中，可於介電層140與重分布層130之間形成交替層疊的多層導電層132與層間介電層146(亦即，相鄰兩導電層132係被一層間介電層146所隔開)，而共同形成內增層結構IL(如第2A圖所示)，但本發明不以此為限。 Referring to FIG. 2, a redistribution layer (RDL) 130 is formed on the metal layer 120 of the substrate 100, and the redistribution layer 130 can be formed by a patterning process, such as a lithography process and an etching process. Metal traces. Next, a dielectric layer 140 is formed to cover the redistribution layer 130, and the dielectric layer 140 has openings 142 to expose portions of the redistribution layer 130. In other embodiments, the multilayer conductive layer 132 and the interlayer dielectric layer 146 may be alternately stacked between the dielectric layer 140 and the redistribution layer 130 (that is, the adjacent conductive layers 132 are separated by an interlayer dielectric layer). 146 are separated), and together form an inner build-up structure IL (as shown in FIG. 2A), but the invention is not limited thereto.
參照第3圖。形成第一導電結構200a、200b與200c於基板100上。基板100可由左至右依序區分為區段A”、區段B”與區段C”，第一導電結構200a、200b與200c係分別形成於基板100之不同區段A”、區段B”與區段C”上。更詳細地說，第一導電結構200a、200b與200c係分別形成於介電層140的不同位置上，且第一導電結構200a、200b與200c可至少部 分地填充於介電層140之開孔142中，使得第一導電結構200a、200b與200c電性連接重分布層130。舉例來說，第一導電結構200a具有較靠近基板100的埋入部210a與較遠離基板100的接合部220a；相似地，第一導電結構200b具有較靠近基板100的埋入部210b與較遠離基板100的接合部220b，而第一導電結構200c具有較靠近基板100的埋入部210c與較遠離基板100的接合部220c，埋入部210a、210b與210c可位於介電層140之開孔142中並接觸重分布層130，以與重分布層130電性連接。接合部220a、220b與220c可突出於介電層140之上表面144，而裸露於基板100上，以利後續與半導體元件上之導電結構接合。於部分實施方式中，可藉由加成法、半加成法(SAP)、減成法、電鍍、無電鍍沉積(electroless plating deposit)或化學沉積等方式形成第一導電結構200a、200b與200c，但本發明不以此為限。圖中之區段A”、區段B”與區段C”僅係用以說明，第一導電結構200a、200b與200c之設置位置並不以此為限制。換句話說，圖中的區段A”、區段B”與區段C”雖繪示為基板100之連續鄰接的區段，但亦可為不連續而相分離的區段。 Refer to Figure 3. The first conductive structures 200a, 200b, and 200c are formed on the substrate 100. The substrate 100 can be sequentially divided into a segment A", a segment B" and a segment C" from left to right. The first conductive structures 200a, 200b and 200c are respectively formed on different segments A" and B of the substrate 100. "With section C". In more detail, the first conductive structures 200a, 200b, and 200c are respectively formed at different positions of the dielectric layer 140, and the first conductive structures 200a, 200b, and 200c may be at least partially The grounding holes 142 of the dielectric layer 140 are filled in the ground, so that the first conductive structures 200a, 200b and 200c are electrically connected to the redistribution layer 130. For example, the first conductive structure 200a has a buried portion 210a closer to the substrate 100 and a joint portion 220a farther from the substrate 100. Similarly, the first conductive structure 200b has a buried portion 210b closer to the substrate 100 and is farther away from the substrate 100. The first conductive structure 200c has a buried portion 210c closer to the substrate 100 and a joint portion 220c farther from the substrate 100. The buried portions 210a, 210b and 210c may be located in the opening 142 of the dielectric layer 140 and contacted. The redistribution layer 130 is electrically connected to the redistribution layer 130. The joints 220a, 220b and 220c may protrude from the upper surface 144 of the dielectric layer 140 and be exposed on the substrate 100 for subsequent bonding with the conductive structures on the semiconductor component. In some embodiments, the first conductive structures 200a, 200b, and 200c may be formed by an additive method, a semi-additive method (SAP), a subtractive method, electroplating, electroless plating deposit, or chemical deposition. However, the invention is not limited thereto. The section A", the section B" and the section C" in the figure are merely for illustration, and the positions at which the first conductive structures 200a, 200b and 200c are disposed are not limited thereto. In other words, the area in the figure The segment A", the segment B" and the segment C" are shown as consecutively adjacent segments of the substrate 100, but may be discontinuous and phase separated segments.
於部分實施方式中，第一導電結構200a、200b與200c的至少一者之材料可為銅、鎳、金、銀或其他適當的導電材料，但本發明不以此為限。舉例而言，於部分實施方式中，第一導電結構200a、200b與200c的至少一者的材料可為銅，亦即，在這樣的實施方式中，第一導電結構200a、200b與200c的至少一者可稱為第一銅結構。也就是說，第一銅結構可形成 於基板100上。 In some embodiments, the material of at least one of the first conductive structures 200a, 200b, and 200c may be copper, nickel, gold, silver, or other suitable conductive material, but the invention is not limited thereto. For example, in some embodiments, the material of at least one of the first conductive structures 200a, 200b, and 200c may be copper, that is, in such an embodiment, at least the first conductive structures 200a, 200b, and 200c One can be referred to as a first copper structure. That is, the first copper structure can be formed On the substrate 100.
於部分實施方式中，可控制第一導電結構的形狀以利後續接合半導體元件之導電結構。舉例來說，如第3圖之區段B”所示，在形成第一導電結構200b的過程中，可形成第一導電結構200b之第一接合面222b，此第一接合面222b為起伏狀的，亦即，此第一接合面222b可為第一導電結構200b之接合部220b的起伏狀頂面，此第一接合面222b的形狀可與半導體元件之導電結構的接合面形狀不匹配，以利兩者的接合，此接合之具體敘述將詳述於後續步驟中。類似於第一導電結構200b，位於區段C”的第一導電結構200c亦可具有第一接合面222c，此第一接合面222c亦可為起伏狀的，且其形狀可與半導體元件之對應導電結構的接合面形狀不匹配，以利兩者的接合。 In some embodiments, the shape of the first conductive structure can be controlled to facilitate subsequent bonding of the conductive structures of the semiconductor elements. For example, as shown in the section B" of FIG. 3, in the process of forming the first conductive structure 200b, the first bonding surface 222b of the first conductive structure 200b may be formed, and the first bonding surface 222b is undulating. That is, the first bonding surface 222b may be an undulating top surface of the bonding portion 220b of the first conductive structure 200b, and the shape of the first bonding surface 222b may not match the shape of the bonding surface of the conductive structure of the semiconductor component. For the purpose of the bonding of the two, the specific description of the bonding will be described in the subsequent steps. Similar to the first conductive structure 200b, the first conductive structure 200c located in the segment C" may also have a first bonding surface 222c, this A bonding surface 222c may also be undulating, and its shape may not match the shape of the bonding surface of the corresponding conductive structure of the semiconductor element to facilitate the bonding of the two.
於部分實施方式中，起伏狀的第一接合面222b與222c之至少一者可為錐狀、突起狀、凹陷狀、或其他適當的起伏形狀，但本發明不以此為限。於部分實施方式中，起伏狀的第一接合面222b與222c之至少一者可藉由調整電鍍製程之摻雜物的比例而形成、或藉由微影製程與蝕刻製程而形成，但本發明不以此為限。也就是說，於部分實施方式中，第一接合面222b與222c之至少一者的起伏形狀可由電鍍製程之摻雜物的比例所控制。 In some embodiments, at least one of the undulating first engaging faces 222b and 222c may be tapered, protruded, recessed, or other suitable undulating shape, but the invention is not limited thereto. In some embodiments, at least one of the undulating first bonding faces 222b and 222c may be formed by adjusting a ratio of dopants of the plating process, or by a lithography process and an etching process, but the present invention Not limited to this. That is, in some embodiments, the undulating shape of at least one of the first bonding faces 222b and 222c can be controlled by the ratio of dopants in the plating process.
於部分實施方式，只要第一導電結構的第一接合面能夠與半導體元件上的導電結構之接合面的形狀不匹配，則第一接合面亦可形成為非起伏狀的。舉例來說，如第3圖之區 段A”所示，第一導電結構200a之第一接合面222a可為實質上平坦的。換句話說，此第一接合面222a可為第一導電結構200a之接合部220a的實質上平坦頂面，此第一接合面222a的實質上平坦形狀可與半導體元件之對應導電結構的接合面形狀不匹配，以利兩者接合。 In some embodiments, the first bonding surface may also be formed as a non-undulating shape as long as the first bonding surface of the first conductive structure can be mismatched with the shape of the bonding surface of the conductive structure on the semiconductor element. For example, as in Figure 3 The first bonding surface 222a of the first conductive structure 200a may be substantially flat, as shown in the segment A". In other words, the first bonding surface 222a may be a substantially flat top of the bonding portion 220a of the first conductive structure 200a. The substantially flat shape of the first bonding surface 222a may not match the shape of the bonding surface of the corresponding conductive structure of the semiconductor element to facilitate the bonding.
參照第4圖。提供一半導體元件300，半導體元件300可由左至右依序區分為區段C’、區段B’與區段A’。於部分實施方式中，半導體元件300包含承載板310與至少一晶片320，晶片320係設置於承載板310之表面312。於部分實施方式中，晶片320可為主動式晶片或被動式晶片，但本發明不以此為限。於部分實施方式中，承載板310可包含交替層疊的多層導電層與層間介電層(未示於圖中)，以利在基板100與半導體元件300組裝後，電性連接晶片320與基板100。 Refer to Figure 4. A semiconductor component 300 is provided which can be sequentially distinguished from left to right into a segment C', a segment B' and a segment A'. In some embodiments, the semiconductor component 300 includes a carrier 310 and at least one wafer 320 disposed on a surface 312 of the carrier 310. In some embodiments, the wafer 320 can be an active wafer or a passive wafer, but the invention is not limited thereto. In some embodiments, the carrier 310 may include a plurality of electrically conductive layers and an interlayer dielectric layer (not shown) that are alternately stacked to electrically connect the substrate 320 and the substrate 100 after the substrate 100 is assembled with the semiconductor device 300. .
參照第5圖。分別形成第二導電結構400a、400b與400c於半導體元件300之區段A’、區段B’與區段C’上。更詳細地說，第二導電結構400a、400b與400c係電性連接半導體元件300之承載板310，並至少部分地裸露於半導體元件300之承載板310的表面314上，且此表面314與晶片320所在的表面312係相對的。於部分實施方式中，可藉由加成法、半加成法(SAP)、減成法、電鍍、無電鍍沉積(electroless plating deposit)或化學沉積等方式形成第二導電結構400a、400b與400c，但本發明不以此為限。圖中之區段A’、區段B’與區段C’僅係用以說明，第二導電結構400a、400b與400c之設置位置並不以此為限制。換句話說，圖中的A’、區段B’與區段C’雖 繪示為連續鄰接的區段，但亦可為不連續而相分離的區段。 Refer to Figure 5. The second conductive structures 400a, 400b, and 400c are formed on the segment A', the segment B', and the segment C' of the semiconductor element 300, respectively. In more detail, the second conductive structures 400a, 400b, and 400c are electrically connected to the carrier 310 of the semiconductor device 300, and are at least partially exposed on the surface 314 of the carrier 310 of the semiconductor device 300, and the surface 314 and the wafer The surface 312 where 320 is located is opposite. In some embodiments, the second conductive structures 400a, 400b, and 400c may be formed by an additive method, a semi-additive method (SAP), a subtractive method, electroplating, electroless plating deposit, or chemical deposition. However, the invention is not limited thereto. The section A', the section B' and the section C' in the figure are merely for illustration, and the positions at which the second conductive structures 400a, 400b and 400c are disposed are not limited thereto. In other words, although A', section B' and section C' in the figure are They are shown as consecutive adjacent segments, but may also be discontinuous and phase separated segments.
於部分實施方式中，第二導電結構400a、400b與400c的至少一者之材料可為銅、鎳、金、銀或其他適當的導電材料，但本發明不以此為限。舉例而言，於部分實施方式中，第二導電結構400a、400b與400c的至少一者的材料可為銅，亦即，在這樣的實施方式中，第二導電結構400a、400b與400c的至少一者可稱為第二銅結構。也就是說，第二銅結構可形成於半導體元件300上。 In some embodiments, the material of at least one of the second conductive structures 400a, 400b, and 400c may be copper, nickel, gold, silver, or other suitable conductive material, but the invention is not limited thereto. For example, in some embodiments, the material of at least one of the second conductive structures 400a, 400b, and 400c may be copper, that is, in such an embodiment, at least the second conductive structures 400a, 400b, and 400c One can be referred to as a second copper structure. That is, the second copper structure may be formed on the semiconductor element 300.
於部分實施方式中，可控制第二導電結構的形狀以利後續接合基板之第一導電結構。舉例來說，第5圖之區段A’上的第二導電結構400a係用以與前述基板100上的第一導電結構200a接合的，故在形成第二導電結構400a的過程中，可形成第二導電結構400a之第二接合面422a，使得此第二接合面422a與第一導電結構200a之第一接合面222a的形狀不匹配，以利兩者的接合。進一步來說，第二接合面422a可為起伏狀的，亦即，此第二接合面422a可為第二導電結構400a的起伏狀底面，而與實質上平坦的第一接合面222a的形狀不匹配，以利兩者的接合。 In some embodiments, the shape of the second conductive structure can be controlled to facilitate subsequent bonding of the first conductive structure of the substrate. For example, the second conductive structure 400a on the segment A' of FIG. 5 is used to be bonded to the first conductive structure 200a on the substrate 100, so that the second conductive structure 400a can be formed during the process of forming the second conductive structure 400a. The second bonding surface 422a of the second conductive structure 400a is such that the second bonding surface 422a does not match the shape of the first bonding surface 222a of the first conductive structure 200a to facilitate the bonding of the two. Further, the second bonding surface 422a may be undulating, that is, the second bonding surface 422a may be an undulating bottom surface of the second conductive structure 400a, and the shape of the substantially flat first bonding surface 222a is not Match to facilitate the joint of the two.
類似於第二導電結構400a，位於區段C’上的第二導電結構400c係用以與前述基板100上的第一導電結構200c接合的，因此，第二導電結構400c的第二接合面422c可與第一導電結構200c的第一接合面222c的形狀不匹配，以利兩者的接合。舉例來說，第二接合面422c可為起伏狀的，且其形狀可與起伏狀的第一接合面222c不匹配。 Similar to the second conductive structure 400a, the second conductive structure 400c on the segment C' is used to be bonded to the first conductive structure 200c on the substrate 100, and thus, the second bonding surface 422c of the second conductive structure 400c The shape of the first bonding surface 222c of the first conductive structure 200c may not match to facilitate the bonding of the two. For example, the second engagement surface 422c can be undulating and its shape can be mismatched with the undulating first engagement surface 222c.
於部分實施方式中，起伏狀的第二接合面422a與422c之至少一者可為錐狀、突起狀、凹陷狀、或其他適當的起伏形狀，但本發明不以此為限。於部分實施方式中，起伏狀的第二接合面422a與422c之至少一者可藉由調整電鍍製程之摻雜物的比例而形成、或藉由微影製程與蝕刻製程而形成，但本發明不以此為限。也就是說，第二接合面422a與422c之至少一者的起伏形狀可由電鍍製程之摻雜物的比例所控制。 In some embodiments, at least one of the undulating second engaging faces 422a and 422c may be tapered, protruding, recessed, or other suitable undulating shape, but the invention is not limited thereto. In some embodiments, at least one of the undulating second bonding surfaces 422a and 422c may be formed by adjusting a ratio of dopants in the electroplating process, or formed by a lithography process and an etching process, but the present invention Not limited to this. That is, the undulating shape of at least one of the second bonding faces 422a and 422c can be controlled by the ratio of the dopant of the plating process.
於部分實施方式，只要第二導電結構的第二接合面能夠與第一導電結構之第一接合面的形狀不匹配，則第二接合面亦可形成為非起伏狀的。舉例來說，位於區段B’上的第二導電結構400b係用以與前述基板100上的第一導電結構200b接合的，而由於第一導電結構200b的第一接合面222b為起伏狀的，故第二導電結構400b之第二接合面422b可為實質上平坦的，使得兩者的形狀不匹配，以利兩者的接合。換句話說，此第二接合面422b可為第二導電結構400b的實質上平坦底面，故此第二接合面422b的實質上平坦形狀可與起伏狀的第一接合面222b的形狀不匹配，以利兩者接合。 In some embodiments, the second bonding surface may also be formed as a non-undulating shape as long as the second bonding surface of the second conductive structure can be mismatched with the shape of the first bonding surface of the first conductive structure. For example, the second conductive structure 400b on the segment B' is used to be bonded to the first conductive structure 200b on the substrate 100, and since the first bonding surface 222b of the first conductive structure 200b is undulating Therefore, the second bonding surface 422b of the second conductive structure 400b may be substantially flat such that the shapes of the two are not matched to facilitate the bonding of the two. In other words, the second bonding surface 422b can be a substantially flat bottom surface of the second conductive structure 400b, so that the substantially flat shape of the second bonding surface 422b can be mismatched with the shape of the undulating first bonding surface 222b. The two are joined.
參照第6圖。翻轉半導體元件300，使得半導體元件300之區段A’、區段B’與區段C’係對應位於基板100之區段A”、區段B”與區段C”上方。承載板310之表面314面對基板100之介電層140之上表面144，基板100上之第一導電結構200a、200b及200c之接合部220a、220b及220c對準半導體元件300上之第二導電結構400a、400b與400c。 Refer to Figure 6. The semiconductor component 300 is flipped such that the segment A', the segment B' and the segment C' of the semiconductor component 300 are correspondingly located above the segment A", the segment B" and the segment C" of the substrate 100. The carrier plate 310 The surface 314 faces the upper surface 144 of the dielectric layer 140 of the substrate 100, and the bonding portions 220a, 220b, and 220c of the first conductive structures 200a, 200b, and 200c on the substrate 100 are aligned with the second conductive structure 400a on the semiconductor device 300, 400b and 400c.
同時參照第7與8圖。壓合基板100與半導體元件 300，使得基板100上之第一導電結構200a、200b與200c分別接合半導體元件300上之第二導電結構400a、400b與400c。如第7圖所示，於壓合的前段過程中，第一導電結構200a、200b及200c分別與第二導電結構400a、400b及400c係局部地接觸而產生應力集中區st1、st2及st3。 Also refer to Figures 7 and 8. Press-bonding substrate 100 and semiconductor components 300, the first conductive structures 200a, 200b, and 200c on the substrate 100 are bonded to the second conductive structures 400a, 400b, and 400c on the semiconductor device 300, respectively. As shown in FIG. 7, during the pre-pressing process, the first conductive structures 200a, 200b, and 200c are in partial contact with the second conductive structures 400a, 400b, and 400c, respectively, to generate stress concentration regions st1, st2, and st3.
以第一導電結構200a與第二導電結構400a為例，由於第一接合面222a與第二接合面422a的形狀不匹配，故在壓合的前段過程中，第一導電結構200a的第一接合面222a之部分區域與第二導電結構400a之第二接合面422a的部分區域相接觸，而第一接合面222a與第二接合面422a的剩餘區域則係相分離的，故第一導電結構200a與第二導電結構400a所承受的應力會集中於第一接合面222a與第二接合面422a的接觸區，而形成應力集中區st1。換句話說，應力集中區st1係形成於實質上平坦的第一接合面222a，亦形成於起伏狀的第二接合面422a。更具體地說，應力集中區st1係形成於實質上平坦的第一接合面222a與起伏狀的第二接合面422a之接觸區。 Taking the first conductive structure 200a and the second conductive structure 400a as an example, since the shapes of the first joint surface 222a and the second joint surface 422a do not match, the first joint of the first conductive structure 200a during the front portion of the press-fit A portion of the surface 222a is in contact with a partial region of the second bonding surface 422a of the second conductive structure 400a, and the remaining regions of the first bonding surface 222a and the second bonding surface 422a are phase separated, so the first conductive structure 200a The stress with the second conductive structure 400a is concentrated on the contact regions of the first joint surface 222a and the second joint surface 422a to form the stress concentration region st1. In other words, the stress concentration region st1 is formed on the substantially flat first joint surface 222a, and is also formed on the undulating second joint surface 422a. More specifically, the stress concentration region st1 is formed in a contact region between the substantially flat first joint surface 222a and the undulating second joint surface 422a.
相似地，由於第一接合面222b與第二接合面422b的形狀不匹配，故第一導電結構200b與第二導電結構400b所承受的應力會集中於第一接合面222b與第二接合面422b的接觸區，而形成應力集中區st2。換句話說，應力集中區st2係形成於起伏狀的第一接合面222b，亦形成於實質上平坦的第二接合面422b。更具體地說，應力集中區st2係形成於起伏狀的的第一接合面222b與實質上平坦的第二接合面422b之接觸 區。 Similarly, since the shapes of the first bonding surface 222b and the second bonding surface 422b do not match, the stresses of the first conductive structure 200b and the second conductive structure 400b may be concentrated on the first bonding surface 222b and the second bonding surface 422b. The contact area forms a stress concentration region st2. In other words, the stress concentration region st2 is formed on the undulating first joint surface 222b and also formed on the substantially flat second joint surface 422b. More specifically, the stress concentration region st2 is formed in contact with the undulating first joint surface 222b and the substantially flat second joint surface 422b. Area.
又相似地，由於第一接合面222c與第二接合面422c的形狀不匹配，故第一導電結構200c與第二導電結構400c所承受的應力會集中於第一接合面222c與第二接合面422c的接觸區，而形成應力集中區st3。換句話說，應力集中區st3係形成於起伏狀的第一接合面222c，亦形成於起伏狀的第二接合面422c。更具體地說，應力集中區st3係形成於起伏狀的的第一接合面222b與起伏狀的第二接合面422b之接觸區。 Similarly, since the shapes of the first bonding surface 222c and the second bonding surface 422c are not matched, the stresses of the first conductive structure 200c and the second conductive structure 400c may be concentrated on the first bonding surface 222c and the second bonding surface. The contact region of 422c forms a stress concentration region st3. In other words, the stress concentration region st3 is formed on the undulating first joint surface 222c and also formed on the undulating second joint surface 422c. More specifically, the stress concentration region st3 is formed in a contact region between the undulating first joint surface 222b and the undulating second joint surface 422b.
上述應力集中區st1、st2與st3可幫助第一導電結構200a、200b及200c與第二導電結構400a、400b及400c的變形，從而利於第一導電結構200a、200b及200c分別與第二導電結構400a、400b及400c接合，故可降低接合所需的溫度，以進一步降低基板100與半導體元件300受熱所產生的翹曲量。 The stress concentration regions st1, st2, and st3 may help the first conductive structures 200a, 200b, and 200c and the second conductive structures 400a, 400b, and 400c to deform, thereby facilitating the first conductive structures 200a, 200b, and 200c and the second conductive structure, respectively. Since 400a, 400b, and 400c are bonded, the temperature required for bonding can be lowered to further reduce the amount of warpage generated by the substrate 100 and the semiconductor element 300 due to heat.
進一步來說，參照第7A圖。第7A圖為第7圖之局部區域A的放大示意圖。第二接合面422a可包含突起部4222a與基底部4224a，突起部4222a突起於基底部4224a。在壓合的前段過程中，第二接合面422a之突起部4222a接觸第一導電結構200a的第一接合面222a而形成接觸區c1，但第二接合面422a之基底部4224a並未接觸第一導電結構200a，故應力集中區st1係形成於接觸區c1。 Further, refer to FIG. 7A. Fig. 7A is an enlarged schematic view of a partial area A of Fig. 7. The second joint surface 422a may include a protrusion portion 4222a and a base portion 4224a, and the protrusion portion 4222a protrudes from the base portion 4224a. During the nip of the nip, the protrusion 4222a of the second bonding surface 422a contacts the first bonding surface 222a of the first conductive structure 200a to form the contact region c1, but the base portion 4224a of the second bonding surface 422a does not contact the first portion. Since the conductive structure 200a is formed, the stress concentration region st1 is formed in the contact region c1.
參照第7B圖。第7B圖為第7圖之局部區域B的放大示意圖。第一接合面222b可包含突起部2222b與基底部 2224b，突起部2222b突起於基底部2224b。在壓合的前段過程中，第一接合面222b之突起部2222b接觸第二導電結構400b之第二接合面422b而形成接觸區c2，但第一接合面222b之基底部2224b並未接觸第二導電結構400b，故應力集中區st2係形成於接觸區c2。 Refer to Figure 7B. Fig. 7B is an enlarged schematic view of a partial region B of Fig. 7. The first joint surface 222b may include a protrusion 2222b and a base portion 2224b, the protrusion 2222b protrudes from the base portion 2224b. During the nip of the nip, the protrusion 2222b of the first bonding surface 222b contacts the second bonding surface 422b of the second conductive structure 400b to form the contact region c2, but the base portion 2224b of the first bonding surface 222b does not contact the second portion. Since the conductive structure 400b is formed, the stress concentration region st2 is formed in the contact region c2.
參照第7C圖。第7C圖為第7圖之局部區域C的剖面放大示意圖。第二接合面422c可包含突起部4222c與基底部4224c，突起部4222c突起於基底部4224c，且第一接合面222c可包含突起部2222c與基底部2224c，突起部2222c突起於基底部2224c。第二接合面422c之突起部4222c接觸第一接合面222c之突起部2222c而形成接觸區c3，且第二接合面422c之基底部4224c不接觸第一接合面222c之基底部2224c，故應力集中區st2係形成於接觸區c2。 Refer to Figure 7C. Fig. 7C is an enlarged schematic cross-sectional view showing a partial region C of Fig. 7. The second joint surface 422c may include a protrusion portion 4222c and a base portion 4224c. The protrusion portion 4222c protrudes from the base portion 4224c, and the first joint surface 222c may include a protrusion portion 2222c and a base portion 2224c, and the protrusion portion 2222c protrudes from the base portion 2224c. The protrusion portion 4222c of the second bonding surface 422c contacts the protrusion portion 2222c of the first bonding surface 222c to form the contact region c3, and the base portion 4224c of the second bonding surface 422c does not contact the base portion 2224c of the first bonding surface 222c, so stress concentration The region st2 is formed in the contact region c2.
於部分實施方式中，壓合製程係指施加作用力於基板100與半導體元件300之至少一者，使得第一導電結構200a、200b及200c分別與第二導電結構400a、400b及400c於接觸區c1、c2及c3會產生固態擴散反應(Solid State Diffusion)。也就是說，第一導電結構200a、200b及200c分別與第二導電結構400a、400b及400c可於接觸區c1、c2及c3產生原子交互擴散(Inter-Diffusion of Atoms)與晶粒成長(Grain Growth)，從而彼此接合。於本發明之部分實施方式中，由於在壓合的前段過程中，第一導電結構200a、200b及200c分別與第二導電結構400a、400b及400c係局部接觸的，從而形成應力集中區st1、st2與st3，故此集中的應力可破壞附 著於第一導電結構200a、200b與200c之不必要的氧化層或其他附著物、或破壞附著於第二導電結構400a、400b與400c之不必要的氧化層或其他附著物，俾利於第一導電結構200a、200b及200c分別與第二導電結構400a、400b及400c能夠無縫地接合。 In some embodiments, the embossing process refers to applying at least one of the substrate 100 and the semiconductor device 300 such that the first conductive structures 200a, 200b, and 200c are in contact with the second conductive structures 400a, 400b, and 400c, respectively. C1, c2, and c3 produce a solid state diffusion (Solid State Diffusion). That is, the first conductive structures 200a, 200b, and 200c and the second conductive structures 400a, 400b, and 400c respectively generate inter-Diffusion of Atoms and grain growth in the contact regions c1, c2, and c3 (Grain Growth), thus joining each other. In some embodiments of the present invention, since the first conductive structures 200a, 200b, and 200c are in partial contact with the second conductive structures 400a, 400b, and 400c, respectively, during the pre-pressing process, the stress concentration region st1 is formed. St2 and st3, so the concentrated stress can be destroyed Unnecessary oxide layers or other deposits on the first conductive structures 200a, 200b and 200c, or unnecessary oxide layers or other deposits attached to the second conductive structures 400a, 400b and 400c, benefiting from the first The conductive structures 200a, 200b, and 200c are seamlessly engageable with the second conductive structures 400a, 400b, and 400c, respectively.
於部分實施方式中，在壓合基板100與半導體元件300的過程中，溫度係介於攝氏60度至160度之間。如此一來，可有效地在不過度高溫的環境下接合第一導電結構200a、200b及200c與第二導電結構400a、400b及400c。此外，當壓合溫度介於攝氏60度至160度之間時，第一導電結構200a、200b及200c與第二導電結構400a、400b及400c可具有良好的導電率。舉例而言，於部分實施方式中，壓合製程可在攝氏溫度80度、一大氣壓下進行70分鐘，以更有效地接合第一導電結構200a、200b及200c與第二導電結構400a、400b及400c，且第一導電結構200a、200b及200c與第二導電結構400a、400b及400c具有良好的導電率。於部分實施方式中，壓合製程可在攝氏60度、一大氣壓下進行10分鐘，或者，壓合製程可在攝氏160度、一大氣壓下進行10分鐘，但本發明不以此為限。值得注意的是，當壓合溫度小於攝氏60度時，可能會導致第一導電結構200a、200b及200c與第二導電結構400a、400b及400c的導電率過低。當壓合溫度大於160度時，則會導致不必要的熱積存(thermal budget)，因此，壓合溫度介於攝氏60度至160度之間，其中較佳壓合溫度可為攝氏80度、攝氏100度或攝氏120度。 In some embodiments, during the process of pressing the substrate 100 and the semiconductor component 300, the temperature is between 60 degrees Celsius and 160 degrees Celsius. As a result, the first conductive structures 200a, 200b, and 200c and the second conductive structures 400a, 400b, and 400c can be effectively bonded in an environment that is not excessively high in temperature. Further, the first conductive structures 200a, 200b, and 200c and the second conductive structures 400a, 400b, and 400c may have good electrical conductivity when the bonding temperature is between 60 degrees Celsius and 160 degrees Celsius. For example, in some embodiments, the embossing process can be performed at 80 degrees Celsius and atmospheric pressure for 70 minutes to more effectively bond the first conductive structures 200a, 200b, and 200c with the second conductive structures 400a, 400b. 400c, and the first conductive structures 200a, 200b, and 200c and the second conductive structures 400a, 400b, and 400c have good electrical conductivity. In some embodiments, the pressing process may be performed at 60 degrees Celsius and one atmosphere for 10 minutes, or the pressing process may be performed at 160 degrees Celsius and atmospheric pressure for 10 minutes, but the invention is not limited thereto. It should be noted that when the pressing temperature is less than 60 degrees Celsius, the conductivity of the first conductive structures 200a, 200b, and 200c and the second conductive structures 400a, 400b, and 400c may be too low. When the pressing temperature is greater than 160 degrees, it will cause unnecessary thermal budget. Therefore, the pressing temperature is between 60 degrees and 160 degrees Celsius, and the preferred pressing temperature can be 80 degrees Celsius. 100 degrees Celsius or 120 degrees Celsius.
參照第9圖。第9圖為依據本發明之另一實施方式於壓合基板100與半導體元件300之前的剖面示意圖。本實施方式與前述實施方式的主要差異在於：在第一導電結構200a、200b及200c分別與第二導電結構400a、400b及400c接合之前，形成抗氧化層500於第一導電結構200a、200b及200c與第二導電結構400a、400b及400c之至少一者。如此一來，抗氧化層500可避免第一導電結構200a、200b及200c與第二導電結構400a、400b及400c之至少一者氧化。於部分實施方式中，抗氧化層500可為低電阻材料或鈍性材料，例如：鈦，但本發明不以此為限。 Refer to Figure 9. FIG. 9 is a schematic cross-sectional view showing the substrate 100 and the semiconductor device 300 before being pressed according to another embodiment of the present invention. The main difference between this embodiment and the foregoing embodiment is that the oxidation resistant layer 500 is formed on the first conductive structures 200a, 200b and before the first conductive structures 200a, 200b, and 200c are bonded to the second conductive structures 400a, 400b, and 400c, respectively. At least one of 200c and second conductive structures 400a, 400b, and 400c. As such, the oxidation resistant layer 500 can prevent oxidation of at least one of the first conductive structures 200a, 200b, and 200c and the second conductive structures 400a, 400b, and 400c. In some embodiments, the oxidation resistant layer 500 can be a low-resistance material or a passive material, such as titanium, but the invention is not limited thereto.
於本發明之部分實施方式中，雖然本發明已以多種實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In some embodiments of the present invention, the present invention has been disclosed in various embodiments, and is not intended to limit the present invention, and various modifications may be made without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims.
100‧‧‧基板 100‧‧‧Substrate
110‧‧‧剝離層 110‧‧‧ peeling layer
120‧‧‧金屬層 120‧‧‧metal layer
130‧‧‧重分布層 130‧‧‧ redistribution layer
140‧‧‧介電層 140‧‧‧Dielectric layer
200a、200b、200c‧‧‧第一導電結構 200a, 200b, 200c‧‧‧ first conductive structure
222a、222b、222c‧‧‧第一接合面 222a, 222b, 222c‧‧‧ first joint
300‧‧‧半導體元件 300‧‧‧Semiconductor components
310‧‧‧承載板 310‧‧‧ carrying board
320‧‧‧晶片 320‧‧‧ wafer
400a、400b、400c‧‧‧第二導電結構 400a, 400b, 400c‧‧‧ second conductive structure
422a、422b、422c‧‧‧第二接合面 422a, 422b, 422c‧‧‧ second joint
A、B、C‧‧‧局部區域 A, B, C‧‧‧ local areas
A’、B’、C’‧‧‧區段 A’, B’, C’‧‧‧ Section
A”、B”、C”‧‧‧區段 A", B", C" ‧ ‧ section
st1、st2、st3‧‧‧應力集中區 St1, st2, st3‧‧‧ stress concentration area
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| US10736215B1 (en) | 2019-04-22 | 2020-08-04 | Unimicron Technology Corp. | Multilayer circuit board structure and manufacturing method thereof |
| US10993332B2 (en) | 2018-08-03 | 2021-04-27 | Unimicron Technology Corp. | Circuit substrate |
| US11424216B2 (en) | 2020-08-31 | 2022-08-23 | Unimicron Technology Corp. | Electronic device bonding structure and fabrication method thereof |
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| TW201128745A (en) * | 2010-02-06 | 2011-08-16 | Ind Tech Res Inst | Bonding structure and method of fabricating the same |
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