TWI612590B - Electronic package and the manufacture thereof - Google Patents

Electronic package and the manufacture thereof Download PDF

Info

Publication number
TWI612590B
TWI612590B TW105114384A TW105114384A TWI612590B TW I612590 B TWI612590 B TW I612590B TW 105114384 A TW105114384 A TW 105114384A TW 105114384 A TW105114384 A TW 105114384A TW I612590 B TWI612590 B TW I612590B
Authority
TW
Taiwan
Prior art keywords
bump
package
substrate
support
packaging
Prior art date
Application number
TW105114384A
Other languages
Chinese (zh)
Other versions
TW201740473A (en
Inventor
賴昶存
符毅民
王愉博
王隆源
江政嘉
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW105114384A priority Critical patent/TWI612590B/en
Priority to CN201610347641.3A priority patent/CN107359141A/en
Publication of TW201740473A publication Critical patent/TW201740473A/en
Application granted granted Critical
Publication of TWI612590B publication Critical patent/TWI612590B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一種電子封裝件，係包括：封裝基板、設於該封裝基板不同側之電子元件與支撐凸塊、以及包覆該電子元件與該支撐凸塊之封裝層，以藉由該支撐凸塊及封裝層之設計，而防止該封裝基板於熱循環時發生翹曲。本發明復提供該電子封裝件之製法。 An electronic package includes: a package substrate, electronic components and support bumps provided on different sides of the package substrate, and a packaging layer covering the electronic components and the support bumps so as to pass the support bumps and the package. Layer design to prevent the package substrate from warping during thermal cycling. The invention further provides a method for manufacturing the electronic package.

Description

電子封裝件及其製法 Electronic package and manufacturing method thereof

本發明係有關一種封裝結構，尤指一種電子封裝件及其製法。 The invention relates to a packaging structure, in particular to an electronic package and a manufacturing method thereof.

隨著電子產業的蓬勃發展，許多高階電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展，且隨著封裝技術之演進，晶片的封裝技術也越來越多樣化，半導體封裝結構之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝結構達到輕薄短小之目的。 With the vigorous development of the electronics industry, many high-end electronic products are gradually moving towards high integration levels such as light, thin, short, and small. With the evolution of packaging technology, the packaging technology of wafers has become more and more diverse. The size or volume of the packaging structure is also continuously reduced, so that the semiconductor packaging structure can be light, thin and short.

第1圖係為習知封裝結構1之剖面示意圖。如第1圖所示，該封裝結構1係包括：一封裝基板10、一結合於該封裝基板10上之半導體晶片11、以及用以包覆該半導體晶片11之封裝膠體13。 FIG. 1 is a schematic cross-sectional view of a conventional package structure 1. FIG. As shown in FIG. 1, the packaging structure 1 includes a packaging substrate 10, a semiconductor wafer 11 coupled to the packaging substrate 10, and a packaging gel 13 for covering the semiconductor wafer 11.

惟，習知封裝結構1於封裝過程中，該封裝基板10係為整版面(即量產尺寸)，且該封裝基板10僅於一側上設置該半導體晶片11，故於形成封裝膠體13時，該封裝基板10因與該封裝膠體13熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)不匹配(mismatch)而容易 發生熱應力不均勻之情況，致使熱循環(thermal cycle)時該封裝基板10產生翹曲(warpage)，進而導致發生植球(即封裝基板10下側之銲球14)掉落、銲球14不沾錫(non-wetting)或該封裝基板10裂開等問題。 However, it is known that during the packaging process of the packaging structure 1, the packaging substrate 10 is a full layout (that is, a mass production size), and the packaging substrate 10 is provided with the semiconductor wafer 11 on only one side, so when the packaging colloid 13 is formed The package substrate 10 is easy to mismatch with the coefficient of thermal expansion (CTE) of the package colloid 13. The occurrence of uneven thermal stress causes the package substrate 10 to warp during a thermal cycle, which in turn causes the bumps (ie, the solder balls 14 on the lower side of the package substrate 10) to fall, and the solder balls 14 Problems such as non-wetting or cracking of the package substrate 10.

再者，翹曲的情況亦會造成該半導體晶片11發生碎裂，致使產品良率降低。 Moreover, the warping condition will also cause the semiconductor wafer 11 to crack, resulting in a lower product yield.

因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned conventional technologies has become an urgent problem to be solved.

鑒於上述習知技術之缺失，本發明提供一種電子封裝件，係包括：封裝基板，係具有相對之第一表面與第二表面；至少一電子元件，係設於該封裝基板之第一表面上；至少一支撐凸塊，係形成於該封裝基板之第二表面上；以及封裝層，係形成於該封裝基板之第一表面與第二表面上，以包覆該電子元件與該支撐凸塊，且令該支撐凸塊之部分表面外露於該封裝層。 In view of the lack of the above-mentioned conventional technology, the present invention provides an electronic package including: a package substrate having a first surface and a second surface opposite to each other; at least one electronic component provided on the first surface of the package substrate ; At least one supporting bump is formed on the second surface of the packaging substrate; and a packaging layer is formed on the first surface and the second surface of the packaging substrate to cover the electronic component and the supporting bump , And a part of the surface of the supporting bump is exposed to the packaging layer.

本發明復提供一種電子封裝件之製法，係包括：提供一具有相對之第一表面與第二表面的封裝基板；設置至少一電子元件於該封裝基板之第一表面上，且形成至少一支撐凸塊於該封裝基板之第二表面上；以及形成封裝層於該封裝基板之第一表面與第二表面上，以包覆該電子元件與該支撐凸塊，且令該支撐凸塊之部分表面外露於該封裝層。 The invention further provides a method for manufacturing an electronic package, comprising: providing a package substrate having a first surface and a second surface opposite to each other; providing at least one electronic component on the first surface of the package substrate, and forming at least one support A bump is formed on the second surface of the package substrate; and an encapsulation layer is formed on the first surface and the second surface of the package substrate to cover the electronic component and the support bump and make a portion of the support bump The surface is exposed from the encapsulation layer.

前述之電子封裝件及其製法中，該支撐凸塊係為金屬凸塊。 In the aforementioned electronic package and its manufacturing method, the support bump is a metal bump.

前述之電子封裝件及其製法中，該支撐凸塊係電性連接該封裝基板。 In the aforementioned electronic package and its manufacturing method, the support bump is electrically connected to the package substrate.

前述之電子封裝件及其製法中，該支撐凸塊復設於該封裝基板之第一表面上之封裝層中。 In the aforementioned electronic package and its manufacturing method, the support bump is reset in a package layer on the first surface of the package substrate.

前述之電子封裝件及其製法中，該電子元件復設於該封裝基板之第二表面上。 In the aforementioned electronic package and its manufacturing method, the electronic component is reset on the second surface of the package substrate.

前述之電子封裝件及其製法中，該支撐凸塊之外露部分表面係齊平該封裝層之表面。 In the aforementioned electronic package and its manufacturing method, the surface of the exposed portion of the support bump is flush with the surface of the packaging layer.

前述之電子封裝件及其製法中，該支撐凸塊之外露部分表面係凸出該封裝層之表面。 In the aforementioned electronic package and its manufacturing method, the surface of the exposed portion of the support bump protrudes from the surface of the packaging layer.

前述之電子封裝件及其製法中，該封裝層係先覆蓋該支撐凸塊，再於該封裝層中形成有至少一用以外露該支撐凸塊之部分表面的開孔。 In the aforementioned electronic package and its manufacturing method, the packaging layer first covers the support bump, and then at least one opening is formed in the packaging layer to expose a part of the surface of the support bump.

前述之電子封裝件及其製法中，復包括形成複數導電元件於該封裝層上並電性連接該支撐凸塊。該支撐凸塊之材質與該導電元件之材質係相同或不同。 In the aforementioned electronic package and its manufacturing method, the method further includes forming a plurality of conductive elements on the packaging layer and electrically connecting the supporting bumps. The material of the supporting bump is the same as or different from that of the conductive element.

由上可知，本發明之電子封裝件及其製法中，主要藉由該電子元件與該支撐凸塊分別設於該封裝基板之第一表面與第二表面上，並於該封裝基板之第一表面與第二表面上形成封裝層，以平衡該封裝基板之應力分佈，故於熱循環時，能防止該封裝基板翹曲，因而能避免該封裝基板發生植球掉落或裂開等問題，且能避免該電子元件發生碎裂。 It can be known from the above that in the electronic package and the manufacturing method thereof of the present invention, the electronic component and the supporting bump are mainly provided on the first surface and the second surface of the packaging substrate, respectively, and on the first surface of the packaging substrate. An encapsulation layer is formed on the surface and the second surface to balance the stress distribution of the encapsulation substrate, so that the encapsulation substrate can be prevented from warping during thermal cycling, and problems such as dropping or cracking of the encapsulation substrate can be avoided. And the electronic component can be prevented from being broken.

1‧‧‧封裝結構 1‧‧‧ package structure

10‧‧‧封裝基板 10‧‧‧ package substrate

11‧‧‧半導體晶片 11‧‧‧Semiconductor wafer

13‧‧‧封裝膠體 13‧‧‧ encapsulated colloid

14‧‧‧銲球 14‧‧‧Solder Ball

2,2’,2”‧‧‧電子封裝件 2,2 ’, 2” ‧‧‧Electronic package

20‧‧‧封裝基板 20‧‧‧ package substrate

20a‧‧‧第一表面 20a‧‧‧first surface

20b‧‧‧第二表面 20b‧‧‧Second surface

21,21’‧‧‧電子元件 21,21’‧‧‧Electronic components

22,22’,22”‧‧‧支撐凸塊 22,22 ’, 22” ‧‧‧‧Supporting bump

22a,22a”‧‧‧端面 22a, 22a ”‧‧‧face

23,33‧‧‧封裝層 23,33‧‧‧Encapsulation layer

23a,23b,33a‧‧‧表面 23a, 23b, 33a‧‧‧ surface

24‧‧‧導電元件 24‧‧‧ conductive element

330‧‧‧開孔 330‧‧‧ opening

第1圖係為習知封裝結構之剖面示意圖； 第2A至2C圖係為本發明之電子封裝件之製法的剖面示意圖；第2A’及2A”圖係為對應第2A圖的其它不同實施例之剖面示意圖；第2C’及2C”圖係為對應第2C圖的其它不同實施例之剖面示意圖；第3A及3B圖係為對應第2B圖的其它不同實施例之局部放大圖；以及第3B’圖係為對應第3B圖的另一實施例之剖面示意圖。 Figure 1 is a schematic cross-sectional view of a conventional package structure; Figures 2A to 2C are schematic sectional views of the manufacturing method of the electronic package of the present invention; Figures 2A 'and 2A "are schematic sectional views of other different embodiments corresponding to Figure 2A; and Figures 2C' and 2C" are Sectional schematic diagrams of other different embodiments corresponding to FIG. 2C; FIGS. 3A and 3B are partial enlarged views of other different embodiments corresponding to FIG. 2B; and FIG. 3B ′ is another embodiment corresponding to FIG. 3B Schematic cross-section.

以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。 The following is a description of specific embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如 「上」、「下」、「第一」、「第二」等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this manual are only used to match the contents disclosed in the manual for the understanding and reading of those skilled in this technology, and are not intended to limit the implementation of this creation. The limited conditions are not technically significant. Any modification of the structure, the change of the proportional relationship, or the adjustment of the size shall remain within the scope of this article without affecting the effects and goals that can be achieved by this creation. The technical content revealed by the creation must be within the scope. At the same time, the The terms "up", "down", "first", "second", etc., are only for the convenience of narrative, and are not used to limit the scope of this creation. The relative relationship changes or adjustments, Without any substantial change in the technical content, it should be considered as the scope of this creation.

請參閱第2A至2C圖係為本發明之電子封裝件2之製法之剖面示意圖。 Please refer to FIGS. 2A to 2C, which are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

如第2A圖所示，提供一具有相對之第一表面20a與第二表面20b的封裝基板20，再設置複數電子元件21,21’於該封裝基板20之第一表面20a上，且形成複數支撐凸塊22於該封裝基板20之第二表面20b上。 As shown in FIG. 2A, a package substrate 20 having a first surface 20a and a second surface 20b opposite to each other is provided, and a plurality of electronic components 21, 21 'are further provided on the first surface 20a of the package substrate 20, and a plurality of components are formed. The supporting bump 22 is on the second surface 20 b of the packaging substrate 20.

於本實施例中，該封裝基板20係例如為陶瓷板材、絕緣板、金屬板或有機板材，即一般封裝基板，且具有至少一線路層(圖未示)。 In this embodiment, the package substrate 20 is, for example, a ceramic plate, an insulating plate, a metal plate, or an organic plate, that is, a general package substrate, and has at least one circuit layer (not shown).

再者，該電子元件21,21’係為主動元件、被動元件或其二者組合，其中，該主動元件(如電子元件21)係例如半導體晶片，而該被動元件(如電子元件21’)係例如電阻、電容及電感。 Furthermore, the electronic component 21, 21 'is an active component, a passive component, or a combination of both, wherein the active component (such as the electronic component 21) is, for example, a semiconductor wafer, and the passive component (such as the electronic component 21') Examples are resistors, capacitors, and inductors.

又，該支撐凸塊22係為金屬凸塊，例如，第2A圖所示之支撐凸塊22係為銅凸塊、或第2A’圖所示之支撐凸塊22’係含有銲錫材料。選擇性地，該導電凸塊22,22’可電性連接該封裝基板20。 The support bump 22 is a metal bump. For example, the support bump 22 shown in Fig. 2A is a copper bump, or the support bump 22 'shown in Fig. 2A' contains a solder material. Optionally, the conductive bumps 22, 22 'can be electrically connected to the packaging substrate 20.

另外，如第2A”圖所示，該支撐凸塊22”亦可形成於該封裝基板20之第一表面20a上。應可理解地，該電子元件21,21’亦可設於該封裝基板20之第二表面20b上。 In addition, as shown in FIG. 2A ″, the supporting bump 22 ″ can also be formed on the first surface 20 a of the packaging substrate 20. It should be understood that the electronic components 21, 21 'can also be disposed on the second surface 20b of the package substrate 20.

如第2B圖所示，接續第2A圖之製程，形成一封裝層23於該封裝基板20之第一表面20a與第二表面20b上，以包覆該些電子元件21,21’與該些支撐凸塊22，且令該些支撐凸塊22之端面22a外露於該封裝層23。 As shown in FIG. 2B, following the process of FIG. 2A, a packaging layer 23 is formed on the first surface 20a and the second surface 20b of the packaging substrate 20 to cover the electronic components 21, 21 'and the The support bumps 22 are exposed, and the end surfaces 22 a of the support bumps 22 are exposed to the packaging layer 23.

於本實施例中，形成該封裝層23之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材。 In this embodiment, the material for forming the encapsulation layer 23 is polyimide (PI), dry film, epoxy, or packaging material.

再者，該支撐凸塊22之端面22a係齊平該封裝層23之表面23a，以令該些支撐凸塊22之端面22a外露於該封裝層23之表面23a。或者，於其它實施例中，如第3A圖所示，該些支撐凸塊22之端面22a係凸出該封裝層33之表面33a，以令該些支撐凸塊22之端面22a外露於該封裝層33之表面33a。亦或，如第3B及3B’圖所示，該封裝層33先覆蓋該些支撐凸塊22,22’，再以如雷射之鑽孔方式形成開孔330，使該封裝層33係具有複數用以外露該些支撐凸塊22,22’之開孔330。 Furthermore, the end surface 22 a of the support bump 22 is flush with the surface 23 a of the packaging layer 23, so that the end surfaces 22 a of the support bumps 22 are exposed on the surface 23 a of the packaging layer 23. Or, in other embodiments, as shown in FIG. 3A, the end surfaces 22a of the support bumps 22 are protruding from the surface 33a of the packaging layer 33, so that the end surfaces 22a of the support bumps 22 are exposed to the package. The surface 33a of the layer 33. Alternatively, as shown in FIGS. 3B and 3B ′, the encapsulation layer 33 first covers the supporting bumps 22, 22 ′, and then forms an opening 330 by drilling as a laser, so that the encapsulation layer 33 has A plurality of openings 330 for the supporting bumps 22, 22 'are exposed.

如第2C圖所示，形成複數導電元件24於該封裝層23上並電性連接該些支撐元件22。 As shown in FIG. 2C, a plurality of conductive elements 24 are formed on the packaging layer 23 and are electrically connected to the support elements 22.

於本實施例中，該導電元件24係含有銲錫材料，故該支撐凸塊22之材質與該導電元件24之材質係不相同。 In this embodiment, the conductive element 24 contains a solder material, so the material of the support bump 22 is different from the material of the conductive element 24.

再者，如第2C’圖所示，若接續第2A’圖所示之製程，將得到另一種電子封裝件2’，其中該支撐凸塊22’之材質與該導電元件24之材質相同。 Furthermore, as shown in FIG. 2C ', if the process shown in FIG. 2A' is continued, another electronic package 2 'will be obtained, in which the material of the support bump 22' is the same as that of the conductive element 24.

又，如第2C”圖所示，若接續第2A”圖所示之製程， 將得到另一種電子封裝件2”，其中該第一表面20a上之支撐凸塊22”之端面22a”外露於該封裝層23之表面23b，俾供結合如另一電子封裝件或晶片之電子裝置(圖略)。應可理解地，該第一表面20a上之支撐凸塊22”之外露方式可參考第2B、3A及3B圖所示之方式。 In addition, as shown in FIG. 2C ”, if the process shown in FIG. 2A” is continued, Another electronic package 2 "will be obtained, in which the end surface 22a" of the support bump 22 "on the first surface 20a is exposed on the surface 23b of the packaging layer 23, for the integration of electronics such as another electronic package or chip Device (illustration omitted). It should be understood that the method for exposing the supporting bumps 22 "on the first surface 20a can refer to the methods shown in Figs. 2B, 3A and 3B.

本發明之電子封裝件2,2’,2”係藉由該支撐凸塊22,22’與該封裝層23之設計，以於該封裝基板20之第一表面20a與第二表面20b上佈設有電子元件21,21’與該支撐凸塊22,22’，並於該封裝基板20之第一表面20a與第二表面20b上形成該封裝層23，而能平衡該封裝基板20上、下側所受之應力，故於熱循環時，能防止該封裝基板20翹曲，避免該封裝基板20發生植球掉落或裂開等問題，且能避免該電子元件21,21’發生碎裂，進而提升產品良率。 The electronic package 2, 2 ′, 2 ″ of the present invention is designed on the first surface 20 a and the second surface 20 b of the package substrate 20 by the design of the supporting bumps 22, 22 ′ and the packaging layer 23. There are electronic components 21, 21 ′ and the supporting bumps 22, 22 ′, and the packaging layer 23 is formed on the first surface 20 a and the second surface 20 b of the packaging substrate 20 to balance the upper and lower surfaces of the packaging substrate 20. The stress on the side can prevent the package substrate 20 from warping during thermal cycling, avoid problems such as dropping or cracking of the package substrate 20, and prevent the electronic components 21, 21 'from cracking. , Thereby improving product yield.

本發明復提供一種電子封裝件2,2’,2”，係包括：一封裝基板20、複數電子元件21,21’、複數支撐凸塊22,22’,22”以及一封裝層23,33。 The present invention further provides an electronic package 2, 2 ', 2 ", which includes: a package substrate 20, a plurality of electronic components 21, 21', a plurality of support bumps 22, 22 ', 22", and a package layer 23, 33. .

所述之封裝基板20係具有相對之第一表面20a與第二表面20b。 The package substrate 20 has a first surface 20a and a second surface 20b opposite to each other.

所述之電子元件21,21’係設於該封裝基板20之第一表面20a上。 The electronic components 21, 21 ′ are disposed on the first surface 20 a of the package substrate 20.

所述之支撐凸塊22,22’係形成於該封裝基板20之第二表面20b上。 The supporting bumps 22, 22 ′ are formed on the second surface 20 b of the packaging substrate 20.

所述之封裝層23,33係形成於該封裝基板20之第一表面20a與第二表面20b上，以包覆該電子元件21,21’與該 支撐凸塊22,22’，且令該支撐凸塊22,22’之部分表面外露於該封裝層23,33。 The packaging layers 23 and 33 are formed on the first surface 20a and the second surface 20b of the packaging substrate 20 to cover the electronic components 21, 21 'and the The supporting bumps 22, 22 'and a part of the surface of the supporting bumps 22, 22' are exposed to the packaging layers 23, 33.

於一實施例中，該支撐凸塊22,22’,22”係為金屬凸塊。 In one embodiment, the supporting bumps 22, 22 ', 22 "are metal bumps.

於一實施例中，該支撐凸塊22”復設於該封裝基板20之第一表面20a上之封裝層23中，且其端面22a”外露於該封裝層23之表面23b。 In one embodiment, the supporting bump 22 ″ is reset in the packaging layer 23 on the first surface 20 a of the packaging substrate 20, and the end surface 22 a ″ is exposed on the surface 23 b of the packaging layer 23.

於一實施例中，該電子元件21,21’復設於該封裝基板20之第二表面20b上。 In one embodiment, the electronic components 21, 21 ′ are reset on the second surface 20 b of the package substrate 20.

於一實施例中，該支撐凸塊22之端面22a係齊平該封裝層23之表面23a。 In one embodiment, the end surface 22 a of the supporting bump 22 is flush with the surface 23 a of the encapsulation layer 23.

於一實施例中，該支撐凸塊22之端面22a係凸出該封裝層33之表面33a。 In one embodiment, the end surface 22 a of the support bump 22 protrudes from the surface 33 a of the packaging layer 33.

於一實施例中，該封裝層33係具有用以外露該些支撐凸塊22,22’之開孔330。 In one embodiment, the packaging layer 33 has an opening 330 for exposing the supporting bumps 22, 22 '.

於一實施例中，該電子元件2,2’,2”復包括複數導電元件24，係形成於該封裝層23上並電性連接該些支撐凸塊22,22’，其中，該支撐凸塊22之材質與該導電元件24之材質係不相同，而該支撐凸塊22’之材質與該導電元件24之材質係相同。 In one embodiment, the electronic component 2, 2 ′, 2 ″ includes a plurality of conductive components 24 formed on the encapsulation layer 23 and electrically connected to the supporting bumps 22, 22 ′. The material of the block 22 is different from that of the conductive element 24, and the material of the support bump 22 ′ is the same as that of the conductive element 24.

綜上所述，本發明之電子封裝件及其製法，主要藉由該支撐凸塊與封裝層之設計，以防止該封裝基板於熱循環時發生翹曲，故能避免因封裝基板翹曲而所衍生之問題。 In summary, the electronic package and its manufacturing method of the present invention mainly rely on the design of the supporting bumps and the packaging layer to prevent the packaging substrate from warping during thermal cycling, so it can avoid the packaging substrate from warping. Problems that arise.

上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above-mentioned embodiments only exemplify the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone familiar with this skill can In the spirit and scope of the present invention, the above embodiments are modified and changed. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

2‧‧‧電子封裝件 2‧‧‧electronic package

20‧‧‧封裝基板 20‧‧‧ package substrate

20a‧‧‧第一表面 20a‧‧‧first surface

20b‧‧‧第二表面 20b‧‧‧Second surface

21,21’‧‧‧電子元件 21,21’‧‧‧Electronic components

22‧‧‧支撐凸塊 22‧‧‧ support bump

23‧‧‧封裝層 23‧‧‧Encapsulation Layer

24‧‧‧導電元件 24‧‧‧ conductive elements

Claims (18)

一種電子封裝件，係包括：封裝基板，係具有相對之第一表面與第二表面；至少一電子元件，係設於該封裝基板之第一表面上而未設於該封裝基板之第二表面上；至少一支撐凸塊，係形成於該封裝基板之第二表面上而未形成於該封裝基板之第一表面上；封裝層，係形成於該封裝基板之第一表面與第二表面上，以包覆該電子元件與該支撐凸塊，且該些支撐凸塊之部分表面係凸出該封裝層之表面，以令該支撐凸塊之部分表面外露於該封裝層；以及複數導電元件，係形成於該封裝層上並電性連接該支撐凸塊。 An electronic package includes: a package substrate having a first surface and a second surface opposite to each other; at least one electronic component provided on the first surface of the package substrate and not provided on the second surface of the package substrate At least one supporting bump is formed on the second surface of the packaging substrate and is not formed on the first surface of the packaging substrate; and a packaging layer is formed on the first surface and the second surface of the packaging substrate To cover the electronic component and the support bump, and a part of the surface of the support bumps protrudes from the surface of the packaging layer, so that a part of the surface of the support bump is exposed to the packaging layer; and a plurality of conductive elements Is formed on the encapsulation layer and is electrically connected to the support bump. 如申請專利範圍第1項所述之電子封裝件，其中，該支撐凸塊係為金屬凸塊。 The electronic package according to item 1 of the scope of patent application, wherein the supporting bump is a metal bump. 如申請專利範圍第1項所述之電子封裝件，其中，該支撐凸塊係電性連接該封裝基板。 The electronic package according to item 1 of the patent application scope, wherein the support bump is electrically connected to the package substrate. 如申請專利範圍第1項所述之電子封裝件，其中，該支撐凸塊之材質與該導電元件之材質係相同或不同。 According to the electronic package described in item 1 of the scope of patent application, the material of the supporting bump is the same as or different from that of the conductive element. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面與第二表面的封裝基板；設置至少一電子元件於該封裝基板之第一表面上而未設於該封裝基板之第二表面上，且形成至少一支撐 凸塊於該封裝基板之第二表面上而未形成於該封裝基板之第一表面上；形成封裝層於該封裝基板之第一表面與第二表面上，以包覆該電子元件與該支撐凸塊，且該些支撐凸塊之部分表面係凸出該封裝層之表面，以令該支撐凸塊之部分表面外露於該封裝層；以及形成複數導電元件於該封裝層上並電性連接該支撐凸塊。 An electronic package manufacturing method includes: providing a package substrate having a first surface and a second surface opposite to each other; and providing at least one electronic component on the first surface of the package substrate but not on a second surface of the package substrate. On the surface and form at least one support A bump is formed on the second surface of the packaging substrate and is not formed on the first surface of the packaging substrate; a packaging layer is formed on the first surface and the second surface of the packaging substrate to cover the electronic component and the support Bumps, and a part of the surfaces of the support bumps protrude from the surface of the encapsulation layer, so that a part of the surface of the support bumps is exposed to the encapsulation layer; and a plurality of conductive elements are formed on the encapsulation layer and electrically connected The support bump. 如申請專利範圍第5項所述之電子封裝件之製法，其中，該支撐凸塊係為金屬凸塊。 According to the method for manufacturing an electronic package described in item 5 of the scope of patent application, wherein the support bump is a metal bump. 如申請專利範圍第5項所述之電子封裝件之製法，其中，該支撐凸塊係電性連接該封裝基板。 According to the method for manufacturing an electronic package described in item 5 of the scope of patent application, wherein the support bump is electrically connected to the package substrate. 如申請專利範圍第5項所述之電子封裝件之製法，其中，該支撐凸塊之材質與該導電元件之材質係相同或不同。 According to the method for manufacturing an electronic package described in item 5 of the scope of patent application, wherein the material of the supporting bump is the same as or different from that of the conductive element. 一種電子封裝件，係包括：封裝基板，係具有相對之第一表面與第二表面；複數電子元件，係設於該封裝基板之第一表面與第二表面上；至少一支撐凸塊，係形成於該封裝基板之第二表面上；封裝層，係形成於該封裝基板之第一表面與第二表面上，以包覆該些電子元件與該支撐凸塊，且該些支撐凸塊之部分表面係凸出該封裝層之表面，以令該支撐凸 塊之部分表面外露於該封裝層；以及複數導電元件，係形成於該封裝層上並電性連接該支撐凸塊。 An electronic package includes: a package substrate having a first surface and a second surface opposite to each other; a plurality of electronic components provided on the first surface and a second surface of the package substrate; at least one supporting bump; Formed on the second surface of the packaging substrate; the packaging layer is formed on the first surface and the second surface of the packaging substrate to cover the electronic components and the support bumps, and Part of the surface protrudes from the surface of the encapsulation layer to make the support convex A part of the surface of the block is exposed on the packaging layer; and a plurality of conductive elements are formed on the packaging layer and are electrically connected to the supporting bump. 如申請專利範圍第9項所述之電子封裝件，其中，該支撐凸塊係為金屬凸塊。 The electronic package according to item 9 of the scope of patent application, wherein the supporting bump is a metal bump. 如申請專利範圍第9項所述之電子封裝件，其中，該支撐凸塊係電性連接該封裝基板。 The electronic package according to item 9 of the scope of the patent application, wherein the support bump is electrically connected to the package substrate. 如申請專利範圍第9項所述之電子封裝件，其中，該支撐凸塊復形成於該封裝基板之第一表面上。 The electronic package according to item 9 of the scope of the patent application, wherein the support bump is formed on the first surface of the package substrate. 如申請專利範圍第9項所述之電子封裝件，其中，該支撐凸塊之材質與該導電元件之材質係相同或不同。 According to the electronic package described in item 9 of the scope of patent application, the material of the supporting bump is the same as or different from that of the conductive element. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面與第二表面的封裝基板；設置複數電子元件於該封裝基板之第一表面與第二表面上，且形成至少一支撐凸塊於該封裝基板之第二表面上；形成封裝層於該封裝基板之第一表面與第二表面上，以包覆該些電子元件與該支撐凸塊，且該些支撐凸塊之部分表面係凸出該封裝層之表面，以令該支撐凸塊之部分表面外露於該封裝層；以及形成複數導電元件於該封裝層上並電性連接該支撐凸塊。 An electronic package manufacturing method includes: providing a package substrate having a first surface and a second surface opposite to each other; providing a plurality of electronic components on the first surface and the second surface of the package substrate, and forming at least one supporting protrusion Blocks on the second surface of the packaging substrate; forming a packaging layer on the first surface and the second surface of the packaging substrate to cover the electronic components and the supporting bumps, and a part of the surfaces of the supporting bumps The surface of the encapsulation layer is protruded so that a part of the surface of the support bump is exposed to the encapsulation layer; and a plurality of conductive elements are formed on the encapsulation layer and electrically connected to the support bump. 如申請專利範圍第14項所述之電子封裝件之製法，其 中，該支撐凸塊係為金屬凸塊。 As for the manufacturing method of the electronic package described in the scope of application for item 14, In the embodiment, the support bump is a metal bump. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該支撐凸塊係電性連接該封裝基板。 According to the manufacturing method of the electronic package described in item 14 of the scope of the patent application, wherein the support bump is electrically connected to the package substrate. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該支撐凸塊復設於該封裝基板之第一表面上。 According to the method for manufacturing an electronic package described in item 14 of the scope of the patent application, wherein the support bump is reset on the first surface of the package substrate. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該支撐凸塊之材質與該導電元件之材質係相同或不同。 According to the manufacturing method of the electronic package described in item 14 of the scope of the patent application, wherein the material of the supporting bump is the same as or different from that of the conductive element.
TW105114384A 2016-05-10 2016-05-10 Electronic package and the manufacture thereof TWI612590B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW105114384A TWI612590B (en) 2016-05-10 2016-05-10 Electronic package and the manufacture thereof
CN201610347641.3A CN107359141A (en) 2016-05-10 2016-05-23 Electronic package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW105114384A TWI612590B (en) 2016-05-10 2016-05-10 Electronic package and the manufacture thereof

Publications (2)

Publication Number Publication Date
TW201740473A TW201740473A (en) 2017-11-16
TWI612590B true TWI612590B (en) 2018-01-21

Family

ID=60270746

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105114384A TWI612590B (en) 2016-05-10 2016-05-10 Electronic package and the manufacture thereof

Country Status (2)

Country Link
CN (1) CN107359141A (en)
TW (1) TWI612590B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111463176A (en) * 2019-01-22 2020-07-28 矽品精密工业股份有限公司 Electronic package and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201232735A (en) * 2011-01-27 2012-08-01 Unimicron Technology Corp Package stack device and method of forming same
TW201521164A (en) * 2013-11-29 2015-06-01 矽品精密工業股份有限公司 Package on package structure and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202585401U (en) * 2012-01-19 2012-12-05 日月光半导体制造股份有限公司 A semiconductor package structure
TWI581376B (en) * 2014-09-17 2017-05-01 矽品精密工業股份有限公司 Package structure and method of manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201232735A (en) * 2011-01-27 2012-08-01 Unimicron Technology Corp Package stack device and method of forming same
TW201521164A (en) * 2013-11-29 2015-06-01 矽品精密工業股份有限公司 Package on package structure and manufacturing method thereof

Also Published As

Publication number Publication date
CN107359141A (en) 2017-11-17
TW201740473A (en) 2017-11-16

Similar Documents

Publication Publication Date Title
TWI641087B (en) Electronic package and substrate for packaging use
TWI645527B (en) Electronic package and method for fabricating the same
US8269337B2 (en) Packaging substrate having through-holed interposer embedded therein and fabrication method thereof
TWI614848B (en) Electronic package and method of manufacture thereof
US10361150B2 (en) Substrate construction and electronic package including the same
TWI652787B (en) Electronic package and its manufacturing method
US9646921B2 (en) Semiconductor package and fabrication method thereof
TW201727852A (en) Substrate structure and method of manufacturing the same
TW201417235A (en) Package structure and fabrication method thereof
TW201812932A (en) Electronic package and method for fabricating the same
TWI694566B (en) Semiconductor package carrier board and manufacturing method thereof and electronic package
TWI669797B (en) Substrate electronic device and method of manufacturing electronic device
TWI550791B (en) Semiconductor package and manufacturing method thereof
TWI736859B (en) Electronic package and manufacturing method thereof
TWI691025B (en) Electronic package and manufacturing method thereof and carrier structure
TWI640068B (en) Electronic package and method of manufacture
TWI637465B (en) Electronic package and the manufacture thereof
TWI567888B (en) Package structure and method of manufacture
TWI733142B (en) Electronic package
TWI697081B (en) Semiconductor package substrate, and manufacturing method and electronic package thereof
TWI612590B (en) Electronic package and the manufacture thereof
TWI624011B (en) Package structure and the manufacture thereof
TWI548049B (en) Semiconductor structure and method of manufacture
US20230163082A1 (en) Electronic package and manufacturing method thereof
TWI573230B (en) Package structure and its package substrate