TWI611390B - Pixel circuit and display device thereof - Google Patents

Pixel circuit and display device thereof Download PDF

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TWI611390B
TWI611390B TW106106722A TW106106722A TWI611390B TW I611390 B TWI611390 B TW I611390B TW 106106722 A TW106106722 A TW 106106722A TW 106106722 A TW106106722 A TW 106106722A TW I611390 B TWI611390 B TW I611390B
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control signal
unit
switch
liquid crystal
control
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TW201833892A (en
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洪嘉澤
林雅婷
盧敏曜
徐明震
小澤德郎
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友達光電股份有限公司
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Abstract

一種畫素電路，其包括資料輸入單元、驅動控制單元、驅動單元、液晶電容控制單元、第一電容以及液晶電容。資料輸入單元用以接收顯示資料訊號並輸出顯示資料訊號至第一電容。驅動控制單元用以接收第一電壓準位並決定是否輸出第一電壓準位。驅動單元與第一電容以及驅動控制單元電性耦接，驅動單元用以輸出顯示電位。液晶電容與驅動單元以及共模電壓電性耦接，液晶電容用以接收顯示電位。液晶電容控制單元與液晶電容、第一開關單元以及第二開關單元電性耦接，液晶電容控制單元用以決定是否使液晶電容與第一開關單元以及第二開關單元彼此導通。A pixel circuit includes a data input unit, a driving control unit, a driving unit, a liquid crystal capacitor control unit, a first capacitor, and a liquid crystal capacitor. The data input unit is configured to receive the display data signal and output the display data signal to the first capacitor. The driving control unit is configured to receive the first voltage level and determine whether to output the first voltage level. The driving unit is electrically coupled to the first capacitor and the driving control unit, and the driving unit is configured to output a display potential. The liquid crystal capacitor is electrically coupled to the driving unit and the common mode voltage, and the liquid crystal capacitor is used to receive the display potential. The liquid crystal capacitor control unit is electrically coupled to the liquid crystal capacitor, the first switch unit and the second switch unit, and the liquid crystal capacitor control unit is configured to determine whether to make the liquid crystal capacitor and the first switch unit and the second switch unit electrically connected to each other.

Description

畫素電路及其顯示裝置Pixel circuit and display device thereof

本發明是有關於一種畫素電路，尤其是有關於一種應用於液晶顯示裝置之畫素電路及其顯示裝置。The present invention relates to a pixel circuit, and more particularly to a pixel circuit for a liquid crystal display device and a display device therefor.

當前之顯示裝置為了有更佳的顯示效果，紛紛提高顯示裝置的解析度以及畫面更新率，然由為了具有較高的畫面更新率，顯示裝置中的畫素單元開啟充電的時間縮短、充電頻率變高。而由於畫素單元之液晶電容在充電時所感受到之電場頻率高過特定頻率時，液晶電容之電容值會因為介電係數變小而減少，當液晶電容關閉回到穩態時，液晶電容所感受到之電場頻率降低，因此液晶電容之電容值會增加，而此時液晶電容會因為電荷守恆定理而導致液晶電容之電壓下降，進而造成顯示亮度損失，發生顯示畫面不均勻的情況。在習知的顯示裝置中常以儲存電容來補償液晶電容的亮度損失，然在操作頻率極高的藍相液晶(Blue Phase LC)顯示裝置、鐵電液晶(Ferroelectric LC)顯示裝置等顯示裝置中，為了有效補償液晶電容，其儲存電容需具有較大的儲存電荷量，進而需要佔據顯示裝置較大的硬體面積以及成本。In order to have a better display effect, the current display device has improved the resolution of the display device and the screen update rate, and in order to have a higher screen update rate, the time for turning on the charging of the pixel unit in the display device is shortened and the charging frequency is shortened. Becomes high. Since the liquid crystal capacitor of the pixel unit senses the electric field frequency higher than a certain frequency when charging, the capacitance value of the liquid crystal capacitor is reduced because the dielectric constant becomes smaller, and when the liquid crystal capacitor is turned back to the steady state, the liquid crystal capacitor feels The frequency of the electric field is reduced, so the capacitance of the liquid crystal capacitor will increase. At this time, the liquid crystal capacitor will decrease the voltage of the liquid crystal capacitor due to the conservation of the charge, thereby causing loss of display brightness and uneven display. In a conventional display device, the storage capacitor is often used to compensate for the luminance loss of the liquid crystal capacitor. However, in a display device such as a blue phase LC display device or a ferroelectric LC display device having an extremely high operating frequency, In order to effectively compensate the liquid crystal capacitor, the storage capacitor needs to have a large storage charge amount, and thus needs to occupy a large hardware area and cost of the display device.

為了解決上述之缺憾，本發明提出一種畫素電路實施例，此畫素電路實施例包括資料輸入單元、驅動控制單元、驅動單元、液晶電容控制單元、第一電容、液晶電容以及第二電容。資料輸入單元用以接收顯示資料訊號以及第一控制訊號，資料輸入單元並根據第一控制訊號決定是否輸出顯示資料訊號。第一電容具有第一端以及第二端，第一電容的第一端與資料輸入單元電性耦接，是用以接收上述的顯示資料訊號。驅動控制單元與第一電容的第二端電性耦接，驅動控制單元接收第一電壓準位以及第二控制訊號，驅動控制單元根據第二控制訊號決定是否輸出第一電壓準位。驅動單元與第一電容的第一端以及驅動控制單元電性耦接，驅動單元用以接收第一電壓準位並輸出顯示電位。液晶電容具有第一端以及第二端，液晶電容的第一端與驅動單元電性耦接，液晶電容的第二端與共模電壓電性耦接，液晶電容用以接收顯示電位。第二電容具有第一端以及第二端，第二電容的第一端與液晶電容的第一端電性偶接，第二電容的第二端與共模電壓電性耦接。液晶電容控制單元與液晶電容的第一端、第一開關單元以及第二開關單元電性耦接，液晶電容控制單元用以接收第三控制訊號並根據第三控制訊號決定是否使液晶電容與第一開關單元以及第二開關單元彼此導通。In order to solve the above drawbacks, the present invention provides a pixel circuit embodiment. The pixel circuit embodiment includes a data input unit, a driving control unit, a driving unit, a liquid crystal capacitor control unit, a first capacitor, a liquid crystal capacitor, and a second capacitor. The data input unit is configured to receive the display data signal and the first control signal, and the data input unit determines whether to output the display data signal according to the first control signal. The first capacitor has a first end and a second end. The first end of the first capacitor is electrically coupled to the data input unit for receiving the display data signal. The driving control unit is electrically coupled to the second end of the first capacitor, the driving control unit receives the first voltage level and the second control signal, and the driving control unit determines whether to output the first voltage level according to the second control signal. The driving unit is electrically coupled to the first end of the first capacitor and the driving control unit, and the driving unit is configured to receive the first voltage level and output the display potential. The liquid crystal capacitor has a first end and a second end. The first end of the liquid crystal capacitor is electrically coupled to the driving unit, and the second end of the liquid crystal capacitor is electrically coupled to the common mode voltage, and the liquid crystal capacitor is configured to receive the display potential. The second capacitor has a first end and a second end. The first end of the second capacitor is electrically coupled to the first end of the liquid crystal capacitor, and the second end of the second capacitor is electrically coupled to the common mode voltage. The liquid crystal capacitor control unit is electrically coupled to the first end of the liquid crystal capacitor, the first switch unit and the second switch unit, and the liquid crystal capacitor control unit is configured to receive the third control signal and determine whether to make the liquid crystal capacitor according to the third control signal A switching unit and a second switching unit are electrically connected to each other.

本發明更提出一種顯示裝置實施例，所述顯示裝置包括資料驅動器、多個畫素電路、多個第一開關單元以及多個第二開關單元。資料驅動器包括多個資料線，資料驅動器是用以輸出多個顯示資料訊號。每一畫素電路與其中之一資料線電性耦接，每一畫素電路包括資料輸入單元、驅動控制單元、驅動單元、液晶電容控制單元、第一電容、液晶電容以及第二電容。資料輸入單元用以接收顯示資料訊號以及第一控制訊號，資料輸入單元並根據第一控制訊號決定是否輸出顯示資料訊號。第一電容具有第一端以及第二端，第一電容的第一端與資料輸入單元電性耦接，是用以接收上述的顯示資料訊號。驅動控制單元與第一電容的第二端電性耦接，驅動控制單元接收第一電壓準位以及第二控制訊號，驅動控制單元根據第二控制訊號決定是否輸出第一電壓準位。驅動單元與第一電容的第一端以及驅動控制單元電性耦接，驅動單元用以接收第一電壓準位並輸出顯示電位。液晶電容具有第一端以及第二端，液晶電容的第一端與驅動單元電性耦接，液晶電容的第二端與共模電壓電性耦接，液晶電容用以接收顯示電位。第二電容具有第一端以及第二端，第二電容的第一端與液晶電容的第一端電性偶接，第二電容的第二端與共模電壓電性耦接。液晶電容控制單元與液晶電容的第一端、第一開關單元以及第二開關單元電性耦接，液晶電容控制單元用以接收第三控制訊號並根據第三控制訊號決定是否使液晶電容與第一開關單元以及第二開關單元彼此導通。第一開關單元與上述之液晶電容控制單元以及第二電壓準位電性耦接，第一開關單元接收第一開關控制訊號並根據第一開關控制訊號決定是否使液晶電容控制單元以及第二電壓準位彼此導通。第二開關單元與上述之液晶電容控制單元以及外部系統電性耦接，第二開關單元接收第二開關控制訊號並根據第二開關控制訊號決定是否使液晶電容控制單元以及外部系統彼此導通。其中，電性耦接同一資料線之多個畫素電路為同一行並與同一第一開關單元以及同一第二開關單元電性耦接。The present invention further provides an embodiment of a display device including a data driver, a plurality of pixel circuits, a plurality of first switching units, and a plurality of second switching units. The data driver includes a plurality of data lines, and the data driver is configured to output a plurality of display data signals. Each pixel circuit is electrically coupled to one of the data lines. Each pixel circuit includes a data input unit, a drive control unit, a driving unit, a liquid crystal capacitor control unit, a first capacitor, a liquid crystal capacitor, and a second capacitor. The data input unit is configured to receive the display data signal and the first control signal, and the data input unit determines whether to output the display data signal according to the first control signal. The first capacitor has a first end and a second end. The first end of the first capacitor is electrically coupled to the data input unit for receiving the display data signal. The driving control unit is electrically coupled to the second end of the first capacitor, the driving control unit receives the first voltage level and the second control signal, and the driving control unit determines whether to output the first voltage level according to the second control signal. The driving unit is electrically coupled to the first end of the first capacitor and the driving control unit, and the driving unit is configured to receive the first voltage level and output the display potential. The liquid crystal capacitor has a first end and a second end. The first end of the liquid crystal capacitor is electrically coupled to the driving unit, and the second end of the liquid crystal capacitor is electrically coupled to the common mode voltage, and the liquid crystal capacitor is configured to receive the display potential. The second capacitor has a first end and a second end. The first end of the second capacitor is electrically coupled to the first end of the liquid crystal capacitor, and the second end of the second capacitor is electrically coupled to the common mode voltage. The liquid crystal capacitor control unit is electrically coupled to the first end of the liquid crystal capacitor, the first switch unit and the second switch unit, and the liquid crystal capacitor control unit is configured to receive the third control signal and determine whether to make the liquid crystal capacitor according to the third control signal A switching unit and a second switching unit are electrically connected to each other. The first switch unit is electrically coupled to the liquid crystal capacitor control unit and the second voltage level, and the first switch unit receives the first switch control signal and determines whether to make the liquid crystal capacitor control unit and the second voltage according to the first switch control signal The standards are conductive to each other. The second switch unit is electrically coupled to the liquid crystal capacitor control unit and the external system, and the second switch unit receives the second switch control signal and determines whether to make the liquid crystal capacitor control unit and the external system conductive to each other according to the second switch control signal. The plurality of pixel circuits electrically coupled to the same data line are in the same row and are electrically coupled to the same first switching unit and the same second switching unit.

綜以上所述，由於本發明之液晶電容並非直接根據當級之閘極控制訊號充電，因此不會因為高畫面更新率而導致液晶電容需操作於高頻率下，顯示裝置進而不需高容量之儲存電容來輔助液晶電容維持穩定的電壓值，有效減少硬體面積以及製造成本的消耗。此外，藉由驅動控制單元控制驅動單元的操作時間，可有效減緩次臨界電流對於顯示電位的影響，且由於液晶材料為電壓驅動元件，藉由第二開關單元直接讀取液晶電容的電壓值變化，更可精準的偵測出驅動單元的電性變化，使顯示裝置可據以調整對應的顯示電位，有效改善顯示裝置的顯示效果不均勻的情況，使用者可因此享有更佳的顯示裝置觀賞體驗，增加顯示裝置於經濟上的效益。In summary, since the liquid crystal capacitor of the present invention is not directly charged according to the gate control signal of the current stage, the liquid crystal capacitor does not need to be operated at a high frequency due to the high picture update rate, and the display device does not need high capacity. The storage capacitor is used to assist the liquid crystal capacitor to maintain a stable voltage value, which effectively reduces the hardware area and the manufacturing cost. In addition, by controlling the operation time of the driving unit by the driving control unit, the influence of the sub-critical current on the display potential can be effectively slowed down, and since the liquid crystal material is a voltage driving element, the voltage value of the liquid crystal capacitor is directly read by the second switching unit. Moreover, the electrical change of the driving unit can be accurately detected, so that the display device can adjust the corresponding display potential, thereby effectively improving the display effect of the display device, and the user can enjoy better display device viewing. Experience, increase the economic benefits of display devices.

為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例並配合所附圖式做詳細說明如下。The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims.

請參閱圖1，圖1為本發明之顯示裝置10實施例，顯示裝置10包括時序控制器11、資料驅動器12、閘極驅動器13、外部系統14以及多個畫素電路15，資料驅動器12透過多個資料線121與畫素電路15電性耦接，閘極驅動器13透過多個閘極線131與畫素電路15電性耦接，顯示裝置10用以透過時序控制器11將多個顯示資料訊號V DATA傳送給資料驅動器12，時序控制器11並控制閘極驅動器13在正確的時間輸出閘極控制訊號，以驅動電性耦接之多個畫素電路15，被驅動的畫素電路15可藉由電性耦接的資料線121接收顯示資料訊號V DATA。其中，在圖1實施例中，電性耦接同一資料線121的多個畫素電路15為同一行，如圖1中虛線框所包含之多個畫素電路15，且同一行的畫素電路15電性耦接至同一偵測線161並藉由同一偵測線161電性耦接至同一個第一開關單元16以及同一個第二開關單元17，但不以此為限。第二開關單元17更與前述之外部系統14電性耦接，所述外部系統14是用以偵測每一畫素電路15之電性特性，並將偵測結果傳送至時序控制器11，使時序控制器11可根據偵測結果調整顯示資料訊號V DATA，使畫素電路15根據顯示資料訊號V DATA正確顯示。 Please refer to FIG. 1. FIG. 1 is an embodiment of a display device 10 of the present invention. The display device 10 includes a timing controller 11, a data driver 12, a gate driver 13, an external system 14, and a plurality of pixel circuits 15. The data driver 12 transmits The plurality of data lines 121 are electrically coupled to the pixel circuit 15. The gate driver 13 is electrically coupled to the pixel circuit 15 through the plurality of gate lines 131. The display device 10 is configured to display the plurality of displays through the timing controller 11. The data signal V DATA is transmitted to the data driver 12, and the timing controller 11 controls the gate driver 13 to output the gate control signal at the correct time to drive the plurality of pixel circuits 15 electrically coupled, the driven pixel circuit. The display data signal V DATA can be received by the electrically coupled data line 121. In the embodiment of FIG. 1, the plurality of pixel circuits 15 electrically coupled to the same data line 121 are in the same row, such as the plurality of pixel circuits 15 included in the broken line frame in FIG. The circuit 15 is electrically coupled to the same detection line 161 and is electrically coupled to the same first switching unit 16 and the same second switching unit 17 by the same detection line 161, but is not limited thereto. The second switch unit 17 is further electrically coupled to the external system 14 . The external system 14 is configured to detect the electrical characteristics of each pixel circuit 15 and transmit the detection result to the timing controller 11 . The timing controller 11 can adjust the display data signal V DATA according to the detection result, so that the pixel circuit 15 displays correctly according to the display data signal V DATA .

請參考圖2，圖2為本發明之畫素電路15實施例示意圖，畫素電路15包括資料輸入單元151、驅動控制單元152、驅動單元153、液晶電容控制單元154、第一電容C S1、液晶電容C LC以及第二電容C S2。資料輸入單元151用以接收上述之顯示資料訊號V DATA以及第一控制訊號G1，資料輸入單元151是用以根據第一控制訊號G1決定是否輸出顯示資料訊號V DATA。第一電容C S1具有第一端以及第二端，第一電容C S1的第一端與資料輸入單元151電性耦接並用以接收資料輸入單元151輸出的顯示資料訊號V DATA，第一電容C S1的第二端用以接收第一電壓準位V DD。驅動控制單元152與第一電容C S1的第二端電性耦接，驅動控制單元152接收上述第一電壓準位V DD以及第二控制訊號G2，驅動控制單元152用以根據第二控制訊號G2決定是否輸出第一電壓準位V DD。驅動單元153與第一電容C S1的第一端以及驅動控制單元152電性耦接，驅動單元153用以接收顯示資料訊號V DATA、驅動控制單元152輸出的第一電壓準位V DD並輸出顯示電位V D。液晶電容C LC具有第一端以及第二端，液晶電容C LC的第一端與驅動單元153電性耦接，液晶電容C LC的第二端與共模電壓V COM電性耦接，液晶電容C LC用以接收顯示電位V D，使畫素電路15可根據顯示電位V D進行顯示。第二電容C S2具有第一端以及第二端，第二電容C S2的第一端與液晶電容C LC的第一端電性偶接，第二電容C S2的第二端與共模電壓V COM電性耦接。液晶電容控制單元154與液晶電容C LC的第一端電性耦接，液晶電容控制單元154用以接收第三控制訊號G3並根據第三控制訊號G3決定是否使液晶電容C LC透過偵測線161與上述之第一開關單元16以及第二開關單元17導通。 Please refer to FIG. 2. FIG. 2 is a schematic diagram of an embodiment of a pixel circuit 15 of the present invention. The pixel circuit 15 includes a data input unit 151, a driving control unit 152, a driving unit 153, a liquid crystal capacitor control unit 154, and a first capacitor C S1 . The liquid crystal capacitor C LC and the second capacitor C S2 . The data input unit 151 is configured to receive the display data signal V DATA and the first control signal G1. The data input unit 151 is configured to determine whether to output the display data signal V DATA according to the first control signal G1. The first capacitor C S1 has a first end and a second end. The first end of the first capacitor C S1 is electrically coupled to the data input unit 151 and configured to receive the display data signal V DATA output by the data input unit 151 . The second end of C S1 is for receiving the first voltage level V DD . The driving control unit 152 is electrically coupled to the second end of the first capacitor C S1 , and the driving control unit 152 receives the first voltage level V DD and the second control signal G2 , and the driving control unit 152 is configured to use the second control signal according to the second control signal G2 determines whether to output the first voltage level V DD . The driving unit 153 is electrically coupled to the first end of the first capacitor C S1 and the driving control unit 152. The driving unit 153 is configured to receive the display voltage signal V DATA , the first voltage level V DD outputted by the driving control unit 152, and output The potential V D is displayed. The liquid crystal capacitance C LC having a first end and a second end, the first end of the drive unit 153 of the liquid crystal capacitance C LC is electrically coupled to the second terminal of the common mode voltage V COM of the liquid crystal capacitance C LC is electrically coupled to the liquid crystal The capacitor C LC is used to receive the display potential V D so that the pixel circuit 15 can display according to the display potential V D . The second capacitor C S2 having a first end and a second end, a second end of the capacitor C S2 of the first liquid crystal capacitor C LC electrically coupling a first terminal connected to the second terminal of the second common mode voltage of the capacitor C S2 V COM is electrically coupled. The liquid crystal capacitor control unit 154 is electrically coupled to the first end of the liquid crystal capacitor C LC . The liquid crystal capacitor control unit 154 is configured to receive the third control signal G3 and determine whether to pass the liquid crystal capacitor C LC through the detection line according to the third control signal G3. The 161 is electrically connected to the first switching unit 16 and the second switching unit 17 described above.

所述資料輸入單元151更包括電晶體T1，電晶體T1具有第一端、第二端以及控制端，電晶體T1的第一端與圖1所述的其中之一資料線121電性耦接並接收顯示資料訊號V DATA，電晶體T1的控制端接收第一控制訊號G1，第一控制訊號G1例如為上述之閘極控制訊號，電晶體T1的第二端與第一電容C S1的第一端電性耦接。驅動控制單元152更包括電晶體T2，電晶體T2具有第一端、第二端以及控制端，電晶體T2的第一端接收第一電壓準位V DD，電晶體T2的控制端接收第二控制訊號G2，電晶體T2的第二端與驅動單元153電性耦接。驅動單元153更包括電晶體T3，電晶體T3具有第一端、第二端以及控制端，電晶體T3的第一端與驅動控制單元152的電晶體T2的第二端電性耦接，電晶體T3的控制端與第一電容C S1的第一端電性耦接，電晶體T3的第二端用以輸出顯示電位V D並與液晶電容C LC的第一端電性耦接。液晶電容控制單元154更包括電晶體T4，電晶體T4具有第一端、第二端以及控制端，電晶體T4的第一端與液晶電容C LC的第一端電性耦接，電晶體T4的控制端接收第三控制訊號G3，電晶體T4的第二端與第一開關單元16以及第二開關單元17電性耦接。 The data input unit 151 further includes a transistor T1 having a first end, a second end, and a control end. The first end of the transistor T1 is electrically coupled to one of the data lines 121 of FIG. And receiving the display data signal V DATA , the control end of the transistor T1 receives the first control signal G1, the first control signal G1 is, for example, the above-mentioned gate control signal, the second end of the transistor T1 and the first capacitor C S1 One end is electrically coupled. The driving control unit 152 further includes a transistor T2 having a first end, a second end, and a control end, the first end of the transistor T2 receiving the first voltage level V DD , and the control end of the transistor T2 receiving the second end The control signal G2, the second end of the transistor T2 is electrically coupled to the driving unit 153. The driving unit 153 further includes a transistor T3 having a first end, a second end, and a control end. The first end of the transistor T3 is electrically coupled to the second end of the transistor T2 of the driving control unit 152. The control terminal of the crystal T3 is electrically coupled to the first end of the first capacitor C S1 , and the second end of the transistor T3 is configured to output the display potential V D and is electrically coupled to the first end of the liquid crystal capacitor C LC . The liquid crystal capacitor control unit 154 further includes a transistor T4 having a first end, a second end, and a control end. The first end of the transistor T4 is electrically coupled to the first end of the liquid crystal capacitor C LC , and the transistor T4 The control terminal receives the third control signal G3, and the second end of the transistor T4 is electrically coupled to the first switch unit 16 and the second switch unit 17.

在本實施例中，第一開關單元16包括電晶體T5，電晶體T5具有第一端、第二端以及控制端，電晶體T5的第一端與上述之電晶體T4的第二端電性耦接，電晶體T5的第二端與第二電壓準位V SS電性耦接，電晶體T5的控制端接收第一開關控制訊號S1，電晶體T5是用以根據第一開關控制訊號S1決定是否使電晶體T4的第二端與第二電壓準位V SS導通。在本實施例中，第二開關單元17包括電晶體T6，電晶體T6具有第一端、第二端以及控制端，電晶體T6的第一端與電晶體T4的第二端電性耦接，電晶體T6的第二端與上述之外部系統14電性耦接，電晶體T6的控制端接收第二開關控制訊號S2，電晶體T6是用以根據第二開關控制訊號S2決定是否使電晶體T4的第二端與外部系統14導通。 In this embodiment, the first switching unit 16 includes a transistor T5 having a first end, a second end, and a control end, and the first end of the transistor T5 and the second end of the transistor T4 are electrically connected. The second end of the transistor T5 is electrically coupled to the second voltage level V SS , the control end of the transistor T5 receives the first switch control signal S1 , and the transistor T5 is used to control the signal S1 according to the first switch It is determined whether the second end of the transistor T4 is turned on with the second voltage level V SS . In this embodiment, the second switch unit 17 includes a transistor T6 having a first end, a second end, and a control end. The first end of the transistor T6 is electrically coupled to the second end of the transistor T4. The second end of the transistor T6 is electrically coupled to the external system 14 , and the control end of the transistor T6 receives the second switch control signal S2. The transistor T6 is configured to determine whether to enable the power according to the second switch control signal S2. The second end of the crystal T4 is electrically connected to the external system 14.

以下將進一步說明本發明之畫素電路15以及顯示裝置10之操作方法。請先參考圖3，圖3為本發明之畫素電路15以及顯示裝置10實施例操作於顯示模式的時序實施例示意圖，所述顯示模式為畫素電路15接收上述之顯示資料訊號V DATA並據以顯示的模式。圖3包括了第一控制訊號G1、第二控制訊號G2、第三控制訊號G3、第一開關控制訊號S1以及第二開關控制訊號S2，圖3並以接收第n級第一控制訊號G1[n]、第n級第二控制訊號G2[n]、第n級第三控制訊號G3[n]為例。請同時參閱圖2以及圖3，在圖3時段Ta時，第n級第一控制訊號G1[n]、第n級第二控制訊號G2[n]以及第二開關控制訊號S2為禁能準位，第一開關控制訊號S1以及第n級第三控制訊號G3[n]為致能準位，在本實施例中，禁能準位例如為邏輯低電位，致能準位例如為邏輯高電位，但不以此為限。因此在時段Ta時接收第n級第一控制訊號G1[n]的資料輸入單元151、接收第n級第二控制訊號G2[n]的驅動控制單元152、接收第二開關控制訊號S2的第二開關單元17為禁能，接收第n級第三控制訊號G3[n]的液晶電容控制單元154以及接收第一開關控制訊號S1的第一開關單元16為致能，液晶電容C LC的第一端因此被重置為第二電壓準位V SS。在圖3時段Tb時，第n級第一控制訊號G1[n]為致能準位，第n級第二控制訊號G2[n]、第n級第三控制訊號G3[n]、第一開關控制訊號S1以及第二開關控制訊號S2為禁能準位，因此接收第n級第一控制訊號G1[n]的資料輸入單元151為致能，接收第n級第二控制訊號G2[n]的驅動控制單元152、接收第n級第三控制訊號G3[n]的液晶電容控制單元154、接收第一開關控制訊號S1的第一開關單元16以及接收第二開關控制訊號S2的第二開關單元17為禁能，因此資料輸入單元151接收顯示資料訊號V DATA並將顯示資料訊號V DATA傳送至第一電容C S1的第一端。在圖3時段Tc時，第n級第二控制訊號G2[n]為致能準位，第n級第一控制訊號G1[n]、第n級第三控制訊號G3[n]、第一開關控制訊號S1以及第二開關控制訊號S2為禁能準位，接收第n級第二控制訊號G2[n]的驅動控制單元152為致能，接收第n級第一控制訊號G1[n]的資料輸入單元151、接收第n級第三控制訊號G3[n]的液晶電容控制單元154、接收第一開關控制訊號S1的第一開關單元16以及接收第二開關控制訊號S2的第二開關單元17為禁能。此時驅動單元153操作於飽和區，根據資料訊號V DATA對於液晶電容C LC充電，以於驅動單元153的電晶體T3的第二端產生顯示電位V D，顯示電位V D同時儲存至液晶電容C LC，顯示電位V D進而可以控制的液晶電容C LC液晶狀態，因此畫素電路15將可根據顯示電位V D進行顯示，其中，顯示電位V D的電壓值等於資料訊號V DATA扣除電晶體T3的臨界電壓V TH的電壓值。 The pixel circuit 15 of the present invention and the method of operating the display device 10 will be further described below. Please refer to FIG. 3, which is a schematic diagram of a timing embodiment of the pixel circuit 15 and the display device 10 of the present invention operating in a display mode. The display mode is that the pixel circuit 15 receives the display data signal V DATA and According to the mode shown. 3 includes a first control signal G1, a second control signal G2, a third control signal G3, a first switch control signal S1, and a second switch control signal S2, and FIG. 3 receives the nth stage first control signal G1 [ n], the nth second control signal G2[n], and the nth third control signal G3[n] are taken as an example. Please refer to FIG. 2 and FIG. 3 simultaneously. In the time period Ta of FIG. 3, the nth first control signal G1[n], the nth second control signal G2[n], and the second switch control signal S2 are disabled. The first switch control signal S1 and the nth third control signal G3[n] are the enable levels. In this embodiment, the disable level is, for example, a logic low level, and the enable level is, for example, a logic high. Potential, but not limited to this. Therefore, the data input unit 151 that receives the nth stage first control signal G1[n], the drive control unit 152 that receives the nth second control signal G2[n], and the second switch control signal S2 are received during the time period Ta. The second switch unit 17 is disabled, and the liquid crystal capacitor control unit 154 that receives the nth third control signal G3[n] and the first switch unit 16 that receives the first switch control signal S1 are enabled, and the liquid crystal capacitor C LC One end is thus reset to the second voltage level Vss . In the period Tb of FIG. 3, the nth first control signal G1[n] is an enable level, the nth second control signal G2[n], the nth third control signal G3[n], the first The switch control signal S1 and the second switch control signal S2 are disabled. Therefore, the data input unit 151 receiving the nth first control signal G1[n] is enabled, and receives the nth second control signal G2[n a drive control unit 152, a liquid crystal capacitance control unit 154 that receives the nth stage third control signal G3[n], a first switch unit 16 that receives the first switch control signal S1, and a second that receives the second switch control signal S2. The switch unit 17 is disabled, so the data input unit 151 receives the display data signal V DATA and transmits the display data signal V DATA to the first end of the first capacitor C S1 . In the period Tc of FIG. 3, the nth second control signal G2[n] is an enable level, the nth first control signal G1[n], the nth third control signal G3[n], the first The switch control signal S1 and the second switch control signal S2 are disabled, and the drive control unit 152 receiving the nth second control signal G2[n] is enabled to receive the nth first control signal G1[n] The data input unit 151, the liquid crystal capacitor control unit 154 receiving the nth third control signal G3[n], the first switch unit 16 receiving the first switch control signal S1, and the second switch receiving the second switch control signal S2 Unit 17 is disabled. At this time, the driving unit 153 operates in the saturation region, and charges the liquid crystal capacitor C LC according to the data signal V DATA , so that the second end of the transistor T3 of the driving unit 153 generates the display potential V D , and the display potential V D is simultaneously stored to the liquid crystal capacitor. C LC , showing the potential V D and thus the liquid crystal capacitance C LC liquid crystal state, so that the pixel circuit 15 can be displayed according to the display potential V D , wherein the voltage value of the display potential V D is equal to the data signal V DATA subtraction transistor The voltage value of the threshold voltage V TH of T3.

圖4為本發明之畫素電路15以及顯示裝置10實施例操作於感測模式的時序實施例示意圖，感測模式可操作於顯示裝置10電源被致能或被禁能的時段，或者於空白時間 (blanking time)執行，即畫素電路15不進行更新的時段，但不以此為限。在此模式中，顯示裝置10將用以感測畫素電路15的顯示電位V D，以根據驅動單元153的畫素的元件特性(例如電晶體的臨界電壓V TH)調整用以顯示的顯示資料訊號V DATA，使畫素電路15可配合臨界電壓V TH顯示正確的顯示畫面。圖4並以同一行不同列的畫素電路15所接收的訊號時序為例，圖4包括第n列畫素電路15所接收的第n級第一控制訊號G1[n]、第n級第三控制訊號G3[n]、第n+1列畫素電路15所接收的第n+1級第一控制訊號G1[n+1]、第n+1級第三控制訊號G3[n+1]、第二控制訊號G2、第一開關控制訊號S1以及第二開關控制訊號S2，其中，在此實施例中，同一行且不同列之多個畫素電路15接收同一個第二控制訊號G2、第一開關控制訊號S1以及第二開關控制訊號S2。以下將同時配合圖1、圖2以及圖4進一步說明。 4 is a schematic diagram of a timing embodiment of the pixel circuit 15 and the display device 10 of the present invention operating in a sensing mode, the sensing mode being operable during a period in which the power of the display device 10 is enabled or disabled, or blank The blanking time is executed, that is, the period in which the pixel circuit 15 is not updated, but is not limited thereto. In this mode, the display device 10 will sense the display potential V D of the pixel circuit 15 to adjust the display for display according to the element characteristics of the pixels of the driving unit 153 (for example, the threshold voltage V TH of the transistor). The data signal V DATA enables the pixel circuit 15 to display the correct display picture in conjunction with the threshold voltage V TH . 4 is an example of a signal sequence received by a pixel circuit 15 of a different row in the same row. FIG. 4 includes an nth-level first control signal G1[n] and an n-th stage received by the n-th column pixel circuit 15. The n+1th first control signal G1[n+1] received by the third control signal G3[n], the n+1th column pixel circuit 15, and the n+1th third control signal G3[n+1 The second control signal G2, the first switch control signal S1, and the second switch control signal S2, wherein, in this embodiment, the plurality of pixel circuits 15 of the same row and different columns receive the same second control signal G2. The first switch control signal S1 and the second switch control signal S2. The following will be further described in conjunction with FIG. 1, FIG. 2 and FIG.

如圖4所示，感測模式包括重置時段T R以及感測時段T S，重置時段T R包括了時段Ta以及時段Tb。在時段Ta，第一開關控制訊號S1為致能準位，第二開關控制訊號S2、第二控制訊號G2、第n級第一控制訊號G1[n]、以及第n+1級第一控制訊號G1[n+1]為禁能準位，第n級第三控制訊號G3[n]以及第n+1級第三控制訊號G3[n+1] 同時為致能準位，也就是不同列但同一行的畫素電路15所接收的第三控制訊號G3同時為致能準位。因此在每一畫素單元15中，接收第一開關控制訊號S1的第一開關單元16為致能，接收第二開關控制訊號S2的第二開關單元17為禁能，接收第三控制訊號G3的液晶電容控制單元154為致能，接收第二控制訊號G2的驅動控制單元152為禁能，因此同一行的每一畫素電路15的液晶電容C LC的第一端因此被重置為第二電壓準位V SS。在時間Tb時，第一開關控制訊號S1維持致能準位，第二開關控制訊號S2維持禁能準位，第二控制訊號G2為禁能準位，第n級第三控制訊號G3[n]以及第n+1級第三控制訊號G3[n+1] 同時為禁能準位，同一行的畫素電路15所接收的第一控制訊號G1依序為致能準位。如圖4所示，第n級第一控制訊號G1[n]由致能準位轉換為禁能準位後，第n+1級第一控制訊號G1[n+1]才由禁能準位轉換為致能準位，也就是每一畫素電路15的資料輸入單元151依序因為第一控制訊號G1而被致能，每一畫素電路15所對應的顯示資料訊號V DATA依序藉由資料輸入單元151傳送至第一電容C s1的第一端。因此，在重置時段T R，第三控制訊號G3的致能期間短於第一開關控制訊號S1的致能期間，第一控制訊號G1的致能期間短於第三控制訊號G3的致能期間，第一控制訊號G1的致能起始時間晚於第三控制訊號G3的致能起始時間，同一行不同列的畫素電路15所接收的第一控制訊號G1彼此致能期間不重疊。 As shown, the sensing mode includes a reset period T R and a sensing period T S 4, comprising a reset period T R period Ta and the period Tb. In the time period Ta, the first switch control signal S1 is an enable level, the second switch control signal S2, the second control signal G2, the nth first control signal G1[n], and the n+1th first control The signal G1[n+1] is the disable level, the nth third control signal G3[n] and the n+1th third control signal G3[n+1] are simultaneously enabling levels, that is, different The third control signal G3 received by the pixel circuit 15 of the same row is simultaneously enabled. Therefore, in each pixel unit 15, the first switch unit 16 that receives the first switch control signal S1 is enabled, and the second switch unit 17 that receives the second switch control signal S2 is disabled, and receives the third control signal G3. The liquid crystal capacitor control unit 154 is enabled, and the driving control unit 152 receiving the second control signal G2 is disabled. Therefore, the first end of the liquid crystal capacitor C LC of each pixel circuit 15 of the same row is thus reset to the first Two voltage levels V SS . At time Tb, the first switch control signal S1 maintains the enable level, the second switch control signal S2 maintains the disable level, the second control signal G2 is the disable level, and the nth third control signal G3[n And the n+1th third control signal G3[n+1] is simultaneously disabled, and the first control signal G1 received by the pixel circuit 15 of the same row is sequentially enabled. As shown in FIG. 4, after the nth stage first control signal G1[n] is converted from the enable level to the disable level, the n+1th first control signal G1[n+1] is disabled. The bits are converted to the enable level, that is, the data input unit 151 of each pixel circuit 15 is sequentially enabled by the first control signal G1, and the display data signal V DATA corresponding to each pixel circuit 15 is sequentially The data is input to the first end of the first capacitor C s1 by the data input unit 151. Therefore, during the reset period T R , the enabling period of the third control signal G3 is shorter than the enabling period of the first switching control signal S1, the enabling period of the first control signal G1 is shorter than the enabling of the third control signal G3. During the period, the enabling start time of the first control signal G1 is later than the enabling start time of the third control signal G3, and the first control signals G1 received by the pixel circuits 15 of different columns in the same row do not overlap each other during the enabling period. .

接著在感測時段T S，第一開關控制訊號S1的致能準位以及禁能準位彼此交錯切換，第一開關控制訊號S1的致能期間短於禁能期間，第二開關控制訊號S2為致能準位，第二控制訊號G2為致能準位，第二控制訊號G2的致能期間與第二開關控制訊號S2的致能期間相同。第三控制訊號G3循序為致能準位，如圖4所示，在感測時段T S，第n級第三控制訊號G3 [n]由致能準位轉換為禁能準位後，第n+1級第三控制訊號G3 [n+1]才由禁能準位轉換為致能準位，且每一第三控制訊號G3的致能期間對應於第一開關控制訊號S1的禁能期間，也就是第三控制訊號G3為致能準位時第一開關控制訊號S1為禁能準位。因此在感測時段T S，藉由第一開關控制訊號S1為致能準位，清除耦接至第一開關單元16以及第二開關單元17的走線上的殘存電壓值，同時因為第二控制訊號G2為致能準位，每一列畫素電路15的顯示電位V D因此依序根據顯示資料訊號V DATA被寫入至液晶電容C LC。當第一開關控制訊號S1為禁能準位且當級第三控制訊號G3為致能準位時，例如圖4中第n級第三控制訊號G3[n]為致能準位，液晶電容C LC所儲存的顯示電位V D將藉由開啟的第二開關單元17而輸出至外部系統14，完成感測模式。在此實施例中，由於外部系統14所接收的顯示電位V D為每一畫素電路15所接收的顯示資料訊號V DATA扣除每一畫素電路15之驅動單元153所對應之臨界電壓V TH的電壓值，在顯示資料訊號V DATA已知的情況下，外部系統14即可根據顯示電位V D輕易偵測並判定當前畫素電路15對應之臨界電壓V TH的變化，外部系統14並將臨界電壓V TH的偵測結果提供至時序控制器11，時序控制器11進而可根據偵測結果調整輸入至畫素電路15的顯示資料訊號V DATA。亦或者是各畫素或者是顯示面板中對於顯示電壓的影響，亦可能透過此機制進行估測，進而調整顯示資料訊號V DATA來補償畫素之間的亮度特性。 Then, during the sensing period T S , the enable level of the first switch control signal S1 and the disable level are alternately switched, and the enable period of the first switch control signal S1 is shorter than the disable period, and the second switch control signal S2 To enable the level, the second control signal G2 is the enable level, and the enable period of the second control signal G2 is the same as the enable period of the second switch control signal S2. The third control signal G3 is sequentially enabled, as shown in FIG. 4, after the sensing period T S , the nth third control signal G3 [n] is converted from the enabling level to the inactive level, The n+1 level third control signal G3 [n+1] is converted from the disable level to the enable level, and the enable period of each third control signal G3 corresponds to the disable of the first switch control signal S1. During the period, that is, when the third control signal G3 is the enable level, the first switch control signal S1 is the disable level. Therefore, during the sensing period T S , the residual voltage value of the trace coupled to the first switching unit 16 and the second switching unit 17 is cleared by the first switch control signal S1 being the enable level, and because the second control is The signal G2 is enabled, and the display potential V D of each column of the pixel circuit 15 is sequentially written to the liquid crystal capacitor C LC according to the display data signal V DATA . When the first switch control signal S1 is the disable level and the third control signal G3 is the enable level, for example, the nth third control signal G3[n] in FIG. 4 is the enable level, the liquid crystal capacitor The display potential V D stored by the C LC will be output to the external system 14 by the turned-on second switching unit 17, completing the sensing mode. In this embodiment, the display potential V D received by the external system 14 is subtracted from the display voltage signal V DATA received by each pixel circuit 15 by the threshold voltage V TH corresponding to the driving unit 153 of each pixel circuit 15 . The voltage value, when the display data signal V DATA is known, the external system 14 can easily detect and determine the change of the threshold voltage V TH corresponding to the current pixel circuit 15 according to the display potential V D , and the external system 14 The detection result of the threshold voltage V TH is supplied to the timing controller 11, and the timing controller 11 can further adjust the display data signal V DATA input to the pixel circuit 15 according to the detection result. Or it is the influence of each pixel or the display panel on the display voltage. It is also possible to estimate through this mechanism, and then adjust the display data signal V DATA to compensate the brightness characteristics between the pixels.

接著請參考圖5，圖5為本發明之畫素電路15以及顯示裝置10實施例操作於上述感測模式的時序實施例二示意圖，圖5實施例與圖4的差別在於，在圖5的感測時段T S中，同一行的不同列畫素電路15所接收的第二控制訊號G2為循序致能，如圖5所示，第n級第二控制訊號G2[n]由致能準位轉換為禁能準位後，第n+1級第二控制訊號G2[n+1]才由禁能準位轉換為致能準位，且在此實施例中，第n級第二控制訊號G2[n]的致能期間與第n級第三控制訊號G3[n]相同，第n+1級第二控制訊號G2[n+1]的致能期間與第n+1級第三控制訊號G3[n+1]相同，因此在接收第三控制訊號G3的液晶電容控制單元154被第三控制訊號G3致能時，接收第二控制訊號G2的驅動控制單元152同時被第二控制訊號G2致能時，顯示電位V D可透過致能的液晶電容控制單元154以及第二開關單元17而輸出到外部系統14。在此實施例中，接收第二控制訊號G2的驅動控制單元152不用長時間保持開啟，有效減少功率消耗並延長元件使用壽命。 Please refer to FIG. 5. FIG. 5 is a schematic diagram of a timing embodiment of the pixel circuit 15 and the display device 10 of the present invention operating in the sensing mode. The difference between the embodiment of FIG. 5 and FIG. 4 lies in FIG. In the sensing period T S , the second control signal G2 received by the different column pixel circuits 15 in the same row is sequentially enabled. As shown in FIG. 5 , the nth second control signal G2[n] is enabled. After the bit is converted to the disable level, the n+1th second control signal G2[n+1] is converted from the disable level to the enable level, and in this embodiment, the nth level second control The enable period of the signal G2[n] is the same as the nth third control signal G3[n], the enabling period of the n+1th second control signal G2[n+1] and the third n+1th third The control signal G3[n+1] is the same. Therefore, when the liquid crystal capacitance control unit 154 receiving the third control signal G3 is enabled by the third control signal G3, the drive control unit 152 receiving the second control signal G2 is simultaneously controlled by the second control. When the signal G2 is enabled, the display potential V D can be output to the external system 14 through the enabled liquid crystal capacitance control unit 154 and the second switching unit 17. In this embodiment, the drive control unit 152 that receives the second control signal G2 does not need to remain on for a long time, effectively reducing power consumption and extending component life.

接著請參閱圖6，圖6為本發明之畫素電路15以及顯示裝置10實施例操作於感測模式的時序實施例三示意圖，以下並同時配合圖2以單一畫素單元15為例進行說明，其中圖6並以接收第n級第一控制訊號G1[n]、第n級第二控制訊號G2[n]、第n級第三控制訊號G3[n]之第n級畫素電路15為例。如圖6所示，感測模式包括重置時段T R以及感測時段T S，在重置時段T R的時點T 1到時點T 5之間，第二開關控制訊號S2以及第n級第二控制訊號G2[n]為禁能準位，第一開關控制訊號S1為致能準位。因此在重置時段T R，接收第一開關控制訊號S1的第一開關單元16為致能，接收第二開關控制訊號S2的第二開關單元17為禁能，接收第n級第二控制訊號G2[n]的驅動控制單元152為禁能。在重置時段T R的時點T 2到時點T 3之間，第n級第一控制訊號G1[n]為禁能準位，第n級第三控制訊號G3[n]為致能準位，因此接收第n級第三控制訊號G3[n]的液晶電容控制單元154為致能，接收第一開關控制訊號S1的第一開關單元16為致能，液晶電容CLC的第一端被重置為第二電壓準位V SS。在重置時段T R的時點T 4到時點T 5之間，第n級第三控制訊號G3[n]為禁能準位，第n級第一控制訊號G1[n]為致能準位，因此在時點T 4到時點T 5時，接收第n級第一控制訊號G1[n]的資料輸入單元151為致能，顯示資料訊號V DATA因此傳送到第一電容C S1的第一端以及驅動單元153的控制端。在重置時段T R，第n級第一控制訊號G1[n]以及第n級第三控制訊號G3[n]的致能期間短於第一開關控制訊號S1的致能期間，第一開關控制訊號S1的致能起始時間早於第n級第一控制訊號G1[n]以及第n級第三控制訊號G3[n]的致能起始時間，第一開關控制訊號S1的致能結束時間晚於第n級第三控制訊號G3[n]的致能結束時間，第一開關控制訊號S1的致能結束時間與第n級第一控制訊號G1[n]的致能結束時間相同，但不以此為限。 Please refer to FIG. 6. FIG. 6 is a schematic diagram of a third embodiment of the pixel circuit 15 and the display device 10 according to the embodiment of the present invention. The following is a description of the single pixel unit 15 as an example. In FIG. 6 , the nth pixel circuit 15 receives the nth first control signal G1[n], the nth second control signal G2[n], and the nth third control signal G3[n]. For example. As shown in FIG. 6, the sensing mode includes a reset period T R and a sensing period T S between the time point T 1 and the time point T 5 of the reset period T R , the second switch control signal S2 and the nth stage The second control signal G2[n] is a disable level, and the first switch control signal S1 is an enable level. Therefore, during the reset period T R , the first switch unit 16 that receives the first switch control signal S1 is enabled, and the second switch unit 17 that receives the second switch control signal S2 is disabled, and receives the nth second control signal. The drive control unit 152 of G2[n] is disabled. Between the time point T 2 and the time point T 3 of the reset period T R , the nth stage first control signal G1[n] is the disable level, and the nth stage third control signal G3[n] is the enable level. Therefore, the liquid crystal capacitor control unit 154 receiving the nth third control signal G3[n] is enabled, and the first switch unit 16 receiving the first switch control signal S1 is enabled, and the first end of the liquid crystal capacitor CLC is heavy. Set to the second voltage level V SS . Between the time point T 4 and the time point T 5 of the reset period T R , the nth third control signal G3[n] is the disable level, and the nth first control signal G1[n] is the enable level. Therefore, when the time point T 4 to the time point T 5 , the data input unit 151 receiving the nth stage first control signal G1[n] is enabled, and the display data signal V DATA is thus transmitted to the first end of the first capacitor C S1 . And a control end of the drive unit 153. During the reset period T R , the enable period of the nth stage first control signal G1[n] and the nth stage third control signal G3[n] is shorter than the enable period of the first switch control signal S1, the first switch The enable start time of the control signal S1 is earlier than the enable start time of the nth first control signal G1[n] and the nth third control signal G3[n], and the first switch control signal S1 is enabled. The end time is later than the enabling end time of the nth third control signal G3[n], and the enabling end time of the first switching control signal S1 is the same as the enabling end time of the nth first control signal G1[n] , but not limited to this.

接著在圖6的感測時段T S，也就是圖6的時點T6到時點T7，第一開關控制訊號S1為禁能準位，第二開關控制訊號S2為致能準位，第n級第一控制訊號G1[n]為禁能準位，第n級第三控制訊號G3[n]以及第n級第二控制訊號G2[n]為致能準位，第二開關控制訊號S2、第n級第三控制訊號G3[n]以及第n級第二控制訊號G2[n]的致能期間為相同。接收第二開關控制訊號S2的第二開關單元17為致能，第n級接收第二控制訊號G2[n]的驅動控制單元152為致能，接收第n級第三控制訊號G3[n]的液晶電容控制單元154為致能，因此驅動單元153將根據第一電容C S1第一端之顯示資料訊號V DATA產生顯示電位V D並儲存至液晶電容C LC，第二開關單元17藉由致能的液晶電容控制單元154將顯示電位V D傳送至外部系統14，結束同一行單一列的畫素電路15的感測模式。 Next, in the sensing period T S of FIG. 6 , that is, the time point T6 to the time point T7 of FIG. 6 , the first switch control signal S1 is the disable level, and the second switch control signal S2 is the enable level, the nth level A control signal G1[n] is a disable level, an nth third control signal G3[n] and an nth second control signal G2[n] are an enable level, and a second switch control signal S2 The enabling period of the nth third control signal G3[n] and the nth second control signal G2[n] is the same. The second switch unit 17 receiving the second switch control signal S2 is enabled, and the drive control unit 152 of the nth stage receiving the second control signal G2[n] is enabled to receive the nth third control signal G3[n] The liquid crystal capacitor control unit 154 is enabled. Therefore, the driving unit 153 generates a display potential V D according to the display data signal V DATA at the first end of the first capacitor C S1 and stores it to the liquid crystal capacitor C LC , and the second switching unit 17 The enabled liquid crystal capacitance control unit 154 transmits the display potential V D to the external system 14 to end the sensing mode of the pixel circuit 15 of the single row of the same row.

綜以上所述，藉由第一電容C S1，本發明之液晶電容C LC非直接根據當級之閘極控制訊號充電，因此不會因為高畫面更新率而導致液晶電容C LC需操作於高頻率下，顯示裝置10進而不需高容量之儲存電容來輔助液晶電容C LC維持穩定的電壓值，有效減少硬體面積以及製造成本的消耗。此外，藉由驅動控制單元152的致能時間控制驅動單元153的操作時間，可有效減緩次臨界電流對於顯示電位V D的影響，且藉由第二開關單元17直接讀取液晶電容C LC的電壓值變化，更可精準的偵測出驅動單元153臨界電壓V TH的電性變化，使顯示裝置可據以調整對應的顯示資料訊號V DATA，進而有效改善顯示裝置的顯示效果不均勻的情況，使用者可因此享有更佳的顯示裝置觀賞體驗，增加顯示裝置於經濟上的效益。 Fully described above, by the first capacitor C S1, the liquid crystal capacitance C LC of the present invention the non-directly from the stage when the charging of the gate control signal, and therefore will not result in a high frame refresh rate required to operate the liquid crystal capacitance C LC to a high At the frequency, the display device 10 further eliminates the need for a high-capacity storage capacitor to assist the liquid crystal capacitor C LC to maintain a stable voltage value, thereby effectively reducing the hardware area and manufacturing cost. In addition, by controlling the operation time of the driving unit 152 by the driving time of the driving control unit 152, the influence of the sub-critical current on the display potential V D can be effectively slowed down, and the liquid crystal capacitor C LC is directly read by the second switching unit 17 The change of the voltage value can more accurately detect the electrical change of the threshold voltage V TH of the driving unit 153, so that the display device can adjust the corresponding display data signal V DATA , thereby effectively improving the display effect of the display device. Therefore, the user can enjoy a better viewing experience of the display device and increase the economic benefit of the display device.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技術者，在不脫離本發明之精神和範圍內，當可做些許之更動與潤飾，因此本發明之保護範圍當視後付之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the patent application scope.

10‧‧‧顯示裝置10‧‧‧ display device

11‧‧‧時序控制器11‧‧‧Timing controller

12‧‧‧資料驅動器12‧‧‧Data Drive

13‧‧‧閘極驅動器13‧‧ ‧ gate driver

14‧‧‧外部系統14‧‧‧External system

15‧‧‧畫素電路15‧‧‧ pixel circuit

16‧‧‧第一開關單元16‧‧‧First switch unit

17‧‧‧第二開關單元17‧‧‧Second switch unit

121‧‧‧資料線121‧‧‧Information line

131‧‧‧閘極線131‧‧‧ gate line

151‧‧‧資料輸入單元151‧‧‧Data input unit

152‧‧‧驅動控制單元152‧‧‧Drive Control Unit

153‧‧‧驅動單元153‧‧‧ drive unit

154‧‧‧液晶電容控制單元154‧‧‧Liquid Crystal Capacitor Control Unit

161‧‧‧偵測線161‧‧‧Detection line

T1、T2、T3、T4、T5、T6‧‧‧電晶體T1, T2, T3, T4, T5, T6‧‧‧ transistors

G1‧‧‧第一控制訊號G1‧‧‧ first control signal

G2‧‧‧第二控制訊號G2‧‧‧second control signal

G3‧‧‧第三控制訊號G3‧‧‧ third control signal

S1‧‧‧第一開關控制訊號S1‧‧‧First switch control signal

S2‧‧‧第二開關控制訊號S2‧‧‧Second switch control signal

CS1‧‧‧第一電容C S1 ‧‧‧first capacitor

CS2‧‧‧第二電容C S2 ‧‧‧second capacitor

CLC‧‧‧液晶電容C LC ‧‧‧Liquid Crystal Capacitor

VDATA‧‧‧顯示資料訊號V DATA ‧‧‧Display data signal

VCOM‧‧‧共模電壓V COM ‧‧‧ Common mode voltage

VD‧‧‧顯示電位V D ‧‧‧ shows potential

VDD‧‧‧第一電壓準位V DD ‧‧‧first voltage level

VSS‧‧‧第二電壓準位V SS ‧‧‧second voltage level

圖1為本發明之顯示裝置實施例示意圖。 圖2為本發明之畫素電路實施例示意圖。 圖3為本發明之畫素電路以及顯示裝置實施例操作於顯示模式的時序實施例示意圖。 圖4為本發明之畫素電路以及顯示裝置實施例操作於感測模式的時序實施例一示意圖。 圖5為本發明之畫素電路以及顯示裝置實施例操作於感測模式的時序實施例二示意圖。 圖6為本發明之畫素電路以及顯示裝置實施例操作於感測模式的時序實施例三示意圖。1 is a schematic view of an embodiment of a display device of the present invention. 2 is a schematic diagram of an embodiment of a pixel circuit of the present invention. 3 is a schematic diagram showing a timing embodiment of a pixel circuit and a display device embodiment of the present invention operating in a display mode. 4 is a schematic diagram showing a timing embodiment of a pixel circuit and a display device embodiment operating in a sensing mode according to the present invention. FIG. 5 is a schematic diagram of a timing embodiment 2 of the pixel circuit and the display device embodiment of the present invention operating in a sensing mode. FIG. 6 is a third schematic diagram of a timing embodiment of a pixel circuit and a display device according to the present invention operating in a sensing mode. FIG.

14‧‧‧外部系統 14‧‧‧External system

15‧‧‧畫素電路 15‧‧‧ pixel circuit

16‧‧‧第一開關單元 16‧‧‧First switch unit

17‧‧‧第二開關單元 17‧‧‧Second switch unit

151‧‧‧資料輸入單元 151‧‧‧Data input unit

152‧‧‧驅動控制單元 152‧‧‧Drive Control Unit

153‧‧‧驅動單元 153‧‧‧ drive unit

154‧‧‧液晶電容控制單元 154‧‧‧Liquid Crystal Capacitor Control Unit

T1、T2、T3、T4、T5、T6‧‧‧電晶體 T1, T2, T3, T4, T5, T6‧‧‧ transistors

G1‧‧‧第一控制訊號 G1‧‧‧ first control signal

G2‧‧‧第二控制訊號 G2‧‧‧second control signal

G3‧‧‧第三控制訊號 G3‧‧‧ third control signal

S1‧‧‧第一開關控制訊號 S1‧‧‧First switch control signal

S2‧‧‧第二開關控制訊號 S2‧‧‧Second switch control signal

CS1‧‧‧第一電容 C S1 ‧‧‧first capacitor

CS2‧‧‧第二電容 C S2 ‧‧‧second capacitor

CLC‧‧‧液晶電容 C LC ‧‧‧Liquid Crystal Capacitor

VDATA‧‧‧顯示資料訊號 V DATA ‧‧‧Display data signal

VCOM‧‧‧共模電壓 V COM ‧‧‧ Common mode voltage

VD‧‧‧顯示電位 V D ‧‧‧ shows potential

VDD‧‧‧第一電壓準位 V DD ‧‧‧first voltage level

VSS‧‧‧第二電壓準位 V SS ‧‧‧second voltage level

Claims (14)

一種顯示裝置，其包括：一資料驅動器，包括多個資料線，用以輸出多個顯示資料訊號；多個畫素電路，每一該些畫素電路與其中之一該資料線電性耦接，其中每一該些畫素電路包括：一資料輸入單元，用以接收該顯示資料訊號以及一第一控制訊號，該資料輸入單元用以根據該第一控制訊號決定是否輸出該顯示資料訊號；一第一電容，具有一第一端以及一第二端，該第一電容的該第一端與該資料輸入單元電性耦接，該第一電容用以接收該顯示資料訊號；一驅動控制單元，與該第一電容的該第二端電性耦接，該驅動控制單元用以接收一第一電壓準位以及一第二控制訊號，該驅動控制單元用以根據該第二控制訊號決定是否輸出該第一電壓準位；一驅動單元，與該第一電容的該第一端以及該驅動控制單元電性耦接，該驅動單元用以接收該第一電壓準位並輸出一顯示電位；一液晶電容，具有一第一端以及一第二端，該液晶電容的該第一端與該驅動單元電性耦接，該液晶電容用以接收該顯示電位；一第二電容，具有一第一端以及一第二端，該第二電容的該第一端與該液晶電容的該第一端電性耦接；以及 一液晶電容控制單元，與該液晶電容的該第一端電性耦接，該液晶電容控制單元用以接收一第三控制訊號；多個第一開關單元，每一該些第一開關單元與該些液晶電容控制單元以及一第二電壓準位電性耦接，每一該些第一開關單元接收一第一開關控制訊號並根據該第一開關控制訊號決定是否使該液晶電容控制單元以及該第二電壓準位彼此導通；以及多個第二開關單元，每一該些第二開關單元與該些液晶電容控制單元以及一外部系統電性耦接，該第二開關單元用以接收一第二開關控制訊號並根據該第二開關控制訊號決定是否使該液晶電容控制單元以及該外部系統導通；其中，電性耦接同一該資料線之該些畫素電路定義為同一行並與同一該第一開關單元以及同一該第二開關單元電性耦接。 A display device includes: a data driver, comprising a plurality of data lines for outputting a plurality of display data signals; and a plurality of pixel circuits, each of the pixel circuits being electrically coupled to one of the data lines Each of the pixel circuits includes: a data input unit for receiving the display data signal and a first control signal, wherein the data input unit is configured to determine whether to output the display data signal according to the first control signal; a first capacitor having a first end and a second end, the first end of the first capacitor being electrically coupled to the data input unit, the first capacitor for receiving the display data signal; and a driving control The unit is electrically coupled to the second end of the first capacitor, the driving control unit is configured to receive a first voltage level and a second control signal, and the driving control unit is configured to determine according to the second control signal Whether to output the first voltage level; a driving unit electrically coupled to the first end of the first capacitor and the driving control unit, the driving unit is configured to receive the first voltage level and a display potential; a liquid crystal capacitor having a first end and a second end, the first end of the liquid crystal capacitor is electrically coupled to the driving unit, the liquid crystal capacitor is configured to receive the display potential; a capacitor having a first end and a second end, the first end of the second capacitor being electrically coupled to the first end of the liquid crystal capacitor; a liquid crystal capacitor control unit electrically coupled to the first end of the liquid crystal capacitor, wherein the liquid crystal capacitor control unit is configured to receive a third control signal; a plurality of first switch units, each of the first switch units and The liquid crystal capacitor control unit and the second voltage level are electrically coupled. Each of the first switch units receives a first switch control signal and determines whether to enable the liquid crystal capacitor control unit according to the first switch control signal. The second voltage level is electrically connected to each other; and each of the second switch units is electrically coupled to the liquid crystal capacitor control unit and an external system, and the second switch unit is configured to receive a second The second switch control signal determines whether the liquid crystal capacitance control unit and the external system are turned on according to the second switch control signal; wherein the pixel circuits electrically coupled to the data line are defined as the same line and are identical The first switching unit and the same second switching unit are electrically coupled. 如請求項第1項所述之顯示裝置，其中，該資料輸入單元具有一第一端、一第二端以及一控制端，該資料輸入單元的該第一端用以接收該顯示資料訊號，該資料輸入單元的該控制端用以接收該第一控制訊號，該資料輸入單元的該第二端與該第一電容的該第一端電性耦接。 The display device of claim 1, wherein the data input unit has a first end, a second end, and a control end, and the first end of the data input unit is configured to receive the display data signal. The control terminal of the data input unit is configured to receive the first control signal, and the second end of the data input unit is electrically coupled to the first end of the first capacitor. 如請求項第1項所述之顯示裝置，其中，該驅動控制單元具有一第一端、一第二端以及一控制端，該驅動控制單元的該第一端接收該第一電壓準位，該驅動控制單元的該控制端接收該第二控制訊號，該驅動控制單元的該第二端與該驅動單元電性耦接。 The display device of claim 1, wherein the driving control unit has a first end, a second end, and a control end, the first end of the driving control unit receiving the first voltage level, The control terminal of the drive control unit receives the second control signal, and the second end of the drive control unit is electrically coupled to the drive unit. 如請求項第1項所述之顯示裝置，其中，該驅動單元具有一第一端、一第二端以及一控制端，該驅動單元的該第一端與該驅動控制單元 電性耦接，該驅動單元的該控制端與該第一電容的該第一端電性耦接，該驅動單元的該第二端與該液晶電容的該第一端電性耦接。 The display device of claim 1, wherein the driving unit has a first end, a second end, and a control end, the first end of the driving unit and the driving control unit The control unit is electrically coupled to the first end of the first capacitor, and the second end of the driving unit is electrically coupled to the first end of the liquid crystal capacitor. 如請求項第1項所述之顯示裝置，其中，該液晶電容控制單元具有一第一端、一第二端以及一控制端，該液晶電容控制單元的該第一端與該液晶電容的該第一端電性耦接，該液晶電容控制單元的該控制端接收該第三控制訊號，該液晶電容控制單元的該第二端與其中之一該第一開關單元以及其中之一該第二開關單元電性耦接。 The display device of claim 1, wherein the liquid crystal capacitor control unit has a first end, a second end, and a control end, the first end of the liquid crystal capacitor control unit and the liquid crystal capacitor The first end is electrically coupled, the control end of the liquid crystal capacitor control unit receives the third control signal, the second end of the liquid crystal capacitor control unit and one of the first switch unit and one of the second The switch unit is electrically coupled. 如請求項第1項所述之顯示裝置，其中，該第一開關單元具有一第一端、一第二端以及一控制端，該第一開關單元的該第一端與該液晶電容控制單元電性耦接，該第一開關單元的該第二端與該第二電壓準位電性耦接，該第一開關單元的該控制端接收該第一開關控制訊號。 The display device of claim 1, wherein the first switch unit has a first end, a second end, and a control end, the first end of the first switch unit and the liquid crystal capacitor control unit The second end of the first switch unit is electrically coupled to the second voltage level, and the control end of the first switch unit receives the first switch control signal. 如請求項第1項所述之顯示裝置，其中，該第二開關單元具有一第一端、一第二端以及一控制端，該第二開關單元的該第一端與該液晶電容控制單元電性耦接，該第二開關單元的該第二端與該外部系統電性耦接，該第二開關單元的該控制端接收該第二開關控制訊號。 The display device of claim 1, wherein the second switch unit has a first end, a second end, and a control end, the first end of the second switch unit and the liquid crystal capacitor control unit The second end of the second switch unit is electrically coupled to the external system, and the control end of the second switch unit receives the second switch control signal. 如請求項第1項所述之顯示裝置，其中，於一第一時段，該第一開關控制訊號為致能準位，該第二開關控制訊號為禁能準位，該第三控制訊號為致能準位，該第三控制訊號的致能期間短於該第一開關控制訊號的致能期間，該第一控制訊號的致能期間短於該第三控制訊號的致能期間，該第一控制訊號的致能起始時間晚於該第三控制訊號的致能起始時間。 The display device of claim 1, wherein, in a first time period, the first switch control signal is an enable level, and the second switch control signal is a disable level, and the third control signal is The enabling period of the third control signal is shorter than the enabling period of the first switching control signal, and the enabling period of the first control signal is shorter than the enabling period of the third control signal, the The enable start time of a control signal is later than the enable start time of the third control signal. 如請求項第8項所述之顯示裝置，其中，於一第二時段，該第二時段接續該第一時段，該第二開關控制訊號為致能準位，該第一開關控 制訊號的禁能準位與致能準位彼此交錯切換，該第一控制訊號為禁能準位，該第三控制訊號為致能準位時該第一開關控制訊號為禁能準位，該第一開關控制訊號以及該第三控制訊號的致能期間短於該第二開關控制訊號的致能期間，該第二控制訊號為致能準位，該第二控制訊號的致能期間與該第二開關控制訊號的致能期間相同。 The display device of claim 8, wherein, in a second time period, the second time period is followed by the first time period, and the second switch control signal is an enable level, the first switch control The disable level and the enable level of the signal are alternately switched, and the first control signal is a disable level. When the third control signal is an enable level, the first switch control signal is a disable level. The first control signal and the third control signal are enabled for a shorter period of time than the second switch control signal is enabled. The second control signal is an enable level, and the second control signal is enabled during the period. The enabling period of the second switch control signal is the same. 如請求項第8項所述之顯示裝置，其中，同一行的該些畫素電路接收同一該第三控制訊號。 The display device of claim 8, wherein the pixel circuits of the same row receive the same third control signal. 如請求項第8項所述之顯示裝置，其中，所有該畫素電路接收同一該第二控制訊號。 The display device of claim 8, wherein all of the pixel circuits receive the same second control signal. 如請求項第8項所述之顯示裝置，其中，於一第二時段，該第二時段接續該第一時段，該第二開關控制訊號為致能準位，該第一開關控制訊號的禁能準位與致能準位彼此交錯切換，該第一控制訊號為禁能準位，該第二控制訊號以及該第三控制訊號為致能準位時該第一開關控制訊號為禁能準位，該第一開關控制訊號、該第二控制訊號以及該第三控制訊號的致能期間短於該第二開關控制訊號的致能期間。 The display device of claim 8, wherein, in a second time period, the second time period is followed by the first time period, the second switch control signal is an enable level, and the first switch controls the signal to be disabled. The first control signal is disabled and the first control signal is disabled. When the second control signal and the third control signal are enabled, the first switch control signal is disabled. The enabling period of the first switch control signal, the second control signal, and the third control signal is shorter than the enable period of the second switch control signal. 如請求項第1項所述之顯示裝置，其中，於一第一時段，該第一控制訊號以及該第三控制訊號的致能期間短於該第一開關控制訊號的致能期間，該第一開關控制訊號的致能起始時間早於該第一控制訊號以及該第三控制訊號的致能起始時間，該第一開關控制訊號的致能結束時間晚於該第三控制訊號的致能結束時間，該第一開關控制訊號的致能結束時間與該第一控制訊號的致能結束時間相同，該第二開關控制訊號以及該第二控制訊號為禁能準位。 The display device of claim 1, wherein the first control signal and the third control signal are enabled for a shorter period of time than the first switch control signal is enabled during the first time period. The activation start time of a switch control signal is earlier than the first control signal and the enable start time of the third control signal, and the enable end time of the first switch control signal is later than the third control signal The second switch control signal and the second control signal are disabled. 如請求項第13項所述之顯示裝置，其中，於一第二時段，該第二時段接續該第一時段，該第一開關控制訊號以及該第一訊號為禁能準位，該第二開關控制訊號、該第三控制訊號以及該第二控制訊號為致能準位，該第二開關控制訊號、該第三控制訊號以及該第二控制訊號的致能期間為相同。 The display device of claim 13, wherein, in a second time period, the second time period is followed by the first time period, the first switch control signal and the first signal are disabled levels, and the second The switch control signal, the third control signal, and the second control signal are the enable levels, and the enable periods of the second switch control signal, the third control signal, and the second control signal are the same.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110491324A (en) * 2019-02-11 2019-11-22 友达光电股份有限公司 Electronic device and driving method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1544975A (en) * 2003-11-18 2004-11-10 友达光电股份有限公司 Circuit and method for generating top rack wave of panel display
US20110050677A1 (en) * 2009-08-28 2011-03-03 Himax Technologies Limited Source driver
TW201248603A (en) * 2011-05-23 2012-12-01 Samsung Electronics Co Ltd Timing controller and a display device including the same
TWM514086U (en) * 2015-07-28 2015-12-11 Giantplus Technology Co Ltd Display driving circuit, display driving chip, and display

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1544975A (en) * 2003-11-18 2004-11-10 友达光电股份有限公司 Circuit and method for generating top rack wave of panel display
US20110050677A1 (en) * 2009-08-28 2011-03-03 Himax Technologies Limited Source driver
TW201248603A (en) * 2011-05-23 2012-12-01 Samsung Electronics Co Ltd Timing controller and a display device including the same
TWM514086U (en) * 2015-07-28 2015-12-11 Giantplus Technology Co Ltd Display driving circuit, display driving chip, and display

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110491324A (en) * 2019-02-11 2019-11-22 友达光电股份有限公司 Electronic device and driving method
TWI688930B (en) * 2019-02-11 2020-03-21 友達光電股份有限公司 Electronic device and driving method thereof
CN110491324B (en) * 2019-02-11 2022-06-28 友达光电股份有限公司 Electronic device and driving method

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