TWI607425B - Pixel structure and driving method - Google Patents
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Description
本揭示內容是一種畫素技術，且特別是有關於一種畫素結構與驅動方法。 The present disclosure is a pixel technology, and in particular relates to a pixel structure and driving method.
於穿戴式顯示裝置(例如智慧手錶、智慧手環)的設計中，畫素的外圍走線隨著資料線的數目增加，導致封裝後的面板邊框寬度難以減少，因此較難應用於窄邊框的產品設計。 In the design of wearable display devices (such as smart watches and smart bracelets), the peripheral trace of the pixels increases with the number of data lines, which makes it difficult to reduce the width of the frame border after packaging, so it is difficult to apply to narrow borders. product design.
本揭示內容的一態樣是提供一種畫素結構，其包含複數個資料線、複數個掃描線與複數個畫素單元。資料線沿第一方向排列，掃描線沿第二方向排列，其中第一方向相異於第二方向。畫素單元沿第一方向與第二方向週期性排列。畫素單元之第一畫素單元包含第一開關元件、第二開關元件與第三開關元件。第一開關元件電性耦接掃描線之第一掃描線與資料線之第一資料線，第二開關元件電性耦接第一掃描線，第三開關元件電性耦接第一掃描線。畫素單元之第 二畫素單元包含第四開關元件與第五開關元件。第四開關元件電性耦接掃描線之第二掃描線、第一資料線與第二開關元件，第五開關元件電性耦接第二掃描線與第三開關元件。畫素單元之第三畫素單元包含第六開關元件。第六開關元件電性耦接掃描線之第三掃描線、第一資料線與第五開關元件。 One aspect of the present disclosure is to provide a pixel structure comprising a plurality of data lines, a plurality of scan lines, and a plurality of pixel units. The data lines are arranged in a first direction, and the scan lines are arranged in a second direction, wherein the first direction is different from the second direction. The pixel units are periodically arranged along the first direction and the second direction. The first pixel unit of the pixel unit includes a first switching element, a second switching element, and a third switching element. The first switching element is electrically coupled to the first scan line of the scan line and the first data line of the data line, the second switch element is electrically coupled to the first scan line, and the third switch element is electrically coupled to the first scan line. The prime unit The two pixel unit includes a fourth switching element and a fifth switching element. The fourth switching element is electrically coupled to the second scan line of the scan line, the first data line and the second switch element, and the fifth switch element is electrically coupled to the second scan line and the third switch element. The third pixel unit of the pixel unit includes a sixth switching element. The sixth switching element is electrically coupled to the third scan line of the scan line, the first data line and the fifth switching element.
於本揭示內容之一實施例中，於第一時段內，第一掃描線、第二掃描線與第三掃描線傳遞致能訊號。第一開關元件接收第一資料線之第一資料訊號。第二開關元件經由第四開關元件接收第一資料訊號。第三開關元件經由第五開關元件與第六開關元件接收第一資料訊號。 In an embodiment of the present disclosure, the first scan line, the second scan line, and the third scan line transmit the enable signal during the first time period. The first switching element receives the first data signal of the first data line. The second switching element receives the first data signal via the fourth switching element. The third switching element receives the first data signal via the fifth switching element and the sixth switching element.
於本揭示內容之一實施例中，於第二時段內，第一掃描線與第二掃描線傳遞致能訊號，第三掃描線傳遞禁能訊號。第一開關元件接收第一資料線之第二資料訊號，第二開關元件經由第四開關元件接收第二資料訊號。 In an embodiment of the present disclosure, in the second time period, the first scan line and the second scan line transmit the enable signal, and the third scan line transmits the disable signal. The first switching element receives the second data signal of the first data line, and the second switching element receives the second data signal via the fourth switching element.
於本揭示內容之一實施例中，於第三時段內，第一掃描線傳遞致能訊號，第二掃描線與第三掃描線傳遞禁能訊號。第一開關元件接收第一資料線之第三資料訊號。 In an embodiment of the present disclosure, the first scan line transmits the enable signal during the third time period, and the second scan line and the third scan line transmit the disable signal. The first switching element receives the third data signal of the first data line.
於本揭示內容之一實施例中，畫素結構更包含複數個資料選擇線。資料選擇線沿第二方向設置於畫素單元之間。資料選擇線用以提供複數個資料訊號至資料線。 In an embodiment of the present disclosure, the pixel structure further includes a plurality of data selection lines. The data selection line is disposed between the pixel units in the second direction. The data selection line is used to provide a plurality of data signals to the data line.
於本揭示內容之一實施例中，第一開關元件、第二開關元件與第三開關元件沿第二方向排列。第四開關元件與第五開關元件沿第二方向排列。 In an embodiment of the present disclosure, the first switching element, the second switching element, and the third switching element are arranged in the second direction. The fourth switching element and the fifth switching element are arranged in the second direction.
於本揭示內容之一實施例中，第一開關元件、 第四開關元件與第六開關元件沿第一方向排列。第二開關元件與第五開關元件沿該第一方向排列。 In an embodiment of the present disclosure, the first switching element, The fourth switching element and the sixth switching element are arranged in the first direction. The second switching element and the fifth switching element are arranged in the first direction.
本揭示內容的另一態樣是提供一種驅動方法，適用於畫素結構。畫素結構包含複數個資料線、複數個掃描線與複數個畫素單元。資料線沿第一方向排列，掃描線沿第二方向排列，第一方向相異於該第二方向。畫素單元沿第一方向與第二方向週期性排列。畫素單元之第一畫素單元包含第一開關元件、第二開關元件與第三開關元件，畫素單元之第二畫素單元包含第四開關元件與第五開關元件，畫素單元之第三畫素單元包含第六開關元件。驅動方法包含以下步驟。於第一時段內，藉由第一掃描線、第二掃描線與第三掃描線傳遞致能訊號。於第一時段內，藉由第一開關元件接收資料線之第一資料線之第一資料訊號，藉由第二開關元件經由第四開關元件接收第一資料訊號，並藉由第三開關元件經由第五開關元件與第六開關元件接收第一資料訊號。 Another aspect of the present disclosure is to provide a driving method suitable for a pixel structure. The pixel structure includes a plurality of data lines, a plurality of scan lines, and a plurality of pixel units. The data lines are arranged in a first direction, and the scan lines are arranged in a second direction, the first direction being different from the second direction. The pixel units are periodically arranged along the first direction and the second direction. The first pixel unit of the pixel unit includes a first switching element, a second switching element and a third switching element, and the second pixel unit of the pixel unit includes a fourth switching element and a fifth switching element, and the pixel element The three pixel unit includes a sixth switching element. The driver method consists of the following steps. The enable signal is transmitted by the first scan line, the second scan line, and the third scan line during the first time period. Receiving, by the first switching element, the first data signal of the first data line of the data line, receiving, by the second switching element, the first data signal via the fourth switching element, and by the third switching element The first data signal is received via the fifth switching element and the sixth switching element.
於本揭示內容之一實施例中，於第二時段內，藉由第一掃描線與第二掃描線傳遞致能訊號，並藉由第三掃描線傳遞禁能訊號。於第二時段內，藉由第一開關元件接收第一資料線之第二資料訊號，並藉由第二開關元件經由第四開關元件接收第二資料訊號。 In an embodiment of the present disclosure, the enable signal is transmitted by the first scan line and the second scan line during the second time period, and the disable signal is transmitted by the third scan line. Receiving, by the first switching element, the second data signal of the first data line, and receiving, by the second switching element, the second data signal by the fourth switching element.
於本揭示內容之一實施例中，於第三時段內，藉由第一掃描線傳遞致能訊號，並藉由第二掃描線與第三掃描線傳遞禁能訊號。於第三時段內，藉由第一開關元件接收第一資料線之第三資料訊號。 In an embodiment of the present disclosure, the enable signal is transmitted by the first scan line and the disable signal is transmitted by the second scan line and the third scan line during the third time period. Receiving, by the first switching component, the third data signal of the first data line during the third time period.
綜上所述，本揭示內容的畫素結構可透過分時分工驅動三個開關元件(亦即驅動三個畫素)以接收並儲存同一資料線的資料訊號，因此可有效地減少畫素結構內資料線的數目，進而達到資料線不須經由畫素結構外圍走線的效果。此外，設置於畫素單元之間的資料選擇線亦可進一步減少畫素結構外圍走線的數目。因此，本揭示內容的畫素結構可適用於窄邊框顯示裝置的設計。 In summary, the pixel structure of the present disclosure can drive three switching elements (that is, drive three pixels) through time division division to receive and store data signals of the same data line, thereby effectively reducing the pixel structure. The number of internal data lines, and thus the effect that the data lines do not need to be routed through the periphery of the pixel structure. In addition, the data selection line disposed between the pixel units can further reduce the number of peripheral traces of the pixel structure. Therefore, the pixel structure of the present disclosure can be applied to the design of a narrow bezel display device.
以下將以實施方式對上述之說明作詳細的描述，並對本揭示內容之技術方案提供更進一步的解釋。 The above description will be described in detail in the following embodiments, and further explanation of the technical solutions of the present disclosure is provided.
為讓本揭示內容之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附符號之說明如下： The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood.
100‧‧‧畫素結構 100‧‧‧ pixel structure
110~180‧‧‧畫素單元 110~180‧‧‧ pixel unit
P1~P24‧‧‧開關元件 P1~P24‧‧‧Switching elements
G1~G4‧‧‧掃描線 G1~G4‧‧‧ scan line
D1~D3‧‧‧資料線 D1~D3‧‧‧ data line
DL1~DL8‧‧‧資料選擇線 DL1~DL8‧‧‧ data selection line
R1、R2‧‧‧方向 R1, R2‧‧‧ direction
T11~T43‧‧‧時段 T11~T43‧‧‧
d11~d43‧‧‧資料訊號 D11~d43‧‧‧Information signal
為了讓本發明之上述和其他目的、特徵、優點與實施例更明顯易懂，所附圖示之說明如下：第1圖係說明本揭示內容一實施例之畫素結構之示意圖；以及第2圖係說明本揭示內容一實施例之驅動訊號時序示意圖。 The above and other objects, features, advantages and embodiments of the present invention will become more apparent from the accompanying drawings. The figure illustrates a timing diagram of a driving signal according to an embodiment of the present disclosure.
為了使本揭示內容之敘述更加詳盡與完備，可參照附圖及以下所述之各種實施例。但所提供之實施例並非用以限制本發明所涵蓋的範圍；步驟的描述亦非用以限制其執行之順序，任何由重新組合，所產生具有均等功效的裝置，皆為本發明所涵蓋的範圍。 To make the description of the present disclosure more detailed and complete, reference is made to the drawings and the various embodiments described below. The examples are not intended to limit the scope of the invention; the description of the steps is not intended to limit the order of execution thereof, and any device having equal efficiency resulting from recombination is covered by the present invention. range.
於實施方式與申請專利範圍中，除非內文中對於冠詞有所特別限定，否則「一」與「該」可泛指單一個或複數個。將進一步理解的是，本文中所使用之「包含」、「包括」、「具有」及相似詞彙，指明其所記載的特徵、區域、整數、步驟、操作、元件與/或組件，但不排除其所述或額外的其一個或多個其它特徵、區域、整數、步驟、操作、元件、組件，與/或其中之群組。 In the scope of the embodiments and claims, "one" and "the" may mean a single or plural unless the context specifically dictates the articles. It will be further understood that the terms "comprising", "comprising", "comprising", and "the" One or more of its other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
關於本文中所使用之「約」、「大約」或「大致約」一般通常係指數值之誤差或範圍約百分之二十以內，較好地是約百分之十以內，而更佳地則是約百分五之以內。文中若無明確說明，其所提及的數值皆視作為近似值，即如「約」、「大約」或「大致約」所表示的誤差或範圍。 As used herein, "about", "about" or "approximately" is generally within an error or range of about 20% of the index value, preferably within about 10%, and more preferably It is about five percent. Unless otherwise stated, the numerical values referred to are regarded as approximations, that is, the errors or ranges indicated by "about", "about" or "approximately".
另外，關於本文中所使用之「耦接」及「連接」，均可指二或多個元件相互直接作實體接觸或電性接觸，相互間接作實體接觸或電性接觸，或是透過無線連接，而「耦接」還可指二或多個元件相互操作或動作。 In addition, "coupled" and "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, indirectly in physical or electrical contact, or through a wireless connection. And "coupled" may also mean that two or more elements operate or act in each other.
請參考第1圖，第1圖係說明本揭示內容一實施例之畫素結構100之示意圖。畫素結構100包含複數個資料線D1~D3、複數個掃描線G1~G4與複數個畫素單元110~180。資料線D1~D3沿第一方向R1排列，掃描線G1~G4沿第二方向R2排列，畫素單元110~180沿第一方向R1與第二方向R2週期性排列，第一方向R1相異於第二方向R2。如第1圖所示，畫素單元110包含開關元件P1~P3，開關元件P1電性耦接掃描線G1與資料線D1，開關元件P2電 性耦接掃描線G1，開關元件P3電性耦接掃描線G1。畫素單元120包含開關元件P4、P5，開關元件P4電性耦接掃描線G2、資料線D1與開關元件P2，開關元件P5電性耦接掃描線G2與開關元件P3。畫素單元130包含開關元件P6，開關元件P6電性耦接掃描線G3、資料線D1與開關元件P5。 Please refer to FIG. 1. FIG. 1 is a schematic diagram showing a pixel structure 100 according to an embodiment of the present disclosure. The pixel structure 100 includes a plurality of data lines D1 to D3, a plurality of scanning lines G1 to G4, and a plurality of pixel units 110 to 180. The data lines D1 to D3 are arranged along the first direction R1, the scanning lines G1 G G4 are arranged along the second direction R2, and the pixel units 110-180 are periodically arranged along the first direction R1 and the second direction R2, and the first direction R1 is different. In the second direction R2. As shown in FIG. 1, the pixel unit 110 includes switching elements P1 to P3, and the switching element P1 is electrically coupled to the scanning line G1 and the data line D1, and the switching element P2 is electrically The switching element G3 is electrically coupled to the scanning line G1. The pixel unit 120 includes switching elements P4 and P5. The switching element P4 is electrically coupled to the scanning line G2, the data line D1 and the switching element P2. The switching element P5 is electrically coupled to the scanning line G2 and the switching element P3. The pixel unit 130 includes a switching element P6 electrically coupled to the scan line G3, the data line D1, and the switching element P5.
如第1圖所示，畫素單元110的開關元件P1~P3(例如電晶體)與畫素單元150的開關元件P13~P15均經由控制端電性耦接至掃描線G1，畫素單元120的開關元件P4、P5、P7與畫素單元160的開關元件P16~P18均經由控制端電性耦接至掃描線G2，畫素單元130的開關元件P6、P8、P9與畫素單元170的開關元件P19~P21均經由控制端電性耦接至掃描線G3，畫素單元140的開關元件P10~P12與畫素單元180的開關元件P22~P24均經由控制端電性耦接至掃描線G4。須說明的是，開關元件P1~P24分別對應一個畫素，亦即每一畫素單元110~180包含三個畫素。然而，本揭示內容不以此為限，畫素單元110~180亦可包含不同數目的開關元件(或畫素)。 As shown in FIG. 1, the switching elements P1 to P3 (for example, a transistor) of the pixel unit 110 and the switching elements P13 to P15 of the pixel unit 150 are electrically coupled to the scanning line G1 via the control terminal, and the pixel unit 120 The switching elements P4, P5, and P7 of the pixel unit 160 and the switching elements P16 to P18 of the pixel unit 160 are electrically coupled to the scan line G2 via the control terminal, and the switching elements P6, P8, and P9 of the pixel unit 130 and the pixel unit 170. The switching elements P19-P21 are electrically coupled to the scan line G3 via the control terminal, and the switching elements P10-P12 of the pixel unit 140 and the switching elements P22-P24 of the pixel unit 180 are electrically coupled to the scan line via the control terminal. G4. It should be noted that the switching elements P1~P24 respectively correspond to one pixel, that is, each pixel unit 110~180 includes three pixels. However, the disclosure is not limited thereto, and the pixel units 110-180 may also include different numbers of switching elements (or pixels).
須說明的是，畫素單元110~180每一者的第一開關元件(例如開關元件P1、P4、P6、P10)均經由其第一端電性耦接至資料線(例如資料線D1)，並且經由其第二端電性耦接至電容器。畫素單元110~180每一者的第二開關元件(例如開關元件P2、P5、P8)均經由其第一端電性耦接至相鄰畫素單元的第一開關元件(例如開關元件P4、P6、P10)，並且經由其第二端電性耦接至電容器。畫素單 元110~180每一者的第三開關元件(例如開關元件P3、P7、P9)均經由其第一端電性耦接至相鄰畫素單元的第二開關元件(例如開關元件P5、P8、P11)，並且經由其第二端電性耦接至電容器。因此，當掃描線G1~G3傳遞致能訊號時，畫素單元110~130的開關元件P1~P9開啟，而此時資料線D1的資料訊號可傳遞至開關元件P1~P6。 It should be noted that the first switching elements (for example, the switching elements P1, P4, P6, and P10) of each of the pixel units 110-180 are electrically coupled to the data line (for example, the data line D1) via the first end thereof. And electrically coupled to the capacitor via its second end. The second switching elements (eg, switching elements P2, P5, P8) of each of the pixel units 110-180 are electrically coupled via their first ends to the first switching elements of adjacent pixel units (eg, switching element P4) , P6, P10), and is electrically coupled to the capacitor via its second end. Picture book The third switching elements of each of the elements 110-180 (eg, the switching elements P3, P7, P9) are electrically coupled via their first ends to the second switching elements of the adjacent pixel units (eg, switching elements P5, P8) , P11), and is electrically coupled to the capacitor via its second end. Therefore, when the scan lines G1 G G3 transmit the enable signal, the switching elements P1 P P9 of the pixel units 110 - 130 are turned on, and the data signals of the data line D1 can be transmitted to the switching elements P1 P P6.
於一實施例中，畫素結構100更包含複數個資料選擇線DL1~DL8。資料選擇線DL1~DL8沿第二方向R2設置於畫素單元110~180之間。於本實施例中，沿第一方向R1相鄰的兩畫素單元之間設置有兩條資料選擇線與一條掃描線。舉例而言，畫素單元110、120之間設置有兩條資料選擇線DL1、DL2與一條掃描線G1。資料選擇線DL1~DL8用以提供複數個資料訊號至資料線。舉例而言，資料選擇線DL1(例如T導線(T-wire)，但本揭示內容不以此為限)電性耦接資料線D1以提供資料訊號至資料線D1，資料選擇線DL2電性耦接資料線D2以提供資料訊號至資料線D2，資料選擇線DL3電性耦接資料線D3以提供資料訊號至資料線D3。 In an embodiment, the pixel structure 100 further includes a plurality of data selection lines DL1 DL DL8. The data selection lines DL1 to DL8 are disposed between the pixel units 110 to 180 in the second direction R2. In this embodiment, two data selection lines and one scan line are disposed between two pixel units adjacent in the first direction R1. For example, two data selection lines DL1, DL2 and one scan line G1 are disposed between the pixel units 110, 120. The data selection lines DL1~DL8 are used to provide a plurality of data signals to the data lines. For example, the data selection line DL1 (for example, T-wire, but not limited thereto) is electrically coupled to the data line D1 to provide a data signal to the data line D1, and the data selection line DL2 is electrically The data line D2 is coupled to provide a data signal to the data line D2, and the data selection line DL3 is electrically coupled to the data line D3 to provide a data signal to the data line D3.
如此一來，設置於畫素結構100內的資料選擇線DL1~DL8可有效地減少資料線D1~D3於畫素結構100外圍的走線。舉例而言，如第1圖所示，畫素結構100可省下掃描線G1~G4兩倍數量的資料線D1~D3於畫素結構100外圍的走線。 In this way, the data selection lines DL1 DL DL8 disposed in the pixel structure 100 can effectively reduce the traces of the data lines D1 DD3 to the periphery of the pixel structure 100. For example, as shown in FIG. 1, the pixel structure 100 can save the traces of the data lines D1 D D3 twice the scan lines G1 G G4 on the periphery of the pixel structure 100.
為了說明畫素結構100的驅動方法，請參考第 1、2圖。於時段T11內，資料選擇線DL1傳遞資料訊號d11至資料線D1，掃描線G1~G3傳遞致能訊號(例如邏輯高位準)，於是開關元件P1~P9、P13~P21開啟，並且其他開關元件P10~P12、P22~P24關閉。因此，開關元件P1、P4、P6直接由資料線D1接收資料訊號d11，開關元件P2經由開關元件P4接收資料訊號d11，開關元件P3經由開關元件P5與開關元件P6接收資料訊號d11。於是，開關元件P1~P6分別儲存資料訊號d11至其耦接的電容器內。 In order to explain the driving method of the pixel structure 100, please refer to the 1, 2 pictures. During the time period T11, the data selection line DL1 transmits the data signal d11 to the data line D1, and the scanning lines G1 to G3 transmit the enable signal (for example, the logic high level), so the switching elements P1~P9, P13~P21 are turned on, and other switching elements are turned on. P10~P12 and P22~P24 are closed. Therefore, the switching elements P1, P4, and P6 receive the data signal d11 directly from the data line D1, the switching element P2 receives the data signal d11 via the switching element P4, and the switching element P3 receives the data signal d11 via the switching element P5 and the switching element P6. Thus, the switching elements P1 to P6 respectively store the data signal d11 into the capacitor to which they are coupled.
接著，於時段T12內，資料選擇線DL1傳遞資料訊號d12至資料線D1，掃描線G1~G2傳遞致能訊號，掃描線G3傳遞禁能訊號(例如邏輯低位準)，於是開關元件P1~P5、P7、P13~P18開啟，並且其他開關元件P6、P8~P12、P19~P24關閉。因此，開關元件P1、P4直接由資料線D1接收資料訊號d12，開關元件P2經由開關元件P4接收資料訊號d12。於是，開關元件P1~P2、P4分別儲存資料訊號d12至其耦接的電容器內，而開關元件P3、P5、P6耦接的電容器則儲存著資料訊號d11。 Then, in the time period T12, the data selection line DL1 transmits the data signal d12 to the data line D1, the scanning lines G1 G G2 transmit the enable signal, and the scan line G3 transmits the disable signal (for example, the logic low level), so the switching elements P1~P5 , P7, P13~P18 are turned on, and other switching elements P6, P8~P12, P19~P24 are turned off. Therefore, the switching elements P1, P4 receive the data signal d12 directly from the data line D1, and the switching element P2 receives the data signal d12 via the switching element P4. Therefore, the switching elements P1~P2 and P4 respectively store the data signal d12 into the capacitor to which they are coupled, and the capacitors coupled to the switching elements P3, P5 and P6 store the data signal d11.
於時段T13內，資料選擇線DL1傳遞資料訊號d13至資料線D1，掃描線G1傳遞致能訊號，掃描線G2~G3傳遞禁能訊號，於是開關元件P1~P3、P13~P15開啟，並且其他開關元件P4~P12、P16~P24關閉。因此，開關元件P1直接由資料線D1接收資料訊號d13。於是，開關元件P1儲存資料訊號d13至其耦接的電容器內，而開關元件P3、P5、P6耦接的電容器則儲存著資料訊號d11，開關元件P2、 P4耦接的電容器則儲存著資料訊號d12。 During the time period T13, the data selection line DL1 transmits the data signal d13 to the data line D1, the scanning line G1 transmits the enable signal, and the scanning lines G2 to G3 transmit the disable signal, so the switching elements P1~P3, P13~P15 are turned on, and the others The switching elements P4 to P12 and P16 to P24 are turned off. Therefore, the switching element P1 directly receives the data signal d13 from the data line D1. Therefore, the switching element P1 stores the data signal d13 into the capacitor coupled thereto, and the capacitor coupled to the switching element P3, P5, P6 stores the data signal d11, the switching element P2. The P4 coupled capacitor stores the data signal d12.
須補充的是，於時段T11~T13內，資料選擇線DL2亦可傳遞相同或不同資料訊號至資料線D2，而開關元件P13~P17、P19的運作類似於開關元件P1~P6，因此不再重複敘述。 It should be added that during the time period T11~T13, the data selection line DL2 can also transmit the same or different data signals to the data line D2, and the switching elements P13~P17, P19 operate similarly to the switching elements P1~P6, so no longer Repeat the narrative.
如此一來，單一資料線D1可於三個時段T11~T13內分別驅動三個畫素的開關元件P1~P3，並將資料訊號d11~d13分別儲存於開關元件P1~P3耦接的電容器內。類似地，單一資料線D2可於三個時段T11~T13內分別驅動三個畫素的開關元件P13~P15，並將資料訊號(未繪示)分別儲存於開關元件P13~P15耦接的電容器內。相較於先前技術，畫素結構100僅需三分之一數目的資料線(亦即減少資料線數目)，進而減少資料線於畫素結構100外圍的走線面積。 In this way, the single data line D1 can drive the three pixel switching elements P1~P3 in three time periods T11~T13, and store the data signals d11~d13 in the capacitors coupled to the switching elements P1~P3, respectively. . Similarly, the single data line D2 can drive the three pixel switching elements P13~P15 in three time periods T11~T13, and store the data signals (not shown) in the capacitors coupled to the switching elements P13~P15. Inside. Compared to the prior art, the pixel structure 100 requires only one-third of the data lines (ie, reduces the number of data lines), thereby reducing the area of the data lines outside the pixel structure 100.
於時段T21~T23內，掃描線G2~G4的運作類似於時段T11~T13內的掃描線G1~G3，因此開關元件P4、P5、P7可分別儲存資料線D1的資料訊號d21~d23至其耦接的電容器內，並且其他耦接至掃描線G2的開關元件亦可儲存其耦接資料線傳遞的資料訊號於電容器內(例如開關元件P16~P18可於時段T21~T23內分別儲存資料線D2的資料訊號至其耦接的電容器內)。如上述，於時段T31~T33內，開關元件P6、P8、P9可分別儲存資料線D1的資料訊號d31~d33至其耦接的電容器內(其他耦接至掃描線G3的開關元件的運作亦同)。於時段T41~T43內，開關元件 P10~P12可分別儲存資料線D1的資料訊號d41~d43至其耦接的電容器內(其他耦接至掃描線G4的開關元件的運作亦同)。 During the period T21~T23, the operation of the scanning lines G2~G4 is similar to the scanning lines G1~G3 in the period T11~T13, so the switching elements P4, P5, P7 can respectively store the data signals d21~d23 of the data line D1 to the same. The switching element coupled to the scan line G2 can also store the data signal transmitted by the coupled data line in the capacitor (for example, the switching elements P16~P18 can respectively store the data line in the period T21~T23). The data signal of D2 is connected to the capacitor it is coupled to). As described above, during the period T31~T33, the switching elements P6, P8, and P9 can respectively store the data signals d31~d33 of the data line D1 into the capacitors coupled thereto (other switching elements coupled to the scanning line G3 also operate) with). In the period T41~T43, the switching element P10~P12 can store the data signals d41~d43 of the data line D1 to the capacitors connected thereto (the operation of other switching elements coupled to the scanning line G4 is also the same).
綜上所述，本揭示內容的畫素結構100可透過分時分工驅動三個開關元件(亦即驅動三個畫素)以接收並儲存同一資料線的資料訊號，因此可有效地減少畫素結構100內資料線的數目，進而達到資料線不須經由畫素結構100外圍走線的效果。此外，設置於畫素單元110~180之間的資料選擇線DL1~DL8亦可進一步減少畫素結構外圍走線的數目。因此，本揭示內容的畫素結構100可適用於窄邊框顯示裝置的設計。 In summary, the pixel structure 100 of the present disclosure can drive three switching elements (that is, drive three pixels) through time division division to receive and store data signals of the same data line, thereby effectively reducing pixels. The number of data lines in the structure 100, and thus the effect that the data lines do not need to be routed through the periphery of the pixel structure 100. In addition, the data selection lines DL1 DL DL8 disposed between the pixel units 110 - 180 can further reduce the number of peripheral traces of the pixel structure. Accordingly, the pixel structure 100 of the present disclosure is applicable to the design of a narrow bezel display device.
雖然本揭示內容已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本揭示內容之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視申請專利範圍所界定者為準。 Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the invention, and the present invention may be modified and retouched without departing from the spirit and scope of the present disclosure. The scope of protection is subject to the definition of the scope of patent application.
100‧‧‧畫素結構 100‧‧‧ pixel structure
110~180‧‧‧畫素單元 110~180‧‧‧ pixel unit
P1~P24‧‧‧開關元件 P1~P24‧‧‧Switching elements
G1~G4‧‧‧掃描線 G1~G4‧‧‧ scan line
D1~D3‧‧‧資料線 D1~D3‧‧‧ data line
DL1~DL8‧‧‧資料選擇線 DL1~DL8‧‧‧ data selection line
R1、R2‧‧‧方向 R1, R2‧‧‧ direction
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| TW200727230A (en) * | 2006-01-13 | 2007-07-16 | Chi Mei Optoelectronics Corp | A display with time-multiplexed driving circuit and driving method thereof |
| TW201137481A (en) * | 2010-03-10 | 2011-11-01 | Samsung Mobile Display Co Ltd | Flat panel display device and method for driving thereof |
| TW201225040A (en) * | 2010-12-01 | 2012-06-16 | Chimei Innolux Corp | Display panel and driving method therefor |
| TW201638919A (en) * | 2009-10-21 | 2016-11-01 | 半導體能源研究所股份有限公司 | Display device and electronic device including display device |
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| TW200727230A (en) * | 2006-01-13 | 2007-07-16 | Chi Mei Optoelectronics Corp | A display with time-multiplexed driving circuit and driving method thereof |
| TW201638919A (en) * | 2009-10-21 | 2016-11-01 | 半導體能源研究所股份有限公司 | Display device and electronic device including display device |
| TW201137481A (en) * | 2010-03-10 | 2011-11-01 | Samsung Mobile Display Co Ltd | Flat panel display device and method for driving thereof |
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