TWI605256B

TWI605256B - Valley detector for flyback convertor

Info

Publication number: TWI605256B
Application number: TW105132112A
Authority: TW
Inventors: 王朝欽; 侯宗佑; 黃鐙緯
Original assignee: 國立中山大學
Priority date: 2016-10-04
Filing date: 2016-10-04
Publication date: 2017-11-11
Also published as: TW201814308A

Description

反馳式轉換器之波谷偵測器Valley detector for flyback converter

本發明是關於一種波谷偵測器，特別是關於一種反馳式轉換器之波谷偵測器。The present invention relates to a valley detector, and more particularly to a valley detector for a flyback converter.

電源轉換器是將不穩定之交流電源轉換為電流穩定的直流電源，以提供電源至需要直流電源的裝置，如發光二極體及一般家用電器設備。其中，由於切換式電源供應器可適用於不同的電壓大小，且具有高效率、高功因及高輸出電壓範圍之功效，使得切換式電源供應器為目前電源轉換器的主要發展類型。The power converter converts unstable AC power into a current-stable DC power supply to provide power to devices that require DC power, such as light-emitting diodes and general household appliances. Among them, since the switching power supply can be applied to different voltage levels, and has high efficiency, high power factor and high output voltage range, the switching power supply is the main development type of the current power converter.

而切換式電源供應器根據其切換模式可大致可區分為硬性切換及柔性切換，硬性切換時開關的電壓及電流的交疊不為零，使得每次開關切換時均會產生切換損失，導致轉換效率的下降以及溫度上升的問題。相對的，柔性切換是縮小切換時開關電壓和電流交疊的時間，一般可利用主電路諧振的方式達成零電壓或零電流切換，但主電路諧振會使峰值電壓及電流提高，使元件需承受的耐壓耐流升高，增加了元件應力及傳導損失。The switching power supply can be roughly divided into hard switching and flexible switching according to the switching mode. When the hard switching is performed, the voltage and current overlap of the switch is not zero, so that switching loss occurs every time the switching is switched, resulting in conversion. The problem of reduced efficiency and temperature rise. In contrast, flexible switching is to reduce the switching voltage and current overlap time when switching. Generally, zero voltage or zero current switching can be achieved by means of main circuit resonance, but the main circuit resonance will increase the peak voltage and current, so that the components have to withstand The increase in withstand voltage and current increases the component stress and conduction loss.

因此，目前發展出準諧振轉換器(Quasi-Resonant Converter)的技術，準諧振轉換器是在開關加入電容、電感，使開關電壓或電流不會急速變化，而可在開關轉態時，才以諧振方式達到柔性切換。因此，如何在電容電感諧振時偵測得其諧振谷值為準諧振轉換器達到零電壓或零電流切換的關鍵技術。Therefore, the Quasi-Resonant Converter technology has been developed. The quasi-resonant converter adds capacitance and inductance to the switch, so that the switching voltage or current does not change rapidly, but when the switch is in the state of transition, The resonant mode achieves flexible switching. Therefore, how to detect the resonance valley when the capacitor inductance is resonant is the key technology for the quasi-resonant converter to achieve zero voltage or zero current switching.

本發明的主要目的在於藉由波谷偵測電路測得諧振訊號的波谷，並透過兩個上緣偵測器及開關訊號確定輔助繞組之輔助感應電壓已上升至高電壓，及確定控制開關已關閉後才進行波谷的偵測，以避免波谷偵測的誤判。The main purpose of the present invention is to measure the valley of the resonant signal by the valley detecting circuit, and determine that the auxiliary induced voltage of the auxiliary winding has risen to a high voltage through the two upper edge detectors and the switching signal, and after determining that the control switch is turned off Wave detection is performed to avoid misjudgment of valley detection.

本發明之一種波谷偵測器，用以偵測一電源轉換器之一控制開關的電壓波谷，且該控制開關受一開關訊號控制，該波谷偵測器包含一輔助繞組、一截波電路、一延遲電路及一波谷偵測電路，該輔助繞組與該電源轉換器之一一次側繞組互感而產成一輔助感應電壓，該截波電路電性連接該輔助繞組，用以對該輔助感應電壓截波而產生一截波電壓，該延遲電路電性連接該截波電路，用以延遲該截波電壓，該波谷偵測電路，電性連接該延遲電路以接收延遲後之該截波電壓，該波谷偵測電路具有一過零偵測器、一第一上緣偵測器及一第二上緣偵測器，該過零偵測器用以偵測延遲後之該截波電壓的零點並輸出一比較訊號，該第一上緣偵測器用以偵測該比較訊號是否上升，以輸出一第一上緣偵測訊號，該第二上緣偵測器用以偵測該開關訊號是否上升，以輸出一第二上緣偵測訊號，其中該波谷偵測電路根據該比較訊號、該第一上緣偵測訊號、該第二上緣偵測訊號及該開關訊號偵測該輔助感應電壓的波谷。A valley detector of the present invention is configured to detect a voltage valley of a switch of a power converter, and the control switch is controlled by a switching signal, the valley detector includes an auxiliary winding, a clipping circuit, a delay circuit and a valley detecting circuit, the auxiliary winding and one of the primary windings of the power converter are mutually inductive to generate an auxiliary induced voltage, and the cutting circuit is electrically connected to the auxiliary winding for the auxiliary induced voltage The chopping circuit generates a chopping voltage, and the delay circuit is electrically connected to the chopping circuit for delaying the chopping voltage. The trough detecting circuit is electrically connected to the delay circuit to receive the delayed chopping voltage. The valley detecting circuit has a zero-crossing detector, a first upper edge detector and a second upper edge detector, wherein the zero-crossing detector detects the zero point of the delayed voltage after the delay And outputting a comparison signal, the first upper edge detector is configured to detect whether the comparison signal is rising to output a first upper edge detection signal, and the second upper edge detector is configured to detect whether the switching signal is rising. Output one The upper edge of the detection signal, wherein the trough detection circuit based on the comparison signal, the upper edge of the first detection signal, the second upper edge of the switch signal detection signal and detecting the induced voltage of the auxiliary valley.

本發明藉由該波谷偵測電路之該過零偵測器測得輔助感應電壓的零點，並分別透過該第一上緣偵測器、該第二上緣偵測器及該開關訊號確保該輔助感應電壓已上升及該控制開關已關閉，可避免零點的誤判，且由於該輔助感應電壓有經過該延遲電路延遲，其零點可代表為輔助感應電壓的波谷，以使該電源轉換器可達到谷值電壓切換。The zero-detection of the auxiliary induced voltage is detected by the zero-crossing detector of the valley detecting circuit, and is ensured by the first upper edge detector, the second upper edge detector and the switching signal respectively The auxiliary induced voltage has risen and the control switch is turned off to avoid false positives of the zero point, and since the auxiliary induced voltage is delayed by the delay circuit, its zero point can represent a valley of the auxiliary induced voltage, so that the power converter can reach Valley voltage switching.

請參閱第1圖，為本發明之一實施例，一種電源轉換裝置D之功能方塊圖，該電源轉換裝置D包含一電源S、一電源轉換器100、一波谷偵測器200、一控制電路300及一負載L。Please refer to FIG. 1 , which is a functional block diagram of a power conversion device D. The power conversion device D includes a power source S, a power converter 100, a valley detector 200, and a control circuit. 300 and a load L.

請參閱第1及2圖，該電源S可為市電或是其他可輸出交流電之發電裝置，該電源S用以輸出一交流電源V _ac，該電源轉換器100電性連接該電源S以接收該交流電源V _ac，並對該交流電源V _ac進行調整而輸出一穩定之直流電源V _dc，其中該電源轉換器100具有一橋式整流電路110、一一次側繞組120、一控制開關130、一二次側繞組140及一濾波電路150，該橋式整流電路110接收該交流電源V _ac，以對該交流電源V _ac進行整流，該一次側繞組120電性連接該橋式整流電路110，以接收該整流後之該交流訊號V _ac，該控制開關130與該一次側繞組120串聯，以對該一次側繞組120的電流路徑進行開關控制，該二次側繞組140與該一次側繞組120纏繞於同一導磁鐵芯上，而能互感而於該二次側繞組140生成一二次側電壓V _sec，該二次側電壓V _sec經由該濾波電路150濾波後即生成該直流電源V _dc而供給至該負載L。 Referring to Figures 1 and 2, the power source S can be a commercial power source or another power generating device that can output an alternating current. The power source S is used to output an AC power source V _ac , and the power converter 100 is electrically connected to the power source S to receive the power. V _ac power supply AC, and the AC power supply V _ac output a stable adjustment of the DC power supply V _dc, wherein the power converter 100 includes a bridge rectifier 110, a primary winding 120, a control switch 130, a secondary winding 140 and a filter circuit 150, the bridge rectifier circuit 110 receives the AC power source V _ac, for rectifying the AC power source V _ac, the primary winding 120 is electrically connected to the bridge rectifier circuit 110 to Receiving the rectified AC signal V _ac , the control switch 130 is connected in series with the primary side winding 120 to perform switching control on the current path of the primary side winding 120 , and the secondary side winding 140 is wound with the primary side winding 120 on the same magnetic core, and can be in the mutual inductance of the secondary winding 140 generates a voltage V _sec of the secondary side, the secondary side voltage of the DC power supply V _sec V _dc generated via the filter circuit 150 is supplied after filtering The load L.

較佳的，該電源轉換器100另包含有一電磁干擾濾波器 (Electromagnetic Interference Filte)160、一輸入濾波電路170及一輸出濾波電容180，該電磁干擾濾波器160電性連接該電源S，以濾除該電源S的雜訊，防止該控制開關130的高頻切換收到影響，該輸入濾波電路170電性連接該電磁干擾濾波器160，以降低總諧波失真(Total Harmonic Distortion)，該輸出濾波電容180電性連接該二次側繞組140，以濾除市電漣波。Preferably, the power converter 100 further includes an electromagnetic interference filter (Electromagnetic Interference Filte) 160, an input filter circuit 170 and an output filter capacitor 180. The electromagnetic interference filter 160 is electrically connected to the power source S for filtering. In addition to the noise of the power source S, the high frequency switching of the control switch 130 is prevented from being affected. The input filter circuit 170 is electrically connected to the electromagnetic interference filter 160 to reduce total harmonic distortion (Total Harmonic Distortion). The filter capacitor 180 is electrically connected to the secondary winding 140 to filter out the mains ripple.

請參閱第1及3圖，該波谷偵測器200具有一輔助繞組210、一截波電路220、一延遲電路230、一波谷偵測電路240及一電壓隨耦器250，該輔助繞組210與該電源轉換器100之該一次側繞組120及該二次側繞組140纏繞於相同之導磁鐵芯上，因此，該輔助繞組210亦與該一次側繞組120互感而產成一輔助感應電壓V _aux，其中該控制開關130關閉且該二次側繞組140放電完後，該一次側繞組120與該控制開關130之一寄生電容131產生一諧振，該諧振具有一諧振週期。 Referring to FIGS. 1 and 3, the valley detector 200 has an auxiliary winding 210, a clipping circuit 220, a delay circuit 230, a valley detecting circuit 240, and a voltage follower 250. The auxiliary winding 210 and The primary winding 120 and the secondary winding 140 of the power converter 100 are wound on the same magnetic core. Therefore, the auxiliary winding 210 also interacts with the primary winding 120 to generate an auxiliary induced voltage V _aux . After the control switch 130 is turned off and the secondary side winding 140 is discharged, the primary side winding 120 and the parasitic capacitance 131 of the control switch 130 generate a resonance, and the resonance has a resonance period.

該截波電路220電性連接該輔助繞組210，以對該輔助感應電壓V _aux截波而產生一截波電壓V _{aux_c}，在本實施例中，該截波電路220具有一限流元件221、一截波元件222及一分壓元件223，該限流元件221及該截波元件222與該輔助繞組210電性連接，該分壓元件223與該截波元件222並聯後，再與該限流元件221及該輔助繞組210串聯，其中，該限流元件221為一二極體，用以限制該輔助感應電壓V _aux的電流方向，該截波元件222為一稽納二極體，用以對該輔助感應電壓V _aux截波，該分壓元件223由兩個電阻串接而成，用以對該截波電壓V _{aux_c}進行分壓。 The chopper circuit 220 is electrically connected to the auxiliary winding 210 to intercept the auxiliary induced voltage V _aux to generate a cutoff voltage V _{aux —} _c . In the embodiment, the _chopper circuit 220 has a current limiting component 221 . a chopping element 222 and a voltage dividing element 223, the current limiting element 221 and the chopping element 222 are electrically connected to the auxiliary winding 210, and the voltage dividing element 223 is connected in parallel with the chopping element 222, and then The flow element 221 and the auxiliary winding 210 are connected in series, wherein the current limiting element 221 is a diode for limiting the current direction of the auxiliary induced voltage V _aux , and the chopping element 222 is a Zener diode. To cut off the auxiliary induced voltage V _aux , the voltage dividing element 223 is formed by connecting two resistors in series to divide the cutoff voltage V _{aux — c} .

該電壓隨耦器250與該截波電路220及該延遲電路230電性連接，該電壓隨耦器250由該截波電路220之該分壓元件223接收分壓後之該截波電壓V _{aux_div}，並將其傳送至該延遲電路230，由於該電壓隨耦器250具有高輸入阻抗及低輸出阻抗，在傳送訊號時可避免訊號的失真。 The voltage follower 250 is electrically connected to the _chopper circuit 220 and the delay circuit 230. The voltage follower 250 receives the divided voltage V _{aux_div} after being divided by the voltage dividing component 223 of the _chopper circuit 220. And transmitting it to the delay circuit 230, since the voltage follower 250 has a high input impedance and a low output impedance, the signal distortion can be avoided when transmitting the signal.

該延遲電路230經由該電壓隨耦器250電性連接該截波電路220，以接收分壓後之該截波電壓V _{aux_div}，該延遲電路230用以延遲分壓後之該截波電壓V _{aux_div}。請參閱第4圖，為該控制開關130之該寄生電容131的電壓V _coss、該一次側繞組120的電壓V _pri及該輔助繞組210之該輔助感應電壓V _aux之波形圖，可以看到該控制開關130之該寄生電容131的電壓V _coss為谷值時，該一次側繞組120的電壓V _pri為峰值，由於該輔助繞組210與該一次側繞組120纏繞於相同導磁鐵芯上，具有相同磁通量，但極性相反，因此，該輔助繞組210之該輔助感應電壓V _aux亦為谷值，而可偵測該輔助感應電壓V _aux的谷值代替該寄生電容131的電壓的谷值V _coss，以避免直接偵測該寄生電容131之谷值V _coss時，該波谷偵測器200接觸到該控制開關130關閉瞬間高頻振盪產生的高電壓而損壞。 The delay circuit 230 is electrically connected to the _chopper circuit 220 via the voltage follower 250 to receive the divided voltage V _{aux — div} , and the delay circuit 230 is configured to delay the divided voltage V _{aux — div} after being _divided. . Please refer to FIG. 4 , which is a waveform diagram of the voltage V _coss of the parasitic capacitor 131 of the control switch 130, the voltage V _{pri of} the primary winding 120, and the auxiliary induced voltage V _aux of the auxiliary winding 210. When the voltage V _coss of the parasitic capacitance 131 of the control switch 130 is a valley value, the voltage V _pri of the primary side winding 120 is a peak, since the auxiliary winding 210 and the primary side winding 120 are wound on the same core core, having the same flux, but opposite polarity, and therefore, the auxiliary winding of the auxiliary _aux the induced voltage V 210 also valley, the valley can detect the induced voltage V _aux auxiliary valley V _coss instead of the voltage of the parasitic capacitance 131, In order to avoid direct detection of the valley value V _{coss of} the parasitic capacitance 131, the valley detector 200 is damaged by the high voltage generated by the high frequency oscillation when the control switch 130 is turned off.

請再參閱第4圖，由於實務上晶片並無法偵測負電壓，因此，在本實施例中，是藉由該延遲電路230將該分壓後之輔助感應電壓V _aux延遲1/4個該諧振週期後，偵測其零點即可代表為該寄生電容131之電壓的谷值。 Please refer to FIG. 4 again. Since the negative voltage is not detected by the chip in practice, in the embodiment, the divided auxiliary voltage V _{aux is} delayed by 1/4 by the delay circuit 230. After the resonance period, the zero point is detected to represent the valley of the voltage of the parasitic capacitor 131.

請參閱第3圖，在本實施例中，該延遲電路230具有一延遲電阻231及一延遲電容232，該延遲電阻231之一端電性經由該電壓隨耦器250連接該分壓元件223以接收分壓後之該截波電壓V _{aux_div}，該延遲電阻231之另一端電性連接該過零偵測器241及該延遲電容232之一端，該延遲電容232之另一端接地。 Referring to FIG. 3, in the embodiment, the delay circuit 230 has a delay resistor 231 and a delay capacitor 232. One end of the delay resistor 231 is electrically connected to the voltage dividing component 223 via the voltage follower 250 to receive After the voltage is _divided , the other end of the delay resistor 232 is electrically connected to one end of the zero-crossing detector 241 and the delay capacitor 232, and the other end of the delay capacitor 232 is grounded.

請參閱第3圖，該波谷偵測電路240電性連接該延遲電路230以接收延遲後之該截波電壓V _{aux_d}，該波谷偵測電路240具有一過零偵測器241、一第一上緣偵測器242、一第二上緣偵測器243、一閂鎖器244及一邏輯單元245，該過零偵測器241用以偵測延遲後之該截波電壓V _{aux_d}的零點並輸出一比較訊號S _c，該第一上緣偵測器242用以偵測該比較訊號S _c是否上升，以輸出一第一上緣偵測訊號R _D1，該第二上緣偵測器243用以偵測該開關訊號SW是否上升，以輸出一第二上緣偵測訊號R _D2，該閂鎖器244具有一設定端244a、一重設端244b、一輸出端244c及一反向輸出端244d，該閂鎖器244之該設定端244a電性連接該第一上緣偵測器242，以接收該第一上緣偵測訊號R _D1，該閂鎖器244之該重設端244b電性連接該第二上緣偵測器243，以接收該第二上緣偵測訊號R _D2，該閂鎖器244之該輸出端244c輸出一輸出訊號O _p，該閂鎖器244之該反向輸出端244d輸出一反向輸出訊號O _{p_i}，該邏輯單元245接收該比較訊號S _c、該反向輸出訊號O _{p_i}及該開關訊號SW，以根據該比較訊號S _c、該第一上緣偵測訊號R _D1、該第二上緣偵測訊號R _D2及該開關訊號SW偵測波谷。 Referring to FIG. 3, the valley detecting circuit 240 is electrically connected to the delay circuit 230 to receive the delayed voltage V _{aux_d} . The valley detecting circuit 240 has a zero-crossing detector 241 and a first The edge detector 242, a second upper edge detector 243, a latch 244 and a logic unit 245, the zero-crossing detector 241 is configured to detect the zero point of the delayed voltage V _{aux_d} after the delay And outputting a comparison signal S _c , the first upper edge detector 242 is configured to detect whether the comparison signal S _c rises to output a first upper edge detection signal R _D1 , and the second upper edge detector 243 For detecting whether the switch signal SW is rising, to output a second upper edge detection signal R _D2 , the latch 244 has a set end 244a, a reset end 244b, an output end 244c and an inverted output end. 244d, the set end 244a of the latch 244 is electrically connected to the first upper edge detector 242 to receive the first upper edge detecting signal R _D1 , and the reset end 244 b of the latch 244 is electrically The second upper edge detector 243 is connected to receive the second upper edge detection signal R _D2 , and the output terminal 244c of the latch 244 outputs an input. A signal O _p, the inverting output of the latch 244 outputs an inverted output signal 244d O _{p_i,} the comparison logic unit 245 receives the signal S _c, the inverted output signal O _{p_i} and the switch signal SW, The trough is detected according to the comparison signal S _c , the first upper edge detection signal R _D1 , the second upper edge detection signal R _{D2 ,} and the switching signal SW.

請參閱第3圖，在本實施例中，較佳的，該過零偵測器241為一遲滯比較器，該過零偵測器241之一正極端241a接收延遲後之該截波電壓V _{aux_d}，該過零偵測器241之一負極端241b接收一參考電壓V _{aux_ref}，並輸出一比較訊號S _c，其中，該過零偵測器241根據該參考訊號V _{aux_ref}產生有一下臨界電壓及一上臨界電壓，當該延遲後之該截波電壓V _{aux_d}大於該上臨界電壓時，該比較訊號V _c為高電位，當該延遲後之該截波電壓V _{aux_d}小於該下臨界電壓時，該比較訊號V _c為低電位，藉由該遲滯比較器可避免訊號的微小振盪造成輸出之該比較訊號S _c的上下變換而導致零點的誤判。 Referring to FIG. 3, in the embodiment, the zero-crossing detector 241 is a hysteresis comparator. The positive terminal 241a of the zero-crossing detector 241 receives the delayed crest voltage V. _{Aux_d} , the negative terminal 241b of the zero-crossing detector 241 receives a reference voltage V _{aux_ref} and outputs a comparison signal S _c , wherein the zero-crossing detector 241 generates a threshold voltage according to the reference signal V _{aux — ref} and An upper threshold voltage, when the delayed crest voltage V _{aux — d is} greater than the upper threshold voltage, the comparison signal V _c is high, and when the delayed crest voltage V _{aux — d is} less than the lower threshold voltage, The comparison signal V _c is low, and the hysteresis comparator can avoid the slight fluctuation of the signal, causing the up-conversion of the comparison signal S _c of the output to cause a false determination of the zero point.

請參閱第5圖，該第一上緣偵測器242是由一反向器串242a及一邏輯元件242b電性連接而成，該反向器串242a接收該比較訊號S _c並輸出反向之該比較訊號S _{c_i}，其中該邏輯元件242b藉由該比較訊號S _c及反向之該比較訊號S _{c_i}判斷該比較訊號S _c是否上升，由於該反向器串242a中各個反向器於處理訊號時會有些許的延遲，再藉由該邏輯元件242b為一及閘，當該比較訊號S _c上升至高電位且反向之該比較訊號S _{c_i}因延遲尚未下降至低電位時，該及閘輸出一高電位訊號，即代表該比較訊號之上緣。請參閱第6圖，該第二上緣偵測器243由一反向器串243a及一邏輯元件243b組成，該反向器串243a接收該開關訊號SW並輸出反向之該開關訊號SW _i，相同地，藉由該反向器串243a中各個反向器處理訊號的延遲搭配該邏輯元件243b即可測得該開關訊號訊號SW的上緣。 Referring to FIG. 5, the first upper edge detector 242 is electrically connected by an inverter string 242a and a logic element 242b. The inverter string 242a receives the comparison signal S _c and outputs a reverse direction. comparison of the signal S _{c_i,} wherein the logic elements 242b of the comparison by the comparison signal S _C and S signal determines the reverse of _{c_i} comparison signal S _C has risen, due to the string of the inverter 242a to the respective inverter There is a slight delay in processing the signal, and the logic component 242b is a NAND gate. When the comparison signal S _c rises to a high potential and the reverse comparison signal S _{c_i} has not dropped to a low potential due to the delay, The gate outputs a high potential signal, which represents the upper edge of the comparison signal. Referring to FIG. 6, the second upper edge detector 243 is composed of an inverter string 243a and a logic element 243b. The inverter string 243a receives the switching signal SW and outputs the inverted switching signal SW _i. Similarly, the upper edge of the switching signal signal SW can be measured by matching the delay of each inverter processing signal in the inverter string 243a with the logic element 243b.

請參閱第3及4圖，該波谷偵測器200的作動方式為：當該控制開關130關閉且該二次側繞組140放電完畢時，該輔助繞組210與該控制開關130之該寄生電容131會產生諧振，使該輔助感應電壓V _aux振盪，而該輔助感應電壓V _aux由該限流元件221限流及該截波元件222截波後產生截波電壓V _{aux_c}，該截波電壓V _{aux_c}再經由該分壓元件223分壓，分壓後之該截波電壓V _{aux_div}經由該電壓隨耦器250傳送至該延遲電路230，並將分壓後之該截波電壓V _{aux_div}延遲1/4個振盪週期後傳送至該過零偵測器241之該正極端241a，由該過零偵測器241比對延遲後之該截波電壓V _{aux_d}及該參考訊號V _{aux_ref}後輸出該比較訊號S _c，其中，當延遲後之該截波電壓V _{aux_d}大於該上臨界電壓時，該比較訊號S _c上升至高電位，當延遲後之該截波電壓V _{aux_d}小於該下臨界電壓時，該比較訊號S _c下降至低電位，因此，當該比較訊號S _c下降至低電位時可表示延遲後之該截波電壓V _{aux_d}的零點。該比較訊號S _c傳送至該邏輯單元245及該第一上緣偵測器242，該第一上緣偵測器242用以測得該比較訊號S _c是否已由低電位上升至高電位，該第一上緣偵測器242之該第一上緣偵測訊號R _D1輸入該閂鎖器224之該設定端244a，以確保該輔助感應電壓V _aux有上升至高電壓且該二次側繞組140正在放電後，再判斷放電完畢後該輔助感應電壓V _aux的波谷訊號。該第二上緣偵測器243接收該開關訊號SW以偵測該開關訊號SW是否上升至高電位，其中，該第二上緣偵測器243之該第二上緣偵測訊號R _D2輸入該閂鎖器244之該重設端244b，以重置該輔助感應電壓V _aux有上升後再進行波谷偵測的條件，而在下一次該控制開關130關閉後才可以進行波谷的偵測。 Referring to FIGS. 3 and 4, the valley detector 200 is operated in such a manner that when the control switch 130 is turned off and the secondary winding 140 is discharged, the parasitic capacitance of the auxiliary winding 210 and the control switch 130 is 131. Resonance is generated to oscillate the auxiliary induced voltage V _aux , and the auxiliary induced voltage V _aux is limited by the current limiting element 221 and the chopping element 222 is chopped to generate a cutoff voltage V _{aux — c} , the cutoff voltage V _{aux — c} The partial voltage component 223 is further divided, and the divided voltage V _{aux_div} is transmitted to the delay circuit 230 via the voltage follower 250, and the divided voltage V _{aux_div is} delayed by 1/4 after the voltage _division. After the oscillation period is transmitted to the positive terminal 241a of the zero-crossing detector 241, the zero-crossing detector 241 compares the delayed voltage V _{aux_d} and the reference signal V _{aux_ref} to output the comparison signal S. _c, where, when the cut-wave voltage _V aux_d after the delay is greater than the upper threshold voltage, the comparison signal S _c to rise to a high potential, when the rear of the delay of the chopped wave voltage _V aux_d less than the lower threshold voltage, the comparison signal S _c dropped to the low potential, and therefore, when the ratio This may represent a truncated wave voltage _V aux_d delay after the zero point signal S _c dropped to the low potential. The comparison signal S _{c is} sent to the logic unit 245 and the first upper edge detector 242, and the first upper edge detector 242 is configured to detect whether the comparison signal S _c has risen from a low potential to a high potential. The first upper edge detection signal R _D1 of the first upper edge detector 242 is input to the set terminal 244a of the latch 224 to ensure that the auxiliary induced voltage V _aux has risen to a high voltage and the secondary winding 140 After the discharge is being performed, the valley signal of the auxiliary induced voltage V _aux after the discharge is completed is judged. The second edge detecting device 243 receives the switching signal SW to detect whether the switching signal SW rises to a high potential, wherein the second upper edge detecting signal R _D2 of the second upper edge detector 243 inputs the The reset terminal 244b of the latch 244 resets the condition that the auxiliary induced voltage V _aux rises before performing the valley detection, and the trough detection can be performed after the next time the control switch 130 is turned off.

請參閱第7圖，為該閂鎖器244之真值表，其中，當該開關訊號SW下降至低電位關閉該控制開關130且該比較訊號S _c上升至高電位時，該閂鎖器244之該反向輸出端244d輸出之該反向輸出訊號O _{p_i}為低電位，該反向輸出訊號O _{p_i}輸入至該邏輯單元245，該邏輯單元245另接收該比較訊號S _c及該開關訊號SW，其中，由於該邏輯單元245為反或閘，因此只有在該反向輸出訊號O _{p_i}、比較訊號S _c及該開關訊號SW均為低電位，也就是該過零偵測器241測得零電位、該比較訊號S _c已由低電位轉至高電位及該開關訊號SW已由高電位轉至低電位值時，該邏輯單元245才會輸出一高電位之偵測訊號S _d，當該邏輯單元245輸出高電位之偵測訊號S _d即代表該延遲後之該輔助感應電壓V _{aux_d}在諧振中到達零點，也就等於了該輔助感應電壓V _aux及該控制開關130之該寄生電容131電壓V _coss的波谷點，此時進行該控制開關130的開啟，可將切換損失降至最低。 Please refer to FIG. 7 , which is a truth table of the latch 244, wherein when the switch signal SW falls to a low level to turn off the control switch 130 and the comparison signal S _c rises to a high level, the latch 244 the inverted output terminal 244d of the output signal O _{p_i} inverted output to a low level, the inverted output signal O _{p_i} input to the logic unit 245, the logic unit 245 further receives the comparison signal S _c and the switch signal SW, Wherein, since the logic unit 245 is a reverse OR gate, only the reverse output signal _{Op_i} , the comparison signal S _c and the switching signal SW are low, that is, the zero-crossing detector 241 measures the zero potential. When the comparison signal S _c has turned from a low potential to a high potential and the switching signal SW has turned from a high potential to a low potential value, the logic unit 245 outputs a high potential detection signal S _d when the logic unit The 245 output high-potential detection signal S _d represents that the auxiliary induced voltage V _{aux_d} reaches the zero point in the resonance after the delay, which is equal to the auxiliary induced voltage V _aux and the parasitic capacitance 131 of the control switch 130. _coss valley points, this time into the The control switch 130 is turned on, the switching loss can be reduced to a minimum.

請參閱第3圖，由於該波谷偵測器200所測得之波谷訊號是用以重新開啟該控制開關130，但由於該電源轉換器100在某些操作點下可能會發生該控制開關130已關閉且交流電電壓亦過零點，卻因能量太小而無法送到二次側造成波谷訊號，導致該控制開關130無法重新導通。較佳的，該波谷偵測電路240另具有一重啟電路260，該重啟電路260電性連接該閂鎖器244，且該重啟電路260接收該開關訊號SW及該閂鎖器244輸出之該輸出訊號O _p，該重啟電路260依據該開關訊號SW及該輸出訊號O _p輸出一重啟訊號R _e，以啟動該電源轉換器100之該控制開關130。 Referring to FIG. 3, since the valley signal measured by the valley detector 200 is used to re-open the control switch 130, the control switch 130 may occur due to the power converter 100 being operated at certain operating points. When the AC voltage is turned off and the AC voltage is too zero, the energy is too small to be sent to the secondary side to cause a valley signal, so that the control switch 130 cannot be turned back on. Preferably, the valley detecting circuit 240 further has a restart circuit 260. The restart circuit 260 is electrically connected to the latch 244, and the restart circuit 260 receives the switch signal SW and the output of the latch 244. signal O _p, the restart circuit 260 outputs a restart signal R _e according to the switch signal SW, and the output signal O _p, 130 to activate the control switch 100 of the power converter.

其中，該重啟電路260具有一邏輯閘261、一開關262、一電流源263、一充電電容264及一比較器265，該邏輯閘261接收該開關訊號SW及該輸出訊號O _p並輸出一開關控制訊號S _{w_c}，該開關262接收該開關控制訊號S _{w_c}並受該開關控制訊號S _{w_c}控制，其中。該電流源263電性連接該開關262及該充電電容264，該開關262與該充電電容264並聯，該比較器265之一正極端265a接收該充電電容264之一電壓V _c，並與一重啟參考電壓V _{r_ref}比較，該比較器265輸出該重啟訊號R _e。 The restart circuit 260 has a logic gate 261, a switch 262, a current source 263, a charging capacitor 264 and a comparator 265. The logic gate 261 receives the switching signal SW and the output signal _Op and outputs a switch. The control signal S _{w_c} receives the switch control signal S _{w — c} and is controlled by the switch control signal S _{w — c} . The current source 263 is electrically connected to the switch 262 and the charging capacitor 264. The switch 262 is connected in parallel with the charging capacitor 264. One of the positive terminals 265a of the comparator 265 receives a voltage V _{c of} the charging capacitor 264 and is restarted. the reference voltage _V r_ref comparator 265 outputs the restart signal of the comparator R _e.

請參閱第3圖，在本實施例中，該邏輯閘261為一反或閘，當該開關訊號SW及該輸出訊號O _p均為低電位時該開關控制訊號S _{w_c}才為高電位，其餘的情況下該開關控制訊號S _{w_c}為低電位。該開關262為一開關閘，當該開關控制訊號S _{w_c}為低電位時，該開關262導通，該充電電容264之跨壓為零，其電壓V _c並未上升，反之，當該開關控制訊號S _{w_c}為高電位時，該開關262關閉，該電流源263輸出之電流流經該充電電容264使其電壓V _c上升，而當該充電電容264之電壓V _c上升超過該重啟參考電壓V _{r_ref}時，該比較器265輸出之該重啟訊號R _e上升至高電位。 See Figure 3, in the present embodiment, the logic gate is a NOR gate 261, when the switch signal SW, and the output signal O _p are both the low potential of the switch control signal _S w_c only for the high level, the remaining In the case of the switch control signal S _{w — c} is low. The switch 262 is a switch gate. When the switch control signal S _{w_c} is low, the switch 262 is turned on, the voltage across the charging capacitor 264 is zero, and the voltage V _c does not rise. Conversely, when the switch controls the signal When S _{w_c} is high, the switch 262 is turned off, and the current output by the current source 263 flows through the charging capacitor 264 to increase the voltage V _c , and when the voltage V _{c of} the charging capacitor 264 rises above the restart reference voltage V _{r — ref} At this time, the restart signal R _e outputted by the comparator 265 rises to a high level.

請再參閱第3圖，該波谷偵測電路240之一邏輯元件246接收該邏輯單元245輸出之該偵測訊號S _d及該比較器265輸出之該重啟訊號R _e，在本實施例中，該邏輯元件246為一反或閘，當該偵測訊號S _d或該重啟訊號R _e為高電位或是兩者均為高電位時，該邏輯元件246輸出低電位之波谷訊號S _v至該控制電路300，進而重新啟動該控制開關130。 Referring to FIG. 3, the logic component 246 of the valley detecting circuit 240 receives the detection signal S _d outputted by the logic unit 245 and the restart signal R _e output by the comparator 265. In this embodiment, the logic element 246 is a NOR gate, when the detection signal S _d R _e or the restart signal to the high potential or a potential when both are high, the output of logic element 246 valley signal S _v to the low level of The control circuit 300, in turn, restarts the control switch 130.

本發明藉由該波谷偵測電路240之該過零偵測器241測得輔助感應電壓V _aux的零點，並分別透過該第一上緣偵測器242、該第二上緣偵測器243及該開關訊號SW確保該輔助感應電壓V _aux已上升及該控制開關130已關閉，可避免零點的誤判，且由於該輔助感應電壓V _aux有經過該延遲電路230延遲，其零點可代表為輔助感應電壓V _aux的波谷，以使該電源轉換器100達到谷值電壓切換。 The zero-crossing detector 241 of the valley detecting circuit 240 detects the zero point of the auxiliary sensing voltage V _aux and transmits the first upper edge detector 242 and the second upper edge detector 243 respectively. And the switching signal SW ensures that the auxiliary induced voltage V _aux has risen and the control switch 130 is turned off, the false positive of the zero point can be avoided, and since the auxiliary induced voltage V _aux is delayed by the delay circuit 230, the zero point can be represented as auxiliary The valley of the voltage V _aux is induced to cause the power converter 100 to reach the valley voltage switching.

本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧電源轉換器
110‧‧‧橋式整流電路
120‧‧‧一次側繞組
130‧‧‧控制開關
131‧‧‧寄生電容
140‧‧‧二次側繞組
150‧‧‧濾波電路
160‧‧‧電磁干擾濾波器
170‧‧‧輸入濾波電路
180‧‧‧輸出濾波電容
200‧‧‧波谷偵測器
210‧‧‧輔助繞組
220‧‧‧截波電路
221‧‧‧限流元件
222‧‧‧截波元件
223‧‧‧分壓元件
230‧‧‧延遲電路
231‧‧‧延遲電阻
232‧‧‧延遲電容
240‧‧‧波谷偵測電路
241‧‧‧過零偵測器
241a‧‧‧正極端
241b‧‧‧負極端
242‧‧‧第一上緣偵測器
242a‧‧‧反向器串
242b‧‧‧邏輯元件
243‧‧‧第二上緣偵測器
243a‧‧‧反向器串
243b‧‧‧邏輯元件
244‧‧‧閂鎖器
244a‧‧‧設定端
244b‧‧‧重設端
244c‧‧‧輸出端
244d‧‧‧反向輸出端
245‧‧‧邏輯單元
246‧‧‧邏輯元件
250‧‧‧電壓隨耦器
260‧‧‧重啟電路
261‧‧‧邏輯閘
262‧‧‧開關
263‧‧‧電流源
264‧‧‧充電電容
265‧‧‧比較器
265a‧‧‧正極端
D‧‧‧電源轉換裝置
S‧‧‧電源
V_ac‧‧‧交流電源
V_dc‧‧‧直流電源
L‧‧‧負載
SW‧‧‧開關訊號
S_v‧‧‧波谷訊號
V_pri‧‧‧一次側電壓
V_sec‧‧‧二次側電壓
V_coss‧‧‧寄生電容之電壓
V_aux‧‧‧輔助感應電壓
V_{aux_c}‧‧‧截波電壓
V_{aux_div}‧‧‧分壓之截波電壓
V_{aux_d}‧‧‧延遲之截波電壓
V_{aux_ref}‧‧‧參考電壓
S_c‧‧‧比較訊號
R_D1‧‧‧第一上緣偵測訊號
R_D2‧‧‧第二上緣偵測訊號
O_p‧‧‧輸出訊號
O_{p_i}‧‧‧反向輸出訊號
S_d‧‧‧偵測訊號
VDD‧‧‧電壓源
R_e‧‧‧重啟訊號
V_{r_ref}‧‧‧重啟參考訊號
S_{c_i}‧‧‧反向比較訊號
SW_i‧‧‧反向開關訊號
S_{w_c}‧‧‧開關控制訊號
V_c‧‧‧充電電容之電壓100‧‧‧Power Converter
110‧‧‧Bridge rectifier circuit
120‧‧‧ primary winding
130‧‧‧Control switch
131‧‧‧Parasitic capacitance
140‧‧‧secondary winding
150‧‧‧Filter circuit
160‧‧‧Electromagnetic interference filter
170‧‧‧Input filter circuit
180‧‧‧ Output Filter Capacitor
200‧‧‧ Valley Detector
210‧‧‧Auxiliary winding
220‧‧‧Chopper circuit
221‧‧‧ Current limiting components
222‧‧‧Chopping components
223‧‧‧Dividing element
230‧‧‧delay circuit
231‧‧‧Delay resistor
232‧‧‧Delay Capacitance
240‧‧‧ Valley Detection Circuit
241‧‧‧ Zero-crossing detector
241a‧‧‧ positive end
241b‧‧‧Negative end
242‧‧‧First upper edge detector
242a‧‧‧ reverser string
242b‧‧‧Logical components
243‧‧‧Second upper edge detector
243a‧‧‧inverter string
243b‧‧‧Logical components
244‧‧‧Latch
244a‧‧‧Setting end
244b‧‧‧Reset
244c‧‧‧output
244d‧‧‧inverted output
245‧‧‧Logical unit
246‧‧‧Logical components
250‧‧‧Voltage follower
260‧‧‧Restart circuit
261‧‧‧Logic gate
262‧‧‧ switch
263‧‧‧current source
264‧‧‧Charging capacitor
265‧‧‧ comparator
265a‧‧‧ positive end
D‧‧‧Power conversion device
S‧‧‧ power supply
V _ac ‧‧‧AC power supply
V _dc ‧‧‧DC power supply
L‧‧‧load
SW‧‧‧Switch signal
S _v ‧‧‧谷谷信号号
V _pri ‧‧‧ primary side voltage
V _sec ‧‧‧secondary voltage
V _coss ‧‧‧Variable capacitance voltage
V _aux ‧‧‧Auxiliary induced voltage
V _{aux_c ‧‧‧Chop} voltage
V _{aux_div ‧ ‧} divided voltage cutoff voltage
V _{aux_d} ‧‧‧ delayed chopping voltage
V _{aux_ref ‧‧‧reference} voltage
S _c ‧‧‧ comparison signal
R _D1 ‧‧‧first upper edge detection signal
R _D2 ‧‧‧Second upper edge detection signal
O _p ‧‧‧ output signal
O _{p_i} ‧‧‧inverted output signal
S _d ‧‧‧detection signal
VDD‧‧‧voltage source
R _e ‧‧‧Restart signal
V _{r_ref ‧‧‧Restart} reference signal
S _{c_i} ‧‧‧reverse comparison signal
SW _i ‧‧‧reverse switch signal
S _{w_c} ‧‧‧ switch control signal
V _c ‧‧‧Voltage of charging capacitor

第1圖：依據本發明之一實施例，一電源轉換裝置的功能方塊圖。第2圖：依據本發明之一實施例，一電源轉換器的電路圖。第3圖：依據本發明之一實施例，一波谷偵測器的電路圖。第4圖：依據本發明之一實施例，控制開關之寄生電容的電壓、一次側繞組的電壓及輔助感應電壓的波形圖。第5圖：依據本發明之一實施例，一第一上緣偵測電路的電路圖。第6圖：依據本發明之一實施例，一第二上緣偵測電路的電路圖。第7圖：依據本發明之一實施例，一閂鎖器的真值表。Figure 1 is a functional block diagram of a power conversion apparatus in accordance with an embodiment of the present invention. Figure 2 is a circuit diagram of a power converter in accordance with an embodiment of the present invention. Figure 3 is a circuit diagram of a valley detector in accordance with an embodiment of the present invention. Fig. 4 is a waveform diagram showing the voltage of the parasitic capacitance of the switch, the voltage of the primary side winding, and the auxiliary induced voltage according to an embodiment of the present invention. Figure 5 is a circuit diagram of a first upper edge detecting circuit in accordance with an embodiment of the present invention. Figure 6 is a circuit diagram of a second upper edge detecting circuit in accordance with an embodiment of the present invention. Figure 7: A truth table of a latch in accordance with an embodiment of the present invention.

200‧‧‧波谷偵測器 200‧‧‧ Valley Detector

210‧‧‧輔助繞組 210‧‧‧Auxiliary winding

220‧‧‧截波電路 220‧‧‧Chopper circuit

221‧‧‧限流元件 221‧‧‧ Current limiting components

222‧‧‧截波元件 222‧‧‧Chopping components

223‧‧‧分壓元件 223‧‧‧Dividing element

230‧‧‧延遲電路 230‧‧‧delay circuit

231‧‧‧延遲電阻 231‧‧‧Delay resistor

232‧‧‧延遲電容 232‧‧‧Delay Capacitance

240‧‧‧波谷偵測電路 240‧‧‧ Valley Detection Circuit

241‧‧‧過零偵測器 241‧‧‧ Zero-crossing detector

241a‧‧‧正極端 241a‧‧‧ positive end

241b‧‧‧負極端 241b‧‧‧Negative end

242‧‧‧第一上緣偵測器 242‧‧‧First upper edge detector

243‧‧‧第二上緣偵測器 243‧‧‧Second upper edge detector

244‧‧‧閂鎖器 244‧‧‧Latch

244a‧‧‧設定端 244a‧‧‧Setting end

244b‧‧‧重設端 244b‧‧‧Reset

244c‧‧‧輸出端 244c‧‧‧output

244d‧‧‧反向輸出端 244d‧‧‧inverted output

245‧‧‧邏輯單元 245‧‧‧Logical unit

246‧‧‧邏輯元件 246‧‧‧Logical components

250‧‧‧電壓隨耦器 250‧‧‧Voltage follower

260‧‧‧重啟電路 260‧‧‧Restart circuit

261‧‧‧邏輯閘 261‧‧‧Logic gate

262‧‧‧開關 262‧‧‧ switch

263‧‧‧電流源 263‧‧‧current source

264‧‧‧充電電容 264‧‧‧Charging capacitor

265‧‧‧比較器 265‧‧‧ comparator

265a‧‧‧正極端 265a‧‧‧ positive end

SW‧‧‧開關訊號 SW‧‧‧Switch signal

S_v‧‧‧波谷訊號 S _v ‧‧‧谷谷信号号

V_aux‧‧‧輔助感應電壓 V _aux ‧‧‧Auxiliary induced voltage

V_{aux_c}‧‧‧截波電壓 V _{aux_c ‧‧‧Chop} voltage

V_{aux_div}‧‧‧分壓之截波電壓 V _{aux_div ‧ ‧} divided voltage cutoff voltage

V_{aux_d}‧‧‧延遲之截波電壓 V _{aux_d} ‧‧‧ delayed chopping voltage

V_{aux_ref}‧‧‧參考電壓 V _{aux_ref ‧‧‧reference} voltage

S_c‧‧‧比較訊號 S _c ‧‧‧ comparison signal

R_D1‧‧‧第一上緣偵測訊號 R _D1 ‧‧‧first upper edge detection signal

R_D2‧‧‧第二上緣偵測訊號 R _D2 ‧‧‧Second upper edge detection signal

O_p‧‧‧輸出訊號 O _p ‧‧‧ output signal

O_{p_i}‧‧‧反向輸出訊號 O _{p_i} ‧‧‧inverted output signal

S_d‧‧‧偵測訊號 S _d ‧‧‧detection signal

R_e‧‧‧重啟訊號 R _e ‧‧‧Restart signal

V_{r_ref}‧‧‧重啟參考訊號 V _{r_ref ‧‧‧Restart} reference signal

S_{w_c}‧‧‧開關控制訊號 S _{w_c} ‧‧‧ switch control signal

V_c‧‧‧充電電容之電壓 V _c ‧‧‧Voltage of charging capacitor

VDD‧‧‧電壓源 VDD‧‧‧voltage source

Claims

一種波谷偵測器，用以偵測一電源轉換器之一控制開關的電壓波谷，該控制開關受一開關訊號控制，該波谷偵測器包含：一輔助繞組，與該電源轉換器之一一次側繞組互感而產成一輔助感應電壓；一截波電路，電性連接該輔助繞組，用以對該輔助感應電壓截波而產生一截波電壓；一延遲電路，電性連接該截波電路，用以延遲該截波電壓；以及一波谷偵測電路，電性連接該延遲電路以接收延遲後之該截波電壓，該波谷偵測電路具有一過零偵測器、一第一上緣偵測器及一第二上緣偵測器，該過零偵測器用以偵測延遲後之該截波電壓的零點並輸出一比較訊號，該第一上緣偵測器用以偵測該比較訊號是否上升，以輸出一第一上緣偵測訊號，該第二上緣偵測器用以偵測該開關訊號是否上升，以輸出一第二上緣偵測訊號，其中該波谷偵測電路根據該比較訊號、該第一上緣偵測訊號、該第二上緣偵測訊號及該開關訊號偵測該輔助感應電壓的波谷。A valley detector for detecting a voltage valley of a switch of a power converter, the control switch being controlled by a switching signal, the valley detector comprising: an auxiliary winding, and one of the power converters The secondary winding has a mutual inductance to generate an auxiliary induced voltage; a cut-off circuit electrically connected to the auxiliary winding for generating a cut-off voltage for the auxiliary induced voltage cutoff; and a delay circuit electrically connecting the cut-off circuit And a valley detecting circuit electrically connected to the delay circuit to receive the delayed cutoff voltage, the valley detecting circuit having a zero-crossing detector and a first upper edge a detector and a second edge detector for detecting a zero point of the delayed voltage after the delay and outputting a comparison signal, wherein the first edge detector is configured to detect the comparison Whether the signal is rising to output a first upper edge detection signal, and the second upper edge detector is configured to detect whether the switching signal is rising to output a second upper edge detection signal, wherein the valley detection circuit is based on The comparison signal The first upper edge detection signal, the second upper edge detection signal, and the switch signal detect a valley of the auxiliary induced voltage.

如申請專利範圍第1項所述之波谷偵測器，其中該電源轉換器具有一控制開關，該控制開關電性連接該一次側繞組，其中該控制開關關閉且該二次側繞組放電完後，該一次側繞組與該控制開關之一寄生電容產生一諧振，該諧振具有一諧振週期。The valley detector of claim 1, wherein the power converter has a control switch electrically connected to the primary side winding, wherein the control switch is turned off and the secondary side winding is discharged, The primary side winding generates a resonance with a parasitic capacitance of one of the control switches, the resonance having a resonant period.

如申請專利範圍第2項所述之波谷偵測器，其中該延遲電路所延遲的時間為1/4個該諧振週期。The valley detector of claim 2, wherein the delay circuit delays by 1/4 of the resonant period.

如申請專利範圍第1項所述之波谷偵測器，其中該截波電路具有一限流元件及一截波元件，該限流元件及該截波元件與該輔助繞組電性連接，該限流元件用以限制該輔助感應電壓的電流方向，該截波元件用以對該輔助感應電壓截波。The trough detector of claim 1, wherein the chopping circuit has a current limiting component and a chopping component, and the current limiting component and the chopping component are electrically connected to the auxiliary winding. The flow element is configured to limit a current direction of the auxiliary induced voltage, and the chopping element is configured to intercept the auxiliary induced voltage.

如申請專利範圍第4項所述之波谷偵測器，其中該截波元件為稽納二極體。The trough detector of claim 4, wherein the chopping element is a Jensen diode.

如申請專利範圍第4或5項所述之波谷偵測器，其中該截波電路另具有一分壓元件，該分壓元件與該截波元件並聯後，再與該限流元件及該輔助繞組串聯，該分壓元件用以對該截波電壓進行分壓。The trough detector of claim 4, wherein the chopping circuit further has a voltage dividing component, the voltage dividing component is connected in parallel with the chopping component, and the current limiting component and the auxiliary The windings are connected in series, and the voltage dividing element is used to divide the chopping voltage.

如申請專利範圍第6項所述之波谷偵測器，其另包含一電壓隨耦器，該電壓隨耦器與該截波電路及該延遲電路電性連接，該電壓隨耦器接收分壓後之該截波電壓，並將其傳送至該延遲電路。The valley detector of claim 6, further comprising a voltage follower, the voltage follower is electrically connected to the chopper circuit and the delay circuit, and the voltage is received by the coupler. This cutoff voltage is then passed to the delay circuit.

如申請專利範圍第1項所述之波谷偵測器，其中該延遲電路具有一延遲電阻及一延遲電容，該延遲電阻之一端接收該截波電壓，該延遲電阻之另一端電性連接該過零偵測器及該延遲電容之一端，該延遲電容之另一端接地。The wavelength detector of claim 1, wherein the delay circuit has a delay resistor and a delay capacitor, and the one end of the delay resistor receives the cutoff voltage, and the other end of the delay resistor is electrically connected to the The zero detector and one end of the delay capacitor are grounded at the other end of the delay capacitor.

如申請專利範圍第6項所述之波谷偵測器，其中該延遲電路具有一延遲電阻及一延遲電容，該延遲電阻之一端電性連接該分壓元件以接收分壓後之該截波電壓，該延遲電阻之另一端電性連接該過零偵測器及該延遲電容之一端，該延遲電容之另一端接地。The wavelength detector of claim 6, wherein the delay circuit has a delay resistor and a delay capacitor, and one end of the delay resistor is electrically connected to the voltage dividing component to receive the divided voltage. The other end of the delay resistor is electrically connected to one end of the zero-crossing detector and the delay capacitor, and the other end of the delay capacitor is grounded.

如申請專利範圍第1項所述之波谷偵測器，其中該過零偵測器為一遲滯比較器，該過零偵測器之一正極端接收延遲後之該截波電壓，該過零偵測器之一負極端接收一參考電壓。The valley detector of claim 1, wherein the zero-crossing detector is a hysteresis comparator, and the positive terminal of one of the zero-crossing detectors receives the delayed chopping voltage, the zero-crossing One of the detectors receives a reference voltage at the negative terminal.

如申請專利範圍第1項所述之波谷偵測器，其中該第一上緣偵測器由一反向器串及一邏輯元件電性連接而成，該反向器串接收該比較訊號並輸出反向之該比較訊號，該邏輯元件藉由該比較訊號及反向之該比較訊號判斷該比較訊號是否上升。The trough detector of claim 1, wherein the first upper edge detector is electrically connected by an inverter string and a logic component, and the inverter string receives the comparison signal and The comparison signal is outputted, and the logic component determines whether the comparison signal is raised by the comparison signal and the comparison signal reversed.

如申請專利範圍第1項所述之波谷偵測器，其中該波谷偵測電路具有一閂鎖器及一邏輯單元，該閂鎖器之一設定端電性連接該第一上緣偵測器，該閂鎖器之一重設端電性連接該第二上緣偵測器，該閂鎖器輸出一輸出訊號及一反向輸出訊號，該邏輯單元接收該比較訊號、該反向輸出訊號及該開關訊號。The trough detector of claim 1, wherein the trough detection circuit has a latch and a logic unit, and one of the latches is electrically connected to the first upper edge detector. One of the latches is electrically connected to the second upper edge detector, and the latch outputs an output signal and a reverse output signal, and the logic unit receives the comparison signal, the reverse output signal, and The switch signal.

如申請專利範圍第12項所述之波谷偵測器，其另包含一重啟電路，該重啟電路電性連接該閂鎖器，且該重啟電路接收該開關訊號及該閂鎖器輸出之該輸出訊號，該重啟電路依據該開關訊號及該輸出訊號輸出一重啟訊號，以啟動該電源轉換器之一控制開關。The valley detector of claim 12, further comprising a restart circuit electrically connected to the latch, and the restart circuit receives the switch signal and the output of the latch output The signal, the restart circuit outputs a restart signal according to the switch signal and the output signal to activate one of the power converter control switches.

如申請專利範圍第13項所述之波谷偵測器，其中該重啟電路具有一邏輯閘、一開關、一電流源、一充電電容及一比較器，該邏輯閘接收該開關訊號及該輸出訊號並輸出一開關控制訊號，該開關接收該開關控制訊號並受該開關控制訊號控制，該電流源電性連接該開關及該充電電容，該開關與該充電電容並聯，該比較器之一正極端接收該充電電容之一電壓，並與一重啟參考電壓比較，該比較器輸出該重啟訊號。The valley detector of claim 13, wherein the restart circuit has a logic gate, a switch, a current source, a charging capacitor and a comparator, and the logic gate receives the switching signal and the output signal And outputting a switch control signal, the switch receives the switch control signal and is controlled by the switch control signal, the current source is electrically connected to the switch and the charging capacitor, the switch is connected in parallel with the charging capacitor, and one of the positive ends of the comparator Receiving a voltage of the charging capacitor and comparing it with a restart reference voltage, the comparator outputs the restart signal.