TWI604535B - Method for fabricating a graphene field effect transistor - Google Patents
Method for fabricating a graphene field effect transistor Download PDFInfo
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- TWI604535B TWI604535B TW105132624A TW105132624A TWI604535B TW I604535 B TWI604535 B TW I604535B TW 105132624 A TW105132624 A TW 105132624A TW 105132624 A TW105132624 A TW 105132624A TW I604535 B TWI604535 B TW I604535B
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims description 77
- 229910021389 graphene Inorganic materials 0.000 title claims description 63
- 238000000034 method Methods 0.000 title claims description 20
- 230000005669 field effect Effects 0.000 title claims description 18
- 239000010410 layer Substances 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 22
- 229910052799 carbon Inorganic materials 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 11
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- -1 carbon ions Chemical class 0.000 claims description 4
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 239000002244 precipitate Substances 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 229910003468 tantalcarbide Inorganic materials 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- GPMBECJIPQBCKI-UHFFFAOYSA-N germanium telluride Chemical compound [Te]=[Ge]=[Te] GPMBECJIPQBCKI-UHFFFAOYSA-N 0.000 claims description 3
- UNASZPQZIFZUSI-UHFFFAOYSA-N methylidyneniobium Chemical compound [Nb]#C UNASZPQZIFZUSI-UHFFFAOYSA-N 0.000 claims description 3
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 3
- WXANAQMHYPHTGY-UHFFFAOYSA-N cerium;ethyne Chemical compound [Ce].[C-]#[C] WXANAQMHYPHTGY-UHFFFAOYSA-N 0.000 claims description 2
- ZKEYULQFFYBZBG-UHFFFAOYSA-N lanthanum carbide Chemical compound [La].[C-]#[C] ZKEYULQFFYBZBG-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims 1
- 239000007943 implant Substances 0.000 claims 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 6
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 125000004432 carbon atom Chemical group C* 0.000 description 2
- 230000003197 catalytic effect Effects 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- JRZJOMJEPLMPRA-UHFFFAOYSA-N olefin Natural products CCCCCCCC=C JRZJOMJEPLMPRA-UHFFFAOYSA-N 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02527—Carbon, e.g. diamond-like carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02642—Mask materials other than SiO2 or SiN
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
- Carbon And Carbon Compounds (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
本發明係關於一種石墨烯場效電晶體之製備方法，尤其是關於獨立雙閘極石墨烯場效電晶體(independent dual gate graphene field effect transistor)之製備方法。 The invention relates to a method for preparing a graphene field effect transistor, in particular to a method for preparing an independent dual gate graphene field effect transistor.
石墨烯之碳原子排列呈蜂巢晶格(honeycomb crystal lattice)，為單層二維晶體，幾乎透明，且具有高硬度、高導熱係數、高電子遷移率、低電阻等特性。石墨烯具有取代矽作為電晶體材料之潛力，使其達到小尺寸、高速度、低能耗、低產熱等目的。 The carbon atoms of graphene are arranged in a honeycomb crystal lattice, which is a single-layer two-dimensional crystal, almost transparent, and has high hardness, high thermal conductivity, high electron mobility, low electrical resistance and the like. Graphene has the potential to replace ruthenium as a transistor material, so that it can achieve small size, high speed, low energy consumption, low heat production and the like.
習知製備石墨烯的主要方法包括：熱分解法及化學氣相沉積法(chemical vapor deposition，CVD)。熱分解法係以單晶碳化矽(SiC)為材料，價格昂貴，且此方法容易形成島狀分佈的石墨烯，難以製備大面積且具單一厚度之石墨烯。 The main methods for preparing graphene include thermal decomposition and chemical vapor deposition (CVD). The thermal decomposition method uses monocrystalline niobium carbide (SiC) as a material, which is expensive, and this method is easy to form island-like distributed graphene, and it is difficult to prepare graphene having a large area and a single thickness.
目前業界較常採用化學氣相沉積法。化學氣相沉積法係將金屬基板(如鎳)置於前驅物(如甲烷、乙烯等)氛圍中，藉由高溫退火將碳原子沉積於基板表面形成石墨烯，接著蝕刻去除金屬基板而獲得石墨烯片。化學氣相沉積法能夠獲得較大面積之石墨烯，並可有效控石墨烯的生長；然而，由於與金屬基板之交互作用，會導致石墨烯部分特性喪失，且 連續性較差，易生成皺褶或裂痕。接著，必須將石墨烯轉移至合適的基板上才能製備電晶體。 At present, chemical vapor deposition is more commonly used in the industry. The chemical vapor deposition method places a metal substrate (such as nickel) in an atmosphere of a precursor (such as methane, ethylene, etc.), deposits carbon atoms on the surface of the substrate to form graphene by high temperature annealing, and then removes the metal substrate by etching to obtain graphite. Olefin. Chemical vapor deposition can obtain a large area of graphene and can effectively control the growth of graphene; however, due to the interaction with the metal substrate, the graphene partial properties are lost, and Poor continuity, easy to generate wrinkles or cracks. Next, the graphene must be transferred to a suitable substrate to prepare a transistor.
目前習知製程為，在矽基板上形成二氧化矽層，於該二氧化矽層上形成催化金屬層，於該催化金屬層上形成石墨烯層，接著進行轉移。為了於轉移步驟中保護石墨烯層，於其上塗佈聚合物。剝離矽基板及二氧化矽層，以化學蝕刻移除催化金屬層，接著，以溶劑移除保護用聚合物，再以所欲基板承接石墨烯，完成轉移步驟。再進行後續電晶體製備程序。 At present, a known process is to form a ruthenium dioxide layer on a ruthenium substrate, form a catalytic metal layer on the ruthenium dioxide layer, form a graphene layer on the catalyzed metal layer, and then transfer. In order to protect the graphene layer in the transfer step, a polymer is coated thereon. The ruthenium substrate and the ruthenium dioxide layer are stripped, and the catalytic metal layer is removed by chemical etching. Then, the protective polymer is removed by a solvent, and then the graphene is subjected to a desired substrate to complete the transfer step. A subsequent transistor preparation procedure is then performed.
於習知製程中，轉移步驟會損害與污染石墨烯結構，特別是對於在化學安定性高的金屬上形成的石墨烯，由於兩者的交互作用，轉移步驟會使石墨烯的優異特性喪失，從而影響後續電晶體之性能。 In the conventional process, the transfer step may damage the graphene structure, especially for graphene formed on a metal with high chemical stability. Due to the interaction between the two, the transfer step may cause the excellent properties of graphene to be lost. Thereby affecting the performance of the subsequent transistor.
習知之石墨烯場效電晶體結構請參照第1(A)至1(C)圖。第1(A)圖為背部閘極(back-gate)場效電晶體。第1(B)圖為頂部閘極(top-gate)場效電晶體，具有石墨烯通道，其為片狀剝離之石墨烯(exfoliated graphene)、或為金屬上生長並轉移至表面覆蓋二氧化矽之矽晶圓上之石墨烯。第1(C)圖為頂部閘極場效電晶體，具有磊晶石墨烯通道(epitaxial-graphene channel)。 For the structure of the conventional graphene field effect transistor, please refer to the figures 1(A) to 1(C). Figure 1(A) shows the back-gate field effect transistor. Figure 1(B) is a top-gate field effect transistor with a graphene channel, exfoliated graphene, or grown on a metal and transferred to a surface-covered dioxide Graphene on the wafer. Figure 1(C) shows the top gate field effect transistor with an epitaxial-graphene channel.
據此，對於石墨烯電晶體之製程仍有其需求。 Accordingly, there is still a need for a process for graphene transistors.
本發明係提供一種製造獨立雙閘極石墨烯場效電晶體之方法，係包括：於矽基板上形成矽化鍺(SiGe)磊晶層；將碳離子植入該基板；熱退火(thermal annealing)以直接合成碳化矽(SiC)沈澱物，其中，該碳化矽係對齊該矽化鍺之晶格；於該碳化矽表面選擇性生長石墨烯；於 該石墨烯上形成一介電層並進行圖案化；以及於該石墨烯上形成源極與汲極，並於該介電層上形成閘極。 The invention provides a method for manufacturing an independent double-gate graphene field effect transistor, which comprises: forming a germanium telluride (SiGe) epitaxial layer on a germanium substrate; implanting carbon ions into the substrate; thermal annealing Directly synthesizing a cerium carbide (SiC) precipitate, wherein the lanthanum carbide is aligned with the crystal lattice of the bismuth telluride; the graphene is selectively grown on the surface of the tantalum carbide; Forming a dielectric layer on the graphene and patterning; forming a source and a drain on the graphene, and forming a gate on the dielectric layer.
於一實施例中，該矽基板可為，例如矽晶圓。 In an embodiment, the germanium substrate can be, for example, a germanium wafer.
於一實施例中，可於siGe磊晶層形成後，對該基板進行光阻塗佈及圖案化步驟。 In one embodiment, after the siGe epitaxial layer is formed, the substrate is subjected to a photoresist coating and patterning step.
於一實施例中，該碳離子植入係於溫度400-600℃下進行。 In one embodiment, the carbon ion implantation is performed at a temperature of 400-600 °C.
於一實施例中，該碳離子植入係於該SiGe磊晶層表面區域獲得碳尖峰(C peak)，且濃度與鍺含量相近(如鍺含量之80%-120%，例如90-110%)或相同。可據此條件選擇離子植入之能量及劑量。 In one embodiment, the carbon ion implantation is performed on a surface region of the SiGe epitaxial layer to obtain a carbon peak (C peak), and the concentration is similar to the germanium content (eg, 80%-120% of the germanium content, for example, 90-110%). ) or the same. The energy and dose of ion implantation can be selected according to this condition.
於一實施例中，該碳化矽沈澱物為β-SiC。 In one embodiment, the niobium carbide precipitate is β-SiC.
於一實施例中，該選擇性生長石墨烯之步驟係以甲烷為石墨烯前驅物，並在氬氣或氫氣之氛圍下進行。於一實施例中，石墨烯生長溫度係600-1500℃。 In one embodiment, the step of selectively growing graphene is performed by using methane as a graphene precursor and under an atmosphere of argon or hydrogen. In one embodiment, the graphene growth temperature is 600-1500 °C.
於一實施例中，該選擇性生長之石墨烯為單層。於另一實施例中，該選擇性生長之石墨烯為多層。 In one embodiment, the selectively grown graphene is a single layer. In another embodiment, the selectively grown graphene is a multilayer.
於一實施例中，該步驟所形成之石墨烯為分離生長之石墨烯帶(isolated growing graphene ribbon)，該石墨烯帶具有較大能隙。於實施例中，該能隙可超過300meV。 In one embodiment, the graphene formed in this step is an isolated graphene ribbon having a larger energy gap. In an embodiment, the energy gap can exceed 300 meV.
於一實施例中，對該介電層之圖案化之圖案寬度小於10nm。 In one embodiment, the patterned pattern width of the dielectric layer is less than 10 nm.
於實施例中，源極與汲極係形成於該石墨烯上，前閘極(front-gate)係形成於該介電層上。 In an embodiment, a source and a drain are formed on the graphene, and a front-gate is formed on the dielectric layer.
於實施例中，該雙閘極之背閘極與前閘極係藉由閘極介電層而與通道材料隔離。 In an embodiment, the back gate and the front gate of the dual gate are isolated from the channel material by a gate dielectric layer.
1、2、3、4‧‧‧石墨烯場效應電晶體 1, 2, 3, 4 ‧ ‧ graphene field effect transistor
11、21‧‧‧背閘極 11, 21‧‧‧ back gate
12、22‧‧‧矽晶體層 12, 22‧‧‧矽 crystal layer
13、23、33‧‧‧二氧化矽層 13, 23, ‧ ‧ cerium oxide layer
14、24、34、44‧‧‧石墨烯層 14, 24, 34, 44‧‧‧ graphene layer
15、25、35、46‧‧‧源極 15, 25, 35, 46‧‧‧ source
16、26、36、47‧‧‧汲極 16, 26, 36, 47‧‧ ‧ bungee
27、37、45‧‧‧介電層 27, 37, 45‧‧‧ dielectric layer
28、38、38‧‧‧頂閘極 28, 38, 38‧‧‧ top gate
31‧‧‧半絕緣碳化矽層 31‧‧‧Semi-insulating tantalum carbide layer
41‧‧‧矽基板 41‧‧‧矽 substrate
42‧‧‧矽化鍺層 42‧‧‧矽化锗层
43‧‧‧碳化矽層 43‧‧‧Carbide layer
48‧‧‧金屬閘極 48‧‧‧Metal gate
49‧‧‧碳離子植入區域 49‧‧‧Carbon ion implantation area
第1(A)至1(C)圖係顯示習知石墨烯場效電晶體結構。 The first (A) to (C) diagrams show a conventional graphene field effect transistor structure.
第2圖係顯示，依據本發明之一實施例之獨立雙閘極石墨烯場效電晶體結構。 Figure 2 is a diagram showing an independent dual gate graphene field effect transistor structure in accordance with an embodiment of the present invention.
第3(A)至3(F)圖係表示，依據本發明之一實施例，製備雙閘極石墨烯場效電晶體結構之步驟。 3(A) through 3(F) are diagrams showing the steps of preparing a double gate graphene field effect transistor structure in accordance with an embodiment of the present invention.
下面將結合示意圖對本發明的方法進行更詳細的描述，其中表示了本發明的較佳實施例，應理解具本領域通常知識者可以對此處描述之本發明進行修改，而仍然實現本發明的有利效果。因此，下列描述應該被理解為對於本領域技術人員的廣泛認知，而並非作為對本發明的限制。 The method of the present invention will now be described in more detail in conjunction with the accompanying drawings in which the preferred embodiment of the invention Favorable effect. Therefore, the following description is to be understood as a broad understanding of the invention, and not as a limitation of the invention.
為了清楚，不描述實際實施例的全部特徵。在下列描述中，不詳細描述眾所周知的功能和結構，因為它們會使本發明由於不必要的細節而混亂。應當認為在任何實際實施例的開發中，必須做出大量實施細節以實現開發者的特定目標，例如按照有關系統或有關商業的限制，由一個實施例改變為另一個實施例。另外，應當認為這種開發工作可能是複雜和耗費時間的，但是對於具本領域通常知識者來說僅僅是常規工作。 In the interest of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail as they may obscure the present invention in unnecessary detail. It should be understood that in the development of any actual embodiment, a large number of implementation details must be made to achieve a particular goal of the developer, such as changing from one embodiment to another in accordance with the limitations of the system or related business. In addition, such development work should be considered complex and time consuming, but is only routine work for those of ordinary skill in the art.
在下列段落中參照圖式以舉例方式更具體地描述本發明。根據下面的說明和申請專利範圍，本發明的優點和特徵將更清楚。需說明的 是，圖式均採用非常簡化的形式且均使用非精準的比例，僅用以方便、明晰地輔助說明本發明實施例的目的。 The invention is more specifically described in the following paragraphs by way of example with reference to the drawings. Advantages and features of the present invention will be apparent from the description and appended claims. Need to explain Yes, the drawings are in a very simplified form and all use non-precise proportions, only to facilitate the purpose of facilitating the description of the embodiments of the present invention.
請參考第2圖，於本實施例中，本發明之獨立雙閘極石墨烯場效電晶體結構包括：矽基板41(即背閘極)、矽化鍺層42、碳化矽層43、石墨烯層44、介電層45、源極46、汲極47、以及金屬閘極48(即前閘極)。 Referring to FIG. 2, in the embodiment, the independent double gate graphene field effect transistor structure of the present invention comprises: a germanium substrate 41 (ie, a back gate), a germanium telluride layer 42, a tantalum carbide layer 43, graphene. Layer 44, dielectric layer 45, source 46, drain 47, and metal gate 48 (ie, the front gate).
依據本發明之一實施例，製備雙閘極石墨烯場效電晶體結構之步驟，請參考第3(A)至3(F)圖。 According to an embodiment of the present invention, the steps of preparing the double gate graphene field effect transistor structure are referred to the figures 3(A) to 3(F).
參照第3(A)圖，提供一矽基板41，例如矽晶圓。參照第3(B)圖，於該矽基板41上形成一SiGe磊晶層42，接著清潔該基板。視需要，可對該基板進行光阻塗佈及圖案化步驟。 Referring to Figure 3(A), a substrate 41, such as a germanium wafer, is provided. Referring to FIG. 3(B), a SiGe epitaxial layer 42 is formed on the germanium substrate 41, and then the substrate is cleaned. The substrate may be subjected to a photoresist coating and patterning step as needed.
參照第3(C)圖，進行碳熱離子植入步驟，於該SiGe磊晶層42上形成碳離子植入區域49。於一實施例中，該碳離子植入區域49之寬度為4-12nm；於較佳實施例中，該碳離子植入區域49之寬度為6-8nm。碳離子植入可於1-100KeV，離子劑量1×1015至1×1018離子/cm2，於溫度400-600℃下進行。接著，可去除光阻(photoresist strip)。進行快速熱退火(rapid thermal annealing，RTA)步驟，條件為溫度400-1200℃，處理1-1000秒，以形成β-SiC。 Referring to FIG. 3(C), a carbothermal ion implantation step is performed to form a carbon ion implantation region 49 on the SiGe epitaxial layer 42. In one embodiment, the carbon ion implantation region 49 has a width of 4-12 nm; in the preferred embodiment, the carbon ion implantation region 49 has a width of 6-8 nm. Carbon ion implantation can be carried out at 1-100 KeV, ion dose 1 x 10 15 to 1 x 10 18 ions/cm 2 at a temperature of 400-600 °C. Then, the photoresist strip can be removed. A rapid thermal annealing (RTA) step is carried out under the conditions of a temperature of 400-1200 ° C and a treatment of 1-1000 seconds to form β-SiC.
參照第3(D)圖，於該碳離子植入區域49上選擇性生長石墨烯層44。於實施例中，該石墨烯層44係於600-1500℃下，以甲烷(CH4)為前驅物，並在氬氣或氫氣之氛圍下形成。該石墨烯層44可為單層或多層。該石墨烯層44可為分離生長之石墨烯帶，該石墨烯帶具有較大能隙，例如，該能隙可超過300meV。 The graphene layer 44 is selectively grown on the carbon ion implantation region 49 with reference to the third (D) diagram. In an embodiment, the graphene layer 44 is at 600-1500 ° C with methane (CH 4 ) as a precursor and is formed under an argon or hydrogen atmosphere. The graphene layer 44 can be a single layer or multiple layers. The graphene layer 44 can be a separately grown graphene ribbon having a larger energy gap, for example, the energy gap can exceed 300 meV.
參照第3(E)圖，以原子層沉積(atomic layer deposition，ALD)進行介電材料沈積，並進行圖案化，以形成介電層45。該介電層為高k介電層(high k dielectric layer)。 Referring to FIG. 3(E), a dielectric material is deposited by atomic layer deposition (ALD) and patterned to form a dielectric layer 45. The dielectric layer is a high k dielectric layer.
參照第3(F)圖，形成源極46、汲極47及金屬閘極48(即前閘極)，該源極46與該汲極47係形成於該石墨烯層44上並以該介電層45分隔，該金屬閘極48係形成於該介電層45上，該雙閘極係藉由閘極介電層而與通道材料隔離。 Referring to FIG. 3(F), a source 46, a drain 47, and a metal gate 48 (ie, a front gate) are formed. The source 46 and the drain 47 are formed on the graphene layer 44 and The electrical layer 45 is spaced apart and the metal gate 48 is formed on the dielectric layer 45, the dual gate being isolated from the channel material by a gate dielectric layer.
依據本發明所得之獨立雙閘極石墨烯場效電晶體，可於所欲基板上形成石墨烯層，避免因轉移步驟所致之損害。本發明之石墨烯場效電晶體能夠維持石墨烯之高硬度、高導熱係數、高電子遷移率、低電阻等優異特性，並達到小尺寸、高速度、低能耗、低產熱之產品性能。 According to the independent double-gate graphene field effect transistor obtained by the invention, a graphene layer can be formed on a desired substrate to avoid damage caused by the transfer step. The graphene field effect transistor of the invention can maintain the excellent properties of graphene, such as high hardness, high thermal conductivity, high electron mobility and low electrical resistance, and achieves product performances of small size, high speed, low energy consumption and low heat production.
上述特定實施例之內容係為了詳細說明本發明，然而，該等實施例係僅用於說明，並非意欲限制本發明。熟習本領域之技藝者可理解，在不悖離後附申請專利範圍所界定之範疇下針對本發明所進行之各種變化或修改係落入本發明之一部分。 The above description of the specific embodiments is intended to be illustrative of the invention, and is not intended to limit the invention. It will be understood by those skilled in the art that various changes or modifications may be made to the present invention without departing from the scope of the appended claims.
4‧‧‧石墨烯場效應電晶體 4‧‧‧ Graphene field effect transistor
41‧‧‧矽基板 41‧‧‧矽 substrate
42‧‧‧矽化鍺層 42‧‧‧矽化锗层
43‧‧‧碳化矽層 43‧‧‧Carbide layer
44‧‧‧石墨烯層 44‧‧‧graphene layer
45‧‧‧介電層 45‧‧‧Dielectric layer
46‧‧‧源極 46‧‧‧ source
47‧‧‧汲極 47‧‧‧汲polar
48‧‧‧金屬閘極 48‧‧‧Metal gate
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