TWI601120B - Buffer, data driving circuit and display device - Google Patents
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Description
本發明係關於一種緩衝器，特別關於一種資料驅動電路之緩衝器。 This invention relates to a buffer, and more particularly to a buffer for a data drive circuit.
顯示面板常因其使用之液晶材料與資料驅動電路的內阻不相匹配，無法提供達到適當液晶穿透率的電壓值，造成部分灰階訊號無法趨近於理想伽瑪曲線，因此需藉由修正伽瑪電壓來改善畫面影像。 The display panel often does not match the internal resistance of the liquid crystal material used by the data driving circuit, and cannot provide a voltage value that achieves proper liquid crystal transmittance, so that some gray scale signals cannot approach the ideal gamma curve, so Correct the gamma voltage to improve the picture.
圖1為習知技術之資料驅動電路及其緩衝器之示意圖，請參照圖1，目前市面上有些資料驅動晶片，其應用規格會包含有兩顆伽瑪緩衝器，以及伽瑪匹配電阻RU1、RU2、RU3、RU4、RD1、RD2、RD3和RD4，在此，以四顆資料驅動晶片IC1~IC4為例，於圖1中，該些資料驅動晶片之輸入訊號簡要表示為Vin，該些資料驅動晶片IC1、IC2、IC3和IC4之伽瑪匹配電阻RU1~RU4和RD1~RD4為11K歐姆，而且，由於四顆資料驅動晶片IC1~IC4係共用伽瑪補償電壓，因此其伽瑪匹配電阻RU1~RU4和RD1~RD4為並聯，其等效電阻為11K/4歐姆。就如圖2所示，其為圖1之資料驅動電路及其緩衝器之簡化示意圖。請參照圖2，資料驅動電路包括有多個伽瑪緩衝器，分別為第一伽瑪緩衝器11、第二伽瑪緩衝器12、第三伽瑪緩衝器13以及第四伽瑪緩衝器14，圖1中資料驅動晶片IC1~IC4之伽瑪匹配電阻RU及RD之等效電阻，於圖2中以第一阻抗R1A和第二阻抗R2A表示，因此第一阻抗R1A和第二阻抗R2A的阻抗值為11K/4歐姆。 1 is a schematic diagram of a data driving circuit and a buffer thereof of the prior art. Please refer to FIG. 1. Currently, there are some data driving chips on the market, and the application specifications include two gamma buffers and a gamma matching resistor RU1. RU2, RU3, RU4, RD1, RD2, RD3 and RD4, here, four data driving chip IC1 ~ IC4 an example, in FIG. 1, the plurality of data input signal driving the wafer schematically represents the V in, the plurality of The gamma matching resistors RU1~RU4 and RD1~RD4 of the data driving chip IC1, IC2, IC3 and IC4 are 11K ohms, and since the four data driving chips IC1~IC4 share the gamma compensation voltage, their gamma matching resistors RU1~RU4 and RD1~RD4 are connected in parallel, and their equivalent resistance is 11K/4 ohms. As shown in FIG. 2, it is a simplified schematic diagram of the data driving circuit of FIG. 1 and its buffer. Referring to FIG. 2, the data driving circuit includes a plurality of gamma buffers, which are a first gamma buffer 11, a second gamma buffer 12, a third gamma buffer 13, and a fourth gamma buffer 14, respectively. The equivalent resistance of the gamma matching resistors RU and RD of the data driving chips IC1 to IC4 in FIG. 1 is represented by the first impedance R1A and the second impedance R2A in FIG. 2, and thus the first impedance R1A and the second impedance R2A The impedance value is 11K/4 ohms.
該些伽瑪緩衝器11、12、13和14之工作電壓皆為16V及0V，而伽瑪緩衝器11、12、13和14之輸入訊號Vin1A、Vin2A、Vin3A和Vin4A分別為15.8V、8.2V、7.8V以及0.23V。伽瑪緩衝器11、12、13和14之輸 出訊號Vout1A、Vout2A、Vout3A和Vout4A則分別為15.8V、8.2V、7.8V以及0.23V(也就是伽瑪補償電壓)。在圖1中，第一阻抗R1A係第一伽瑪緩衝器11到第二伽瑪緩衝器12之輸出端之間的等效阻抗，而第二阻抗R2A則是第三伽瑪緩衝器13到第四伽瑪緩衝器14之輸出端之間的等效阻抗，而第一阻抗R1和第二阻抗R2A的阻抗值係11K/4。因此，流經第一阻抗R1A及第二阻抗R2A的電流IR1A和IR2A分別為(15.8V-8.2V)/(11K/4)及(7.8V-0.23V)/(11K/4)，其約為2.76毫安培。其中，第一伽瑪緩衝器11上所消耗之功率，係第一伽瑪緩衝器11上的跨壓(16V-15.8V)乘上電流IR1A(2.76mA)，即為(16V-15.8V)*2.76mA，約為0.552mW；第二伽瑪緩衝器12所消耗之功率，係(8.2V-0V)*2.76mA，約為22.6mW；第三伽瑪緩衝器13上所消耗之功率，係(16V-7.8V)*2.76mA，約為22.632mW；而第四伽瑪緩衝器14所消耗之功率，係(0.23V-0V)*2.76mA，約為0.552mW。由上述可知，第二伽瑪緩衝器12和第三伽瑪緩衝器13所消耗的功率，遠大於第一伽瑪緩衝器11和第四伽瑪緩衝器14，因此會造成整個電路功率的消耗大幅提升。另外，因習知電路消耗功率較大，而會有過熱的問題。 The operating voltages of the gamma buffers 11, 12, 13 and 14 are both 16V and 0V, and the input signals V in1A , V in2A , V in3A and V in4A of the gamma buffers 11, 12, 13 and 14 are respectively 15.8V, 8.2V, 7.8V and 0.23V. The output signals V out1A , V out2A , V out3A , and V out4A of the gamma buffers 11, 12, 13, and 14 are 15.8V, 8.2V, 7.8V, and 0.23V, respectively, which are gamma compensation voltages. In FIG. 1, the first impedance R1A is an equivalent impedance between the output ends of the first gamma buffer 11 to the second gamma buffer 12, and the second impedance R2A is the third gamma buffer 13 to The equivalent impedance between the outputs of the fourth gamma buffer 14 and the impedance values of the first impedance R1 and the second impedance R2A are 11K/4. Therefore, the currents I R1A and I R2A flowing through the first impedance R1A and the second impedance R2A are (15.8V-8.2V)/(11K/4) and (7.8V-0.23V)/(11K/4), respectively. It is about 2.76 milliamperes. The power consumed by the first gamma buffer 11 is the voltage across the first gamma buffer 11 (16V-15.8V) multiplied by the current I R1A (2.76mA), which is (16V-15.8V). *2.76mA, approximately 0.552mW; the power consumed by the second gamma buffer 12 is (8.2V-0V)*2.76mA, approximately 22.6mW; the power consumed by the third gamma buffer 13 The system (16V-7.8V)*2.76mA is about 22.632mW; and the power consumed by the fourth gamma buffer 14 is (0.23V-0V)*2.76mA, which is about 0.552mW. As can be seen from the above, the power consumed by the second gamma buffer 12 and the third gamma buffer 13 is much larger than that of the first gamma buffer 11 and the fourth gamma buffer 14, thus causing the entire circuit power consumption. Significantly improved. In addition, since the conventional circuit consumes a large amount of power, there is a problem of overheating.
因此，如何提供一種緩衝器，能夠降低進行伽瑪補償時所造成之功率損耗，已成為重要課題之一。 Therefore, how to provide a buffer that can reduce the power loss caused by gamma compensation has become one of the important topics.
有鑑於上述課題，本發明之目的為提供一種能夠在進行伽瑪補償時，有效降低功率損耗之緩衝器及資料驅動電路及顯示裝置。 In view of the above problems, an object of the present invention is to provide a buffer, a data driving circuit, and a display device capable of effectively reducing power loss when performing gamma compensation.
為達上述目的，依據本發明之一種緩衝器。緩衝器包括有一輸入電路、一偵測電路以及一輸出電路。輸入電路接收一輸入訊號。偵測電路係電性連接至輸入電路，並將輸入訊號與一參考電壓進行比較而輸出一開關訊號。輸出電路具有一訊號輸出端，並電性連接至輸入電路和偵測電路。輸出電路依據開關訊號的狀態而選擇依據一第一高工作電壓和一第一低工作電壓，或依據一第二高工作電壓和一第二低工作電壓，而將輸入訊號當作一輸出訊號而從訊號輸出端輸出，其中輸出訊號的電位介於第一高工作電壓和第一低工作電壓之間，或介於第二高工作電壓和第二低工作 電壓之間。 A buffer according to the invention is achieved for the above purposes. The buffer includes an input circuit, a detection circuit, and an output circuit. The input circuit receives an input signal. The detection circuit is electrically connected to the input circuit, and compares the input signal with a reference voltage to output a switching signal. The output circuit has a signal output end and is electrically connected to the input circuit and the detection circuit. The output circuit selects the input signal as an output signal according to a first high operating voltage and a first low operating voltage according to a state of the switching signal, or according to a second high operating voltage and a second low operating voltage. Output from the signal output terminal, wherein the potential of the output signal is between the first high working voltage and the first low working voltage, or between the second high working voltage and the second low working voltage Between voltages.
在一實施例中，輸出電路包括有一電壓提供電路、一第一工作電壓選擇電路以及一第二工作電壓選擇電路。電壓提供電路係電性連接至輸入電路和訊號輸出端，電壓提供電路提供一第一操作電壓和一第二操作電壓，並依據輸入訊號而產生輸出訊號。第一工作電壓選擇電路係電性連接至電壓提供電路和偵測電路，並電性連接至訊號輸出端。當開關訊號係為一第一狀態時，第一工作電壓選擇電路依據該第一操作電壓和輸出訊號之間的電壓差，以及輸出訊號和第二操作電壓之間的電壓差而使輸入電路電性連接第一高工作電壓和第一低工作電壓，並使得輸出訊號介於第一高工作電壓和第一低工作電壓之間。第二工作電壓選擇電路係電性連接至電壓提供電路和偵測電路，並電性連接至訊號輸出端，當開關訊號係為一第二狀態時，第二工作電壓選擇電路依據輸出訊號和第一操作電壓之間的電壓差，以及第二操作電壓和輸出訊號之間的電壓差而使輸入電路電性連接第二高工作電壓和第二低工作電壓，並使得輸出訊號介於第二高工作電壓和第二低工作電壓之間。 In an embodiment, the output circuit includes a voltage supply circuit, a first operating voltage selection circuit, and a second operating voltage selection circuit. The voltage supply circuit is electrically connected to the input circuit and the signal output terminal, and the voltage supply circuit provides a first operating voltage and a second operating voltage, and generates an output signal according to the input signal. The first working voltage selection circuit is electrically connected to the voltage supply circuit and the detection circuit, and is electrically connected to the signal output end. When the switching signal is in a first state, the first working voltage selection circuit makes the input circuit electrically according to the voltage difference between the first operating voltage and the output signal, and the voltage difference between the output signal and the second operating voltage. The first high operating voltage and the first low operating voltage are connected, and the output signal is between the first high operating voltage and the first low operating voltage. The second working voltage selection circuit is electrically connected to the voltage supply circuit and the detection circuit, and is electrically connected to the signal output end. When the switching signal is in a second state, the second working voltage selection circuit is based on the output signal and the a voltage difference between the operating voltages, and a voltage difference between the second operating voltage and the output signal, electrically connecting the input circuit to the second high operating voltage and the second low operating voltage, and causing the output signal to be the second highest Between the operating voltage and the second low operating voltage.
在一實施例中，偵測電路包括有一比較器以及一反相器。比較器係接收輸入訊號與參考電壓，並將二者進行比較而產生開關訊號。反相器係電性連接至比較器的輸出端，接收開關訊號，輸出一開關訊號之反相訊號。其中，輸出電路依據開關訊號及開關訊號之反相訊號的狀態而選擇依據一第一高工作電壓和一第一低工作電壓，或依據一第二高工作電壓和一第二低工作電壓。 In an embodiment, the detection circuit includes a comparator and an inverter. The comparator receives the input signal and the reference voltage and compares the two to generate a switching signal. The inverter is electrically connected to the output of the comparator, receives the switching signal, and outputs an inverted signal of the switching signal. The output circuit selects according to a first high operating voltage and a first low operating voltage, or a second high operating voltage and a second low operating voltage according to the state of the switching signal and the inverted signal of the switching signal.
在一實施例中，第一低工作電壓等於第二高工作電壓。 In an embodiment, the first low operating voltage is equal to the second high operating voltage.
在一實施例中，第一高工作電壓和第一低工作電壓之電壓差等於第二高工作電壓和第二低工作電壓之電壓差。 In an embodiment, the voltage difference between the first high operating voltage and the first low operating voltage is equal to the voltage difference between the second high operating voltage and the second low operating voltage.
在一實施例中，輸出訊號係為伽瑪補償電壓訊號。 In one embodiment, the output signal is a gamma compensation voltage signal.
為達上述目的，依據本發明之一種資料驅動電路，其適用於顯示裝置，資料驅動電路包括有一電路板、一第一伽瑪緩衝器以及一第二伽瑪緩衝器。第一伽瑪緩衝器配置於該電路板上，並具有一第一訊號輸入端和一第一訊號輸出端，第一伽瑪緩衝器從第一訊號輸入端接收一第一輸 入訊號，且第一伽瑪緩衝器依據一第一高工作電壓和一第一低工作電壓而將第一輸入訊號當作一第一伽瑪補償電壓訊號從第一訊號輸出端輸出，其中第一伽瑪補償電壓訊號的電位係介於第一高工作電壓和第一低工作電壓之間。第二伽瑪緩衝器配置於該電路板上，並具有第二訊號輸入端和一第二訊號輸出端，第二伽瑪緩衝器從第二訊號輸入端接收一第二輸入訊號，且第二伽瑪緩衝器依據一第二高工作電壓和一第二低工作電壓而將第二輸入訊號當作一第二伽瑪補償電壓訊號從第二訊號輸出端輸出，其中第二伽瑪補償電壓訊號的電位係介於第二高工作電壓和第二低工作電壓之間。 To achieve the above object, a data driving circuit according to the present invention is applicable to a display device. The data driving circuit includes a circuit board, a first gamma buffer, and a second gamma buffer. The first gamma buffer is disposed on the circuit board and has a first signal input end and a first signal output end, and the first gamma buffer receives a first input from the first signal input end Entering a signal, and the first gamma buffer outputs the first input signal as a first gamma compensation voltage signal from the first signal output according to a first high operating voltage and a first low operating voltage, wherein The potential of a gamma compensation voltage signal is between the first high operating voltage and the first low operating voltage. The second gamma buffer is disposed on the circuit board and has a second signal input end and a second signal output end, the second gamma buffer receives a second input signal from the second signal input end, and the second The gamma buffer outputs the second input signal as a second gamma compensation voltage signal from the second signal output terminal according to a second high operating voltage and a second low operating voltage, wherein the second gamma compensation voltage signal The potential is between the second high operating voltage and the second low operating voltage.
在一實施例中，資料驅動電路還包括多個資料驅動單元，而第一伽瑪緩衝器和第二伽瑪緩衝器位於相同或不同的資料驅動單元中。 In an embodiment, the data driving circuit further includes a plurality of data driving units, and the first gamma buffer and the second gamma buffer are located in the same or different data driving units.
在一實施例中，第一低工作電壓等於該第二高工作電壓。 In an embodiment, the first low operating voltage is equal to the second high operating voltage.
在一實施例中，第一高工作電壓和第一低工作電壓之電壓差等於第二高工作電壓和第二低工作電壓之電壓差。 In an embodiment, the voltage difference between the first high operating voltage and the first low operating voltage is equal to the voltage difference between the second high operating voltage and the second low operating voltage.
為達上述目的，依據本發明之一種顯示裝置，包括有一顯示面板以及一資料驅動電路。資料驅動電路電性連接至顯示面板。資料電路包括有一電路板、一第一伽瑪緩衝器以及一第二伽瑪緩衝器。第一伽瑪緩衝器配置於電路板上，並具有一第一訊號輸入端和一第一訊號輸出端，第一伽瑪緩衝器從第一訊號輸入端接收一第一輸入訊號，且第一伽瑪緩衝器依據一第一高工作電壓和一第一低工作電壓而將第一輸入訊號當作一第一伽瑪補償電壓訊號從第一訊號輸出端輸出，其中第一伽瑪補償電壓訊號的電位係介於第一高工作電壓和第一低工作電壓之間。第二伽瑪緩衝器配置於電路板上，並具有第二訊號輸入端和一第二訊號輸出端，第二伽瑪緩衝器從第二訊號輸入端接收一第二輸入訊號，且第二伽瑪緩衝器依據一第二高工作電壓和一第二低工作電壓而將第二輸入訊號當作一第二伽瑪補償電壓訊號從該第二訊號輸出端輸出，其中第二伽瑪補償電壓訊號的電位係介於第二高工作電壓和第二低工作電壓之間。 To achieve the above object, a display device according to the present invention includes a display panel and a data driving circuit. The data driving circuit is electrically connected to the display panel. The data circuit includes a circuit board, a first gamma buffer, and a second gamma buffer. The first gamma buffer is disposed on the circuit board and has a first signal input end and a first signal output end. The first gamma buffer receives a first input signal from the first signal input end, and the first The gamma buffer outputs the first input signal as a first gamma compensation voltage signal from the first signal output terminal according to a first high operating voltage and a first low operating voltage, wherein the first gamma compensation voltage signal The potential is between the first high operating voltage and the first low operating voltage. The second gamma buffer is disposed on the circuit board and has a second signal input end and a second signal output end, and the second gamma buffer receives a second input signal from the second signal input end, and the second gamma The mega buffer outputs the second input signal as a second gamma compensation voltage signal from the second signal output terminal according to a second high operating voltage and a second low operating voltage, wherein the second gamma compensation voltage signal The potential is between the second high operating voltage and the second low operating voltage.
在一實施例中，資料驅動電路還包括多個資料驅動單元，而該第一伽瑪緩衝器和該第二伽瑪緩衝器位於相同或不同的資料驅動單元中。 In an embodiment, the data driving circuit further includes a plurality of data driving units, and the first gamma buffer and the second gamma buffer are located in the same or different data driving units.
在一實施例中，第一低工作電壓等於第二高工作電壓。 In an embodiment, the first low operating voltage is equal to the second high operating voltage.
在一實施例中，第一高工作電壓和第一低工作電壓之電壓差等於第二高工作電壓和第二低工作電壓之電壓差。 In an embodiment, the voltage difference between the first high operating voltage and the first low operating voltage is equal to the voltage difference between the second high operating voltage and the second low operating voltage.
在一實施例中，顯示面板係為液晶顯示面板或有機發光二極體顯示面板。 In an embodiment, the display panel is a liquid crystal display panel or an organic light emitting diode display panel.
綜上所述，本發明之緩衝器係藉由選擇不同工作電壓區間，降低功率損耗，亦使具有多個該緩衝器之資料驅動電路可避免部份緩衝器因跨壓過大而產生過熱的情況，進而降低使用該資料驅動電路之顯示裝置的功率消耗。 In summary, the buffer of the present invention reduces power loss by selecting different operating voltage intervals, and also enables a data driving circuit having a plurality of buffers to avoid overheating of some buffers due to excessive voltage across the voltage. Thereby reducing the power consumption of the display device using the data driving circuit.
1、3、42‧‧‧資料驅動電路 1, 3, 42‧‧‧ data drive circuit
2‧‧‧緩衝器 2‧‧‧buffer
11、311‧‧‧第一伽瑪緩衝器 11, 311‧‧‧ first gamma buffer
12、312‧‧‧第二伽瑪緩衝器 12, 312‧‧‧Second gamma buffer
13、313‧‧‧第三伽瑪緩衝器 13, 313‧‧‧ third gamma buffer
14、314‧‧‧第四伽瑪緩衝器 14, 314‧‧‧ fourth gamma buffer
21‧‧‧輸入電路 21‧‧‧Input circuit
22‧‧‧偵測電路 22‧‧‧Detection circuit
23‧‧‧輸出電路 23‧‧‧Output circuit
210‧‧‧輸入端 210‧‧‧ input
221‧‧‧比較器 221‧‧‧ comparator
222‧‧‧反相器 222‧‧‧Inverter
230‧‧‧輸出端 230‧‧‧ Output
231‧‧‧第一工作電壓選擇電路 231‧‧‧First working voltage selection circuit
232‧‧‧第二工作電壓選擇電路 232‧‧‧Second working voltage selection circuit
233‧‧‧電壓提供電路 233‧‧‧Voltage supply circuit
2331‧‧‧浮動電流源 2331‧‧‧Floating current source
30、421、422、423、424‧‧‧資料驅動單元 30, 421, 422, 423, 424‧‧‧ data drive unit
31‧‧‧電路板 31‧‧‧ boards
4‧‧‧顯示裝置 4‧‧‧ display device
41‧‧‧顯示面板 41‧‧‧ display panel
43‧‧‧掃描驅動電路 43‧‧‧Scan drive circuit
C1‧‧‧第一電容 C1‧‧‧first capacitor
C2‧‧‧第二電容 C2‧‧‧second capacitor
HV1‧‧‧第一高工作電壓 HV1‧‧‧ first high working voltage
HV2‧‧‧第二高工作電壓 HV2‧‧‧ second high working voltage
IC1、IC2、IC3、IC4‧‧‧資料驅動晶片 IC1, IC2, IC3, IC4‧‧‧ data drive chip
IR1A‧‧‧流經第一阻抗之電流 I R1A ‧‧‧current flowing through the first impedance
IR2A‧‧‧流經第二阻抗之電流 I R2A ‧‧‧current flowing through the second impedance
LV1‧‧‧第一低工作電壓 LV1‧‧‧First low operating voltage
LV2‧‧‧第二低工作電壓 LV2‧‧‧ second low working voltage
MP1‧‧‧第一P型電晶體 MP1‧‧‧First P-type transistor
MP2‧‧‧第二P型電晶體 MP2‧‧‧Second P-type transistor
MP3‧‧‧第三P型電晶體 MP3‧‧‧ Third P-type transistor
MP4‧‧‧第四P型電晶體 MP4‧‧‧4th P-type transistor
MP5‧‧‧第五P型電晶體 MP5‧‧‧ Fifth P-type transistor
MP6‧‧‧第六P型電晶體 MP6‧‧‧6th P-type transistor
MP7‧‧‧第七P型電晶體 MP7‧‧‧ seventh P-type transistor
MP8‧‧‧第八P型電晶體 MP8‧‧‧ eighth P-type transistor
MN1‧‧‧第一N型電晶體 MN1‧‧‧First N-type transistor
MN2‧‧‧第二N型電晶體 MN2‧‧‧Second N-type transistor
MN3‧‧‧第三N型電晶體 MN3‧‧‧ Third N-type transistor
MN4‧‧‧第四N型電晶體 MN4‧‧‧4th N-type transistor
MN5‧‧‧第五N型電晶體 MN5‧‧‧ fifth N-type transistor
MN6‧‧‧第六N型電晶體 MN6‧‧‧6th N-type transistor
MN7‧‧‧第七N型電晶體 MN7‧‧‧ seventh N-type transistor
MN8‧‧‧第八N型電晶體 MN8‧‧‧8th N-type transistor
N1‧‧‧第一端 N1‧‧‧ first end
N2‧‧‧第二端 N2‧‧‧ second end
N3‧‧‧第三端 N3‧‧‧ third end
N4‧‧‧第四端 N4‧‧‧ fourth end
R1A‧‧‧第一阻抗 R1A‧‧‧first impedance
R2A‧‧‧第二阻抗 R2A‧‧‧second impedance
RU1、RU2、RU3、RU4、RD1、RD2、RD3、RD4‧‧‧伽瑪匹配電阻 RU1, RU2, RU3, RU4, RD1, RD2, RD3, RD4‧‧ gamma matching resistor
SW1‧‧‧第一開關 SW1‧‧‧ first switch
SW2‧‧‧第二開關 SW2‧‧‧second switch
SW3‧‧‧第三開關 SW3‧‧‧ third switch
SW4‧‧‧第四開關 SW4‧‧‧fourth switch
SW5‧‧‧第五開關 SW5‧‧‧ fifth switch
SW6‧‧‧第六開關 SW6‧‧‧ sixth switch
SWS1‧‧‧開關訊號 SWS1‧‧‧Switch signal
SWS2‧‧‧反相開關訊號 SWS2‧‧‧Inverted Switch Signal
V+‧‧‧正電源 V+‧‧‧ positive power supply
Vref‧‧‧參考電壓 V ref ‧‧‧reference voltage
Vbias1‧‧‧第一工作偏壓 V bias1 ‧‧‧First working bias
Vbias2‧‧‧第二工作偏壓 V bias2 ‧‧‧second working bias
Vbias3‧‧‧第三工作偏壓 V bias3 ‧‧‧third working bias
Vbias4‧‧‧第四工作偏壓 V bias4 ‧‧‧four working bias
Vop1‧‧‧第一操作電壓 V op1 ‧‧‧first operating voltage
Vop2‧‧‧第二操作電壓 V op2 ‧‧‧second operating voltage
Vin、Vin1、Vin2、Vin3、Vin4、Vin1A、Vin2A、Vin3A、Vin4A‧‧‧輸入訊號 V in, V in1, V in2 , V in3, V in4, V in1A, V in2A, V in3A, V in4A ‧‧‧ input signal
Vout、Vout1、Vout2、Vout3、Vout4、Vout1A、Vout2A、Vout3A、Vout4A‧‧‧輸出訊號 V out , V out1 , V out2 , V out3 , V out4 , V out1A , V out2A , V out3A , V out4A ‧‧‧ output signal
圖1為習知技術之資料驅動電路及其緩衝器之示意圖。 1 is a schematic diagram of a data driving circuit and a buffer thereof of the prior art.
圖2為圖1習知技術之資料驅動電路及其緩衝器之簡化示意圖。 2 is a simplified schematic diagram of a data driving circuit of the prior art of FIG. 1 and a buffer thereof.
圖3為本發明較佳實施例之一種緩衝器之電路示意圖。 3 is a circuit diagram of a buffer in accordance with a preferred embodiment of the present invention.
圖4為本發明較佳實施例之一種資料驅動電路之示意圖。 4 is a schematic diagram of a data driving circuit in accordance with a preferred embodiment of the present invention.
圖5為顯示面板之伽瑪補償電壓對輸入資料之關係曲線示意圖。 FIG. 5 is a schematic diagram showing the relationship between the gamma compensation voltage of the display panel and the input data.
圖6為本發明較佳實施例之一種顯示裝置之示意圖。 FIG. 6 is a schematic diagram of a display device according to a preferred embodiment of the present invention.
以下將參照相關圖式，說明依本發明較佳實施例之一種緩衝器、資料驅動電路及顯示裝置，其中相同的元件將以相同的參照符號加以說明。 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a buffer, a data driving circuit, and a display device according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein the same elements will be described with the same reference numerals.
圖3為本發明較佳實施例之一種緩衝器之電路示意圖。為方便說明，於以下敘述中，圖中各電晶體朝向上方之端點為第一端，朝向下方的端點為第二端。其中，第一端或第二端可分別為源極端或汲極端，以下將不再特別說明。另外，各元件之控制閘極或其他特殊用途之端點則另作說明。 3 is a circuit diagram of a buffer in accordance with a preferred embodiment of the present invention. For convenience of description, in the following description, the end point of each of the transistors facing upward is the first end, and the end facing downward is the second end. Wherein, the first end or the second end may be a source terminal or a 汲 terminal, respectively, and will not be specifically described below. In addition, the control gates of each component or other special purpose end points are otherwise specified.
請參照圖3，緩衝器2包括一輸入電路21、一偵測電路22以及一輸出電路23。輸入電路21電性連接偵測電路22和輸出電路23，並 且偵測電路22也會電性連接輸出電路23。在本實施例中，輸出電路21係接收輸入訊號Vin。另外，偵測電路22會將輸入訊號Vin與一參考電壓Vref進行比較，並且輸出開關訊號SWS1。此時，輸出電路23會依據開關訊號SWS1的狀態而選擇依據一第一高工作電壓HV1和一第一低工作電壓LV1，或依據一第二高工作電壓HV2和一第二低工作電壓LV2，而將輸入訊號Vin當作一輸出訊號Vout而從輸出端230輸出。其中，輸出訊號Vout的電壓係介於第一高工作電壓HV1和第一低工作電壓LV1之間，或介於第二高工作電壓HV2和第二低工作電壓LV2之間。 Referring to FIG. 3, the buffer 2 includes an input circuit 21, a detection circuit 22, and an output circuit 23. The input circuit 21 is electrically connected to the detection circuit 22 and the output circuit 23, and the detection circuit 22 is also electrically connected to the output circuit 23. In the present embodiment, the output circuit 21 receives the input signal V in . In addition, the detecting circuit 22 compares the input signal V in with a reference voltage V ref and outputs a switching signal SWS1. At this time, the output circuit 23 is selected according to the state of the switching signal SWS1 according to a first high operating voltage HV1 and a first low operating voltage LV1, or according to a second high operating voltage HV2 and a second low operating voltage LV2. The input signal V in is output from the output terminal 230 as an output signal V out . The voltage of the output signal V out is between the first high working voltage HV1 and the first low working voltage LV1 or between the second high working voltage HV2 and the second low working voltage LV2.
在本實施例中，緩衝器2可以利用運算放大器來實現。因此，在輸入電路21中，可以包括有一第一N型電晶體MN1、一第二N型電晶體MN2，一第三N型電晶體MN3、一第四N型電晶體MN4、一第五N型電晶體MN5、一第六N型電晶體MN6、一第一P型電晶體MP1、一第二P型電晶體MP2、一第三P型電晶體MP3、一第四P型電晶體MP4、一第五P型電晶體MP5以及一第六P型電晶體MP6。上述的N型電晶體和P型電晶體皆可利用金氧半導體(MOS)電晶體來實現。此外，本領域具有通常知識者當知，上述的N型半導體和P型半導體可以互換，並不影響本發明的精神，而同樣的原則也可以應用於以下的敘述，因此以下各段中將不再贅述。 In the present embodiment, the buffer 2 can be implemented using an operational amplifier. Therefore, in the input circuit 21, a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3, a fourth N-type transistor MN4, and a fifth N may be included. a transistor MN5, a sixth N-type transistor MN6, a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a fourth P-type transistor MP4, A fifth P-type transistor MP5 and a sixth P-type transistor MP6. Both the N-type transistor and the P-type transistor described above can be realized by a metal oxide semiconductor (MOS) transistor. Further, it is known to those skilled in the art that the above-described N-type semiconductor and P-type semiconductor are interchangeable and do not affect the spirit of the present invention, and the same principles can be applied to the following description, and therefore will not be described in the following paragraphs. Let me repeat.
請繼續參照圖3，第三P型電晶體MP3之第二端電性連接至第一P型電晶體MP1之第一端及第二P型電晶體MP2之第一端。類似地，第三N型電晶體MN3之第一端電性連接至第一N型電晶體MN1之第二端及第二N型電晶體MN2之第二端。第三P型電晶體MP3的第一端電性連接至一正電源V+，而第三N型電晶體MN3之第二端係接地，其中正電源V+的電位可以(但是並不限制)與第一高工作電壓HV1的電位相同。此外，第三P型電晶體MP3的閘極電性連接一第一工作偏壓Vbias1，而第三N型電晶體MN3的閘極則電性連接一第二工作偏壓Vbias2。另外，第一P型電晶體MP1的閘極與第一N型電晶體MN1的閘極電性連接，並且共同電性連接至輸出端230。此外，第二P型電晶體MP2的閘極亦與第二N型電晶體MN2的閘極電性連接。第一N型電晶體MN1之第一端電性連接至 第五P型電晶體MP5的第二端，而第二N型電晶體MN2的第一端則電性連接至第四P型電晶體MP4的第二端。此外，第一P型電晶體MP1的第二端電性連接至第五N型電晶體MN5的第一端，而第二P型電晶體MP2的第二端則是電性連接至第四N型電晶體MN4的第一端。 Referring to FIG. 3, the second end of the third P-type transistor MP3 is electrically connected to the first end of the first P-type transistor MP1 and the first end of the second P-type transistor MP2. Similarly, the first end of the third N-type transistor MN3 is electrically connected to the second end of the first N-type transistor MN1 and the second end of the second N-type transistor MN2. The first end of the third P-type transistor MP3 is electrically connected to a positive power source V+, and the second end of the third N-type transistor MN3 is grounded, wherein the potential of the positive power source V+ can be (but is not limited to) The potential of a high operating voltage HV1 is the same. In addition, the gate of the third P-type transistor MP3 is electrically connected to a first operating bias voltage Vbias1 , and the gate of the third N-type transistor MN3 is electrically coupled to a second operating bias voltage Vbias2 . In addition, the gate of the first P-type transistor MP1 is electrically connected to the gate of the first N-type transistor MN1, and is electrically connected to the output terminal 230 in common. In addition, the gate of the second P-type transistor MP2 is also electrically connected to the gate of the second N-type transistor MN2. The first end of the first N-type transistor MN1 is electrically connected to the second end of the fifth P-type transistor MP5, and the first end of the second N-type transistor MN2 is electrically connected to the fourth P-type transistor. The second end of the MP4. In addition, the second end of the first P-type transistor MP1 is electrically connected to the first end of the fifth N-type transistor MN5, and the second end of the second P-type transistor MP2 is electrically connected to the fourth N The first end of the type transistor MN4.
於本實施例中，第二P型電晶體MP2的閘極端係輸入電路21的輸入端210(也是運算放大器其中一輸入端)，係接收一輸入訊號Vin，並且第二N型電晶體MN2的閘極端電性連接第二P型電晶體MP2的閘極端。類似地，第一P型電晶體MP1的閘極也電性連接至第一N型電晶體MN1的閘極端(也是運算放大器的另一輸入端)，並且共同電性連接至緩衝器2的輸出端230。上述的第一N型電晶體MN1、第二N型電晶體MN2、第三N型電晶體MN3、第一P型電晶體MP1、第二P型電晶體MP2與第三P型電晶體MP3共同組成一差動放大電路。 In this embodiment, the gate terminal of the second P-type transistor MP2 is the input terminal 210 of the input circuit 21 (also one of the input terminals of the operational amplifier), receives an input signal V in , and the second N-type transistor MN2 The gate is electrically connected to the gate terminal of the second P-type transistor MP2. Similarly, the gate of the first P-type transistor MP1 is also electrically connected to the gate terminal of the first N-type transistor MN1 (also the other input terminal of the operational amplifier), and is electrically connected to the output of the buffer 2 in common. End 230. The first N-type transistor MN1, the second N-type transistor MN2, the third N-type transistor MN3, the first P-type transistor MP1, the second P-type transistor MP2 and the third P-type transistor MP3 are collectively A differential amplifying circuit is formed.
請繼續參照圖3，第四P型電晶體MP4和第五P型電晶體MP5的第一端共同耦接至上述的正電源V+，並且第四P型電晶體MP4的閘極與第五P型電晶體MP5的閘極共同電性連接至與該第六N型電晶體MN6及該第六P型電晶體MP6的第一端。其中，第五P型電晶體MP5的第二端與第六N型電晶體MN6及第六P型電晶體MP6之第一端電性連接，而第四P型電晶體MP4的第二端則電性連接至輸出電路23。 Referring to FIG. 3, the first ends of the fourth P-type transistor MP4 and the fifth P-type transistor MP5 are commonly coupled to the positive power supply V+ described above, and the gates of the fourth P-type transistor MP4 and the fifth P The gate of the type transistor MP5 is electrically connected to the first ends of the sixth N-type transistor MN6 and the sixth P-type transistor MP6. The second end of the fifth P-type transistor MP5 is electrically connected to the first ends of the sixth N-type transistor MN6 and the sixth P-type transistor MP6, and the second end of the fourth P-type transistor MP4 is Electrically connected to the output circuit 23.
相對應地，第四N型電晶體MN4的第二端與第五N型電晶體MN5的第二端共同接地，並且第四N型電晶體MN4與第五N型電晶體MN5的閘極端共同地性連接至第六P型電晶體MP6與第六N型電晶體MN6的第二端。其中，第五N型電晶體MN5的第一端電性連接至第六P型電晶體MP6與第六N型電晶體的第二端，而第四N型電晶體MN4的第一端則電性連接至輸出電路23。另外，第六P型電晶體MP6和第六N型電晶體MN6的閘極分別電性連接工作偏壓Vbias3和Vbias4。其中，第四P型電晶體MP4、第五P型電晶體MP5、第六P型電晶體MP6、第四N型電晶體MN4、第五N型電晶體MN5以及第六N型電晶體MN6係電流鏡電路。 Correspondingly, the second end of the fourth N-type transistor MN4 is commonly grounded to the second end of the fifth N-type transistor MN5, and the fourth N-type transistor MN4 is common to the gate terminal of the fifth N-type transistor MN5. The second end of the sixth P-type transistor MP6 and the sixth N-type transistor MN6 are connected to the ground. The first end of the fifth N-type transistor MN5 is electrically connected to the second end of the sixth P-type transistor MP6 and the sixth N-type transistor, and the first end of the fourth N-type transistor MN4 is electrically The connection is made to the output circuit 23. In addition, the gates of the sixth P-type transistor MP6 and the sixth N-type transistor MN6 are electrically connected to the operating bias voltages V bias3 and V bias4 , respectively . The fourth P-type transistor MP4, the fifth P-type transistor MP5, the sixth P-type transistor MP6, the fourth N-type transistor MN4, the fifth N-type transistor MN5, and the sixth N-type transistor MN6 are Current mirror circuit.
偵測電路22係與該輸入電路21電性連接，並且包括有一比 較器221。比較器221之一輸入端(例如正輸入端)係電性連接輸入電路210的輸入端210，以接收輸入訊號Vin。另外，比較器221的另一輸入端(例如是負輸入端)則電性連接一參考電壓Vref。如此一來，比較器221係將輸入訊號Vin與參考電壓Vref進行比較，並且從其輸出端230輸出一開關訊號SWS1。在本實施例中，偵測電路22還配置一反相器222，其輸入端電性連接比較器221的輸出端，以接收開關訊號SWS1，並且輸出反相開關訊號SWS2。 The detecting circuit 22 is electrically connected to the input circuit 21 and includes a comparator 221. An input terminal (eg, a positive input terminal) of the comparator 221 is electrically connected to the input terminal 210 of the input circuit 210 to receive the input signal V in . In addition, the other input terminal (for example, the negative input terminal) of the comparator 221 is electrically connected to a reference voltage V ref . In this way, the comparator 221 compares the input signal V in with the reference voltage V ref and outputs a switching signal SWS1 from its output terminal 230 . In this embodiment, the detecting circuit 22 is further configured with an inverter 222, the input end of which is electrically connected to the output end of the comparator 221 to receive the switching signal SWS1, and outputs the inverted switching signal SWS2.
在本實施中，輸出電路23包括一第一工作電壓選擇電路231、一第二工作電壓選擇電路232以及一電壓提供電路233。電壓提供電路233包括一浮動電流源2331、第一電容元件C1及一第二電容元件C2。另外，第一工作電壓選擇電路231包括有一第七P型電晶體MP7、第七N型電晶體MN7、第一開關SW1、第二開關SW2以及一第三開關SW3。類似地，第二工作電壓選擇電路232包括有一第八P型電晶體MP8、一第八N型電晶體MN8、第四開關SW4、第五開關SW5以及一第六開關SW6。其中，第一開關SW1、第二開關SW2以及第三開關SW3係同時作動，第四開關SW4、第五開關SW5以及第六開關SW6亦為同時作動。在一些實施例中，第一開關SW1、第二開關SW2、第三開關SW3、第四開關SW4、第五開關SW5以及第六開關SW6可以利用MOS電晶體來實現。 In the present embodiment, the output circuit 23 includes a first operating voltage selection circuit 231, a second operating voltage selection circuit 232, and a voltage supply circuit 233. The voltage supply circuit 233 includes a floating current source 2331, a first capacitive element C1, and a second capacitive element C2. In addition, the first working voltage selection circuit 231 includes a seventh P-type transistor MP7, a seventh N-type transistor MN7, a first switch SW1, a second switch SW2, and a third switch SW3. Similarly, the second operating voltage selection circuit 232 includes an eighth P-type transistor MP8, an eighth N-type transistor MN8, a fourth switch SW4, a fifth switch SW5, and a sixth switch SW6. The first switch SW1, the second switch SW2, and the third switch SW3 are simultaneously activated, and the fourth switch SW4, the fifth switch SW5, and the sixth switch SW6 are also simultaneously operated. In some embodiments, the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, the fifth switch SW5, and the sixth switch SW6 may be implemented using a MOS transistor.
該浮動電流源2331具有一第一端N1、一第二端N2、一第三端N3以及一第四端N4。浮動電流源2331之第一端N1與第四P型電晶體MP4之第二端電性連接，而浮動電流源2331之第二端N2與第四N型電晶體MN4之第一端電性連接。此外，浮動電流源2331之第三端N3和第四端N4，分別連接第一電容元件C1之第一端及第二電容元件C2之第二端。另外，第一電容元件C1之第二端和第二電容元件C2之第一端電性連接，並且共同電性連接至訊號輸出端230。其中，浮動電流源2331係於第一電容元件C1之第一端提供一第一操作電壓Vop1，並且於第二電容元件C2之第二端提供一第二操作電壓Vop2。 The floating current source 2331 has a first end N1, a second end N2, a third end N3, and a fourth end N4. The first end N1 of the floating current source 2331 is electrically connected to the second end of the fourth P-type transistor MP4, and the second end N2 of the floating current source 2331 is electrically connected to the first end of the fourth N-type transistor MN4. . In addition, the third end N3 and the fourth end N4 of the floating current source 2331 are respectively connected to the first end of the first capacitive element C1 and the second end of the second capacitive element C2. In addition, the second end of the first capacitive element C1 and the first end of the second capacitive element C2 are electrically connected, and are electrically connected to the signal output end 230 in common. The floating current source 2331 provides a first operating voltage V op1 at a first end of the first capacitive element C1 and a second operating voltage V op2 at a second end of the second capacitive element C2.
於第一工作電壓選擇電路231中，第七P型電晶體MP7之一第一端係電性連接第一高工作電壓HV1，相對地，第七N電晶體MN7 之第二端係電性連接第一低工作電壓LV1。此外，第七P型電晶體MP7之第二端電性連接第七N型電晶體MN7之第一端，並且透過第三開關SW3電性連接至訊號輸出端230。另外，第七P型電晶體MP7的閘極及第七N型電晶體MN7的閘極分別透過第一開關SW1和第二開關SW2電性連接該第一操作電壓Vop1與第二操作電壓Vop2。 In the first working voltage selection circuit 231, the first end of the seventh P-type transistor MP7 is electrically connected to the first high working voltage HV1, and the second end of the seventh N-type transistor MN7 is electrically connected. The first low operating voltage LV1. In addition, the second end of the seventh P-type transistor MP7 is electrically connected to the first end of the seventh N-type transistor MN7, and is electrically connected to the signal output terminal 230 through the third switch SW3. In addition, the gate of the seventh P-type transistor MP7 and the gate of the seventh N-type transistor MN7 are electrically connected to the first operating voltage V op1 and the second operating voltage V through the first switch SW1 and the second switch SW2, respectively. Op2 .
相對地，於第二工作電壓選擇電路232中，第八P型電晶體MP8的第一端電性連接第二高工作電壓HV2，而第八N電晶體MN8的第二端係電性連接第二低工作電壓LV2。此外，第八P型電晶體MP8之第二端電性連接第八N型電晶體MN8之第一端，並且透過第六開關SW6電性連接至訊號輸出端230。第八P型電晶體MP8的閘極及第八N型電晶體MN8的閘極分別透過第四開關SW4和第五開關SW5電性連接第一操作電壓Vop1與第二操作電壓Vop2。在本實施例中，第二低工作電壓LV2可以是接地電位。 In the second working voltage selection circuit 232, the first end of the eighth P-type transistor MP8 is electrically connected to the second high working voltage HV2, and the second end of the eighth N-type transistor MN8 is electrically connected. Two low operating voltages LV2. In addition, the second end of the eighth P-type transistor MP8 is electrically connected to the first end of the eighth N-type transistor MN8, and is electrically connected to the signal output terminal 230 through the sixth switch SW6. The gate of the eighth P-type transistor MP8 and the gate of the eighth N-type transistor MN8 are electrically connected to the first operating voltage V op1 and the second operating voltage V op2 through the fourth switch SW4 and the fifth switch SW5, respectively. In this embodiment, the second low operating voltage LV2 may be a ground potential.
在本實施例中，第一低工作電壓LV1的電位與第二高工作電壓HV2的電位可以是相同，並且第一高工作電壓HV1和第一低工作電壓LV1的電壓差，可以與第二高工作電壓HV2和第二低工作電壓LV2之間的電壓差相同，但是上述二電壓差所形成的電壓區間並不互相重疊。從另一個角度來看，第一低工作電壓LV1的電位值可以是正電源之電位值的一半。例如，第一高工作電壓HV1可以是16V，而第一低工作電壓LV1(或第二高工作電壓HV2)則可以是8V。 In this embodiment, the potential of the first low operating voltage LV1 and the potential of the second high operating voltage HV2 may be the same, and the voltage difference between the first high operating voltage HV1 and the first low operating voltage LV1 may be the second highest The voltage difference between the operating voltage HV2 and the second low operating voltage LV2 is the same, but the voltage intervals formed by the above two voltage differences do not overlap each other. From another point of view, the potential value of the first low operating voltage LV1 may be half of the potential value of the positive power source. For example, the first high operating voltage HV1 may be 16V, and the first low operating voltage LV1 (or the second high operating voltage HV2) may be 8V.
請繼續參照圖3，第三P型電晶體MP3和第三N型電晶體MN3會因為偏壓Vbias1和Vbias2的緣故而分別導通。當輸入訊號Vin是低電位時，由於第一P型電晶體MP1和第二P型電晶體MP2係的閘極端會因為虛短路的特性，因此輸入訊號Vin會被複製到第一電晶體MP1的閘極端，因此第一P型電晶體MP1和第二P型電晶體MP2會被導通(Turn on)，而第一N型電晶體MN1和第二N型電晶體MN2則會關閉(Turn off)，並且輸出訊號Vout也會被拉至低電位。此時，正電源V+的電壓會施加到第四N型電晶體MN4與第五N型電晶體MN5的第一端。由於第五N型電晶體MN5的第一端與閘極端電性連接，因此，第四N型電晶體MN4與第五N 型電晶體MN5都會導通。另外，第六P型電晶體MP6和第六N型電晶體MN6由於閘極被施加偏壓Vbias3和Vbias4的緣故也會導通，因此正電源V+的電壓也會施加到第四P型電晶體MP4和第五P型電晶體MP5的閘極端，而使第四P型電晶體MP4和第五P型電晶體MP5關閉。由於第四N型電晶體MN4與第五N型電晶體MN5會形成電流鏡結構，因此浮動電流源2331會從第三端N3產生電流，並且流經第二電容C2和第一電容C1，因而導致浮動電流源2331的第四端N4是低電位，而第三端N3則是高電位。 Referring to FIG. 3, the third P-type transistor MP3 and the third N-type transistor MN3 are respectively turned on due to the bias voltages V bias1 and V bias2 . When the input signal V in is low level, since the first P-type transistor MP1 and the gate of the second P-type transistor MP2-based terminal because of the characteristics of the imaginary short, and therefore the input signal V in is copied to the first transistor The gate terminal of MP1, so the first P-type transistor MP1 and the second P-type transistor MP2 are turned on, and the first N-type transistor MN1 and the second N-type transistor MN2 are turned off (Turn Off), and the output signal V out is also pulled low. At this time, the voltage of the positive power source V+ is applied to the first ends of the fourth N-type transistor MN4 and the fifth N-type transistor MN5. Since the first end of the fifth N-type transistor MN5 is electrically connected to the gate terminal, the fourth N-type transistor MN4 and the fifth N-type transistor MN5 are both turned on. In addition, the sixth P-type transistor MP6 and the sixth N-type transistor MN6 are also turned on because the gate is biased by the bias voltages Vbias3 and Vbias4 , so the voltage of the positive power source V+ is also applied to the fourth P-type battery. The gate terminals of the crystal MP4 and the fifth P-type transistor MP5 are turned off, and the fourth P-type transistor MP4 and the fifth P-type transistor MP5 are turned off. Since the fourth N-type transistor MN4 and the fifth N-type transistor MN5 form a current mirror structure, the floating current source 2331 generates a current from the third terminal N3 and flows through the second capacitor C2 and the first capacitor C1. The fourth terminal N4 of the floating current source 2331 is caused to be low, and the third terminal N3 is high.
另一方面，由於輸入訊號Vin是低電位，因此比較器221會輸出具有第一狀態(例如是低電位，但並不限定)的開關訊號SWS1，使得第四開關SW4、第五開關SW5和第六開關SW6導通，並且第八N型電晶體MN8和第八P型電晶體MP8也會導通。此時，輸出訊號Vout係低電位，並且介於第二高工作電壓HV2和第二低工作電壓LV2之間。 Switch signal SWS1 the other hand, since the input signal V in is low, and therefore the comparator 221 outputs having a first state (e.g., a low, but not limited to), so that the fourth switch SW4 is, the fifth switch SW5 and The sixth switch SW6 is turned on, and the eighth N-type transistor MN8 and the eighth P-type transistor MP8 are also turned on. At this time, the output signal V out is low and is between the second high operating voltage HV2 and the second low operating voltage LV2.
反之，若是輸入訊號Vin是高電位時，第一P型電晶體MP1和第二P型電晶體MP2會關閉，而第一N型電晶體MN1和MN2則會導通。而與以上所輸入訊號相反，第四N型電晶體MN4與第五N型電晶體MN5會關閉，而第四P型電晶體MP4和第五P型電晶體MP5則會導通，並且也會形成電流鏡的結構。因此，浮動電流源2331會從第三端N3產生電流，並且流經第二電容C1和第一電容C2，使得浮動電流源233的第三端N3是低電位，而第四端N4係高電位。另外，由於輸入訊號Vin是高電位，因此比較器221會輸出具有第二狀態(例如是高電位)的開關訊號SWS1，使得第一開關SW1、第二開關SW2和第三開關SW3會導通，並且第七P型電晶體MP7和第七N型電晶體MN7也會導通。此時，輸出訊號Vout係被推至高電位，並且會介於第一高工作電壓HV1和第一低工作電壓LV1之間。於本實施例中，輸出訊號Vout係為伽瑪補償電壓訊號。 Conversely, if the input signal V in is high potential, the first P-type transistor MP1 and the second P-type transistor MP2 will be closed, and the first N-type transistor MN1 and MN2 will be turned on. In contrast to the above input signals, the fourth N-type transistor MN4 and the fifth N-type transistor MN5 are turned off, and the fourth P-type transistor MP4 and the fifth P-type transistor MP5 are turned on, and are also formed. The structure of the current mirror. Therefore, the floating current source 2331 generates a current from the third terminal N3 and flows through the second capacitor C1 and the first capacitor C2 such that the third terminal N3 of the floating current source 233 is low and the fourth terminal N4 is high. . Further, since the input signal V in it is high, and therefore the comparator 221 outputs a switching signal having a second state SWS1 (e.g. high potential) such that the first switch SW1, the second switch SW2 and the third switch SW3 will be turned on, And the seventh P-type transistor MP7 and the seventh N-type transistor MN7 are also turned on. At this time, the output signal V out is pushed to the high potential line, and will work between the first high voltage and a first low operating voltage HV1 LV1. In the present embodiment, the output signal V out for the gamma compensation voltage signal lines.
請參閱圖4及圖5，圖4為本發明較佳實施例之一種資料驅動電路3之示意圖。圖5為顯示面板之伽瑪補償電壓對輸入資料之關係曲線示意圖。資料驅動電路3包括一電路板31、一第一伽瑪緩衝器311、一第二伽瑪緩衝器312、一第三伽瑪緩衝器313及一第四伽瑪緩衝器314，資料驅動電路3可包括有多個資料驅動單元，例如資料驅動單元30。在本實 施例中，資料驅動單元30包括第二伽瑪緩衝器312和第三伽瑪緩衝器313。然而，在另外一些實施例中，第二伽瑪緩衝器312和第三伽瑪緩衝器313可以位於不同的資料驅動單元中，於本發明不作限制。此外，第一伽瑪緩衝器311及第四伽瑪緩衝器314則屬於其他資料驅動單元。於本實施例中，第一伽瑪緩衝器311及第二伽瑪緩衝器312之輸入端間係透過一被動元件(圖未示)電性連接，第三伽瑪緩衝器313及第四伽瑪緩衝器314之輸入端間亦係透過一被動元件(圖未示)電性連接，上述之被動元件可為阻抗元件、電容元件或是電感元件，或是其他被動元件。於本實施例中，資料驅動單元中之伽瑪緩衝器數量可依據實際需求而定，並不做其他限制。 Please refer to FIG. 4 and FIG. 5. FIG. 4 is a schematic diagram of a data driving circuit 3 according to a preferred embodiment of the present invention. FIG. 5 is a schematic diagram showing the relationship between the gamma compensation voltage of the display panel and the input data. The data driving circuit 3 includes a circuit board 31, a first gamma buffer 311, a second gamma buffer 312, a third gamma buffer 313, and a fourth gamma buffer 314. The data driving circuit 3 A plurality of data driving units, such as the data driving unit 30, may be included. In this reality In the embodiment, the data driving unit 30 includes a second gamma buffer 312 and a third gamma buffer 313. However, in other embodiments, the second gamma buffer 312 and the third gamma buffer 313 may be located in different data driving units, which are not limited in the present invention. In addition, the first gamma buffer 311 and the fourth gamma buffer 314 belong to other data driving units. In this embodiment, the input ends of the first gamma buffer 311 and the second gamma buffer 312 are electrically connected through a passive component (not shown), and the third gamma buffer 313 and the fourth gamma The input terminals of the snubber 314 are also electrically connected through a passive component (not shown). The passive components may be impedance components, capacitive components or inductive components, or other passive components. In this embodiment, the number of gamma buffers in the data driving unit may be determined according to actual needs, and is not limited.
第一伽瑪緩衝器311及第二伽瑪緩衝器312之輸出訊號端間的等效阻抗係第一阻抗R1A，而第三伽瑪緩衝器313及第四伽瑪緩衝器314之輸出訊號端之間的等效阻抗則為第二阻抗R2A。於本實施例中，第一阻抗R1A及第二阻抗R2A的阻抗值係11K/4(請參照圖1和圖2的敘述)。另外，第一伽瑪緩衝器311及第二伽瑪緩衝器312係根據第一高工作電壓HV1及第一低工作電壓LV1工作，相對地第三伽瑪緩衝器313及第四伽瑪緩衝器314則是根據第二高工作電壓HV2及第二低工作電壓LV2工作，其中第一高工作電壓HV1例如是16V，第一低工作電壓LV1與第二高工作電壓HV2則例如是8V，第二低工作電壓LV2可以是接地。根據圖4，第一伽瑪緩衝器311及第二伽瑪緩衝器312之輸入訊號Vin1和Vin2分別為15.8V及8.2V，第三伽瑪緩衝器313及第四伽瑪緩衝器314之輸入訊號Vin3和Vin4分別為7.8V及0.23V，因此，第一伽瑪緩衝器311及第二伽瑪緩衝器312之輸出訊號Vout1、Vout2分別為15.8V及8.2V，第三伽瑪緩衝器313及第四伽瑪緩衝器314之輸出訊號Vout3、Vout4分別為7.8V及0.23V。 The equivalent impedance between the output signal terminals of the first gamma buffer 311 and the second gamma buffer 312 is the first impedance R1A, and the output signals of the third gamma buffer 313 and the fourth gamma buffer 314 are output. The equivalent impedance between them is the second impedance R2A. In the present embodiment, the impedance values of the first impedance R1A and the second impedance R2A are 11K/4 (please refer to the description of FIGS. 1 and 2). In addition, the first gamma buffer 311 and the second gamma buffer 312 are operated according to the first high working voltage HV1 and the first low working voltage LV1, and the third gamma buffer 313 and the fourth gamma buffer are oppositely operated. 314 is operated according to the second high working voltage HV2 and the second low working voltage LV2, wherein the first high working voltage HV1 is, for example, 16V, and the first low working voltage LV1 and the second high working voltage HV2 are, for example, 8V, second. The low operating voltage LV2 can be grounded. According to FIG. 4, the input signals V in1 and V in2 of the first gamma buffer 311 and the second gamma buffer 312 are 15.8V and 8.2V, respectively, and the third gamma buffer 313 and the fourth gamma buffer 314 the input signal V in4 V in3 and 7.8V and 0.23V, respectively, and therefore, the first gamma buffer 311 and the output signal of the second gamma buffer 312 V out1, V out2 8.2V and 15.8V, respectively, of The output signals V out3 and V out4 of the three gamma buffer 313 and the fourth gamma buffer 314 are 7.8V and 0.23V, respectively.
於本實施例中，流經第一阻抗R1A及第二阻抗R2A之電流IR1A和IR2A分別為(15.8V-8.2V)/(11K/4)及(7.8V-0.23V)/(11K/4)，兩者皆約為2.76毫安培，第一伽瑪緩衝器311上所消耗之功率，係為(16V-15.8V)*2.76mA，約為0.552mW，第二伽瑪緩衝器312所消耗之功率，係為(8.2V-8V)*2.76mA，約為0.552mW，第三伽瑪緩衝器313上所消耗之功率，係為(8V-7.8V)*2.76mA，約為0.552mW，第四伽瑪緩衝器 314所消耗之功率，係為(0.23V-0V)*2.76mA，約為0.552mW，本資料驅動電路3中的伽瑪緩衝器，共消耗功率2.208mW。本發明之資料驅動電路消耗之功率(2.208mW)較之習知資料驅動電路之消耗功率(46.336mW)，約減少44.128mW。 In this embodiment, the currents IR1A and IR2A flowing through the first impedance R1A and the second impedance R2A are (15.8V-8.2V)/(11K/4) and (7.8V-0.23V)/(11K/4, respectively). ), both are about 2.76 milliamperes, and the power consumed by the first gamma buffer 311 is (16V-15.8V)*2.76mA, which is about 0.552mW, and is consumed by the second gamma buffer 312. The power is (8.2V-8V)*2.76mA, which is about 0.552mW, and the power consumed by the third gamma buffer 313 is (8V-7.8V)*2.76mA, which is about 0.552mW. Fourth gamma buffer The power consumed by 314 is (0.23V-0V)*2.76mA, which is about 0.552mW. The gamma buffer in the drive circuit 3 of this data consumes a total power of 2.208mW. The power consumed by the data driving circuit of the present invention (2.208 mW) is reduced by about 44.128 mW compared with the power consumption of the conventional data driving circuit (46.336 mW).
圖6為本發明較佳實施例之一種顯示裝置4之示意圖。該顯示裝置4包括有一顯示面板41、至少一資料驅動電路42以及至少一掃描驅動電路43。於本實施例中，資料驅動電路42包括多個資料驅動單元，例如421、422、423和424，而這些資料驅動單元421、422、423和424都如圖3中的資料驅動單元30，分別包含有至少一伽瑪緩衝器。資料驅動電路42及資料驅動單元421、422、423、424及伽瑪緩衝器之結構及動作敘述，皆與上述實施例中之資料驅動電路、資料驅動單元及伽碼緩衝器相同，於此不再贅述。另外，該顯示面板41可為液晶顯示面板(Liquid Crystal Display Panel)或是有機發光二極體顯示面板(Organic Light Emitting Diode Display Panel)。在本實施例中，顯示面板41係液晶顯示面板。由於液晶顯示面板的架構已由眾所皆知，因此不再贅述。 FIG. 6 is a schematic diagram of a display device 4 according to a preferred embodiment of the present invention. The display device 4 includes a display panel 41, at least one data driving circuit 42, and at least one scan driving circuit 43. In this embodiment, the data driving circuit 42 includes a plurality of data driving units, such as 421, 422, 423, and 424, and the data driving units 421, 422, 423, and 424 are all as the data driving unit 30 in FIG. Contains at least one gamma buffer. The structure and operation descriptions of the data driving circuit 42 and the data driving units 421, 422, 423, and 424 and the gamma buffer are the same as those of the data driving circuit, the data driving unit, and the gamma buffer in the above embodiments. Let me repeat. In addition, the display panel 41 can be a liquid crystal display panel or an organic light emitting diode display panel (Organic Light Emitting Diode Display Panel). In the present embodiment, the display panel 41 is a liquid crystal display panel. Since the architecture of the liquid crystal display panel is well known, it will not be described again.
其中，掃描驅動電路43係電性連接該顯示面板41，並提供開關該顯示面板41中各畫素所須的掃描訊號。另外，資料驅動電路42係電性連接顯示面板41，以提供資料訊號，並且可依據第一高工作電壓HV1及第一低工作電壓LV1或第二高工作電壓HV2及第二低工作電壓LV2等不同工作電壓區間而產生伽瑪補償電壓訊號。如此一來，本實施例所提供的顯示裝置4可以降低消耗功率、並避免元件過熱，提供伽瑪補償電壓訊號至顯示面板41，補強該顯示面板41之顯示特性。 The scan driving circuit 43 is electrically connected to the display panel 41 and provides a scanning signal required for switching the pixels in the display panel 41. In addition, the data driving circuit 42 is electrically connected to the display panel 41 to provide a data signal, and can be based on the first high working voltage HV1 and the first low working voltage LV1 or the second high working voltage HV2 and the second low working voltage LV2. A gamma compensation voltage signal is generated for different operating voltage intervals. In this way, the display device 4 provided in this embodiment can reduce power consumption and avoid overheating of components, and provide gamma compensation voltage signals to the display panel 41 to enhance the display characteristics of the display panel 41.
綜上所述，本發明之緩衝器係藉由選擇不同工作電壓區間，降低功率損耗，亦使具有多個緩衝器之資料驅動電路可避免部份緩衝器因跨壓過大而產生過熱的情況，進而降低使用該資料驅動電路之顯示裝置的功率消耗。 In summary, the buffer of the present invention reduces the power loss by selecting different operating voltage intervals, and also enables the data driving circuit with multiple buffers to avoid overheating of some buffers due to excessive voltage. Further, the power consumption of the display device using the data driving circuit is reduced.
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。 The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.
2‧‧‧緩衝器 2‧‧‧buffer
21‧‧‧輸入電路 21‧‧‧Input circuit
22‧‧‧偵測電路 22‧‧‧Detection circuit
23‧‧‧輸出電路 23‧‧‧Output circuit
210‧‧‧輸入端 210‧‧‧ input
221‧‧‧比較器 221‧‧‧ comparator
222‧‧‧反相器 222‧‧‧Inverter
230‧‧‧輸出端 230‧‧‧ Output
231‧‧‧第一工作電壓選擇電路 231‧‧‧First working voltage selection circuit
232‧‧‧第二工作電壓選擇電路 232‧‧‧Second working voltage selection circuit
233‧‧‧電壓提供電路 233‧‧‧Voltage supply circuit
2331‧‧‧浮動電流源 2331‧‧‧Floating current source
C1‧‧‧第一電容 C1‧‧‧first capacitor
C2‧‧‧第二電容 C2‧‧‧second capacitor
HV1‧‧‧第一高工作電壓 HV1‧‧‧ first high working voltage
HV2‧‧‧第二高工作電壓 HV2‧‧‧ second high working voltage
LV1‧‧‧第一低工作電壓 LV1‧‧‧First low operating voltage
LV2‧‧‧第二低工作電壓 LV2‧‧‧ second low working voltage
MP1‧‧‧第一P型電晶體 MP1‧‧‧First P-type transistor
MP2‧‧‧第二P型電晶體 MP2‧‧‧Second P-type transistor
MP3‧‧‧第三P型電晶體 MP3‧‧‧ Third P-type transistor
MP4‧‧‧第四P型電晶體 MP4‧‧‧4th P-type transistor
MP5‧‧‧第五P型電晶體 MP5‧‧‧ Fifth P-type transistor
MP6‧‧‧第六P型電晶體 MP6‧‧‧6th P-type transistor
MP7‧‧‧第七P型電晶體 MP7‧‧‧ seventh P-type transistor
MP8‧‧‧第八P型電晶體 MP8‧‧‧ eighth P-type transistor
MN1‧‧‧第一N型電晶體 MN1‧‧‧First N-type transistor
MN2‧‧‧第二N型電晶體 MN2‧‧‧Second N-type transistor
MN3‧‧‧第三N型電晶體 MN3‧‧‧ Third N-type transistor
MN4‧‧‧第四N型電晶體 MN4‧‧‧4th N-type transistor
MN5‧‧‧第五N型電晶體 MN5‧‧‧ fifth N-type transistor
MN6‧‧‧第六N型電晶體 MN6‧‧‧6th N-type transistor
MN7‧‧‧第七N型電晶體 MN7‧‧‧ seventh N-type transistor
MN8‧‧‧第八N型電晶體 MN8‧‧‧8th N-type transistor
N1‧‧‧第一端 N1‧‧‧ first end
N2‧‧‧第二端 N2‧‧‧ second end
N3‧‧‧第三端 N3‧‧‧ third end
N4‧‧‧第四端 N4‧‧‧ fourth end
SWS1‧‧‧開關訊號 SWS1‧‧‧Switch signal
SWS2‧‧‧反相開關訊號 SWS2‧‧‧Inverted Switch Signal
SW1‧‧‧第一開關 SW1‧‧‧ first switch
SW2‧‧‧第二開關 SW2‧‧‧second switch
SW3‧‧‧第三開關 SW3‧‧‧ third switch
SW4‧‧‧第四開關 SW4‧‧‧fourth switch
SW5‧‧‧第五開關 SW5‧‧‧ fifth switch
SW6‧‧‧第六開關 SW6‧‧‧ sixth switch
V+‧‧‧正電源 V+‧‧‧ positive power supply
Vin‧‧‧輸入訊號 V in ‧‧‧ input signal
Vout‧‧‧輸出訊號 V out ‧‧‧output signal
Vref‧‧‧參考電壓 V ref ‧‧‧reference voltage
Vbias1‧‧‧第一工作偏壓 V bias1 ‧‧‧First working bias
Vbias2‧‧‧第二工作偏壓 V bias2 ‧‧‧second working bias
Vbias3‧‧‧第三工作偏壓 V bias3 ‧‧‧third working bias
Vbias4‧‧‧第四工作偏壓 V bias4 ‧‧‧four working bias
Vop1‧‧‧第一操作電壓 V op1 ‧‧‧first operating voltage
Vop2‧‧‧第二操作電壓 V op2 ‧‧‧second operating voltage
Claims (14)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200822011A (en) * | 2006-11-08 | 2008-05-16 | Chunghwa Picture Tubes Ltd | Driving apparatus |
| TW201126490A (en) * | 2010-01-19 | 2011-08-01 | Silicon Works Co Ltd | Gamma voltage output circuit of source driver |
| US20140240208A1 (en) * | 2013-02-25 | 2014-08-28 | Samsung Electronics Co., Ltd. | Voltage level conversion circuits and display devices including the same |
| TW201505019A (en) * | 2013-04-19 | 2015-02-01 | Magnachip Semiconductor Ltd | Column driver of display device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200822011A (en) * | 2006-11-08 | 2008-05-16 | Chunghwa Picture Tubes Ltd | Driving apparatus |
| TW201126490A (en) * | 2010-01-19 | 2011-08-01 | Silicon Works Co Ltd | Gamma voltage output circuit of source driver |
| US20140240208A1 (en) * | 2013-02-25 | 2014-08-28 | Samsung Electronics Co., Ltd. | Voltage level conversion circuits and display devices including the same |
| TW201505019A (en) * | 2013-04-19 | 2015-02-01 | Magnachip Semiconductor Ltd | Column driver of display device |
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