TWI601118B - Display device and e-paper display device - Google Patents
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Description
本案涉及電子裝置。具體而言，本案涉及一種顯示裝置及電子紙顯示裝置。 This case relates to electronic devices. Specifically, the present invention relates to a display device and an electronic paper display device.
隨著科技的發展，顯示裝置已廣泛地應用在人們的生活當中。 With the development of technology, display devices have been widely used in people's lives.
一般而言，顯示裝置可包括閘極線、資料線、開關、與畫素電極。閘極線用以傳遞閘極訊號，以開啟開關，以令資料線得以提供資料電壓至畫素電極。然而，閘極線與畫素電極會產生電容，而影響閘極訊號的傳遞。因此，如何設置閘極線與畫素電極，為本領域的重要研究議題。 In general, the display device can include a gate line, a data line, a switch, and a pixel electrode. The gate line is used to transmit a gate signal to turn on the switch so that the data line can supply the data voltage to the pixel electrode. However, the gate line and the pixel electrode generate capacitance, which affects the transmission of the gate signal. Therefore, how to set the gate line and the pixel electrode is an important research topic in the field.
本案一實施態樣涉及一種顯示裝置。根據本案一實施例，顯示裝置包括：一第一畫素電極、一第一選擇開關、一第一區域開關、一第一選擇閘極線、一第二畫素電極、一第二選擇開關、一第二區域開關、一第二選擇閘極線、及一區域閘極線。該第一選擇開關電性連接該第一 畫素電極。該第一區域開關電性連接該第一選擇開關及該第一畫素電極。該第一選擇閘極線用以提供一第一選擇閘極訊號至該第一選擇開關的一控制端，以導通或關斷該第一選擇開關。該第二畫素電極相鄰於該第一畫素電極。該第二選擇開關電性連接該第二畫素電極。該第二區域開關電性連接該第二選擇開關及該第二畫素電極。該第二選擇閘極線用以提供一第二選擇閘極訊號至該第二選擇開關的一控制端，以導通或關斷該第二選擇開關，其中當該第一選擇開關導通時，該第二選擇開關關斷，且當該第二選擇開關導通時，該第一選擇開關關斷。該區域閘極線用以提供一區域閘極訊號至該第一區域開關的一控制端以及該第二區域開關的一控制端，以令該第一區域開關及該第二區域開關同時導通或關斷。 An embodiment of the present invention relates to a display device. According to an embodiment of the present disclosure, a display device includes: a first pixel electrode, a first selection switch, a first area switch, a first selection gate line, a second pixel electrode, and a second selection switch, a second area switch, a second selection gate line, and an area gate line. The first selection switch is electrically connected to the first Pixel electrode. The first area switch is electrically connected to the first selection switch and the first pixel electrode. The first selection gate line is configured to provide a first selection gate signal to a control terminal of the first selection switch to turn the first selection switch on or off. The second pixel electrode is adjacent to the first pixel electrode. The second selection switch is electrically connected to the second pixel electrode. The second area switch is electrically connected to the second selection switch and the second pixel electrode. The second selection gate line is configured to provide a second selection gate signal to a control terminal of the second selection switch to turn on or off the second selection switch, wherein when the first selection switch is turned on, the The second selection switch is turned off, and when the second selection switch is turned on, the first selection switch is turned off. The gate line of the area is configured to provide a region gate signal to a control end of the first area switch and a control end of the second area switch, so that the first area switch and the second area switch are simultaneously turned on or Shut down.
根據本案一實施例，其中該第一畫素電極的電極圖案與該第二畫素電極的電極圖案沿該區域閘極線彼此大致對稱。 According to an embodiment of the present invention, the electrode pattern of the first pixel electrode and the electrode pattern of the second pixel electrode are substantially symmetrical with each other along the gate line of the region.
根據本案一實施例，其中該第一畫素電極與該第二畫素電極大致設置於該第一選擇閘極線、該第二選擇閘極線、及/或該區域閘極線的相對兩側。 According to an embodiment of the present invention, the first pixel electrode and the second pixel electrode are substantially disposed on the first selection gate line, the second selection gate line, and/or the opposite sides of the gate line of the region. side.
根據本案一實施例，該顯示裝置更包括：一第一畫素電極、一第一選擇開關、以及一第一區域開關。該第三畫素電極相鄰於該第一畫素電極。該第三選擇開關電性連接該第三畫素電極，其中該第三選擇開關的一控制端用以接收來自該第一選擇閘極線的該第一選擇閘極訊號， 以令該第一選擇開關及該第三選擇開關同時導通或關斷。該第三區域開關電性連接該第三選擇開關及該第三畫素電極，其中該第三區域開關的一控制端用以接收來自該區域閘極線的該區域閘極訊號，以令該第一區域開關、該第二區域開關、及該第三區域開關同時導通或關斷。該第一畫素電極的電極圖案與該第三畫素電極的電極圖案彼此大致對稱。 According to an embodiment of the present disclosure, the display device further includes: a first pixel electrode, a first selection switch, and a first area switch. The third pixel electrode is adjacent to the first pixel electrode. The third selection switch is electrically connected to the third pixel electrode, wherein a control terminal of the third selection switch is configured to receive the first selection gate signal from the first selection gate line, The first selection switch and the third selection switch are simultaneously turned on or off. The third area switch is electrically connected to the third selection switch and the third pixel electrode, wherein a control end of the third area switch is configured to receive the gate signal of the area from the gate line of the area, so that the The first area switch, the second area switch, and the third area switch are simultaneously turned on or off. The electrode pattern of the first pixel electrode and the electrode pattern of the third pixel electrode are substantially symmetrical to each other.
根據本案一實施例，該顯示裝置更包括：一第一資料線及一第二資料線。該第一資料線用以提供一第一資料電壓至該第一畫素電極。該第二資料線用以提供一第二資料電壓至該第三畫素電極。其中該第一畫素電極與該第三畫素電極大致設置於該第一資料線與該第二資料線之間。 According to an embodiment of the present disclosure, the display device further includes: a first data line and a second data line. The first data line is configured to provide a first data voltage to the first pixel electrode. The second data line is configured to provide a second data voltage to the third pixel electrode. The first pixel electrode and the third pixel electrode are disposed substantially between the first data line and the second data line.
本案另一實施態樣涉及一種電子紙顯示裝置。根據本案一實施例，電子紙顯示裝置包括：一電子墨水層、一共通電極、一第一畫素電極、一第一選擇開關、一第一區域開關、一第一選擇閘極線、一第二畫素電極、一第二選擇開關、一第二區域開關、一第二選擇閘極線、及一區域閘極線。該共通電極設置於該電子墨水層的一第一側。該第一畫素電極設置於該電子墨水層的一第二側。該第一選擇開關電性連接該第一畫素電極。該第一區域開關電性連接該第一選擇開關及該第一畫素電極。該第一選擇閘極線用以提供一第一選擇閘極訊號至該第一選擇開關的一控制端，以導通或關斷該第一選擇開關。該第二畫素電極相 鄰於該第一畫素電極，並設置於該電子墨水層的該第二側。該第二選擇開關電性連接該第二畫素電極。該第二區域開關電性連接該第二選擇開關及該第二畫素電極。該第二選擇閘極線用以提供一第二選擇閘極訊號至該第二選擇開關的一控制端，以導通或關斷該第二選擇開關。該區域閘極線用以提供一區域閘極訊號至該第一區域開關的一控制端以及該第二區域開關的一控制端，以令該第一區域開關及該第二區域開關同時導通或關斷。 Another embodiment of the present invention relates to an electronic paper display device. According to an embodiment of the present invention, an electronic paper display device includes: an electronic ink layer, a common electrode, a first pixel electrode, a first selection switch, a first area switch, a first selection gate line, and a first a two-pixel electrode, a second selection switch, a second area switch, a second selection gate line, and an area gate line. The common electrode is disposed on a first side of the electronic ink layer. The first pixel electrode is disposed on a second side of the electronic ink layer. The first selection switch is electrically connected to the first pixel electrode. The first area switch is electrically connected to the first selection switch and the first pixel electrode. The first selection gate line is configured to provide a first selection gate signal to a control terminal of the first selection switch to turn the first selection switch on or off. The second pixel electrode phase Adjacent to the first pixel electrode and disposed on the second side of the electronic ink layer. The second selection switch is electrically connected to the second pixel electrode. The second area switch is electrically connected to the second selection switch and the second pixel electrode. The second selection gate line is configured to provide a second selection gate signal to a control terminal of the second selection switch to turn the second selection switch on or off. The gate line of the area is configured to provide a region gate signal to a control end of the first area switch and a control end of the second area switch, so that the first area switch and the second area switch are simultaneously turned on or Shut down.
根據本案一實施例，其中該第一畫素電極的電極圖案與該第二畫素電極的電極圖案沿該區域閘極線彼此大致對稱。 According to an embodiment of the present invention, the electrode pattern of the first pixel electrode and the electrode pattern of the second pixel electrode are substantially symmetrical with each other along the gate line of the region.
根據本案一實施例，其中該共通電極包括：一第一部份及一第二部份。該第一部份對應於該第一畫素電極。該第二部份對應於該第二畫素電極。該共通電極的該第一部份的電極圖案與該共通電極的該第二部份的電極圖案沿該區域閘極線彼此大致對稱。 According to an embodiment of the present disclosure, the common electrode includes: a first portion and a second portion. The first portion corresponds to the first pixel electrode. The second portion corresponds to the second pixel electrode. The electrode pattern of the first portion of the common electrode and the electrode pattern of the second portion of the common electrode are substantially symmetrical to each other along the gate line of the region.
根據本案一實施例，其中該第一畫素電極與該第二畫素電極大致設置於該第一選擇閘極線、該第二選擇閘極線、及/或該區域閘極線的相對兩側。 According to an embodiment of the present invention, the first pixel electrode and the second pixel electrode are substantially disposed on the first selection gate line, the second selection gate line, and/or the opposite sides of the gate line of the region. side.
根據本案一實施例，該顯示裝置更包括：一第一畫素電極、一第一選擇開關、以及一第一區域開關。該第三畫素電極相鄰於該第一畫素電極。該第三選擇開關電性連接該第三畫素電極，其中該第三選擇開關的一控制端用以接收來自該第一選擇閘極線的該第一選擇閘極訊號， 以令該第一選擇開關及該第三選擇開關同時導通或關斷。該第三區域開關電性連接該第三選擇開關及該第三畫素電極，其中該第三區域開關的一控制端用以接收來自該區域閘極線的該區域閘極訊號，以令該第一區域開關、該第二區域開關、及該第三區域開關同時導通或關斷。該第一畫素電極的電極圖案與該第三畫素電極的電極圖案彼此大致對稱。 According to an embodiment of the present disclosure, the display device further includes: a first pixel electrode, a first selection switch, and a first area switch. The third pixel electrode is adjacent to the first pixel electrode. The third selection switch is electrically connected to the third pixel electrode, wherein a control terminal of the third selection switch is configured to receive the first selection gate signal from the first selection gate line, The first selection switch and the third selection switch are simultaneously turned on or off. The third area switch is electrically connected to the third selection switch and the third pixel electrode, wherein a control end of the third area switch is configured to receive the gate signal of the area from the gate line of the area, so that the The first area switch, the second area switch, and the third area switch are simultaneously turned on or off. The electrode pattern of the first pixel electrode and the electrode pattern of the third pixel electrode are substantially symmetrical to each other.
透過應用上述一實施例，即可減少閘極線的數量，而增加畫素電極的設置空間。 By applying the above embodiment, the number of gate lines can be reduced, and the space for setting the pixel electrodes can be increased.
100‧‧‧顯示裝置 100‧‧‧ display device
110‧‧‧資料驅動器 110‧‧‧Data Drive
120‧‧‧閘極驅動器 120‧‧‧gate driver
PXA‧‧‧畫素陣列 PXA‧‧‧ pixel array
PXAa‧‧‧畫素陣列 PXAa‧‧‧ pixel array
PXAb‧‧‧畫素陣列 PXAb‧‧‧ pixel array
PX‧‧‧畫素單元 PX‧‧‧ pixel unit
PX1‧‧‧畫素單元 PX1‧‧‧ pixel unit
PX2‧‧‧畫素單元 PX2‧‧‧ pixel unit
PX3‧‧‧畫素單元 PX3‧‧‧ pixel unit
PX4‧‧‧畫素單元 PX4‧‧‧ pixel unit
GS1‧‧‧第一選擇閘極線 GS1‧‧‧First choice gate line
GS2‧‧‧第二選擇閘極線 GS2‧‧‧second choice gate line
GB‧‧‧區域閘極線 GB‧‧‧Regional gate line
DL1‧‧‧第一資料線 DL1‧‧‧ first data line
DL2‧‧‧第二資料線 DL2‧‧‧ second data line
TS1‧‧‧選擇開關 TS1‧‧‧Selection switch
TS2‧‧‧選擇開關 TS2‧‧‧Selection switch
TS3‧‧‧選擇開關 TS3‧‧‧Selection switch
TS4‧‧‧選擇開關 TS4‧‧‧Selection switch
TB1‧‧‧區域開關 TB1‧‧‧ area switch
TB2‧‧‧區域開關 TB2‧‧‧ area switch
TB3‧‧‧區域開關 TB3‧‧‧ area switch
TB4‧‧‧區域開關 TB4‧‧‧ area switch
DS1‧‧‧顯示單元 DS1‧‧‧ display unit
DS2‧‧‧顯示單元 DS2‧‧‧ display unit
DS3‧‧‧顯示單元 DS3‧‧‧ display unit
DS4‧‧‧顯示單元 DS4‧‧‧ display unit
CTD‧‧‧共通電極 CTD‧‧‧ common electrode
CTD1‧‧‧共通電極的第一部份 The first part of the CTD1‧‧‧ common electrode
CTD2‧‧‧共通電極的第二部份 The second part of the CTD2‧‧‧ common electrode
CTD3‧‧‧共通電極的第三部份 The third part of the CTD3‧‧‧ common electrode
CTD4‧‧‧共通電極的第四部份 The fourth part of the CTD4‧‧‧ common electrode
ILR‧‧‧電子墨水層 ILR‧‧‧electronic ink layer
PTD1‧‧‧畫素電極 PTD1‧‧‧ pixel electrode
PTD2‧‧‧畫素電極 PTD2‧‧‧ pixel electrode
PTD3‧‧‧畫素電極 PTD3‧‧‧ pixel electrode
PTD4‧‧‧畫素電極 PTD4‧‧‧ pixel electrode
FS‧‧‧第一側 FS‧‧‧ first side
SS‧‧‧第二側 SS‧‧‧ second side
BP‧‧‧黑色粒子 BP‧‧‧ black particles
WP‧‧‧白色粒子 WP‧‧‧White particles
MDL‧‧‧線 MDL‧‧‧ line
WR‧‧‧導線 WR‧‧‧ wire
TR‧‧‧轉接件 TR‧‧‧Adapters
第1圖為根據本案一實施例所繪示的顯示裝置的示意圖；第2圖為根據本案一實施例所繪示的畫素陣列的示意圖；第3圖為根據本案一實施例所繪示的共同電極、畫素電極、及電子紙墨水層的示意圖；第4圖為根據本案一實施例所繪示的畫素陣列的佈局圖；第5圖為根據本案另一實施例所繪示的畫素陣列的佈局圖；第6圖為根據本案另一實施例所繪示的畫素陣列的示意圖；第7圖為根據本案另一實施例所繪示的畫素陣列的佈局圖；第8圖為根據本案另一實施例所繪示的畫素陣列的示意 圖；及第9圖為根據本案另一實施例所繪示的畫素陣列的佈局圖。 1 is a schematic diagram of a display device according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a pixel array according to an embodiment of the present invention; FIG. 3 is a schematic diagram of an embodiment of the present invention. A schematic diagram of a common electrode, a pixel electrode, and an electronic paper ink layer; FIG. 4 is a layout view of a pixel array according to an embodiment of the present invention; and FIG. 5 is a drawing according to another embodiment of the present invention. Layout of a pixel array; FIG. 6 is a schematic diagram of a pixel array according to another embodiment of the present invention; FIG. 7 is a layout diagram of a pixel array according to another embodiment of the present invention; Schematic representation of a pixel array according to another embodiment of the present disclosure FIG. 9 and FIG. 9 are layout diagrams of a pixel array according to another embodiment of the present invention.
以下將以圖式及詳細敘述清楚說明本揭示內容之精神，任何所屬技術領域中具有通常知識者在瞭解本揭示內容之實施例後，當可由本揭示內容所教示之技術，加以改變及修飾，其並不脫離本揭示內容之精神與範圍。 The spirit and scope of the present disclosure will be apparent from the following description of the embodiments of the present disclosure, which may be modified and modified by the teachings of the present disclosure. It does not depart from the spirit and scope of the disclosure.
關於本文中所使用之『第一』、『第二』、...等，並非特別指稱次序或順位的意思，亦非用以限定本發明，其僅為了區別以相同技術用語描述的元件或操作。 The terms "first", "second", etc., as used herein, are not intended to refer to the order or the order, and are not intended to limit the invention, only to distinguish between elements described in the same technical terms or operating.
關於本文中所使用之『電性耦接』，可指二或多個元件相互直接作實體或電性接觸，或是相互間接作實體或電性接觸，而『電性耦接』還可指二或多個元件元件相互操作或動作。 "Electrical coupling" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "electrically coupled" may also refer to Two or more component elements operate or operate with each other.
關於本文中所使用之『包含』、『包括』、『具有』、『含有』等等，均為開放性的用語，即意指包含但不限於。 The terms "including", "including", "having", "containing", etc., as used in this document are all open terms, meaning, but not limited to.
關於本文中所使用之『及/或』，係包括所述事物的任一或全部組合。 With respect to "and/or" as used herein, it is meant to include any or all combinations of the recited.
關於本文中所使用之方向用語，例如：上、下、左、右、前或後等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明並非用來限制本案。 Regarding the directional terms used in this article, such as: up, down, left, right, front or back, etc., only refer to the direction of the additional schema. Therefore, the directional terminology used is used to illustrate that it is not intended to limit the case.
關於本文中所使用之用語『大致』、『約』等，係用以修飾任何可些微變化的數量或誤差，但這種些微變化或誤差並不會改變其本質。 The terms "substantially", "about", and the like, as used herein, are used to modify the quantity or error of any slight variation, but such slight variations or errors do not alter the nature.
關於本文中所使用之用詞(terms)，除有特別註明外，通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。某些用以描述本揭露之用詞將於下或在此說明書的別處討論，以提供本領域技術人員在有關本揭露之描述上額外的引導。 The terms used in this document, unless otherwise specified, generally have the usual meaning of each term used in the art, in the context of the disclosure, and in the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.
參照第1圖，第1圖為根據本案一實施例所繪示的顯示裝置100的示意圖。在一實施例中，顯示裝置100可為電子紙顯示裝置，然本案不以此為限。 Referring to FIG. 1 , FIG. 1 is a schematic diagram of a display device 100 according to an embodiment of the present disclosure. In an embodiment, the display device 100 can be an electronic paper display device, but the present invention is not limited thereto.
在本實施例中，顯示裝置100包括資料驅動器110、閘極驅動器120、以及畫素陣列PXA。在本實施例中，畫素陣列PXA包括多個畫素單元PX，畫素單元PX以矩陣方式排列。 In the present embodiment, the display device 100 includes a data driver 110, a gate driver 120, and a pixel array PXA. In the present embodiment, the pixel array PXA includes a plurality of pixel units PX, and the pixel units PX are arranged in a matrix manner.
在本實施例中，閘極驅動器120用以提供閘極訊號至畫素陣列PXA，以逐列導通畫素單元PX的開關。資料驅動器110用以提供資料電壓至畫素陣列PXA，以令開關被導通的畫素單元PX的畫素電極根據資料電壓進行充電或放電。 In this embodiment, the gate driver 120 is configured to provide a gate signal to the pixel array PXA to turn on the switches of the pixel unit PX column by column. The data driver 110 is configured to supply a data voltage to the pixel array PXA so that the pixel electrodes of the pixel unit PX whose switches are turned on are charged or discharged according to the data voltage.
參照第2圖，第2圖為根據本案一實施例所繪示的畫素陣列PXA的示意圖。在本實施例中，畫素陣列PXA包括畫素單元PX1-PX4，其中每一畫素單元PX1-PX4可為前述畫素單元PX中的一者。前述閘極驅動器120可透過第一選擇 閘極線GS1、第二選擇閘極線GS2、及區域閘極線GB提供閘極訊號至畫素單元PX1-PX4。前述資料驅動器110可透過第一資料線DL1及第二資料線DL2提供資料電壓至畫素單元PX1-PX4。應注意到，以上閘極線、資料線、及畫素單元的數量僅為例示，其它數量的閘極線、資料線、及畫素單元亦在本案範圍之中。例如，在一些實施例中，畫素單元PX3-PX4及第二資料線DL2可省略。 Referring to FIG. 2, FIG. 2 is a schematic diagram of a pixel array PXA according to an embodiment of the present invention. In the present embodiment, the pixel array PXA includes pixel elements PX1-PX4, wherein each of the pixel units PX1-PX4 may be one of the aforementioned pixel units PX. The gate driver 120 can pass the first selection The gate line GS1, the second selection gate line GS2, and the area gate line GB provide gate signals to the pixel units PX1-PX4. The data driver 110 can provide the data voltage to the pixel units PX1-PX4 through the first data line DL1 and the second data line DL2. It should be noted that the number of the above gate lines, data lines, and pixel units is merely an example, and other numbers of gate lines, data lines, and pixel units are also within the scope of the present case. For example, in some embodiments, pixel elements PX3-PX4 and second data line DL2 may be omitted.
在一實施例中，第一選擇閘極線GS1、第二選擇閘極線GS2、及區域閘極線GB彼此平行。在一實施例中，區域閘極線GB與第一選擇閘極線GS1的距離等同區域閘極線GB與第二選擇閘極線GS2的距離。在一實施例中，第一資料線DL1及第二資料線DL2彼此平行。 In an embodiment, the first selection gate line GS1, the second selection gate line GS2, and the area gate line GB are parallel to each other. In one embodiment, the distance between the regional gate line GB and the first selected gate line GS1 is equal to the distance between the area gate line GB and the second selected gate line GS2. In an embodiment, the first data line DL1 and the second data line DL2 are parallel to each other.
在一實施例中，畫素單元PX1包括選擇開關TS1、區域開關TB1、及顯示單元DS1，畫素單元PX2包括選擇開關TS2、區域開關TB2、及顯示單元DS2，畫素單元PX3包括選擇開關TS3、區域開關TB3、及顯示單元DS3，畫素單元PX4包括選擇開關TS4、區域開關TB4、及顯示單元DS4。 In an embodiment, the pixel unit PX1 includes a selection switch TS1, a region switch TB1, and a display unit DS1. The pixel unit PX2 includes a selection switch TS2, a region switch TB2, and a display unit DS2. The pixel unit PX3 includes a selection switch TS3. The area switch TB3 and the display unit DS3, the pixel unit PX4 includes a selection switch TS4, an area switch TB4, and a display unit DS4.
在一實施例中，選擇開關TS1與區域開關TB1彼此電性串聯連接，且選擇開關TS1與區域開關TB1電性連接於第一資料線DL1與顯示單元DS1之間。選擇開關TS2與區域開關TB2彼此電性串聯連接，且選擇開關TS2與區域開關TB2電性連接於第一資料線DL1與顯示單元DS2之間。選擇開關TS3與區域開關TB3彼此電性串聯連接，且選 擇開關TS3與區域開關TB3電性連接於第二資料線DL2與顯示單元DS3之間。選擇開關TS4與區域開關TB4彼此電性串聯連接，且選擇開關TS4與區域開關TB4電性連接於第二資料線DL2與顯示單元DS4之間。 In one embodiment, the selection switch TS1 and the area switch TB1 are electrically connected in series with each other, and the selection switch TS1 and the area switch TB1 are electrically connected between the first data line DL1 and the display unit DS1. The selection switch TS2 and the area switch TB2 are electrically connected in series with each other, and the selection switch TS2 and the area switch TB2 are electrically connected between the first data line DL1 and the display unit DS2. The selection switch TS3 and the area switch TB3 are electrically connected in series with each other, and are selected The switch TS3 and the area switch TB3 are electrically connected between the second data line DL2 and the display unit DS3. The selection switch TS4 and the area switch TB4 are electrically connected in series with each other, and the selection switch TS4 and the area switch TB4 are electrically connected between the second data line DL2 and the display unit DS4.
特別參照第3圖，在一實施例中，每一顯示單元DS1-DS4可包括共通電極CTD的一部分、一畫素電極、及電子墨水層ILR的一部分。例如，在一實施例中，顯示單元DS1包括畫素電極PTD1，共通電極CTD中對應畫素電極PTD1的第一部份CTD1，及電子墨水層ILR中對應畫素電極PTD1的部份，且顯示單元DS2包括畫素電極PTD2，共通電極CTD中對應畫素電極PTD2的第二部份CTD2，及電子墨水層ILR中對應畫素電極PTD2的部份。 With particular reference to FIG. 3, in one embodiment, each display unit DS1-DS4 can include a portion of a common electrode CTD, a pixel electrode, and a portion of an electronic ink layer ILR. For example, in an embodiment, the display unit DS1 includes a pixel electrode PTD1, a first portion CTD1 of the corresponding pixel electrode PTD1 in the common electrode CTD, and a portion of the corresponding pixel electrode PTD1 in the electronic ink layer ILR, and display The unit DS2 includes a pixel electrode PTD2, a second portion CTD2 corresponding to the pixel electrode PTD2 in the common electrode CTD, and a portion corresponding to the pixel electrode PTD2 in the electronic ink layer ILR.
在一實施例中，共通電極CTD設置於電子墨水層ILR的第一側FS，畫素電極PTD1及畫素電極PTD2設置於電子墨水層ILR的第二側SS。畫素電極PTD1及畫素電極PTD2可分別與共通電極CTD的第一部份CTD1及第二部份CTD2產生電場，以分別驅使電子墨水層ILR中的黑色粒子BP及白色粒子WP向電子墨水層ILR的第一側FS及第二側SS聚集，以令顯示單元DS1-DS4得以顯示黑色或白色。應注意到，以上電子墨水層ILR的形態僅為例示，其它形態的電子墨水層ILR亦在本案範圍之中。 In one embodiment, the common electrode CTD is disposed on the first side FS of the electronic ink layer ILR, and the pixel electrode PTD1 and the pixel electrode PTD2 are disposed on the second side SS of the electronic ink layer ILR. The pixel electrode PTD1 and the pixel electrode PTD2 respectively generate an electric field with the first portion CTD1 and the second portion CTD2 of the common electrode CTD to respectively drive the black particles BP and the white particles WP in the electronic ink layer ILR toward the electronic ink layer. The first side FS and the second side SS of the ILR are gathered to allow the display units DS1-DS4 to display black or white. It should be noted that the form of the above electronic ink layer ILR is merely an example, and other forms of the electronic ink layer ILR are also within the scope of the present invention.
再次參照第2圖，在一實施例中，第一選擇閘極線GS1電性連接選擇開關TS1、TS3的控制端，用以提供一第一選擇閘極訊號至選擇開關TS1、TS3的控制端，以同 時導通或關斷選擇開關TS1、TS3。第二選擇閘極線GS2電性連接選擇開關TS2、TS4的控制端，用以提供一第二選擇閘極訊號至選擇開關TS2、TS4的控制端，以同時導通或關斷選擇開關TS2、TS4。區域閘極線GB電性連接區域開關TB1-TB4的控制端，用以提供區域閘極訊號至區域開關TB1-TB4，以同時導通或關斷區域開關TB1-TB4。 Referring again to FIG. 2, in an embodiment, the first selection gate line GS1 is electrically connected to the control terminals of the selection switches TS1, TS3 for providing a first selection gate signal to the control terminals of the selection switches TS1, TS3. With the same Turn on or off select switches TS1, TS3. The second selection gate line GS2 is electrically connected to the control terminals of the selection switches TS2 and TS4 for providing a second selection gate signal to the control terminals of the selection switches TS2 and TS4 to simultaneously turn on or off the selection switches TS2 and TS4. . The control terminal of the regional gate line GB electrically connected area switches TB1-TB4 is used to provide the area gate signal to the area switches TB1-TB4 to simultaneously turn on or off the area switches TB1-TB4.
換言之，在一實施例中，區域閘極訊號可用以同時導通多列顯示單元的區域開關，第一選擇閘極訊號及第二選擇閘極訊號可用以導通一列顯示單元的選擇開關。 In other words, in an embodiment, the regional gate signal can be used to simultaneously turn on the area switches of the plurality of columns of display units, and the first selection gate signal and the second selection gate signal can be used to turn on the selection switches of the column of display units.
在一實施例中，區域閘極訊號的週期大於第一選擇閘極訊號及第二選擇閘極訊號的週期。例如，區域閘極訊號的週期可為5毫秒，且第一選擇閘極訊號及第二選擇閘極訊號的週期可為1.25毫秒或80微秒。 In one embodiment, the period of the regional gate signal is greater than the period of the first selected gate signal and the second selected gate signal. For example, the period of the regional gate signal may be 5 milliseconds, and the period of the first selection gate signal and the second selection gate signal may be 1.25 milliseconds or 80 microseconds.
在一實施例中，在第一期間中，當區域閘極訊號同時導通區域開關TB1-TB4，第一選擇閘極訊號同時導通選擇開關TS1、TS3，且第二選擇閘極訊號同時關斷選擇開關TS2、TS4時，第一資料線DL1通過導通的選擇開關TS1及區域開關TB1提供第一資料電壓至顯示單元DS1，以令顯示單元DS1中的畫素電極據以充電或放電，且第二資料線DL2通過導通的選擇開關TS3及區域開關TB3提供第三資料電壓至顯示單元DS3，以令顯示單元DS3中的畫素電極據以充電或放電。 In an embodiment, in the first period, when the regional gate signal simultaneously turns on the area switches TB1-TB4, the first selection gate signal turns on the selection switches TS1 and TS3 simultaneously, and the second selection gate signal simultaneously turns off the selection. When the switches TS2 and TS4 are switched, the first data line DL1 supplies the first data voltage to the display unit DS1 through the turned-on selection switch TS1 and the area switch TB1, so that the pixel electrodes in the display unit DS1 are charged or discharged, and the second The data line DL2 supplies the third data voltage to the display unit DS3 through the turned-on selection switch TS3 and the area switch TB3 to cause the pixel electrodes in the display unit DS3 to be charged or discharged.
在第一期間後的第二期間中，當區域閘極訊號同時導通區域開關TB1-TB4，第一選擇閘極訊號同時關斷 選擇開關TS1、TS3，且第二選擇閘極訊號同時導通選擇開關TS2、TS4時，第一資料線DL1通過導通的選擇開關TS2及區域開關TB2提供第二資料電壓至顯示單元DS2，以令顯示單元DS2中的畫素電極據以充電或放電，且第二資料線DL2通過導通的選擇開關TS4及區域開關TB4提供第四資料電壓至顯示單元DS4，以令顯示單元DS4中的畫素電極據以充電或放電。 During the second period after the first period, when the area gate signal simultaneously turns on the area switches TB1-TB4, the first selection gate signal is simultaneously turned off. When the switches TS1 and TS3 are selected, and the second selection gate signal simultaneously turns on the selection switches TS2 and TS4, the first data line DL1 provides the second data voltage to the display unit DS2 through the conduction selection switch TS2 and the area switch TB2 to display The pixel electrode in the unit DS2 is charged or discharged, and the second data line DL2 supplies the fourth data voltage to the display unit DS4 through the conductive selection switch TS4 and the area switch TB4, so that the pixel electrode in the display unit DS4 is To charge or discharge.
藉由上述選擇開關TS1-TS4及區域開關TB1-TB4的設置，可避免顯示單元DS1-DS4錯誤地充放電。 By the setting of the selection switches TS1-TS4 and the area switches TB1-TB4, the display units DS1-DS4 can be prevented from being erroneously charged and discharged.
在一實施例中，畫素單元PX1與畫素單元PX2彼此大致對稱。在一實施例中，畫素單元PX1與畫素單元PX2是沿區域閘極線GB彼此大致對稱。更具體來說，在一實施例中，選擇開關TS1、區域開關TB1、及顯示單元DS1的形狀及/或結構皆沿區域閘極線GB大致對稱於選擇開關TS2、區域開關TB2、及顯示單元DS2的形狀及/或結構。在一實施例中，畫素單元PX3與畫素單元PX4亦可彼此大致對稱，其對稱關係可相同或相似於畫素單元PX1與畫素單元PX2間的對稱關係，故在此不贅述。 In an embodiment, the pixel unit PX1 and the pixel unit PX2 are substantially symmetrical to each other. In an embodiment, the pixel unit PX1 and the pixel unit PX2 are substantially symmetrical with each other along the area gate line GB. More specifically, in an embodiment, the shape and/or structure of the selection switch TS1, the area switch TB1, and the display unit DS1 are substantially symmetric with respect to the selection switch TS2, the area switch TB2, and the display unit along the area gate line GB. The shape and / or structure of the DS2. In one embodiment, the pixel unit PX3 and the pixel unit PX4 may also be substantially symmetrical with each other, and the symmetric relationship may be the same or similar to the symmetric relationship between the pixel unit PX1 and the pixel unit PX2, and thus will not be described herein.
藉由上述的設置，即可使畫素單元PX1與畫素單元PX2共用區域閘極線GB，而無須額外地走線。 With the above arrangement, the pixel unit PX1 and the pixel unit PX2 can share the area gate line GB without additional routing.
在一些作法中，不同的畫素單元對應不同的區域閘極線。在如此作法下，區域閘極線的數量較多，故畫素電極的設置空間受到限制。 In some practices, different pixel units correspond to different regional gate lines. In this way, the number of gate lines in the area is large, so the installation space of the pixel electrodes is limited.
在本案實施例中，畫素單元PX1與畫素單元PX2共用一條區域閘極線GB，如此即可減少區域閘極線的數量，而增加畫素電極的設置空間。如此一來，可增加畫素電極的面積，以減少電子墨水層ILR不可控制區域，從而提升顯示品質。 In the embodiment of the present invention, the pixel unit PX1 and the pixel unit PX2 share an area gate line GB, so that the number of area gate lines can be reduced, and the setting space of the pixel electrodes can be increased. In this way, the area of the pixel electrode can be increased to reduce the uncontrollable area of the ILR layer of the electronic ink layer, thereby improving the display quality.
並且，在本案實施例中，畫素單元PX1與畫素單元PX2是沿區域閘極線GB彼此大致對稱，如此可在不增加額外走線的情況下使畫素單元PX1與畫素單元PX2共用同一區域閘極線GB。 Moreover, in the embodiment of the present invention, the pixel unit PX1 and the pixel unit PX2 are substantially symmetrical with each other along the area gate line GB, so that the pixel unit PX1 and the pixel unit PX2 can be shared without adding additional traces. The same area gate line GB.
參照第4圖，第4圖為根據本案一實施例所繪示的畫素陣列PXA的佈局圖。如圖所示，在本實施例中，畫素電極PTD1相鄰於畫素電極PTD2、PTD3，畫素電極PTD4相鄰於畫素電極PTD2、PTD3，畫素電極PTD1、PTD4彼此相對，且畫素電極PTD2、PTD3彼此相對。 Referring to FIG. 4, FIG. 4 is a layout diagram of a pixel array PXA according to an embodiment of the present invention. As shown in the figure, in the present embodiment, the pixel electrode PTD1 is adjacent to the pixel electrodes PTD2 and PTD3, the pixel electrode PTD4 is adjacent to the pixel electrodes PTD2 and PTD3, and the pixel electrodes PTD1 and PTD4 are opposite to each other. The element electrodes PTD2 and PTD3 are opposed to each other.
在本實施例中，畫素單元PX1、PX3的畫素電極PTD1、PTD3的電極圖案與畫素單元PX2、PX4的畫素電極PTD2、PTD4的電極圖案沿區域閘極線GB各別(respectively)彼此大致對稱。在本實施例中，共通電極CTD中對應畫素電極PTD1的第一部份CTD1的電極圖案與共通電極CTD中對應畫素電極PTD2的第二部份CTD2彼此大致對稱。在本實施例中，共通電極CTD中對應畫素電極PTD3的第三部份CTD3的電極圖案與共通電極CTD中對應畫素電極PTD4的第四部份CTD4彼此大致對稱。 In the present embodiment, the electrode patterns of the pixel electrodes PTD1, PTD3 of the pixel units PX1, PX3 and the electrode patterns of the pixel electrodes PTD2, PTD4 of the pixel units PX2, PX4 are differently along the area gate line GB (respectively) They are roughly symmetrical to each other. In this embodiment, the electrode pattern of the first portion CTD1 of the corresponding pixel electrode PTD1 in the common electrode CTD and the second portion CTD2 of the corresponding pixel electrode PTD2 in the common electrode CTD are substantially symmetrical with each other. In the present embodiment, the electrode pattern of the third portion CTD3 of the corresponding pixel electrode PTD3 in the common electrode CTD and the fourth portion CTD4 of the corresponding pixel electrode PTD4 in the common electrode CTD are substantially symmetrical with each other.
在本實施例中，畫素電極PTD1、PTD3大致設置 於第一選擇閘極線GS1、第二選擇閘極線GS2、及/或區域閘極線GB的一側，且畫素電極PTD2、PTD4大致設置於第一選擇閘極線GS1、第二選擇閘極線GS2、及/或區域閘極線GB的相對另一側。 In this embodiment, the pixel electrodes PTD1 and PTD3 are substantially set. On the side of the first selection gate line GS1, the second selection gate line GS2, and/or the area gate line GB, and the pixel electrodes PTD2, PTD4 are substantially disposed on the first selection gate line GS1, the second selection The opposite side of the gate line GS2 and/or the area gate line GB.
在本實施例中，共通電極CTD中對應畫素電極PTD1、PTD3的第一部份CTD1、第三部份CTD3大致設置於第一選擇閘極線GS1、第二選擇閘極線GS2、及/或區域閘極線GB的一側，且共通電極CTD中對應畫素電極PTD2、PTD4的第二部份CTD2、第四部份CTD4大致設置於第一選擇閘極線GS1、第二選擇閘極線GS2、及/或區域閘極線GB的相對另一側。 In this embodiment, the first portion CTD1 and the third portion CTD3 of the corresponding pixel electrodes PTD1 and PTD3 in the common electrode CTD are substantially disposed on the first selection gate line GS1, the second selection gate line GS2, and/or Or the side of the regional gate line GB, and the second portion CTD2 and the fourth portion CTD4 of the corresponding pixel electrodes PTD2 and PTD4 in the common electrode CTD are substantially disposed on the first selection gate line GS1 and the second selection gate The other side of the line GS2, and/or the area gate line GB.
在本實施例中，畫素電極PTD1、畫素電極PTD2、及共通電極CTD中對應畫素電極PTD1、PTD2的第一部份CTD1、第二部份CTD2皆大致設置於第一資料線DL1及第二資料線DL2之間。 In this embodiment, the first portion CTD1 and the second portion CTD2 of the corresponding pixel electrodes PTD1 and PTD2 of the pixel electrode PTD1, the pixel electrode PTD2, and the common electrode CTD are substantially disposed on the first data line DL1 and Between the second data line DL2.
參照第5圖，第5圖為根據本案一實施例所繪示的畫素陣列PXA的佈局圖。第5圖中的畫素陣列PXA大致與第4圖中的畫素陣列PXA相似，故重複的部份在此不贅述。 Referring to FIG. 5, FIG. 5 is a layout diagram of a pixel array PXA according to an embodiment of the present invention. The pixel array PXA in FIG. 5 is substantially similar to the pixel array PXA in FIG. 4, and thus the repeated portions are not described herein.
在本實施例中，顯示裝置100可更包括轉接件TR。在本實施例中，轉接件TR用以電性連接不同導電層。在本實施例中，轉接件TR可設置於縱向的資料線DL1、DL2與橫向的導線WR間的交叉點，用以電性連接彼此垂直資料線DL1、DL2與導線WR。 In the embodiment, the display device 100 may further include an adapter TR. In this embodiment, the adapter TR is used to electrically connect different conductive layers. In this embodiment, the adapter TR can be disposed at an intersection between the longitudinal data lines DL1, DL2 and the lateral wires WR for electrically connecting the mutually perpendicular data lines DL1, DL2 and the wires WR.
藉由如此設置，資料電壓的提供方式可更為多 樣。例如，在一些實施例中，不同資料線(如資料線DL1、DL2)可透過轉接件TR電性連接至同一導線WR。如此一來，同一資料電壓可同時提供至不同的資料線。 With this setting, the data voltage can be supplied in more ways. kind. For example, in some embodiments, different data lines (such as data lines DL1, DL2) can be electrically connected to the same wire WR through the adapter TR. In this way, the same data voltage can be provided to different data lines at the same time.
參照第6圖，第6圖為根據本案一實施例所繪示的畫素陣列PXAa的示意圖。第6圖中的畫素陣列PXAa與第2圖中的畫素陣列PXA相似，故以下僅就相異之處進行說明。 Referring to FIG. 6, FIG. 6 is a schematic diagram of a pixel array PXAa according to an embodiment of the present invention. The pixel array PXAa in Fig. 6 is similar to the pixel array PXA in Fig. 2, and therefore only the differences will be described below.
在本實施例中，在一實施例中，畫素單元PX1與畫素單元PX3彼此大致對稱。在一實施例中，畫素單元PX1與畫素單元PX3是沿線MDL彼此大致對稱，其中線MDL平行於第一資料線DL1與第二資料線DL2，且線MDL與第一資料線DL1的距離等同線MDL與第二資料線DL2的距離。 In the present embodiment, in one embodiment, the pixel unit PX1 and the pixel unit PX3 are substantially symmetrical to each other. In an embodiment, the pixel unit PX1 and the pixel unit PX3 are substantially symmetrical with each other along the line MDL, wherein the line MDL is parallel to the first data line DL1 and the second data line DL2, and the distance between the line MDL and the first data line DL1 The distance between the equivalent line MDL and the second data line DL2.
更具體來說，在一實施例中，選擇開關TS1、區域開關TB1、及顯示單元DS1的形狀及/或結構皆沿線MDL大致對稱於選擇開關TS3、區域開關TB3、及顯示單元DS3的形狀及/或結構。在一實施例中，畫素單元PX2與畫素單元PX4亦可彼此大致對稱，其對稱關係可相同或相似於畫素單元PX1與畫素單元PX3間的對稱關係，故在此不贅述。 More specifically, in an embodiment, the shape and/or structure of the selection switch TS1, the area switch TB1, and the display unit DS1 are substantially symmetric with respect to the shape of the selection switch TS3, the area switch TB3, and the display unit DS3 along the line MDL. / or structure. In one embodiment, the pixel unit PX2 and the pixel unit PX4 may also be substantially symmetrical with each other, and the symmetric relationship may be the same or similar to the symmetric relationship between the pixel unit PX1 and the pixel unit PX3, and thus will not be described herein.
在一實施例中，畫素單元PX1-PX4大致設置於第一資料線DL1與第二資料線DL2之間。在一實施例中，畫素單元PX1-PX2大致設置於第一資料線DL1及線MDL之間。在一實施例中，畫素單元PX3-PX4大致設置於第二資料線DL2及線MDL之間。 In an embodiment, the pixel units PX1-PX4 are disposed substantially between the first data line DL1 and the second data line DL2. In an embodiment, the pixel units PX1-PX2 are disposed substantially between the first data line DL1 and the line MDL. In an embodiment, the pixel units PX3-PX4 are disposed substantially between the second data line DL2 and the line MDL.
參照第7圖，第7圖為根據本案一實施例所繪示的畫素陣列PXAa的佈局圖。第7圖中的畫素陣列PXAa與第4圖 中的畫素陣列PXA相似，故以下僅就相異之處進行說明。 Referring to FIG. 7, FIG. 7 is a layout diagram of a pixel array PXAa according to an embodiment of the present invention. Pixel array PXAa and Figure 4 in Figure 7 The pixel array PXA is similar, so the following only explains the differences.
如圖所示，在本實施例中，畫素單元PX1、PX2的畫素電極PTD1、PTD2的電極圖案與畫素單元PX3、PX4的畫素電極PTD3、PTD4的電極圖案各別(respectively)沿線MDL彼此大致對稱。在本實施例中，共通電極CTD的電極圖案沿線MDL彼此大致對稱。 As shown in the figure, in the present embodiment, the electrode patterns of the pixel electrodes PTD1, PTD2 of the pixel units PX1, PX2 and the electrode patterns of the pixel electrodes PTD3, PTD4 of the pixel units PX3, PX4 are separately observed. The MDLs are roughly symmetrical to each other. In the present embodiment, the electrode patterns of the common electrode CTD are substantially symmetrical to each other along the line MDL.
在本實施例中，畫素電極PTD1-PTD4及共通電極CTD皆大致設置於第一資料線DL1及第二資料線DL2之間。在本實施例中，畫素電極PTD1-PTD2大致設置於第一資料線DL1及線MDL之間，且畫素電極PTD3-PTD4大致設置於第二資料線DL2及線MDL之間。 In this embodiment, the pixel electrodes PTD1-PTD4 and the common electrode CTD are disposed substantially between the first data line DL1 and the second data line DL2. In this embodiment, the pixel electrodes PTD1-PTD2 are disposed substantially between the first data line DL1 and the line MDL, and the pixel electrodes PTD3-PTD4 are disposed substantially between the second data line DL2 and the line MDL.
參照第8圖，第8圖為根據本案一實施例所繪示的畫素陣列PXAb的示意圖。第8圖中的畫素陣列PXAb與第2圖中的畫素陣列PXA相似，故以下僅就相異之處進行說明。 Referring to FIG. 8, FIG. 8 is a schematic diagram of a pixel array PXAb according to an embodiment of the present invention. The pixel array PXAb in Fig. 8 is similar to the pixel array PXA in Fig. 2, and therefore only the differences will be described below.
在本實施例中，在一實施例中，畫素單元PX1與畫素單元PX3彼此大致對稱。在一實施例中，畫素單元PX1與畫素單元PX3是沿線MDL彼此大致對稱，其中線MDL平行於第一資料線DL1與第二資料線DL2，且線MDL與第一資料線DL1的距離等同線MDL與第二資料線DL2的距離。 In the present embodiment, in one embodiment, the pixel unit PX1 and the pixel unit PX3 are substantially symmetrical to each other. In an embodiment, the pixel unit PX1 and the pixel unit PX3 are substantially symmetrical with each other along the line MDL, wherein the line MDL is parallel to the first data line DL1 and the second data line DL2, and the distance between the line MDL and the first data line DL1 The distance between the equivalent line MDL and the second data line DL2.
更具體來說，在一實施例中，選擇開關TS1、區域開關TB1、及顯示單元DS1的形狀及/或結構皆沿線MDL大致對稱於選擇開關TS3、區域開關TB3、及顯示單元DS3的形狀及/或結構。在一實施例中，畫素單元PX2與畫素單元PX4亦可彼此大致對稱，其對稱關係可相同或相似於畫 素單元PX1與畫素單元PX3間的對稱關係，故在此不贅述。 More specifically, in an embodiment, the shape and/or structure of the selection switch TS1, the area switch TB1, and the display unit DS1 are substantially symmetric with respect to the shape of the selection switch TS3, the area switch TB3, and the display unit DS3 along the line MDL. / or structure. In an embodiment, the pixel unit PX2 and the pixel unit PX4 may also be substantially symmetrical with each other, and the symmetrical relationship may be the same or similar to the drawing. The symmetry relationship between the prime unit PX1 and the pixel unit PX3 is not described here.
在一實施例中，第一資料線DL1與第二資料線DL2大致設置於畫素單元PX1、PX3之間。在一實施例中，第一資料線DL1與第二資料線DL2大致設置於畫素單元PX2、PX4之間。換言之，畫素單元PX1-PX2大致設置於第一資料線DL1與第二資料線DL2的一側，畫素單元PX3-PX4大致設置於第一資料線DL1與第二資料線DL2的相對另一側。 In an embodiment, the first data line DL1 and the second data line DL2 are disposed substantially between the pixel units PX1 and PX3. In an embodiment, the first data line DL1 and the second data line DL2 are disposed substantially between the pixel units PX2 and PX4. In other words, the pixel units PX1-PX2 are disposed substantially on one side of the first data line DL1 and the second data line DL2, and the pixel units PX3-PX4 are disposed substantially on the opposite side of the first data line DL1 and the second data line DL2. side.
參照第9圖，第9圖為根據本案一實施例所繪示的畫素陣列PXAb的佈局圖。第9圖中的畫素陣列PXAb與第4圖中的畫素陣列PXA相似，故以下僅就相異之處進行說明。 Referring to FIG. 9, FIG. 9 is a layout diagram of a pixel array PXAb according to an embodiment of the present invention. The pixel array PXAb in Fig. 9 is similar to the pixel array PXA in Fig. 4, and therefore only the differences will be described below.
如圖所示，在本實施例中，畫素單元PX1、PX2的畫素電極PTD1、PTD2的電極圖案與畫素單元PX3、PX4的畫素電極PTD3、PTD4的電極圖案各別(respectively)沿線MDL彼此大致對稱。在本實施例中，對應於畫素電極PTD1、PTD2的共通電極CTD的第一部份CTD1、第二部份CTD2的電極圖案與對應於畫素電極PTD3、PTD4的共通電極CTD的第三部份CTD3、第四部份CTD4的電極圖案各別(respectively)沿線MDL彼此大致對稱。 As shown in the figure, in the present embodiment, the electrode patterns of the pixel electrodes PTD1, PTD2 of the pixel units PX1, PX2 and the electrode patterns of the pixel electrodes PTD3, PTD4 of the pixel units PX3, PX4 are separately observed. The MDLs are roughly symmetrical to each other. In this embodiment, the electrode pattern corresponding to the first portion CTD1 of the common electrode CTD1 of the pixel electrodes PTD1, PTD2 and the second portion CTD2 and the third portion of the common electrode CTD corresponding to the pixel electrodes PTD3, PTD4 The electrode patterns of the CTD3 and the fourth portion CTD4 are substantially symmetric with each other along the line MDL.
在本實施例中，畫素電極PTD1、PTD2大致設置於第一資料線DL1及第二資料線DL2的一側，且畫素電極PTD3、PTD4大致設置於第一資料線DL1及第二資料線DL2的相對另一側。在本實施例中，共通電極CTD的第一部份CTD1、第三部份CTD2大致設置於第一資料線DL1及第二資 料線DL2的一側，且共通電極CTD的第三部份CTD3、第四部份CTD4大致設置於第一資料線DL1及第二資料線DL2的相對另一側。 In this embodiment, the pixel electrodes PTD1 and PTD2 are disposed substantially on one side of the first data line DL1 and the second data line DL2, and the pixel electrodes PTD3 and PTD4 are substantially disposed on the first data line DL1 and the second data line. The opposite side of DL2. In this embodiment, the first portion CTD1 and the third portion CTD2 of the common electrode CTD are substantially disposed on the first data line DL1 and the second resource. One side of the material line DL2, and the third portion CTD3 and the fourth portion CTD4 of the common electrode CTD are disposed substantially on opposite sides of the first data line DL1 and the second data line DL2.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and retouched without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.
PXA‧‧‧畫素陣列 PXA‧‧‧ pixel array
PX1‧‧‧畫素單元 PX1‧‧‧ pixel unit
PX2‧‧‧畫素單元 PX2‧‧‧ pixel unit
PX3‧‧‧畫素單元 PX3‧‧‧ pixel unit
PX4‧‧‧畫素單元 PX4‧‧‧ pixel unit
GS1‧‧‧第一選擇閘極線 GS1‧‧‧First choice gate line
GS2‧‧‧第二選擇閘極線 GS2‧‧‧second choice gate line
GB‧‧‧區域閘極線 GB‧‧‧Regional gate line
DL1‧‧‧第一資料線 DL1‧‧‧ first data line
DL2‧‧‧第二資料線 DL2‧‧‧ second data line
TS1‧‧‧選擇開關 TS1‧‧‧Selection switch
TS2‧‧‧選擇開關 TS2‧‧‧Selection switch
TS3‧‧‧選擇開關 TS3‧‧‧Selection switch
TS4‧‧‧選擇開關 TS4‧‧‧Selection switch
TB1‧‧‧區域開關 TB1‧‧‧ area switch
TB2‧‧‧區域開關 TB2‧‧‧ area switch
TB3‧‧‧區域開關 TB3‧‧‧ area switch
TB4‧‧‧區域開關 TB4‧‧‧ area switch
DS1‧‧‧顯示單元 DS1‧‧‧ display unit
DS2‧‧‧顯示單元 DS2‧‧‧ display unit
DS3‧‧‧顯示單元 DS3‧‧‧ display unit
DS4‧‧‧顯示單元 DS4‧‧‧ display unit
Claims (10)
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| JP2008268853A (en) * | 2007-03-29 | 2008-11-06 | Seiko Epson Corp | Electrophoretic display device, driving method thereof, and electronic apparatus |
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