TWI600131B - Lead frame manufacturing method - Google Patents
Lead frame manufacturing method Download PDFInfo
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- TWI600131B TWI600131B TW104138669A TW104138669A TWI600131B TW I600131 B TWI600131 B TW I600131B TW 104138669 A TW104138669 A TW 104138669A TW 104138669 A TW104138669 A TW 104138669A TW I600131 B TWI600131 B TW I600131B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- ing And Chemical Polishing (AREA)
Description
本發明係關於引線架之製造方法，特別是關於對表面實施粗化處理之引線架之製造方法。 The present invention relates to a method of manufacturing a lead frame, and more particularly to a method of manufacturing a lead frame for roughening a surface.
一直以來，在搭載半導體元件並對其進行樹脂密封之半導體封裝所使用之引線架中，在以提高與樹脂之密接力為目的而對引線架進行粗化處理之情況下，首先，對成為材料之金屬材料表背面整體進行粗化處理，而後使用該材料成形引線架。在該情況下，形成引線架之蝕刻加工面或衝壓加工面形成未進行粗化處理之引線架。 In a lead frame used for a semiconductor package in which a semiconductor element is mounted and resin-sealed, in the case of roughening the lead frame for the purpose of improving the adhesion to the resin, first, the material is used as a material. The back surface of the metal material is roughened as a whole, and then the material is used to form the lead frame. In this case, the etched surface or the press-formed surface on which the lead frame is formed forms a lead frame that is not roughened.
另外，當在形成引線架形狀後實施粗化處理之情況下，形成表背面與側面整面被粗化之引線架。 Further, in the case where the roughening treatment is performed after the shape of the lead frame is formed, a lead frame in which the front and back sides and the side surface are roughened is formed.
在任一種方法中，均存在如下問題，即由於引線架表面被粗化，所以在需要光澤度之引線架中，即使對表面實施電鍍，也存在無法獲得所要求之光澤度之情況。另外，在搭載半導體元件之部分(PAD部)中，也存在如下問題，即存在用於接著搭載之半導體元件之糊劑從PAD部流出之情況。 In any of the methods, there is a problem that the surface of the lead frame is roughened, so that in the lead frame requiring gloss, even if the surface is plated, the desired glossiness may not be obtained. Further, in the portion (PAD portion) on which the semiconductor element is mounted, there is a problem in that the paste for the semiconductor element mounted next is discharged from the PAD portion.
針對上述問題，在專利文獻1中，公開了先形成電鍍層，而後將該電鍍層設為光罩並利用蝕刻液對引線架進行粗化之技術。 In order to solve the above problems, Patent Document 1 discloses a technique in which a plating layer is formed first, and then the plating layer is used as a mask, and the lead frame is roughened by an etching solution.
[專利文獻1]日本特開2008-187045號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2008-187045
然而，在專利文獻1所記載之結構中，存在電鍍面依據所要求之電鍍之種類而粗化之情況，存在也需要選定蝕刻液之情況進而存在並非通用之問題。另外，也需要在不需要粗化之部分形成電鍍層，因此也存在導致成本上升之問題。 However, in the structure described in Patent Document 1, there is a case where the plating surface is roughened depending on the type of plating required, and there is a case where it is necessary to select an etching liquid, and there is a problem that it is not common. In addition, it is also necessary to form a plating layer in a portion that does not require roughening, and thus there is a problem that the cost is increased.
然而，近年來，要求半導體封裝之小型、薄型化，因此產生因該封裝所使用之樹脂與引線架因熱膨脹係數之差異等而從其邊界面產生剝離之問題。例如，在QFN(Quad Flat Non-Leaded)類型之封裝中，被使用之引線架之側面與表面和樹脂連接，背面露出至封裝下表面，因此引線架之表面側基於避免用於搭載並接著半導體元件之糊劑流出之問題而不需要粗化。相同地，需要藉由引線結合而與半導體元件電連接之部位，也因結合而不需要粗化。而且，在與樹脂連接之側面以及如上所述不對半導體元件之接著、結合產生影響之部位需要表面粗化。 However, in recent years, semiconductor packages have been required to be small and thin, and there has been a problem that peeling occurs from the boundary surface of the resin and the lead frame used in the package due to a difference in thermal expansion coefficient or the like. For example, in a QFN (Quad Flat Non-Leaded) type package, the side surface of the lead frame to be used is connected to the surface and the resin, and the back surface is exposed to the lower surface of the package, so that the surface side of the lead frame is based on avoidance for mounting and then semiconductor The problem of the outflow of the paste of the component does not require roughening. Similarly, a portion to be electrically connected to the semiconductor element by wire bonding is required, and no roughening is required due to bonding. Further, it is necessary to roughen the surface on the side connected to the resin and the portion which does not affect the bonding and bonding of the semiconductor element as described above.
然而，在形成覆蓋引線架之表面與背面之光罩並對側面進行粗化之方法、將對整個面進行了粗化之引線架之表面恢復平坦之方法中，步驟數之增加、成本上升較為明顯，從而無法保持原樣地採用這些方法。 However, in the method of forming the mask covering the surface and the back surface of the lead frame and roughening the side surface, and reducing the surface of the lead frame which has been roughened over the entire surface, the number of steps is increased and the cost is increased. Obviously, these methods cannot be used as they are.
因此，本發明之目的在於提供一種能夠不使步驟數、製造成本增加地僅對需要之部位實施表面粗化處理之引線架之製造方法。 Accordingly, an object of the present invention is to provide a method of manufacturing a lead frame capable of performing surface roughening treatment only on a required portion without increasing the number of steps and manufacturing cost.
為了實現上述目的，本發明之一態樣提供一種引線架之製造方法，該引線架具有藉由半蝕刻加工形成之凹部，並且表面局部地被粗化處理，上述引線架之製造方法具有：使用具有半蝕刻加工用圖案和貫通蝕刻加工用圖案之光罩對金屬板進行蝕刻，在該金屬板形成上述凹部和貫通圖案之蝕刻步驟；將上述半蝕刻加工用圖案變形為粗化處理用之開口之光罩變形步驟；以及使用上述半蝕刻加工用圖案變形為上述粗化處理用之開口之上述光罩，對上述金屬板進行粗化處理之粗化處理步驟。 In order to achieve the above object, an aspect of the present invention provides a method of manufacturing a lead frame having a recess formed by a half etching process, and the surface is partially roughened, and the lead frame manufacturing method has the following advantages: An etching process for etching a metal plate by a mask having a half etching process pattern and a through etching process pattern, forming the concave portion and the through pattern on the metal plate; and deforming the half etching process pattern into an opening for roughening processing a mask deformation step; and a roughening step of roughening the metal sheet by using the mask in which the half etching processing pattern is deformed into the opening for the roughening treatment.
根據本發明，能夠獲得不追加新的步驟，而僅對需要之區域實施粗化處理之引線架。 According to the present invention, it is possible to obtain a lead frame which is subjected to roughening treatment only to a required region without adding a new step.
10‧‧‧金屬板 10‧‧‧Metal plates
11‧‧‧半導體元件搭載部 11‧‧‧Semiconductor component mounting department
12‧‧‧端子部 12‧‧‧ Terminals
11a、12a‧‧‧表面 11a, 12a‧‧‧ surface
11b、12b‧‧‧背面 11b, 12b‧‧‧ back
11c、12c‧‧‧側面 11c, 12c‧‧‧ side
13‧‧‧貫通圖案 13‧‧‧through pattern
14‧‧‧凹部 14‧‧‧ recess
15‧‧‧引線架 15‧‧‧ lead frame
20‧‧‧粗化處理層 20‧‧‧ roughening layer
30‧‧‧電鍍層 30‧‧‧Electroplating
40‧‧‧半導體元件 40‧‧‧Semiconductor components
50‧‧‧接合線 50‧‧‧bonding line
60‧‧‧樹脂 60‧‧‧Resin
70‧‧‧半導體封裝 70‧‧‧ semiconductor package
80、80a‧‧‧光罩 80, 80a‧‧‧ mask
81‧‧‧抗蝕劑層 81‧‧‧resist layer
82‧‧‧開口 82‧‧‧ openings
83‧‧‧貫通蝕刻加工用圖案 83‧‧‧through etching processing pattern
84‧‧‧半蝕刻加工用圖案 84‧‧‧ Half etching processing pattern
圖1是顯示使用了利用本發明實施形態之引線架之製造方法而製造之引線架之半導體封裝之一例的圖。 Fig. 1 is a view showing an example of a semiconductor package using a lead frame manufactured by the method for manufacturing a lead frame according to an embodiment of the present invention.
圖2是放大顯示利用本發明實施形態之引線架之製造方法而製造之引線架之半導體元件搭載部之粗化處理層之形成部分的圖。 FIG. 2 is a view showing a part of a roughened layer of a semiconductor element mounting portion of a lead frame manufactured by a method for manufacturing a lead frame according to an embodiment of the present invention.
圖3是顯示本發明實施形態所涉及之引線架之製造方法之一例之一系列步驟的圖。圖3(a)是顯示電鍍層形成步驟以及蝕刻光罩形成步驟之一例的圖。圖3(b)是顯示蝕刻步驟以及蝕刻光罩變形步驟之一例的圖。圖3(c)是顯示粗化處理步驟之一例的圖。圖3(d)是顯示光罩除去步驟之一例的圖。 Fig. 3 is a view showing a series of steps of an example of a method of manufacturing a lead frame according to an embodiment of the present invention. Fig. 3 (a) is a view showing an example of a plating layer forming step and an etching mask forming step. Fig. 3(b) is a view showing an example of an etching step and a step of deforming the etching mask. Fig. 3(c) is a view showing an example of the roughening processing procedure. Fig. 3(d) is a view showing an example of a mask removal step.
以下，參照圖式對用於實施本發明之形態進行說明。 Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
圖1是顯示使用了利用本發明實施方式之引線架之製造方法而製造之引線架之半導體封裝之一例的圖。 1 is a view showing an example of a semiconductor package using a lead frame manufactured by the method for manufacturing a lead frame according to an embodiment of the present invention.
使用了利用本發明實施方式之引線架之製造方法而製造之引線架之半導體封裝70具有引線架15、粗化處理層20、電鍍層30、半導體元件40、接合線50以及樹脂60。另外，引線架15具有半導體元件搭載部11以及端子部12。在半導體元件搭載部11與端子部12之間形成有貫通圖案13，在半導體元件搭載部11之表面形成有凹部14。 The semiconductor package 70 using the lead frame manufactured by the method for manufacturing a lead frame according to an embodiment of the present invention has a lead frame 15, a roughened layer 20, a plating layer 30, a semiconductor element 40, a bonding wire 50, and a resin 60. Further, the lead frame 15 has a semiconductor element mounting portion 11 and a terminal portion 12. A through pattern 13 is formed between the semiconductor element mounting portion 11 and the terminal portion 12, and a concave portion 14 is formed on the surface of the semiconductor element mounting portion 11.
引線架15在表面上搭載半導體元件40，並且將半導體元件40之端子與端子部12電連接，從而形成從端子部12呈放射狀向外側延伸之導線，進而發揮將來自半導體元件40之端子之配線向外部引出之作用。因此，引線架15在中央具有搭載半導體元件40之半導體元件搭載部11，並在其周圍具有用於引出配線之端子部12。 The lead frame 15 is mounted with the semiconductor element 40 on the surface, and the terminal of the semiconductor element 40 is electrically connected to the terminal portion 12 to form a lead wire extending radially outward from the terminal portion 12, thereby functioning as a terminal from the semiconductor element 40. The function of wiring to the outside. Therefore, the lead frame 15 has the semiconductor element mounting portion 11 on which the semiconductor element 40 is mounted at the center, and has a terminal portion 12 for drawing the wiring around the lead frame 15.
在半導體元件搭載部11之表面11a以及端子部12之表面12a分別形成有具有凹陷之形狀之凹部14。凹部14是為了使半導體元件搭載部11之表面積增加，並提高與樹脂60之接合性以及密接性而形成之構造部。因此，凹部14僅形成於與樹脂60接觸之表面(上表面)11a、12a側，即半導體元件搭載面側之面11a、12a，而不形成於不與樹脂60接觸之背面(下表面)11b側，即半導體元件非搭載面側之面11b、12b。 A concave portion 14 having a concave shape is formed on the surface 11a of the semiconductor element mounting portion 11 and the surface 12a of the terminal portion 12, respectively. The recessed portion 14 is a structural portion formed by increasing the surface area of the semiconductor element mounting portion 11 and improving the adhesion to the resin 60 and the adhesion. Therefore, the concave portion 14 is formed only on the surface (upper surface) 11a, 12a side in contact with the resin 60, that is, the surface 11a, 12a on the semiconductor element mounting surface side, and is not formed on the back surface (lower surface) 11b which is not in contact with the resin 60. The side, that is, the surfaces 11b and 12b on the non-mounting surface side of the semiconductor element.
此外，在圖1中，顯示了在半導體元件搭載部11以及端子部12雙方之表面11a、12a分別形成有凹部14之例，但也可以根據用途在半導體元件搭載部11之表面11a或者端子部12之表面12a之任意一方形成 凹部14。另外，一般情況下，端子部12存在複數個，因此也可以選擇任意之端子部12，而在任意之端子部12之表面12a選擇性地形成凹部14。 In addition, in FIG. 1, although the recessed part 14 was formed in the surface 11a and 12a of the semiconductor element mounting part 11 and the terminal part 12, respectively, the surface 11a or the terminal part of the semiconductor element mounting part 11 may be used according to a use. Any one of the surfaces 12a of 12 is formed Concave portion 14. Further, in general, since there are a plurality of terminal portions 12, any of the terminal portions 12 may be selected, and the concave portions 14 may be selectively formed on the surface 12a of any of the terminal portions 12.
粗化處理層20與凹部14相同地是為了提高與樹脂60之接合性以及密接性而形成。粗化處理層20形成於半導體元件搭載部11之側面11c以及端子部12之側面12c和凹部14凹陷之區域之表面，但未形成於與半導體元件40直接接觸之半導體元件搭載部11之表面上以及與接合線50直接接觸之端子部12之表面上。供半導體元件40接觸之區域不與樹脂60接觸，因此不需要形成粗化處理層20，另外，在供接合線50接觸之區域需要形成電鍍層30。因此，在利用本實施形態所涉及之引線架15之製造方法而製造之引線架15中，僅在與樹脂60接觸並且未形成電鍍層30之半導體元件搭載部11以及端子部12之側面11c、12c和凹部14之表面形成粗化處理層20。 Similarly to the concave portion 14, the roughened layer 20 is formed to improve the adhesion to the resin 60 and the adhesion. The roughened layer 20 is formed on the surface of the side surface 11c of the semiconductor element mounting portion 11 and the side surface 12c of the terminal portion 12 and the recessed portion 14, but is not formed on the surface of the semiconductor element mounting portion 11 which is in direct contact with the semiconductor element 40. And on the surface of the terminal portion 12 that is in direct contact with the bonding wire 50. The region where the semiconductor element 40 is in contact is not in contact with the resin 60, so that it is not necessary to form the roughened layer 20, and it is necessary to form the plating layer 30 in the region where the bonding wire 50 is in contact. Therefore, in the lead frame 15 manufactured by the method of manufacturing the lead frame 15 according to the present embodiment, only the side surface 11c of the semiconductor element mounting portion 11 and the terminal portion 12 where the plating layer 30 is not formed is in contact with the resin 60, The roughened layer 20 is formed on the surface of the 12c and the recess 14.
粗化處理層20只要能夠對引線架10之表面進行粗化，則也可以由各種方法以及材料形成，例如也可以藉由將粗化處理溶液供給至引線架10之表面而形成。 The roughening layer 20 may be formed by various methods and materials as long as the surface of the lead frame 10 can be roughened, and may be formed, for example, by supplying a roughening solution to the surface of the lead frame 10.
電鍍層30是為了使設置於半導體元件40之底面之端子(未圖示)與半導體元件搭載部11之電連接以及藉由引線結合之接合線50與端子部12之電連接變得良好而設置。因此，電鍍層30設置於進行電連接之位置。 The plating layer 30 is provided in order to electrically connect the terminal (not shown) provided on the bottom surface of the semiconductor element 40 to the semiconductor element mounting portion 11 and to electrically connect the bonding wire 50 and the terminal portion 12 by wire bonding. . Therefore, the plating layer 30 is disposed at a position where electrical connection is made.
半導體元件40是包含半導體並用於實現預定之功能之元件。在本實施形態所涉及之引線架之製造方法中，列舉將半導體元件40構成為發光二極體(LED，Light-emitting Diode)之例子進行說明。在將半導體 元件40構成為發光二極體之情況下，發光二極體是具有陽極與陰極之兩端子之元件，一方之端子電連接於半導體元件搭載部11，另一方之端子電連接於端子部12。因此，在圖1中，在半導體元件搭載部11與半導體元件40之間設置有電鍍層30。 The semiconductor element 40 is an element including a semiconductor and used to achieve a predetermined function. In the method of manufacturing the lead frame according to the present embodiment, an example in which the semiconductor element 40 is configured as a light-emitting diode (LED) will be described. Semiconductor When the element 40 is configured as a light-emitting diode, the light-emitting diode is an element having two terminals of an anode and a cathode, and one terminal is electrically connected to the semiconductor element mounting portion 11 and the other terminal is electrically connected to the terminal portion 12. Therefore, in FIG. 1, the plating layer 30 is provided between the semiconductor element mounting portion 11 and the semiconductor element 40.
另一方面，在半導體元件40為搭載了實現預定功能之電路之積體電路(IC，Integrated Circuit)之情況下，半導體元件40在半導體元件搭載部11上以端子成為上表面之方式被接著劑接著，位於上表面之複數個端子與端子部12透過接合線50而電連接。在該情況下，在半導體元件40與半導體元件搭載部11之間設置接著層，而非電鍍層30。本發明能夠應用於將半導體元件40構成為發光二極體之情況和構成為積體電路之情況雙方。在往後之說明中，對將半導體元件40構成為發光二極體且半導體元件40與半導體元件搭載部11之間是電鍍層30之例子進行說明，但也能夠應用於將電鍍層30置換成接著層，將半導體元件40構成為積體電路之情況。 On the other hand, when the semiconductor element 40 is an integrated circuit (IC) in which a circuit for realizing a predetermined function is mounted, the semiconductor element 40 is bonded to the semiconductor element mounting portion 11 so that the terminal becomes the upper surface. Next, a plurality of terminals on the upper surface and the terminal portion 12 are electrically connected through the bonding wires 50. In this case, an adhesive layer is provided between the semiconductor element 40 and the semiconductor element mounting portion 11 instead of the plating layer 30. The present invention can be applied to both the case where the semiconductor element 40 is configured as a light-emitting diode and the case where it is configured as an integrated circuit. In the following description, the semiconductor element 40 is configured as a light-emitting diode, and the plating layer 30 is interposed between the semiconductor element 40 and the semiconductor element mounting portion 11. However, the plating layer 30 can be replaced with the plating layer 30. Next, the semiconductor element 40 is configured as an integrated circuit.
接合線50是用於對位於半導體元件40之上表面之端子與形成於端子部12上之電鍍層30進行電連接之連接線。將半導體元件40之上表面之端子連接于接合線50之一端，將接合線50之另一端連接於端子部12之電鍍層30，藉此對半導體元件40之上表面之端子與端子部12進行電連接。 The bonding wire 50 is a connecting wire for electrically connecting the terminal located on the upper surface of the semiconductor element 40 and the plating layer 30 formed on the terminal portion 12. The terminal of the upper surface of the semiconductor element 40 is connected to one end of the bonding wire 50, and the other end of the bonding wire 50 is connected to the plating layer 30 of the terminal portion 12, whereby the terminal of the upper surface of the semiconductor element 40 and the terminal portion 12 are performed. Electrical connection.
樹脂60是用於對搭載了半導體元件40之引線架10進行密封以保護半導體元件40並且成形為一個半導體封裝70從而零件化之機構。藉由利用該樹脂60進行之密封，使半導體封裝70之操作變得容易。 The resin 60 is a mechanism for sealing the lead frame 10 on which the semiconductor element 40 is mounted to protect the semiconductor element 40 and forming it into one semiconductor package 70. The sealing of the resin 60 is facilitated by the sealing by the resin 60.
圖2是放大顯示利用本發明實施方式所涉及之引線架之製 造方法而製造之引線架15之半導體元件搭載部11之粗化處理層20之形成部分的圖。如圖2所示，在引線架15之半導體元件搭載部11中，在與樹脂60接合之表面11a側形成凹部14，在表面11a上形成電鍍層30。另一方面，在不進行與樹脂60接合之半導體元件搭載部11之背面11b不形成凹部14也不形成電鍍層30，從而保持未施加任何加工之平坦面。此外，凹部14藉由半蝕刻加工形成。 2 is an enlarged view showing the manufacture of a lead frame according to an embodiment of the present invention. A view showing a portion where the roughened layer 20 of the semiconductor element mounting portion 11 of the lead frame 15 manufactured by the method is formed. As shown in FIG. 2, in the semiconductor element mounting portion 11 of the lead frame 15, a concave portion 14 is formed on the surface 11a side joined to the resin 60, and a plating layer 30 is formed on the surface 11a. On the other hand, the plating layer 30 is not formed without forming the concave portion 14 on the back surface 11b of the semiconductor element mounting portion 11 to which the resin 60 is bonded, and the flat surface to which no processing is applied is maintained. Further, the recess 14 is formed by a half etching process.
另外，側面11c藉由貫通蝕刻加工形成貫通孔之貫通圖案13，從而形成藉由蝕刻而被削除之側面11c。而且，不形成電鍍層30，並且在與樹脂60接觸之側面11c以及凹部14之表面上形成粗化處理層20。藉由上述結構，不對電鍍層30造成任何粗化處理之影響從而確保充分之電連接功能，並且對與樹脂60接觸之側面11c以及凹部14之表面實施粗化處理而形成粗化處理層20，從而能夠提高與樹脂60之接合性以及密接性。 Moreover, the side surface 11c forms the through-hole pattern 13 of the through-hole by a through-etching process, and the side surface 11c which is removed by etching is formed. Further, the plating layer 30 is not formed, and the roughening treatment layer 20 is formed on the side surface 11c which is in contact with the resin 60 and the surface of the concave portion 14. With the above configuration, the plating layer 30 is not affected by any roughening treatment to ensure a sufficient electrical connection function, and the surface of the side surface 11c and the concave portion 14 which are in contact with the resin 60 are roughened to form the roughened layer 20, Thereby, the bondability with the resin 60 and the adhesion can be improved.
接下來，使用圖3對具有上述結構之引線架之製造方法進行說明。圖3是顯示本發明實施形態所涉及之引線架之製造方法之一例之一系列步驟的圖。此外，對與至此進行了說明之構成要素相同之構成要素標注與至此之說明相同之參照符號，並省略其說明。 Next, a method of manufacturing the lead frame having the above structure will be described using FIG. Fig. 3 is a view showing a series of steps of an example of a method of manufacturing a lead frame according to an embodiment of the present invention. The same components as those described above are denoted by the same reference numerals, and their description is omitted.
圖3(a)是顯示電鍍層形成步驟以及蝕刻光罩形成步驟之一例的圖。在電鍍層形成步驟以及蝕刻光罩形成步驟中，在成為引線架15之材料之金屬板10表面上形成電鍍層30以及蝕刻光罩80。 Fig. 3 (a) is a view showing an example of a plating layer forming step and an etching mask forming step. In the plating layer forming step and the etching mask forming step, the plating layer 30 and the etching mask 80 are formed on the surface of the metal plate 10 which is the material of the lead frame 15.
首先，就成為引線架15之材料之金屬板10而言，例如可以使用由銅材料或者包含銅之合金構成之金屬板10。準備金屬板10後，在金屬板10表面上之預定區域形成電鍍層30。電鍍層30如上述，形成於搭載 有半導體元件40之區域、連接有接合線50之區域。電鍍層30也可以由各種金屬材料構成，例如也可以由在金屬板10表面上形成鍍鎳層、在鍍鎳層上形成鍍鈀層、進一步在鍍鈀層上形成鍍金層之三層構成。此外，能夠根據用途，使用各種電鍍材料。 First, as the metal plate 10 which is a material of the lead frame 15, for example, a metal plate 10 made of a copper material or an alloy containing copper can be used. After the metal plate 10 is prepared, the plating layer 30 is formed on a predetermined region on the surface of the metal plate 10. The plating layer 30 is formed as described above. There is a region of the semiconductor element 40 and a region to which the bonding wires 50 are connected. The plating layer 30 may be made of various metal materials, and may be formed of, for example, a nickel plating layer formed on the surface of the metal plate 10, a palladium plating layer formed on the nickel plating layer, and a gold plating layer formed on the palladium plating layer. Further, various plating materials can be used depending on the application.
此外，在電鍍層30之形成過程中，也可以使用電鍍用光罩進行電鍍處理，而僅在預定區域形成電鍍層30。 Further, in the formation of the plating layer 30, the plating treatment may be performed using a photomask for electroplating, and the plating layer 30 is formed only in a predetermined region.
當在電鍍層形成步驟中形成電鍍層30後，在包含電鍍層30之金屬板10表面上形成抗蝕劑層81。抗蝕劑層81能夠根據用途，使用各種抗蝕劑材料，例如可以將乾膜抗蝕劑黏貼於金屬板10表面來形成抗蝕劑層81。 After the plating layer 30 is formed in the plating layer forming step, a resist layer 81 is formed on the surface of the metal plate 10 including the plating layer 30. The resist layer 81 can be made of various resist materials depending on the application. For example, a resist film 81 can be formed by adhering a dry film resist to the surface of the metal plate 10.
抗蝕劑層81藉由曝光以及顯影除去不需要之部分，由此成形為具有預定之圖案之蝕刻光罩80。蝕刻光罩80在殘留之抗蝕劑層81與被除去而成為開口82之部分形成光罩圖案。此外，抗蝕劑層81構成光罩圖案之光罩部，開口82構成光罩圖案之開口部。 The resist layer 81 removes unnecessary portions by exposure and development, thereby forming an etch mask 80 having a predetermined pattern. The etching mask 80 forms a mask pattern on the remaining resist layer 81 and the portion that is removed to form the opening 82. Further, the resist layer 81 constitutes a mask portion of the mask pattern, and the opening 82 constitutes an opening portion of the mask pattern.
開口82為實施貫通蝕刻加工而形成為貫通蝕刻加工用圖案83之區域。另一方面，將交替地形成抗蝕劑層81與開口82而使抗蝕劑層81呈條紋狀或者如浮雕般的狀態的部分形成為半蝕刻加工用圖案84。藉由交替地配置開口82與抗蝕劑層81之抗蝕劑圖案，與通常之開口82相比更限制蝕刻液與金屬板10之接觸，與形成為較大之開口82相比，蝕刻率變小，進而能夠進行形成凹陷形狀之半蝕刻加工。此外，上述半蝕刻加工用圖案84僅形成於金屬板10之表面10a側。因此，在表面10a側形成包含較大之開口82之貫通蝕刻加工用圖案83、和細緻之圖案之抗蝕劑層81與較小之 開口82交替地呈條紋狀或者浮雕狀地形成之半蝕刻加工用圖案84雙方。 The opening 82 is a region formed to penetrate the etching processing pattern 83 by performing a through etching process. On the other hand, a portion in which the resist layer 81 and the opening 82 are alternately formed and the resist layer 81 is stripe-like or embossed is formed as the half etching processing pattern 84. By alternately arranging the resist pattern of the opening 82 and the resist layer 81, the contact of the etching liquid with the metal plate 10 is more restricted than the normal opening 82, and the etching rate is compared with the opening 82 formed as a larger one. The size is reduced, and further, a half etching process for forming a concave shape can be performed. Further, the half etching processing pattern 84 is formed only on the surface 10a side of the metal plate 10. Therefore, a through etching process pattern 83 including a large opening 82 and a resist pattern 81 having a fine pattern are formed on the surface 10a side and the smaller The openings 82 are alternately formed in a stripe shape or a embossed shape of the half etching processing pattern 84.
另一方面，在金屬板10之背面10b側僅形成有具有較大之開口82之貫通蝕刻加工用圖案83。 On the other hand, only the through etching processing pattern 83 having the large opening 82 is formed on the back surface 10b side of the metal plate 10.
圖3(b)是顯示蝕刻步驟以及蝕刻光罩變形步驟之一例的圖。在蝕刻步驟中，進行濕式之蝕刻處理，從而形成貫通蝕刻圖案13以及凹部14。對於蝕刻處理而言，向兩面被蝕刻光罩80覆蓋之金屬板10供給蝕刻液，從而從兩面對金屬板10進行蝕刻處理。在供給相同時間蝕刻液之情況下，在形成有較大之開口82之貫通蝕刻加工用圖案83之區域形成貫通孔進而形成貫通蝕刻圖案13。在交替地形成較小之抗蝕劑層81與開口82之半蝕刻加工用圖案84中，形成有凹陷形狀之凹部14。此外，藉由貫通蝕刻圖案13之形成，半導體元件搭載部11與端子部12被分離形成，金屬板10成形為引線架15之形狀。 Fig. 3(b) is a view showing an example of an etching step and a step of deforming the etching mask. In the etching step, a wet etching process is performed to form the through etching pattern 13 and the recess 14 . For the etching treatment, the etching liquid is supplied to the metal plate 10 covered on both sides by the etching mask 80, thereby performing etching processing from the both facing metal sheets 10. When the etching liquid is supplied for the same time, a through hole is formed in a region where the through etching processing pattern 83 having the large opening 82 is formed, and the through etching pattern 13 is formed. In the half etching processing pattern 84 in which the small resist layer 81 and the opening 82 are alternately formed, a concave portion 14 having a concave shape is formed. Further, the semiconductor element mounting portion 11 and the terminal portion 12 are separated by the formation of the through etching pattern 13, and the metal plate 10 is formed into the shape of the lead frame 15.
此外，蝕刻液也可以根據金屬板10之材料而使用能夠適當地蝕刻金屬板10之蝕刻液，例如，在金屬板10為銅材料之情況下，也可以使用氯化鐵溶液。另外，蝕刻處理也可以藉由利用噴槍向被蝕刻光罩80覆蓋之金屬板10之兩面噴射供給預定時間蝕刻液之噴射蝕刻來進行，也可以藉由使被蝕刻光罩80覆蓋之金屬板10浸入蝕刻液預定時間之浸入式蝕刻來進行。蝕刻方法能夠根據用途採用各種方法。 Further, the etching liquid may use an etching liquid capable of appropriately etching the metal plate 10 depending on the material of the metal plate 10. For example, in the case where the metal plate 10 is a copper material, a ferric chloride solution may be used. In addition, the etching process may be performed by jetting the etchant to the both sides of the metal plate 10 covered by the etched reticle 80 by a blasting agent for a predetermined time, or by the metal plate 10 covered by the etched reticle 80. Immersion etching is performed by immersing the etching solution for a predetermined time. The etching method can adopt various methods depending on the use.
在蝕刻處理結束後，除去位於半蝕刻加工用圖案84之抗蝕劑層81(光罩部)，從而半蝕刻加工用圖案84變形為粗化處理用之開口82。藉此，蝕刻光罩80變形為粗化處理用之光罩80a，從而能夠對凹部14之凹陷形狀部分之表面整體實施粗化處理。 After the etching process is completed, the resist layer 81 (photomask portion) located in the half etching processing pattern 84 is removed, and the half etching processing pattern 84 is deformed into the opening 82 for roughening processing. Thereby, the etching mask 80 is deformed into the mask 80a for roughening processing, and the entire surface of the recessed part of the recessed part 14 can be roughened.
圖3(c)是顯示粗化處理步驟之一例的圖。在粗化處理步驟中，向具有被變形之粗化處理用之光罩80a覆蓋之引線架15之形狀之金屬板10(以下，稱為「引線架15」。)表面供給粗化處理液，從而對未被光罩80覆蓋之區域進行粗化處理。粗化處理液也可以使用能夠對引線架15進行粗化處理之各種溶液。另外，粗化處理液之供給例如也可以藉由噴槍噴射來進行，也可以使被光罩80a覆蓋之引線架15浸入粗化處理液來進行。藉由上述粗化處理，在半導體元件搭載部11之側面11a、端子部12之側面12c以及凹部14之表面形成粗化處理層20。 Fig. 3(c) is a view showing an example of the roughening processing procedure. In the roughening process, the roughening treatment liquid is supplied to the surface of the metal plate 10 (hereinafter referred to as "lead frame 15") having the shape of the lead frame 15 covered with the mask 80a for deformation roughening treatment. Thereby, the region not covered by the mask 80 is roughened. As the roughening treatment liquid, various solutions capable of roughening the lead frame 15 can also be used. Further, the supply of the roughening treatment liquid may be performed by, for example, lance injection, or the lead frame 15 covered by the reticle 80a may be immersed in the roughening treatment liquid. The roughening treatment layer 20 is formed on the side surface 11a of the semiconductor element mounting portion 11, the side surface 12c of the terminal portion 12, and the surface of the concave portion 14 by the above-described roughening treatment.
圖3(d)是顯示光罩除去步驟之一例的圖。在光罩除去步驟中，剝離除去粗化處理用之光罩80a。光罩80a之除去例如也可以使引線架15浸入剝離溶液來剝離除去光罩80a。剝離溶液也可以使用各種溶液，例如，也可以使用氫氧化鈉溶液。 Fig. 3(d) is a view showing an example of a mask removal step. In the mask removal step, the mask 80a for roughening treatment is peeled off. Removal of the mask 80a may, for example, cause the lead frame 15 to be immersed in the peeling solution to peel off the mask 80a. Various solutions can also be used for the stripping solution, for example, a sodium hydroxide solution can also be used.
以此方式，製造了引線架15。此外，在圖3之例中，最先形成電鍍層30，然後形成引線架15之形狀，但也可以先形成引線架15之形狀，最後形成電鍍層。此時，在圖3(a)中，不進行形成電鍍層30之步驟，而僅進行形成蝕刻光罩80之步驟。而且，在結束到圖3(d)為止之步驟後，只要形成電鍍層30即可。此時，也能夠在形成之引線架15之整個面形成電鍍層30，也能夠使用電鍍光罩僅在需要電鍍層30之預定區域形成電鍍層30。 In this way, the lead frame 15 is manufactured. Further, in the example of Fig. 3, the plating layer 30 is formed first, and then the shape of the lead frame 15 is formed, but the shape of the lead frame 15 may be formed first, and finally a plating layer is formed. At this time, in FIG. 3(a), the step of forming the plating layer 30 is not performed, and only the step of forming the etching mask 80 is performed. Further, after the step up to FIG. 3(d) is completed, the plating layer 30 may be formed. At this time, the plating layer 30 can also be formed on the entire surface of the formed lead frame 15, and the plating layer 30 can be formed only in a predetermined region where the plating layer 30 is required using the plating mask.
根據本實施方式所涉及之引線架之製造方法，能夠不造成粗化處理之影響即形成電鍍層30，並且在與樹脂60之接觸面形成凹部14以及粗化處理層20，從而提高與樹脂60之接合性以及密接性。並且，該製造 方法能夠不追加新的步驟而僅以簡單之步驟實現，從而能夠製造不使成本上升並具有良好之密接性之引線架。 According to the method of manufacturing a lead frame according to the present embodiment, the plating layer 30 can be formed without causing the influence of the roughening treatment, and the concave portion 14 and the roughened layer 20 can be formed on the contact surface with the resin 60, thereby improving the resin 60. Bonding and adhesion. And the manufacturing The method can be realized in a simple step without adding a new step, and it is possible to manufacture a lead frame which does not increase the cost and has good adhesion.
接下來，對實施了本發明實施形態所涉及之引線架之製造方法之實施例進行說明。 Next, an embodiment in which a method of manufacturing a lead frame according to an embodiment of the present invention is carried out will be described.
作為金屬板，使用厚度為0.2mm之銅材料，並在兩面黏貼乾膜抗蝕劑(旭化成電子材料株式會社：AQ-2058)來形成抗蝕劑層。 As a metal plate, a copper material having a thickness of 0.2 mm was used, and a dry film resist (Asahi Kasei Electronic Material Co., Ltd.: AQ-2058) was adhered to both surfaces to form a resist layer.
接下來，使用形成有用於形成電鍍之圖案之上表面側用與背面側用之玻璃光罩，並進行曝光、顯影，從而形成除去形成電鍍之部分之抗蝕劑而局部地使金屬板表面露出之電鍍光罩。 Next, a glass mask for forming the upper surface side and the back side of the pattern for forming plating is formed, and exposure and development are performed to form a resist which removes the portion where the plating is formed, thereby partially exposing the surface of the metal plate. Electroplated reticle.
然後，進行電鍍加工，在金屬板表面之露出部分形成電鍍層。在本實施例中，從金屬板側按順序實施設定值1.0μm之鍍鎳、設定值0.05μm之鍍鈀、設定值0.02μm之鍍金作業，從而形成三層電鍍層。 Then, electroplating is performed to form a plating layer on the exposed portion of the surface of the metal plate. In the present embodiment, a nickel plating having a set value of 1.0 μm, a palladium plating having a set value of 0.05 μm, and a gold plating operation of a set value of 0.02 μm were sequentially performed from the metal plate side to form a three-layer plating layer.
接下來，藉由3%之氫氧化鈉水溶液將形成於金屬板之兩面之電鍍光罩剝離，更進行利用3%之硫酸之清洗處理。 Next, the plating mask formed on both sides of the metal plate was peeled off by a 3% aqueous sodium hydroxide solution, and further washed with 3% sulfuric acid.
然後，在形成有電鍍層之金屬板之兩面再次黏貼乾膜抗蝕劑(旭化成電子材料株式會社：AQ-4096)來形成抗蝕劑層，使用形成有引線架之形狀與半蝕刻處理用之圖案之玻璃光罩，形成對兩面進行曝光並進行顯影而形成之覆蓋有電鍍層之蝕刻光罩。此時，進行半蝕刻之部位不需要與貫通蝕刻相同量之蝕刻液，為了控制蝕刻液量而形成為如獨立浮雕般之狀態之光罩。 Then, a dry film resist (Asahi Kasei Electronic Materials Co., Ltd.: AQ-4096) is adhered to both surfaces of the metal plate on which the plating layer is formed to form a resist layer, and the shape of the lead frame and the half etching process are used. The patterned glass reticle forms an etch mask covered with a plating layer formed by exposing and developing both sides. At this time, the portion where the half etching is performed does not need to have the same amount of etching liquid as the through etching, and is formed into a photomask in a state of being independently embossed in order to control the amount of the etching liquid.
而且，使用氯化鐵溶液進行噴射蝕刻加工來進行引線架之形 成。該蝕刻加工使用液溫70℃，比重1.47之氯化鐵溶液，並利用擺動之噴槍噴嘴以0.3MPa之設定壓力進行噴射，進行約160秒之處理。蝕刻光罩藉由該蝕刻加工成為新的粗化處理用光罩。 Moreover, the shape of the lead frame is performed by using a ferric chloride solution for jet etching processing. to make. This etching process uses a ferric chloride solution having a liquid temperature of 70 ° C and a specific gravity of 1.47, and is sprayed at a set pressure of 0.3 MPa by a oscillating spray gun nozzle, and is treated for about 160 seconds. The etching mask is processed into a new mask for roughening processing by this etching.
接下來，在藉由利用噴槍噴射之鹽酸清洗除去附著於蝕刻溶解面之銅結晶後，利用粗化處理液(MEC株式會社：CZ8100)進行利用噴槍噴射之粗化處理。該粗化處理液以液溫35℃、比重1.145、銅濃度35g/L進行調液，並藉由噴槍噴射進行20秒之粗化處理。粗化面之表面粗糙度成為SRa0.2~0.4。 Then, the copper crystal adhered to the etching-dissolved surface was removed by washing with a lance spray, and the roughening treatment (MEC Co., Ltd.: CZ8100) was used to carry out the roughening treatment by the spray gun. The roughening treatment liquid was adjusted at a liquid temperature of 35 ° C, a specific gravity of 1.145, and a copper concentration of 35 g / L, and was subjected to a roughening treatment by a spray gun for 20 seconds. The surface roughness of the roughened surface is SRa 0.2 to 0.4.
接下來，藉由利用噴槍噴射之鹽酸清洗除去附著於粗化面之粗化處理液之殘留物，然後，使用氫氧化鈉水溶液剝離粗化處理用光罩。然後，進行利用硫酸之酸處理，使表面乾燥，由此完成蝕刻溶解面被局部粗化之引線架。 Next, the residue of the roughening treatment liquid adhering to the roughened surface was removed by washing with hydrochloric acid sprayed with a spray gun, and then the mask for roughening treatment was peeled off using an aqueous sodium hydroxide solution. Then, the surface is dried by the acid treatment with sulfuric acid, thereby completing the lead frame in which the etching dissolution surface is partially roughened.
此外，如上所述，本實施例是在形成電鍍層後形成引線架形狀之例，但在先形成引線架之情況下，能夠不使用電鍍光罩之形成步驟、電鍍步驟以及電鍍光罩之除去步驟而從蝕刻光罩之形成步驟開始。而且，也能夠在形成之引線架之整個面形成電鍍層，還能夠使用電鍍光罩在需要之部位形成電鍍層。 Further, as described above, the present embodiment is an example in which the shape of the lead frame is formed after the plating layer is formed, but in the case where the lead frame is formed first, the formation step of the plating mask, the plating step, and the removal of the plating mask can be eliminated. The step begins with the step of forming the etch mask. Further, it is also possible to form a plating layer on the entire surface of the formed lead frame, and it is also possible to form a plating layer at a desired portion using a plating mask.
以上，對本發明之較佳實施形態以及實施例進行了詳細說明，但本發明不限定於上述實施形態以及實施例，只要不脫離本發明之範圍，則能夠對上述實施形態以及實施例施加各種變形以及置換。 The preferred embodiments and examples of the present invention have been described in detail above, but the present invention is not limited to the above-described embodiments and examples, and various modifications can be made to the above-described embodiments and examples without departing from the scope of the invention. And replacement.
10‧‧‧金屬板 10‧‧‧Metal plates
11‧‧‧半導體元件搭載部 11‧‧‧Semiconductor component mounting department
12‧‧‧端子部 12‧‧‧ Terminals
10a、11a‧‧‧表面 10a, 11a‧‧‧ surface
10b、11b‧‧‧背面 10b, 11b‧‧‧ back
11c、12c‧‧‧側面 11c, 12c‧‧‧ side
13‧‧‧貫通圖案 13‧‧‧through pattern
14‧‧‧凹部 14‧‧‧ recess
15‧‧‧引線架 15‧‧‧ lead frame
20‧‧‧粗化處理層 20‧‧‧ roughening layer
30‧‧‧電鍍層 30‧‧‧Electroplating
80、80a‧‧‧光罩 80, 80a‧‧‧ mask
81‧‧‧抗蝕劑層 81‧‧‧resist layer
82‧‧‧開口 82‧‧‧ openings
83‧‧‧貫通蝕刻加工用圖案 83‧‧‧through etching processing pattern
84‧‧‧半蝕刻加工用圖案 84‧‧‧ Half etching processing pattern
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Families Citing this family (11)
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| JP6259139B1 (en) * | 2017-03-24 | 2018-01-10 | シチズンファインデバイス株式会社 | Plate member, member, rectangular piece, member manufacturing method, and fluid ejection orifice plate manufacturing method |
| JP6724851B2 (en) | 2017-04-14 | 2020-07-15 | 株式会社デンソー | Base material, mold package using the same, base material manufacturing method, and mold package manufacturing method |
| JP7353794B2 (en) | 2019-05-13 | 2023-10-02 | ローム株式会社 | Semiconductor device, its manufacturing method, and module |
| TW202129077A (en) * | 2019-10-11 | 2021-08-01 | 日商聯合精密科技股份有限公司 | Metal machined component, component-mounted module equipped with same, and method for manufacturing same |
| JP7292776B2 (en) * | 2020-01-30 | 2023-06-19 | 大口マテリアル株式会社 | Lead frame |
| CN113534612B (en) * | 2020-04-17 | 2023-02-17 | 中铝洛阳铜加工有限公司 | Rapid method for detecting flatness of high-precision lead frame material for etching |
| CN112151489B (en) * | 2020-09-01 | 2023-06-06 | 通富微电科技(南通)有限公司 | Lead frame, method for forming lead frame, and lead frame package |
| CN116670820A (en) * | 2020-11-30 | 2023-08-29 | 罗姆股份有限公司 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
| JP7494107B2 (en) | 2020-12-28 | 2024-06-03 | 新光電気工業株式会社 | Lead frame, manufacturing method thereof and semiconductor device |
| WO2024157758A1 (en) * | 2023-01-25 | 2024-08-02 | ローム株式会社 | Semiconductor device |
| JP7413626B1 (en) | 2023-05-02 | 2024-01-16 | 長華科技股▲ふん▼有限公司 | Lead frame and its manufacturing method |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0231844B2 (en) * | 1986-08-18 | 1990-07-17 | Toppan Printing Co Ltd | HANDOTAISOCHORIIDOFUREEMUNOSEIZOHOHO |
| JP3077918B2 (en) * | 1991-07-04 | 2000-08-21 | 共同印刷株式会社 | Etching method |
| JPH11126859A (en) * | 1997-10-23 | 1999-05-11 | Toppan Printing Co Ltd | Manufacture of lead frame |
| JP2000195984A (en) * | 1998-12-24 | 2000-07-14 | Shinko Electric Ind Co Ltd | Semiconductor device, its manufacture carrier substrate therefor and its manufacture |
| JP3879410B2 (en) * | 2001-02-06 | 2007-02-14 | 凸版印刷株式会社 | Lead frame manufacturing method |
| JP3963655B2 (en) * | 2001-03-22 | 2007-08-22 | 三洋電機株式会社 | Circuit device manufacturing method |
| EP1602749A1 (en) * | 2003-01-17 | 2005-12-07 | Toppan Printing Co., Ltd. | Metal photo-etching product and production method therefor |
| JP4857594B2 (en) * | 2005-04-26 | 2012-01-18 | 大日本印刷株式会社 | Circuit member and method of manufacturing circuit member |
| JP2008187045A (en) * | 2007-01-30 | 2008-08-14 | Matsushita Electric Ind Co Ltd | Lead frame for semiconductor device, manufacturing method therefor, and the semiconductor device |
| JP5087787B2 (en) * | 2008-02-12 | 2012-12-05 | 住友金属鉱山株式会社 | Method for manufacturing partially plated lead frame |
| JP2009302209A (en) * | 2008-06-11 | 2009-12-24 | Nec Electronics Corp | Lead frame, semiconductor device, manufacturing method of lead frame, and manufacturing method of semiconductor device |
| JP2010010634A (en) * | 2008-06-30 | 2010-01-14 | Shinko Electric Ind Co Ltd | Lead frame, and method of manufacturing semiconductor device |
| JP5387374B2 (en) * | 2009-12-04 | 2014-01-15 | 住友金属鉱山株式会社 | Lead frame manufacturing method |
| TW201250964A (en) * | 2011-01-27 | 2012-12-16 | Dainippon Printing Co Ltd | Resin-attached lead frame, method for manufacturing same, and lead frame |
| JP5813335B2 (en) * | 2011-02-08 | 2015-11-17 | 新光電気工業株式会社 | Lead frame, semiconductor device, lead frame manufacturing method, and semiconductor device manufacturing method |
| JP6052734B2 (en) * | 2013-03-18 | 2016-12-27 | Ｓｈマテリアル株式会社 | Lead frame for mounting a semiconductor element and manufacturing method thereof |
| JP2014187122A (en) * | 2013-03-22 | 2014-10-02 | Toppan Printing Co Ltd | Led package and method for producing the same |
| JP6347960B2 (en) * | 2014-01-29 | 2018-06-27 | Ａｓｔｉ株式会社 | Microneedle unit and injection device |
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