TWI599285B - Circuit board structure with chip embedded therein and power module - Google Patents
Circuit board structure with chip embedded therein and power module Download PDFInfo
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Description
本發明涉及一種功率元件，且還涉及一種晶片埋入式電路板結構及功率模組。 The invention relates to a power component, and to a wafer embedded circuit board structure and a power module.
為降低電子產品的尺寸並提高供電效率，電子產品所使用的電路板結構內大都將功率晶片埋置於內。但，現有的功率晶片(如：高功率晶片)並無法獨自進行相對應的(高功率)測試，所以大都是在功率晶片埋置於電路板結構後，再對經由電路板結構的導電線路進行功率晶片的相關測試。然而，現有電路板結構須先形成多個貫孔，而後才於多個貫孔內填入導電材料以成形上述導電線路，而連接於所述功率晶片各個電極上的多條導電線路並不具備導熱功能，使得所述功率晶片產生的熱能不易被排除。再者，當所述電路板結構進行測試得知功率晶片有缺失時，更是會導致整個電路板結構無法使用，進而提升製造成本。 In order to reduce the size of electronic products and improve the efficiency of power supply, most of the circuit boards used in electronic products are embedded in power chips. However, existing power chips (such as high-power chips) cannot perform the corresponding (high-power) tests by themselves, so most of the power chips are buried in the circuit board structure, and then the conductive lines through the circuit board structure are performed. Related tests for power chips. However, the existing circuit board structure has to form a plurality of through holes, and then a plurality of through holes are filled with a conductive material to form the conductive lines, and a plurality of conductive lines connected to the respective electrodes of the power chip are not provided. The heat conduction function makes the heat energy generated by the power chip difficult to be eliminated. Moreover, when the circuit board structure is tested to find that the power chip is missing, the entire circuit board structure is unusable, thereby increasing the manufacturing cost.
於是，本發明人認為上述缺陷可改善，乃特潛心研究並配合科學原理的運用，終於提出一種設計合理且有效改善上述缺陷的本發明。 Accordingly, the inventors believe that the above-mentioned defects can be improved, and that the invention has been studied with great interest and with the use of scientific principles, and finally proposes a present invention which is rational in design and effective in improving the above-mentioned defects.
本發明實施例在於提供一種晶片埋入式電路板結構及功率模組，能有效地改善現有電路板結構所產生的缺失。 Embodiments of the present invention provide a wafer embedded circuit board structure and a power module, which can effectively improve the defects caused by the existing circuit board structure.
本發明實施例公開一種功率模組，包括：一絕緣基材，具有 位於相反側的一第一表面與一第二表面；兩個功率單元，彼此分離且埋置於所述絕緣基材內，並且每個所述功率單元包括有：一電熱傳導座，為一體成型的構造並包含有一傳導部及垂直地相連於所述傳導部的一承載部；及至少一功率晶片，具有位於相反側的一第一電極層與一第二電極層，所述第一電極層固定且電性連接於所述承載部，並且所述功率晶片相鄰於所述傳導部；以及一線路層，設置於所述絕緣基材的所述第一表面，所述線路層電性連接於兩個所述電熱傳導座與兩個所述功率晶片的所述第二電極層，以使所述功率模組能通過所述線路層與兩個所述電熱傳導座而測試每個所述功率晶片。 The embodiment of the invention discloses a power module, comprising: an insulating substrate, having a first surface and a second surface on opposite sides; two power units separated from each other and embedded in the insulating substrate, and each of the power units includes: an electrothermal conducting seat, integrally formed The structure includes a conductive portion and a bearing portion vertically connected to the conductive portion; and at least one power chip having a first electrode layer and a second electrode layer on opposite sides, the first electrode layer Fixedly and electrically connected to the carrying portion, and the power chip is adjacent to the conductive portion; and a circuit layer disposed on the first surface of the insulating substrate, the circuit layer is electrically connected Testing the second electrode layer of the two power planes and the two electrode layers of the two power chips to enable the power module to pass each of the circuit layers and two of the electrothermal conduction blocks to test each of the Power chip.
本發明實施例也公開一種晶片埋入式電路板結構，包括：至少一功率模組，包括：一絕緣基材，具有位於相反側的一第一表面與一第二表面；兩個功率單元，彼此分離且埋置於所述絕緣基材內，並且每個所述功率單元包括有：一電熱傳導座，為一體成型的構造並包含有一傳導部及垂直地相連於所述傳導部的一承載部；及至少一功率晶片，具有位於相反側的一第一電極層與一第二電極層，所述第一電極層固定且電性連接於所述承載部，並且所述功率晶片相鄰於所述傳導部；及一線路層，設置於所述絕緣基材的所述第一表面，所述線路層電性連接於兩個所述電熱傳導座與兩個所述功率晶片的所述第二電極層，以使所述功率模組能通過所述線路層與兩個所述電熱傳導座而測試每個所述功率晶片；以及一多層板，內部埋置有至少一所述功率模組。 The embodiment of the present invention also discloses a wafer embedded circuit board structure, comprising: at least one power module, comprising: an insulating substrate having a first surface and a second surface on opposite sides; two power units, Separating from each other and embedded in the insulating substrate, and each of the power units includes: an electrothermal conductive seat, being an integrally formed structure and including a conducting portion and a bearing vertically connected to the conducting portion And at least one power chip having a first electrode layer and a second electrode layer on opposite sides, the first electrode layer being fixed and electrically connected to the carrying portion, and the power chip being adjacent to The conductive portion; and a circuit layer disposed on the first surface of the insulating substrate, the circuit layer electrically connected to the two of the electrothermal conductive pads and the two of the power chips a two-electrode layer to enable the power module to test each of the power chips through the circuit layer and two of the electrothermal conductive seats; and a multi-layer board having at least one of the power modes embedded therein group.
綜上所述，本發明實施例所公開的晶片埋入式電路板結構及功率模組，具備用來同時傳遞熱能與電能的電熱傳導座，所以功率晶片能夠通過接觸於上述電熱傳導座，而使所述功率晶片與電熱傳導座間能夠較為快速地傳遞熱能與電能。再者，所述功率模組是將功率晶片埋置於絕緣基材內以隔絕外部干擾，並通過所述線路層與電熱傳導座進行電壓或電流傳輸，以使功率晶片能夠接 收到預定的電壓或電流。藉此，所述晶片埋入式電路板結構能在埋置功率模組之前，就先測得功率模組是否正常，以避免產生整個晶片埋入式電路板結構無法使用的情況。 In summary, the embedded circuit board structure and the power module disclosed in the embodiments of the present invention have an electrothermal conduction seat for transmitting heat energy and electric energy at the same time, so that the power chip can be in contact with the electrothermal conduction seat. The heat energy and the electric energy can be transmitted between the power chip and the electric heat conduction seat relatively quickly. Furthermore, the power module embeds the power chip in the insulating substrate to isolate external interference, and performs voltage or current transmission through the circuit layer and the electric heat conduction seat to enable the power chip to be connected. Received a predetermined voltage or current. Therefore, the embedded circuit board structure can measure whether the power module is normal before the power module is buried, so as to avoid the situation that the entire buried circuit board structure cannot be used.
為使能更進一步瞭解本發明的特徵及技術內容，請參閱以下有關本發明的詳細說明與附圖，但是此等說明與附圖僅用來說明本發明，而非對本發明的保護範圍作任何的限制。 For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying drawings limits.
100‧‧‧晶片埋入式電路板結構 100‧‧‧ wafer embedded circuit board structure
1‧‧‧功率模組 1‧‧‧Power Module
11‧‧‧絕緣基材 11‧‧‧Insulation substrate
111‧‧‧第一表面 111‧‧‧ first surface
112‧‧‧第二表面 112‧‧‧ second surface
113‧‧‧導電層 113‧‧‧ Conductive layer
12‧‧‧功率單元 12‧‧‧Power unit
121‧‧‧電熱傳導座 121‧‧‧Electrothermal conduction seat
1211‧‧‧傳導部 1211‧‧‧Transmission Department
1212‧‧‧承載部 1212‧‧‧Loading Department
1213‧‧‧側牆 1213‧‧‧ Side wall
1214‧‧‧承載面 1214‧‧‧ bearing surface
122‧‧‧功率晶片 122‧‧‧Power chip
1221‧‧‧第一電極層 1221‧‧‧First electrode layer
1222‧‧‧第二電極層 1222‧‧‧Second electrode layer
123‧‧‧絕緣散熱體 123‧‧‧Insulated heat sink
13‧‧‧線路層 13‧‧‧Line layer
131‧‧‧串接線路 131‧‧‧Sequence line
132‧‧‧延伸線路 132‧‧‧Extended lines
14‧‧‧金屬層 14‧‧‧metal layer
15‧‧‧絕緣黏著層 15‧‧‧Insulating adhesive layer
2‧‧‧多層板 2‧‧‧Multilayer board
21‧‧‧第一板面 21‧‧‧ first board
22‧‧‧第二板面 22‧‧‧ second board
200‧‧‧導熱件 200‧‧‧Heat-conducting parts
圖1A為本發明晶片埋入式電路板結構黏貼在導熱件的剖視示意圖。 1A is a cross-sectional view showing the structure of a wafer embedded circuit board adhered to a heat conducting member according to the present invention.
圖1B為圖1A變化態樣的剖視示意圖。 Figure 1B is a cross-sectional view of the variation of Figure 1A.
圖2為本發明功率模組的剖視示意圖。 2 is a cross-sectional view of a power module of the present invention.
圖3為圖2中的功率單元的立體示意圖。 3 is a perspective view of the power unit of FIG. 2.
圖4為圖2中的功率單元的另一立體示意圖。 4 is another perspective view of the power unit of FIG. 2.
圖5為本發明功率模組在絕緣基材內設有導電層的剖視示意圖。 FIG. 5 is a cross-sectional view showing a power module of the present invention with a conductive layer disposed in an insulating substrate.
圖6為本發明功率模組黏貼在導熱件的剖視示意圖。 6 is a cross-sectional view showing the power module of the present invention adhered to a heat conductive member.
圖7為本發明功率模組另一實施例的剖視示意圖。 7 is a cross-sectional view showing another embodiment of a power module of the present invention.
圖8為圖7中的功率單元的立體示意圖。 8 is a perspective view of the power unit of FIG. 7.
請參閱圖1A至圖6，為本發明的實施例一，需先說明的是，本實施例對應附圖所提及的相關數量與外型，僅用來具體地說明本發明的實施方式，以便於了解本發明的內容，而非用來侷限本發明的保護範圍。 Please refer to FIG. 1A to FIG. 6 , which are the first embodiment of the present invention. It should be noted that the related embodiments of the present invention are only used to specifically describe the embodiments of the present invention. The scope of the present invention is not to be construed as limiting the scope of the present invention.
如圖1A所示，本實施例公開一種晶片埋入式電路板結構100，特別是指具備高功率晶片的車用電路板結構，但不以此為限。其中，所述晶片埋入式電路板結構100包括至少一功率模組1 以及一多層板2，上述功率模組1是埋置於多層板2內。須說明的是，所述晶片埋入式電路板結構100可包含有埋置於多層板2內的多個功率模組1，並且所述功率模組1也可單獨地被應用在其他裝置上，不侷限上述多層板2。以下將先就本實施例晶片埋入式電路板結構100的功率模組1及多層板2構造作說明，而後再介紹功率模組1及多層板2彼此間的連接關係。 As shown in FIG. 1A, the present embodiment discloses a die-embedded circuit board structure 100, and particularly refers to a circuit board structure for a vehicle having a high-power chip, but is not limited thereto. The chip embedded circuit board structure 100 includes at least one power module 1 And a multi-layer board 2, the power module 1 is embedded in the multi-layer board 2. It should be noted that the chip embedded circuit board structure 100 may include a plurality of power modules 1 embedded in the multi-layer board 2, and the power module 1 may also be separately applied to other devices. The above multilayer board 2 is not limited. Hereinafter, the structure of the power module 1 and the multilayer board 2 of the wafer-embedded circuit board structure 100 of the present embodiment will be described first, and then the connection relationship between the power module 1 and the multilayer board 2 will be described.
如圖2和圖3所示，所述功率模組1包括一絕緣基材11、彼此分離且埋置於上述絕緣基材11內的兩個功率單元12、及位於絕緣基材11相反兩個表面的一線路層13與一金屬層14。其中，、所述絕緣基材11於本實施例中較佳為高散熱絕緣材質所製成的板狀構造並具有位於相反側的一第一表面111(如圖2中的絕緣基材11頂面)與一第二表面112(如圖2中的絕緣基材11底面)，但不受限於此。 As shown in FIG. 2 and FIG. 3, the power module 1 includes an insulating substrate 11, two power units 12 separated from each other and embedded in the insulating substrate 11, and two opposite insulating substrates 11. A wiring layer 13 and a metal layer 14 of the surface. In the embodiment, the insulating substrate 11 is preferably a plate-like structure made of a high heat-dissipating insulating material and has a first surface 111 on the opposite side (such as the insulating substrate 11 in FIG. 2). And a second surface 112 (such as the bottom surface of the insulating substrate 11 in FIG. 2), but is not limited thereto.
每個功率單元12包括有一電熱傳導座121與設置於上述電熱傳導座121上的至少一功率晶片122，其中，每個功率單元12的功率晶片122數量於本實施例中是以一個為例作說明，但本發明並不受限於此。例如：請參閱圖1B所示，每個功率單元12也可以包括有多個功率晶片122，並且上述多個功率晶片122較佳是以並聯方式安裝於電熱傳導座121上。由於每個功率單元12的構造大致相同，為便於理解本實施例，下述說明將先就單個功率單元12的構造作介紹。 Each power unit 12 includes an electrothermal conduction seat 121 and at least one power chip 122 disposed on the electrothermal conduction block 121. The number of power chips 122 of each power unit 12 is taken as an example in this embodiment. Note, but the invention is not limited thereto. For example, as shown in FIG. 1B, each power unit 12 may also include a plurality of power chips 122, and the plurality of power chips 122 are preferably mounted in parallel on the electrothermal conduction seat 121. Since the configuration of each power unit 12 is substantially the same, in order to facilitate the understanding of the present embodiment, the following description will first introduce the construction of a single power unit 12.
所述電熱傳導座121為一體成型的金屬(如：銅)構造並包含有一傳導部1211及垂直地相連於傳導部1211的一承載部1212，並且上述傳導部1211與承載部1212呈L型構造。每個所述功率晶片122於本實施例中優選是無法進行獨立測試的一高功率晶片122，上述高功率晶片122是指應用於超過5千瓦特(KW)的功率晶片122，而於本實施例中更可以是應用於超過100KW的功率晶片 122，但本發明並不以此為限。再者，所述功率晶片122具有位於相反側的一第一電極層1221(如圖2中的功率晶片122底層)與一第二電極層1222(如圖2中的功率晶片122頂層)，所述第一電極層1221固定且電性連接於承載部1212，並且功率晶片122相鄰於所述傳導部1211。 The electrothermal conduction seat 121 is an integrally formed metal (eg, copper) structure and includes a conducting portion 1211 and a bearing portion 1212 vertically connected to the conducting portion 1211, and the conducting portion 1211 and the carrying portion 1212 have an L-shaped configuration. . Each of the power chips 122 is preferably a high power wafer 122 that cannot be independently tested in the present embodiment. The high power wafer 122 refers to a power chip 122 applied to more than 5 kilowatts (KW). In the case, it can be applied to power chips exceeding 100KW. 122, but the invention is not limited thereto. Furthermore, the power chip 122 has a first electrode layer 1221 (such as the bottom layer of the power chip 122 in FIG. 2) and a second electrode layer 1222 (such as the top layer of the power chip 122 in FIG. 2) on the opposite side. The first electrode layer 1221 is fixed and electrically connected to the carrying portion 1212, and the power chip 122 is adjacent to the conducting portion 1211.
藉此，由於所述電熱傳導座121於本實施例中是用來同時傳遞熱能與電能，所以功率晶片122能夠通過接觸於上述電熱傳導座121，而使所述功率晶片122與電熱傳導座121間能夠較為快速地傳遞熱能與電能。 Therefore, since the electrothermal conduction seat 121 is used to transmit thermal energy and electric energy at the same time in the embodiment, the power chip 122 can contact the electrothermal conduction seat 121 to make the power chip 122 and the electrothermal conduction seat 121. It can transfer heat and electricity more quickly.
進一步地說，用來固定所述功率晶片122的所述承載部1212表面定義為一承載面1214(如圖3中的承載部1212頂面)，並且上述承載面1214的面積不小於功率晶片122的截面積。其中，所述功率晶片122的截面積於本實施例中是指垂直於第一電極層1221的功率晶片122截面的面積。 Further, the surface of the bearing portion 1212 for fixing the power chip 122 is defined as a bearing surface 1214 (such as the top surface of the bearing portion 1212 in FIG. 3), and the area of the bearing surface 1214 is not less than the power chip 122. Cross-sectional area. The cross-sectional area of the power chip 122 in this embodiment refers to the area of the cross section of the power chip 122 perpendicular to the first electrode layer 1221.
藉此，所述功率晶片122的第一電極層1221通過完全接觸於上述承載面1214，以有效地提升所述功率晶片122與承載部1212間的每單位時間內的電能與熱能傳輸量。再者，遠離功率晶片122的所述承載部1212表面(如圖2中的承載部1212底面)較佳是與所述絕緣基材11的第二表面112呈共平面設置。而所述功率晶片122的第二電極層1222與所述傳導部1211皆鄰近於所述第一表面111並與上述第一表面111相隔有一距離。 Thereby, the first electrode layer 1221 of the power chip 122 is completely contacted with the bearing surface 1214 to effectively increase the amount of electrical energy and thermal energy transfer per unit time between the power chip 122 and the carrying portion 1212. Moreover, the surface of the carrying portion 1212 away from the power chip 122 (such as the bottom surface of the carrying portion 1212 in FIG. 2) is preferably disposed in a plane with the second surface 112 of the insulating substrate 11. The second electrode layer 1222 of the power chip 122 and the conductive portion 1211 are both adjacent to the first surface 111 and spaced apart from the first surface 111 by a distance.
須說明的是，所述功率晶片122的第一電極層1221以及所述電熱傳導座121的承載部1212於本實施例中是以導熱及導電的金屬相互接合，例如通過銀燒結法(silver sintering)或擴散焊接法(diffusion soldering)等方式接合。 It should be noted that the first electrode layer 1221 of the power chip 122 and the carrying portion 1212 of the electrothermal conductive seat 121 are mutually joined by a thermally conductive and conductive metal in the embodiment, for example, by silver sintering. ) or by means of diffusion soldering.
以上所述為每個功率單元12的構造說明，但本發明不侷限於此。舉例來說，如圖4所示，每個所述電熱傳導座121可進一步包含有垂直地相連於所述傳導部1211與承載部1212的一側牆 1213，並且於每個所述功率單元12中的功率晶片122位於相對應的傳導部1211、承載部1212、及側牆1213所包圍形成的空間內。另，所述側牆1213的具體構造也可依據設計者的實際需求而加以調整變化，並不以圖4所示為限。 The above description is for the configuration of each power unit 12, but the present invention is not limited thereto. For example, as shown in FIG. 4, each of the electrothermal conduction seats 121 may further include a side wall vertically connected to the conducting portion 1211 and the carrying portion 1212. 1213, and the power chip 122 in each of the power units 12 is located in a space surrounded by the corresponding conductive portion 1211, the bearing portion 1212, and the side wall 1213. In addition, the specific configuration of the side wall 1213 can also be adjusted according to the actual needs of the designer, and is not limited to the one shown in FIG.
此外，如圖5所示，所述絕緣基材11內也可設有至少一功能模組(圖中未示出)及相連於上述功能模組的至少一導電層113，並且埋置於絕緣基材11內的所述導電層113未接觸於任一個電熱傳導座121與任一個功率晶片122。 In addition, as shown in FIG. 5, at least one functional module (not shown) and at least one conductive layer 113 connected to the functional module may be disposed in the insulating substrate 11 and embedded in the insulating layer. The conductive layer 113 in the substrate 11 is not in contact with any one of the electrothermal conduction pads 121 and any of the power chips 122.
如圖2和圖3所示，所述線路層13設置於絕緣基材11的第一表面111，並且線路層13電性連接於兩個所述電熱傳導座121與兩個所述功率晶片122的第二電極層1222，以使所述功率模組1能通過線路層13與兩個電熱傳導座121而測試每個功率晶片122。更詳細地說，由於功率晶片122在進行單獨測時，容易受到配線或治具等外部干擾影響，而導致功率晶片122無法接收到預定的電壓或電流，而本實施例的功率模組1是將功率晶片122埋置於絕緣基材11內以隔絕外部干擾，並通過所述線路層13與電熱傳導座121進行電壓或電流傳輸，以使功率晶片122能夠接收到預定的電壓或電流。並且，所述功率模組1可在置入多層板2之前先進行測試，藉以避免多層板2因為埋入有問題的功率模組1而造成不必要的損失。 As shown in FIG. 2 and FIG. 3, the circuit layer 13 is disposed on the first surface 111 of the insulating substrate 11, and the circuit layer 13 is electrically connected to the two electrothermal conduction blocks 121 and the two power chips 122. The second electrode layer 1222 is configured to enable the power module 1 to test each of the power chips 122 through the circuit layer 13 and the two electrothermal conduction pads 121. In more detail, since the power chip 122 is susceptible to external interference such as wiring or jig when performing separate measurement, the power chip 122 cannot receive a predetermined voltage or current, and the power module 1 of the embodiment is The power chip 122 is buried in the insulating substrate 11 to isolate external interference, and voltage or current is transmitted through the wiring layer 13 and the electrothermal conduction seat 121 to enable the power chip 122 to receive a predetermined voltage or current. Moreover, the power module 1 can be tested before being placed in the multi-layer board 2 to avoid unnecessary loss of the multi-layer board 2 due to the buried power module 1 being buried.
再者，所述線路層13具有相互分離的一串接線路131及兩個延伸線路132，所述串接線路131連接於屬於不同所述功率單元12(且相鄰近)的傳導部1211與所述第二電極層1222，而未與所述串接線路131連接(且相互遠離)的傳導部1211與第二電極層1222則分別連接於兩個所述延伸線路132，以使兩個功率單元12經由線路層13而並聯地電性連接。所述兩個功率單元12於本實施例中所包括兩個功率晶片122優選是並聯配合運作，所以單顆獨立運作的功率晶片(圖中未示出)並非是本實施例所指的功率晶片 122。 Furthermore, the circuit layer 13 has a series of lines 131 and two extension lines 132 which are separated from each other, and the series lines 131 are connected to the conducting portions 1211 and the portions belonging to different power units 12 (and adjacent thereto). The second electrode layer 1222, and the conductive portion 1211 and the second electrode layer 1222 that are not connected to the series line 131 (and away from each other) are respectively connected to the two extension lines 132 to make two power units 12 is electrically connected in parallel via the line layer 13 . The two power cells 12 included in the embodiment are preferably operated in parallel, so that a single independently operated power chip (not shown) is not the power chip referred to in this embodiment. 122.
其中，所述串接線路131及兩個延伸線路132是分別自絕緣基材11的第一表面111延伸入絕緣基材11內，以連接在遠離第二表面112的所述傳導部1211表面(如圖2中的傳導部1211頂面)及第二電極層1222。而所述兩個延伸線路132則可分別用以施加測試電壓或是輸入/輸出測試電流。 The serial connection line 131 and the two extension lines 132 respectively extend from the first surface 111 of the insulating substrate 11 into the insulating substrate 11 to be connected to the surface of the conductive portion 1211 away from the second surface 112 ( The top surface of the conductive portion 1211 in FIG. 2 and the second electrode layer 1222. The two extension lines 132 can be used to apply a test voltage or an input/output test current, respectively.
進一步地說，所述線路層13可以通過下述方式成型，但不受限於此。先在絕緣基材11的第一表面111形成貫通至功率晶片122第二電極層1222與電熱傳導座121傳導部1211的多個通孔(未標示)，而後再以一導電材料填滿(如：電鍍於)上述多個通孔並覆蓋於通孔旁的第一表面111部位，藉以成形上述的串接線路131及兩個延伸線路132。 Further, the wiring layer 13 can be formed in the following manner, but is not limited thereto. First, a plurality of through holes (not labeled) penetrating to the second electrode layer 1222 of the power chip 122 and the conductive portion 1211 of the electrothermal conducting block 121 are formed on the first surface 111 of the insulating substrate 11 and then filled with a conductive material (eg, And plating the plurality of through holes and covering the first surface 111 portion beside the through hole, thereby forming the above-mentioned serial connection line 131 and the two extension lines 132.
所述金屬層14設置於所述絕緣基材11的第二表面112，並且金屬層14包含至少兩個分離的區塊(未標示)，並且所述兩個電熱傳導座121的承載部1212分別一體連接於上述金屬層14的兩個區塊。此外，如圖6所示，所述功率模組1可進一步包括有一絕緣黏著層15，上述絕緣黏著層15設置於所述金屬層14以及絕緣基材11的至少部分第二表面112(如圖6中位於金屬層14兩個區塊間的第二表面112部位)，藉以使所述功率模組1能通過絕緣黏著層15而貼附於一導熱件200。 The metal layer 14 is disposed on the second surface 112 of the insulating substrate 11, and the metal layer 14 includes at least two separate blocks (not labeled), and the carrying portions 1212 of the two electrothermal conductive seats 121 are respectively The two blocks of the metal layer 14 are integrally connected. In addition, as shown in FIG. 6, the power module 1 may further include an insulating adhesive layer 15 disposed on the metal layer 14 and at least a portion of the second surface 112 of the insulating substrate 11 (as shown in FIG. 6 is located at the second surface 112 between the two blocks of the metal layer 14 so that the power module 1 can be attached to a heat conducting member 200 through the insulating adhesive layer 15.
此外，在另一未繪示的實施例中，所述傳導座121可改用陶瓷材料，並且於所述陶瓷材料內形成有導電線路，藉以作為傳導電流。其中，由於傳導座121改用陶瓷材料，所以能夠有效地改善功率晶片122與周圍材料間的膨脹係數差異、並且提升不同功率晶片122間的絕緣效果。 In addition, in another embodiment not shown, the conductive seat 121 can be replaced with a ceramic material, and a conductive line is formed in the ceramic material as a conduction current. Wherein, since the conductive seat 121 is changed to a ceramic material, the difference in expansion coefficient between the power wafer 122 and the surrounding material can be effectively improved, and the insulation effect between the different power chips 122 can be improved.
如圖1A所示，所述多層板2具有位於相反側的一第一板面21與一第二板面22，而所述多層板2於本實施例中是指經由壓合 成型並已完成線路佈局的多層式電路板。其中，所述功率模組1自第二板面22埋入於多層板2內而構成本實施例所指的晶片埋入式電路板結構100，並且所述功率模組1的絕緣基材11的第二表面112自第一板面21而裸露於所述多層板2外，而所述晶片埋入式電路板結構100能通過所述絕緣黏著層15而貼附於導熱件200。 As shown in FIG. 1A, the multilayer board 2 has a first board surface 21 and a second board surface 22 on opposite sides, and the multi-layer board 2 in this embodiment means via pressing. A multi-layer board that has been formed and has completed the layout of the circuit. The power module 1 is embedded in the multi-layer board 2 from the second board surface 22 to form the chip-embedded circuit board structure 100 of the embodiment, and the insulating substrate 11 of the power module 1 is formed. The second surface 112 is exposed from the first board surface 21 outside the multi-layer board 2, and the wafer-embedded circuit board structure 100 can be attached to the heat conducting member 200 through the insulating adhesive layer 15.
再者，所述功率模組1的絕緣基材11可採用不同於多層板2的材料(如：高散熱絕緣材質)，藉以提升晶片埋入式電路板結構100的散熱效果，並且能夠改善熱應力所造成的問題(如：多層板2彎翹或功率晶片122碎裂)。 Furthermore, the insulating substrate 11 of the power module 1 can adopt a material different from the multilayer board 2 (for example, a high heat dissipation insulating material), thereby improving the heat dissipation effect of the wafer embedded circuit board structure 100 and improving heat. Problems caused by stress (eg, multi-layer board 2 bending or power chip 122 chipping).
請參閱圖7和圖8，為本發明的實施例二，本實施例類似於上述實施例一，所以兩個實施例相同處則不再加以贅述，而兩個實施例的差異主要在於所述功率模組1的構造。 Referring to FIG. 7 and FIG. 8 , which is the second embodiment of the present invention, the embodiment is similar to the first embodiment, so the two embodiments are not described in detail, and the differences between the two embodiments are mainly in the above description. The construction of the power module 1.
具體來說，本實施例的功率模組1省略金屬層14，每個功率單元12並且進一步包含有一絕緣散熱體123，上述絕緣散熱體123於本實施例中為陶瓷塊體作說明，但不受限於此。而於每個所述功率單元12中，所述電熱傳導座121的承載部1212設置於絕緣散熱體123上，並且遠離功率晶片122的所述絕緣散熱體123表面是與絕緣基材11的第二表面112呈共平面設置。 Specifically, the power module 1 of the present embodiment omits the metal layer 14, each power unit 12 and further includes an insulating heat sink 123. The insulating heat sink 123 is a ceramic block in this embodiment, but Limited by this. In each of the power units 12, the bearing portion 1212 of the electrothermal conduction seat 121 is disposed on the insulating heat sink 123, and the surface of the insulating heat sink 123 away from the power wafer 122 is the same as the insulating substrate 11. The two surfaces 112 are coplanar.
進一步地說，用來承載所述電熱傳導座121的每個絕緣散熱體123表面較佳是大於所述承載部1212的承載面1214，並且絕緣散熱體123於本實施例的體積是大於電熱傳導座121的體積，但不受限於此。再者，所述絕緣黏著層15設置於所述絕緣散熱體123以及絕緣基材11的至少部分第二表面112，藉以使所述功率模組1能通過絕緣黏著層15而貼附於一導熱件200。 Further, the surface of each insulating heat sink 123 for carrying the electrothermal conduction seat 121 is preferably larger than the bearing surface 1214 of the carrying portion 1212, and the volume of the insulating heat sink 123 in the embodiment is greater than the electric heat conduction. The volume of the seat 121 is, but is not limited to, this. Furthermore, the insulating adhesive layer 15 is disposed on the insulating heat sink 123 and at least a portion of the second surface 112 of the insulating substrate 11 , so that the power module 1 can be attached to a heat conducting layer through the insulating adhesive layer 15 . Piece 200.
以上所述僅為本發明的優選可行實施例，並非用來侷限本發明的保護範圍，凡依本發明申請專利範圍所做的同等變化與修 飾，皆應屬本發明的涵蓋範圍。 The above description is only a preferred possible embodiment of the present invention, and is not intended to limit the scope of the present invention. Decorations are all within the scope of the present invention.
1‧‧‧功率模組 1‧‧‧Power Module
11‧‧‧絕緣基材 11‧‧‧Insulation substrate
111‧‧‧第一表面 111‧‧‧ first surface
112‧‧‧第二表面 112‧‧‧ second surface
12‧‧‧功率單元 12‧‧‧Power unit
121‧‧‧電熱傳導座 121‧‧‧Electrothermal conduction seat
1211‧‧‧傳導部 1211‧‧‧Transmission Department
1212‧‧‧承載部 1212‧‧‧Loading Department
1214‧‧‧承載面 1214‧‧‧ bearing surface
122‧‧‧功率晶片 122‧‧‧Power chip
1221‧‧‧第一電極層 1221‧‧‧First electrode layer
1222‧‧‧第二電極層 1222‧‧‧Second electrode layer
13‧‧‧線路層 13‧‧‧Line layer
131‧‧‧串接線路 131‧‧‧Sequence line
132‧‧‧延伸線路 132‧‧‧Extended lines
14‧‧‧金屬層 14‧‧‧metal layer
15‧‧‧絕緣黏著層 15‧‧‧Insulating adhesive layer
Claims (10)
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| TW105120923A TWI599285B (en) | 2016-07-01 | 2016-07-01 | Circuit board structure with chip embedded therein and power module |
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| TWI831247B (en) * | 2022-06-16 | 2024-02-01 | 先豐通訊股份有限公司 | Power module and method for manufacturing the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030231669A1 (en) * | 2002-06-15 | 2003-12-18 | Kozlovsky William J. | Chip carrier apparatus and method |
| TW200621099A (en) * | 2004-12-03 | 2006-06-16 | Phoenix Prec Technology Corp | Embedded resistance structure integrated in circuit board |
| TW200802756A (en) * | 2006-06-26 | 2008-01-01 | Univ Nat Cheng Kung | Embedded metal heat sink for semiconductor device and method for manufacturing the same |
| TW201417650A (en) * | 2012-10-18 | 2014-05-01 | Zhen Ding Technology Co Ltd | Connecting substrate and package on package structure |
| TW201448220A (en) * | 2013-04-10 | 2014-12-16 | Samsung Electronics Co Ltd | Semiconductor device and method for fabricating the same |
| TW201513301A (en) * | 2013-09-23 | 2015-04-01 | 台達電子企業管理（上海）有限公司 | Power module |
-
2016
- 2016-07-01 TW TW105120923A patent/TWI599285B/en active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030231669A1 (en) * | 2002-06-15 | 2003-12-18 | Kozlovsky William J. | Chip carrier apparatus and method |
| TW200621099A (en) * | 2004-12-03 | 2006-06-16 | Phoenix Prec Technology Corp | Embedded resistance structure integrated in circuit board |
| TW200802756A (en) * | 2006-06-26 | 2008-01-01 | Univ Nat Cheng Kung | Embedded metal heat sink for semiconductor device and method for manufacturing the same |
| TW201417650A (en) * | 2012-10-18 | 2014-05-01 | Zhen Ding Technology Co Ltd | Connecting substrate and package on package structure |
| TW201448220A (en) * | 2013-04-10 | 2014-12-16 | Samsung Electronics Co Ltd | Semiconductor device and method for fabricating the same |
| TW201513301A (en) * | 2013-09-23 | 2015-04-01 | 台達電子企業管理（上海）有限公司 | Power module |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI831247B (en) * | 2022-06-16 | 2024-02-01 | 先豐通訊股份有限公司 | Power module and method for manufacturing the same |
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