TWI597853B - Shottcky diode structure and method for forming the same - Google Patents
Shottcky diode structure and method for forming the same Download PDFInfo
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本發明是關於一種蕭基二極體的結構及其形成方法。 The present invention relates to a structure of a Schottky diode and a method of forming the same.
蕭基二極體(Schottky Diode)是利用金屬與半導體接觸而形成蕭基障壁(Schottky Barrier)，由於金屬中沒有少數載子，故蕭基二極體切換於導通與不導通之間不會造成時間延遲，因此，蕭基二極體被廣泛地應用於電子裝置中，特別是作為開關來使用。 Schottky Diode uses Schottky Barrier to form a Schottky Barrier by contacting metal with a semiconductor. Since there are few carriers in the metal, the Schottky diode switches between conduction and non-conduction. The time delay, therefore, the Xiaoji diode is widely used in electronic devices, especially as a switch.
然而，由於蕭基二極體的反向偏壓較低及反向漏電流較大，且其漏電流大小與溫度成正比，也就是說，當蕭基二極體操作之環境的溫度愈高時，蕭基二極體的缺點就愈顯著。因此，在製造蕭基二極體時，如何提高其擊穿電壓(Breakdown Voltage)及降低漏電流(Leakage Current)是必然面對的課題。再者，在半導體製程中，微影製程對於整體製造成本產生極大的貢獻，其包含製程時間成本和製程中所使用的光罩數量成本，而習知之蕭基二極體之製造方法通常需要四道光罩才能實現，如此造成製造成本大幅地提升。 However, because the reverse bias of the Xiaoji diode is lower and the reverse leakage current is larger, and the leakage current is proportional to the temperature, that is, the higher the temperature of the environment in which the Xiaoji diode is operated. At the time, the shortcomings of the Xiaoji diode are more pronounced. Therefore, how to increase the breakdown voltage and reduce the leakage current (Leakage Current) is an inevitable problem when manufacturing the Schottky diode. Moreover, in the semiconductor manufacturing process, the lithography process greatly contributes to the overall manufacturing cost, including the process time cost and the cost of the reticle used in the process, and the conventional manufacturing method of the Schottky diode usually requires four. The reticle can be realized, which causes a significant increase in manufacturing costs.
有鑑於此，本發明提出一種蕭基二極體的結構及其形成方法。 In view of this, the present invention proposes a structure of a Xiaoji diode and a method of forming the same.
在一實施例中，蕭基二極體結構包含半導體基板、磊晶層、金屬層及隔離結構。半導體基板具有一第一導電型且半導體基板包含一第一上表面、一側表面與一第二上表面。其中，第二上表面與第一上表面不共平面，第二上表面環繞第一上表面且經由側表面連接於第一上表面。磊晶層具有第一導電型且磊晶層係覆蓋第一上表面，磊晶層之表面形成具有第二導電型之一護環結構。金屬層包含一上表面及一下表面，其下表面覆蓋磊晶層。隔離結構係覆蓋半導體基板之第二上表面、半導體基板之側表面、磊晶層之側表面與金屬層之側表面，且隔離結構突出金屬層之上表面。 In one embodiment, the Schottky diode structure comprises a semiconductor substrate, an epitaxial layer, a metal layer, and an isolation structure. The semiconductor substrate has a first conductivity type and the semiconductor substrate includes a first upper surface, a side surface, and a second upper surface. Wherein the second upper surface is not coplanar with the first upper surface, and the second upper surface surrounds the first upper surface and is connected to the first upper surface via the side surface. The epitaxial layer has a first conductivity type and the epitaxial layer covers the first upper surface, and the surface of the epitaxial layer forms a guard ring structure having a second conductivity type. The metal layer comprises an upper surface and a lower surface, the lower surface of which covers the epitaxial layer. The isolation structure covers the second upper surface of the semiconductor substrate, the side surface of the semiconductor substrate, the side surface of the epitaxial layer and the side surface of the metal layer, and the isolation structure protrudes from the upper surface of the metal layer.
在一實施例中，前述隔離結構覆蓋金屬層之局部之下表面。 In an embodiment, the isolation structure covers a portion of the lower surface of the metal layer.
在一實施例中，前述隔離結構覆蓋金屬層之局部之上表面。 In an embodiment, the isolation structure covers a portion of the upper surface of the metal layer.
在一實施例中，蕭基二極體結構的形成方法包含形成一磊晶層於一半導體基板上，磊晶層及半導體基板具有第一導電型；於磊晶層之表面形成一護環結構，護環結構具有第二導電型；形成一金屬層於磊晶層上；形成一溝渠貫穿金屬層、護環結構、磊晶層，且延伸至局部之半導體基板中；及填充隔離材料於溝渠以形成一隔離結構，此隔離結構突出金屬層之表面。 In one embodiment, the method for forming a Schottky diode structure includes forming an epitaxial layer on a semiconductor substrate, the epitaxial layer and the semiconductor substrate having a first conductivity type; forming a guard ring structure on the surface of the epitaxial layer The guard ring structure has a second conductivity type; forming a metal layer on the epitaxial layer; forming a trench through the metal layer, the guard ring structure, the epitaxial layer, and extending into the local semiconductor substrate; and filling the isolation material in the trench To form an isolation structure that protrudes from the surface of the metal layer.
在一實施例中，於執行前述填充隔離材料之步驟前，更包含乾蝕刻溝渠中之護環結構、磊晶層及半導體基板以局部暴露金屬層朝向磊晶層之表面。 In one embodiment, before performing the step of filling the isolation material, the ring structure, the epitaxial layer and the semiconductor substrate in the dry etching trench are further included to partially expose the metal layer toward the surface of the epitaxial layer.
在一實施例中，填充隔離材料於溝渠以形成隔離結構之步驟包含覆蓋隔離材料於金屬層朝向磊晶層之表面。 In one embodiment, the step of filling the isolation material in the trench to form the isolation structure comprises covering the isolation material to the surface of the metal layer toward the epitaxial layer.
在一實施例中，填充隔離材料於溝渠以形成隔離結構之步驟 更包含覆蓋隔離材料於金屬層之局部上表面。 In one embodiment, the step of filling the isolation material in the trench to form the isolation structure Further comprising covering the isolation material on a partial upper surface of the metal layer.
綜上所述，根據本發明之蕭基二極體結構之一實施例，其隔離結構係突出於金屬層之上表面，且隔離結構覆蓋局部之金屬層之下表面及金屬層之上表面。基此，前述之蕭基二極體之漏電流較小，且具有較穩定的擊穿電壓，進而提升其可靠度(reliability)及抗靜電能力並大幅地節省了光罩成本。 In summary, according to an embodiment of the Schottky diode structure of the present invention, the isolation structure protrudes from the upper surface of the metal layer, and the isolation structure covers the lower surface of the local metal layer and the upper surface of the metal layer. Therefore, the aforementioned Schottky diode has a small leakage current and a relatively stable breakdown voltage, thereby improving its reliability and antistatic capability and greatly reducing the cost of the mask.
1‧‧‧蕭基二極體 1‧‧‧Xiaoji diode
11‧‧‧半導體基板 11‧‧‧Semiconductor substrate
11A‧‧‧第一上表面 11A‧‧‧First upper surface
11B‧‧‧第二上表面 11B‧‧‧Second upper surface
11C‧‧‧下表面 11C‧‧‧ lower surface
11D‧‧‧側表面 11D‧‧‧ side surface
11E‧‧‧側表面 11E‧‧‧ side surface
12‧‧‧磊晶層 12‧‧‧ epitaxial layer
12A‧‧‧側表面 12A‧‧‧ side surface
12B‧‧‧上表面 12B‧‧‧ upper surface
121‧‧‧護環結構 121‧‧‧Guard ring structure
13‧‧‧第一金屬層 13‧‧‧First metal layer
131‧‧‧突出部 131‧‧‧Protruding
13A‧‧‧上表面 13A‧‧‧Upper surface
13B‧‧‧下表面 13B‧‧‧ lower surface
13C‧‧‧側表面 13C‧‧‧ side surface
14‧‧‧隔離結構 14‧‧‧Isolation structure
15‧‧‧氧化層 15‧‧‧Oxide layer
15A‧‧‧凹槽 15A‧‧‧ Groove
15B‧‧‧凹槽 15B‧‧‧ Groove
16‧‧‧溝渠 16‧‧‧ditch
17‧‧‧第二金屬層 17‧‧‧Second metal layer
18‧‧‧保護層 18‧‧‧Protective layer
[圖1]為根據本發明之蕭基二極體結構之一實施例之剖面圖。 Fig. 1 is a cross-sectional view showing an embodiment of a Schottky diode structure according to the present invention.
[圖2]為圖1之蕭基二極體之一實施態樣之剖面圖。 FIG. 2 is a cross-sectional view showing an embodiment of the Schottky diode of FIG. 1. FIG.
[圖3]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(一)。 Fig. 3 is an exploded perspective view (1) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖4]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(二)。 Fig. 4 is an exploded perspective view (2) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖5]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(三)。 Fig. 5 is an exploded perspective view (III) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖6]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(四)。 Fig. 6 is an exploded perspective view (4) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖7]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(五)。 Fig. 7 is an exploded perspective view (5) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖8]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(六)。 Fig. 8 is an exploded perspective view (6) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖9]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(七)。 Fig. 9 is an exploded perspective view (7) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖10]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(八)。 Fig. 10 is an exploded perspective view (8) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖11]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(九)。 Fig. 11 is an exploded perspective view (9) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖12]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(十)。 Fig. 12 is an exploded perspective view (10) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖13]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(十一)。 Fig. 13 is an exploded perspective view (11) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
[圖14]為根據本發明之蕭基二極體結構之形成方法之一實施例之步驟分解圖(十二)。 Fig. 14 is an exploded view (12) of an embodiment of a method for forming a Schottky diode structure according to the present invention.
圖1為根據本發明之蕭基二極體結構之一實施例之剖面圖。應能了解，圖式中的比例僅為示意，本發明並不以此為限。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing an embodiment of a Schottky diode structure in accordance with the present invention. It should be understood that the ratios in the drawings are merely schematic and the invention is not limited thereto.
請參照圖1，揭露一蕭基二極體1，包含半導體基板11、磊晶層12、兩金屬層(為方便描述，分別稱之為第一金屬層13及第二金屬層17)及隔離(passivation)結構14。半導體基板11包含兩上表面(為方便描述分別稱之為第一上表面11A及第二上表面11B)、下表面11C及兩側表面11D、11E。其中，第二上表面11B與第一上表面11A不共平面，第二上表面11B環繞第一上表面11A，且第二上表面11B經由側表面11D連接於第一上表面11A。換言之，側表面11E、第二上表面11B、側表面11D及第一上 表面11A形成中間突起之一平台(mesa)結構。在本實施例中，半導體基板11具有第一導電型，例如，半導體基板11可為具重摻雜之N型矽基板。 Referring to FIG. 1 , a Schottky diode 1 is disclosed, including a semiconductor substrate 11 , an epitaxial layer 12 , and two metal layers (referred to as a first metal layer 13 and a second metal layer 17 for convenience of description) and isolation. (passivation) structure 14. The semiconductor substrate 11 includes two upper surfaces (referred to as a first upper surface 11A and a second upper surface 11B, respectively for convenience of description), a lower surface 11C, and both side surfaces 11D, 11E. Wherein, the second upper surface 11B is not coplanar with the first upper surface 11A, the second upper surface 11B surrounds the first upper surface 11A, and the second upper surface 11B is connected to the first upper surface 11A via the side surface 11D. In other words, the side surface 11E, the second upper surface 11B, the side surface 11D, and the first upper surface The surface 11A forms a mesa structure of the intermediate protrusions. In the present embodiment, the semiconductor substrate 11 has a first conductivity type. For example, the semiconductor substrate 11 may be a heavily doped N-type germanium substrate.
磊晶層12覆蓋並接觸半導體基板11之第一上表面11A，並且，磊晶層12之上表面12B具有護環結構121，此護環結構121是用以避免蕭基二極體與鄰近之元件之間產生電性干擾而導致漏電現象發生。在本實施例中，磊晶層12為同質磊晶(homoepitaxial)，也就是說，磊晶層12亦具有第一導電型，例如，磊晶層12之材質可為具輕摻雜之N型矽。另一方面，護環結構121具有第二導電型，例如，P型，且其濃度大於鄰近之磊晶層12之摻質濃度。 The epitaxial layer 12 covers and contacts the first upper surface 11A of the semiconductor substrate 11, and the upper surface 12B of the epitaxial layer 12 has a guard ring structure 121 for avoiding the Schottky diode and the adjacent Electrical interference between components causes leakage. In this embodiment, the epitaxial layer 12 is homoepitaxial, that is, the epitaxial layer 12 also has a first conductivity type. For example, the material of the epitaxial layer 12 may be a lightly doped N-type. Hey. On the other hand, the grommet structure 121 has a second conductivity type, for example, a P-type, and its concentration is greater than the dopant concentration of the adjacent epitaxial layer 12.
第一金屬層13具有上表面13A及下表面13B，其下表面13B接觸且覆蓋磊晶層12，以形成蕭基接觸(schottky contact)。第二金屬層17接觸並覆蓋半導體基板11之下表面11C，以形成歐姆接觸(ohmic contact)。第一金屬層13及第二金屬層17之材質可以是Ti、Ni、Ag、Al等任何可導電之金屬以及前述項目之組合。在一些實施例中，第一金屬層13及第二金屬層17可包含障蔽區域，且第一金屬層13及第二金屬層17之表面可塗保護層以提高其表面抗性。 The first metal layer 13 has an upper surface 13A and a lower surface 13B, the lower surface 13B of which contacts and covers the epitaxial layer 12 to form a schottky contact. The second metal layer 17 contacts and covers the lower surface 11C of the semiconductor substrate 11 to form an ohmic contact. The material of the first metal layer 13 and the second metal layer 17 may be any electrically conductive metal such as Ti, Ni, Ag, Al or the like and a combination of the foregoing items. In some embodiments, the first metal layer 13 and the second metal layer 17 may include a barrier region, and the surfaces of the first metal layer 13 and the second metal layer 17 may be coated with a protective layer to improve surface resistance.
隔離結構14接觸並覆蓋半導體基板11之第二上表面11B、側表面11D、磊晶層12之側表面12A及第一金屬層13之側表面13C。換言之，隔離結構14依序經由第一金屬層13、磊晶層12延伸至半導體基板11而貫穿局部之半導體基板11，且隔離結構14遮蔽半導體基板11之第二上表面11B、側表面11D、磊晶層12之側表面12A及第一金屬層13之側表面13C。進一步來看，隔離結構14在半導體基板11至金屬層13之延伸方向上突出於 第一金屬層13之上表面13A，使得電子活動於上表面13A時較不易越過隔離結構14，以降低漏電流效應。而隔離結構14之材質可為聚醯亞胺(polyimide，PI)。相較於習知的蕭基二極體，蕭基二極體1之漏電流較小，且具有較穩定的擊穿(breakdown)電壓，進而具有較佳的可靠度(reliability)及較佳的抗靜電(ESD)能力。較佳地，其抗靜電力可達30KV。 The isolation structure 14 contacts and covers the second upper surface 11B of the semiconductor substrate 11, the side surface 11D, the side surface 12A of the epitaxial layer 12, and the side surface 13C of the first metal layer 13. In other words, the isolation structure 14 extends through the first metal layer 13 and the epitaxial layer 12 to the semiconductor substrate 11 to penetrate the local semiconductor substrate 11 , and the isolation structure 14 shields the second upper surface 11B and the side surface 11D of the semiconductor substrate 11 . The side surface 12A of the epitaxial layer 12 and the side surface 13C of the first metal layer 13. Further, the isolation structure 14 protrudes from the extending direction of the semiconductor substrate 11 to the metal layer 13 The upper surface 13A of the first metal layer 13 makes it less likely to pass over the isolation structure 14 when the electrons move on the upper surface 13A to reduce the leakage current effect. The material of the isolation structure 14 may be polyimide (PI). Compared with the conventional Xiaoji diode, the Xiaoji diode 1 has a small leakage current and a relatively stable breakdown voltage, which has better reliability and better performance. Antistatic (ESD) capability. Preferably, the antistatic force is up to 30 kV.
在一些實施態樣中，如圖2所示，第一金屬層13於緊鄰護環結構121之兩側突出於磊晶層12而形成一突出部131，也就是說，第一金屬層13之下表面13B之局部不被磊晶層12所覆蓋而與半導體基板11之第二上表面11B面對面。此時，隔離結構14接觸且覆蓋第一金屬層13之局部之下表面13B，且隔離結構14接觸並覆蓋第一金屬層13之上表面13A。於是，相較於圖1之隔離結構14，圖2中所繪示之隔離結構14包圍突出部131而與第一金屬層13相互卡合，如此便可避免隔離結構14因受力而脫落，進而提升蕭基二極體1之耐用性。 In some embodiments, as shown in FIG. 2, the first metal layer 13 protrudes from the epitaxial layer 12 on both sides of the guard ring structure 121 to form a protrusion 131, that is, the first metal layer 13 A portion of the lower surface 13B is not covered by the epitaxial layer 12 and faces the second upper surface 11B of the semiconductor substrate 11. At this time, the isolation structure 14 contacts and covers the partial lower surface 13B of the first metal layer 13, and the isolation structure 14 contacts and covers the upper surface 13A of the first metal layer 13. Therefore, compared with the isolation structure 14 of FIG. 1, the isolation structure 14 illustrated in FIG. 2 surrounds the protrusion 131 and is engaged with the first metal layer 13, so that the isolation structure 14 can be prevented from falling off due to the force. In turn, the durability of the Xiaoji diode 1 is improved.
圖3至圖14為根據本發明之蕭基二極體之形成方法之一實施例之分解步驟圖。請同時參照圖3至圖14，首先，如圖3所示，提供第一導電型之重摻雜之半導體基板11，例如，前述之N+矽基板。接著，以一常規磊晶製程在半導體基板11的第一上表面11A上形成第一導電型之一磊晶層12，且磊晶層12的摻雜濃度小於半導體基板11。 3 to 14 are exploded perspective views of an embodiment of a method for forming a Schottky diode according to the present invention. Referring to FIG. 3 to FIG. 14 simultaneously, first, as shown in FIG. 3, a heavily doped semiconductor substrate 11 of the first conductivity type, for example, the aforementioned N+ germanium substrate, is provided. Next, one epitaxial layer 12 of the first conductivity type is formed on the first upper surface 11A of the semiconductor substrate 11 by a conventional epitaxial process, and the doping concentration of the epitaxial layer 12 is smaller than that of the semiconductor substrate 11.
接著，如圖4及圖5所示，藉由乾式或溼式氧化製程在磊晶層12的上表面12B形成氧化層15。並且，藉由微影(lithography)及蝕刻(etching)製程對氧化層15進行圖案化(pattern)，以形成兩凹槽15A、 15B。如圖5所示，磊晶層12之局部之上表面12B經由兩凹槽15A、15B暴露，如此便可定義出欲形成護環結構121之區域。在本實施例中，氧化層15的材質可為二氧化矽(SiO2)。 Next, as shown in FIGS. 4 and 5, an oxide layer 15 is formed on the upper surface 12B of the epitaxial layer 12 by a dry or wet oxidation process. And, the oxide layer 15 is patterned by a lithography and etching process to form the two grooves 15A, 15B. As shown in FIG. 5, the partial upper surface 12B of the epitaxial layer 12 is exposed through the two grooves 15A, 15B, so that the area where the guard ring structure 121 is to be formed can be defined. In the present embodiment, the material of the oxide layer 15 may be cerium oxide (SiO 2 ).
接著，藉由兩凹槽15A、15B以擴散(Diffusion)方法或以離子佈植(ion implantation)的方式在磊晶層12之表面摻雜雜質，例如硼(Boron)，以在鄰近磊晶層12之上表面12B之區域形成具第二導電型之護環結構121，如圖6所示。 Then, the surface of the epitaxial layer 12 is doped with impurities, such as boron (Boron), by a diffusion method or ion implantation by the two grooves 15A, 15B to be adjacent to the epitaxial layer. The region of the upper surface 12B of 12 forms a guard ring structure 121 having a second conductivity type, as shown in FIG.
接著，如圖7所示，將氧化層15完全移除以暴露磊晶層12之全部之上表面12B。如圖8所示，在上表面12B上形成第一金屬層13，以形成蕭基接面，且在半導體基板11之下表面11C上形成第二金屬層17，以形成歐姆接面。在一些實施例中，在形成第一金屬層13及第二金屬層17之前，對磊晶層12之上表面12B及半導體基板11之下表面11C進行平坦化製程，例如，利用王水(aqua regia)來化學機械平坦化(Chemical Mechanical Polishing；CMP)製程，再經由沉積製程之化學氣相沉積法(chemical vapor deposition；CVD)或物理氣象沉積法(physical vapor deposition；PVD)來形成第一金屬層13及第二金屬層17。並且，且在形成第一金屬層13及第二金屬層17之後進行退火(anneal)處理。 Next, as shown in FIG. 7, the oxide layer 15 is completely removed to expose the entire upper surface 12B of the epitaxial layer 12. As shown in FIG. 8, a first metal layer 13 is formed on the upper surface 12B to form a Schottky junction, and a second metal layer 17 is formed on the lower surface 11C of the semiconductor substrate 11 to form an ohmic junction. In some embodiments, the upper surface 12B of the epitaxial layer 12 and the lower surface 11C of the semiconductor substrate 11 are planarized before the first metal layer 13 and the second metal layer 17 are formed, for example, using aqua (aqua) Regia) to the chemical mechanical polishing (CMP) process, and then through the deposition process of chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form the first metal Layer 13 and second metal layer 17. Further, after the first metal layer 13 and the second metal layer 17 are formed, an annealing treatment is performed.
接著形成溝渠16。如圖10所示，溝渠16貫穿第一金屬層13、護環結構121、磊晶層12而延伸至局部之半導體基板11中，以暴露半導體基板11之第二上表面11B、側表面11D、磊晶層12之側表面12A、護環結構121之側表面及第一金屬層13之側表面13C。於此，兩溝渠16之間形成前述之平台結構。在一些實施例中，可藉由機械切割來形成溝渠16，例如， 經由鑽石刀具(Diamond Blade)沿著預先形成之切割道來形成溝渠16。或者，可藉由雷射切割來形成溝渠16；並且，在進行切割製程之前，在半導體基板11之下表面11C貼上膠帶(例如，blue tape)，並在溝渠16形成之後將膠帶除去。 A trench 16 is then formed. As shown in FIG. 10, the trench 16 extends through the first metal layer 13, the guard ring structure 121, and the epitaxial layer 12 to extend into the local semiconductor substrate 11 to expose the second upper surface 11B and the side surface 11D of the semiconductor substrate 11. The side surface 12A of the epitaxial layer 12, the side surface of the guard ring structure 121, and the side surface 13C of the first metal layer 13. Here, the aforementioned platform structure is formed between the two trenches 16. In some embodiments, the trench 16 can be formed by mechanical cutting, for example, The trench 16 is formed along a pre-formed scribe line via a Diamond Blade. Alternatively, the trench 16 may be formed by laser cutting; and before the cutting process is performed, a tape (for example, a blue tape) is attached to the lower surface 11C of the semiconductor substrate 11, and the tape is removed after the trench 16 is formed.
接著，便可將隔離材料填充於溝渠16，如圖12所示，並填充至突出於第一金屬層13之上表面13A以形成隔離結構14。在此情況下，隔離結構14接觸並覆蓋半導體基板11之第二上表面11B、側表面11D、磊晶層12之側表面12A、護環結構121之側表面及第一金屬層13之側表面13C。進一步，如前所述，為增加隔離結構14之耐用性，如圖11所示，在填充隔離材料之前，對溝渠16進行乾蝕刻(dry etching)製程，以蝕刻溝渠16兩側鄰接護環結構121、磊晶層12及半導體基板11之表面。於此便形成金屬層13之突出部131，進而局部暴露出金屬層13朝向磊晶層12之表面(即下表面13B)。在此情況下，如圖12所示，隔離結構14更接觸並覆蓋金屬層13之局部之下表面13B。如此一來，便提高了隔離結構14之耐用性。 Next, the isolation material may be filled in the trench 16, as shown in FIG. 12, and filled to protrude from the upper surface 13A of the first metal layer 13 to form the isolation structure 14. In this case, the isolation structure 14 contacts and covers the second upper surface 11B of the semiconductor substrate 11, the side surface 11D, the side surface 12A of the epitaxial layer 12, the side surface of the guard ring structure 121, and the side surface of the first metal layer 13. 13C. Further, as described above, in order to increase the durability of the isolation structure 14, as shown in FIG. 11, the trench 16 is subjected to a dry etching process to etch the adjacent guard ring structures on both sides of the trench 16 before filling the isolation material. 121, the surface of the epitaxial layer 12 and the semiconductor substrate 11. Here, the protruding portion 131 of the metal layer 13 is formed, thereby partially exposing the metal layer 13 toward the surface of the epitaxial layer 12 (i.e., the lower surface 13B). In this case, as shown in FIG. 12, the isolation structure 14 more contacts and covers a portion of the lower surface 13B of the metal layer 13. As a result, the durability of the isolation structure 14 is improved.
在一些實施例中，可藉由化學氣相沉積法或物理氣象沉積法來形成隔離結構14。 In some embodiments, the isolation structure 14 can be formed by chemical vapor deposition or physical weather deposition.
在一些實施例中，為避免進行切割製程時不慎破壞第一金屬層15，如圖9至圖12所示，在進行切割製程之前可在第一金屬層13之上表面13A塗佈保護層18。並且，在形成隔離結構14之後將保護層18完全移除。在將保護層18移除之前，如圖12所示，隔離結構14未接觸第一金屬層13之上表面13A；在將保護層18完全移除之後，如圖13所示，隔離結構14接觸並覆蓋第一金屬層13之上表面13A之局部，以增加隔離結構14之耐 用性。 In some embodiments, in order to avoid inadvertently destroying the first metal layer 15 during the cutting process, as shown in FIGS. 9 to 12, the protective layer may be coated on the upper surface 13A of the first metal layer 13 before the cutting process is performed. 18. Also, the protective layer 18 is completely removed after the isolation structure 14 is formed. Before the protective layer 18 is removed, as shown in FIG. 12, the isolation structure 14 does not contact the upper surface 13A of the first metal layer 13; after the protective layer 18 is completely removed, as shown in FIG. 13, the isolation structure 14 contacts And covering a portion of the upper surface 13A of the first metal layer 13 to increase the resistance of the isolation structure 14 Use sex.
最後，如圖14所示，沿著隔離結構14對半導體基板11以及第二金屬層17進行切割以進行分離製程(singulation)，進而形成多個分離之蕭基二極體1。如圖14所示，進行分離製程後便形成多個分離的蕭基二極體1。相較於習知的蕭基二極體，蕭基二極體1之漏電流較小，且具有較穩定的擊穿(breakdown)電壓，進而提升蕭基二極體1之可靠度及抗靜電能力(ESD)。進一步，在形成蕭基二極體1之製程步驟中，僅在對氧化層15進行圖案化時需使用光罩來進行，相較於習知之蕭基二極體的形成方法需要四道光罩，大幅地節省了光罩成本。 Finally, as shown in FIG. 14, the semiconductor substrate 11 and the second metal layer 17 are diced along the isolation structure 14 to perform a separation process, thereby forming a plurality of separated Schottky diodes 1. As shown in FIG. 14, after the separation process is performed, a plurality of separated Schottky diodes 1 are formed. Compared with the conventional Xiaoji diode, the Xiaoji diode 1 has a small leakage current and a relatively stable breakdown voltage, thereby improving the reliability and antistatic of the Xiaoji diode 1 . Ability (ESD). Further, in the process of forming the Schottky diode 1 , only the photomask is used for patterning the oxide layer 15 , which requires four masks compared to the conventional method of forming the Schottky diode. Significant savings in mask costs.
綜上所述，根據本發明之蕭基二極體結構之一實施例，其隔離結構係突出於金屬層之上表面，且隔離結構覆蓋局部之金屬層之下表面及金屬層之上表面。基此，前述之蕭基二極體之漏電流較小，且具有較穩定的擊穿電壓，進而提升其可靠度及抗靜電能力並大幅地節省了光罩成本。 In summary, according to an embodiment of the Schottky diode structure of the present invention, the isolation structure protrudes from the upper surface of the metal layer, and the isolation structure covers the lower surface of the local metal layer and the upper surface of the metal layer. Therefore, the aforementioned Schottky diode has a small leakage current and a relatively stable breakdown voltage, thereby improving its reliability and antistatic capability and greatly reducing the cost of the mask.
雖然本發明已以實施例揭露如上然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之專利申請範圍所界定者為準。 The present invention has been disclosed in the above embodiments, and it is not intended to limit the present invention. Any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended patent application.
1‧‧‧蕭基二極體 1‧‧‧Xiaoji diode
11‧‧‧半導體基板 11‧‧‧Semiconductor substrate
11A‧‧‧第一上表面 11A‧‧‧First upper surface
11B‧‧‧第二上表面 11B‧‧‧Second upper surface
11C‧‧‧下表面 11C‧‧‧ lower surface
11D‧‧‧側表面 11D‧‧‧ side surface
11E‧‧‧側表面 11E‧‧‧ side surface
12‧‧‧磊晶層 12‧‧‧ epitaxial layer
12A‧‧‧側表面 12A‧‧‧ side surface
12B‧‧‧上表面 12B‧‧‧ upper surface
121‧‧‧護環結構 121‧‧‧Guard ring structure
13‧‧‧第一金屬層 13‧‧‧First metal layer
131‧‧‧突出部 131‧‧‧Protruding
13A‧‧‧上表面 13A‧‧‧Upper surface
13B‧‧‧下表面 13B‧‧‧ lower surface
13C‧‧‧側表面 13C‧‧‧ side surface
14‧‧‧隔離結構 14‧‧‧Isolation structure
17‧‧‧第二金屬層 17‧‧‧Second metal layer
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| CN110277437A (en) * | 2018-03-16 | 2019-09-24 | 张峻玮 | A kind of Xiao's based diode structure and its manufacturing method of the high-effect low-leakage current of outer cladding formula |
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