TWI596709B - Memory device and method of fabricating the same - Google Patents
Memory device and method of fabricating the same Download PDFInfo
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Description
本發明是有關於一種半導體元件及其製造方法，且特別是有關於一種記憶體元件及其製造方法。 The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device and a method of fabricating the same.
在記憶體元件中，為了增加電晶體的通道長度、充分利用基底空間、增加不同層級的導線之間的距離等等目的，往往會在基底中形成埋入式導線。為了保護埋入式導線使其免於被後續製程影響，通常會在埋入式導線上方設置蓋層，以保護埋入式導線。然而，在蓋層中常常會有空隙(void)的存在，而大大減少了蓋層的保護功效。 In the memory element, in order to increase the channel length of the transistor, make full use of the substrate space, increase the distance between wires of different levels, and the like, a buried wire is often formed in the substrate. In order to protect the buried conductor from being affected by subsequent processes, a cap layer is typically placed over the buried conductor to protect the buried conductor. However, there is often a void in the cap layer, which greatly reduces the protective effect of the cap layer.
本發明提供一種記憶體元件，其增加對埋入式導線的保護。 The present invention provides a memory component that increases protection of buried wires.
本發明還提供一種記憶體元件的製造方法。 The present invention also provides a method of fabricating a memory device.
本發明的記憶體元件包括基底、多個第一導線、蝕刻停 止層、介電層以及多個接觸窗。基底具有多個第一區域以及多個第二區域，第一區域和第二區域沿第一方向交錯排列。第一導線埋入於基底中，沿第一方向延伸。第一導線包括導電層和位於所述導電層上的蓋層，蓋層的上表面具有凹槽。蝕刻停止層位於基底上以及蓋層上，並填入於凹槽中。介電層位於基底上，在第一區域中具有多個接觸窗開口。接觸窗開口暴露出基底和蝕刻停止層。接觸窗填入接觸窗開口，包覆所述凹槽的頂角，而與基底電性連接。 The memory component of the present invention includes a substrate, a plurality of first wires, and an etch stop a stop layer, a dielectric layer, and a plurality of contact windows. The substrate has a plurality of first regions and a plurality of second regions, the first regions and the second regions being staggered along the first direction. The first wire is embedded in the substrate and extends in the first direction. The first wire includes a conductive layer and a cap layer on the conductive layer, and the upper surface of the cap layer has a groove. The etch stop layer is on the substrate and on the cap layer and is filled in the recess. The dielectric layer is on the substrate and has a plurality of contact openings in the first region. The contact window opening exposes the substrate and the etch stop layer. The contact window fills the contact window opening and covers the top corner of the groove to be electrically connected to the substrate.
本發明的記憶體元件包括多個第一導線、介電層、蝕刻停止層以及多個接觸窗。第一導線做為多數個字元線，分別沿第一方向延伸，埋入於基底中，第一導線包括導電層和位於導電層上的蓋層。介電層位於基底上。蝕刻停止層位於蓋層與介電層之間以及介電層與基底之間。接觸窗穿過介電層與蝕刻停止層。接觸窗與基底的上表面以及蓋層所裸露的基底的側壁電性連接。此外，蝕刻停止層與接觸窗的下側壁接觸。 The memory device of the present invention includes a plurality of first leads, a dielectric layer, an etch stop layer, and a plurality of contact windows. The first wire is formed as a plurality of word lines extending in the first direction and buried in the substrate. The first wire includes a conductive layer and a cap layer on the conductive layer. The dielectric layer is on the substrate. The etch stop layer is between the cap layer and the dielectric layer and between the dielectric layer and the substrate. The contact window passes through the dielectric layer and the etch stop layer. The contact window is electrically connected to the upper surface of the substrate and the sidewall of the exposed substrate of the cap layer. Further, the etch stop layer is in contact with the lower sidewall of the contact window.
本發明的記憶體元件的製造方法包括：提供具有多個第一區域和多個第二區域的基底，其中第一區域和第二區域沿第一方向交錯排列。在基底中形成多個沿第一方向延伸的第一導線。第一導線包括導電層和位於導電層上的蓋層。移除部分蓋層，以在蓋層的上表面形成凹槽。形成蝕刻停止層，蝕刻停止層至少覆蓋蓋層並填入凹槽。形成介電層，在第一區域中的介電層覆蓋第一導線以及基底。在第一區域中的介電層中形成多個開口，開口 暴露出蝕刻停止層的上表面。對開口進行蝕刻，形成多個接觸窗開口，接觸窗開口暴露出基底的上表面以及凹槽。形成多個接觸窗，接觸窗填入接觸窗開口並與基底電性連接。 A method of fabricating a memory device of the present invention includes providing a substrate having a plurality of first regions and a plurality of second regions, wherein the first regions and the second regions are staggered in a first direction. A plurality of first wires extending in the first direction are formed in the substrate. The first wire includes a conductive layer and a cap layer on the conductive layer. A portion of the cover layer is removed to form a groove on the upper surface of the cover layer. An etch stop layer is formed, and the etch stop layer covers at least the cap layer and fills the recess. A dielectric layer is formed, the dielectric layer in the first region covering the first wire and the substrate. Forming a plurality of openings in the dielectric layer in the first region, the openings The upper surface of the etch stop layer is exposed. The opening is etched to form a plurality of contact openings that expose the upper surface of the substrate and the recess. A plurality of contact windows are formed, and the contact window fills the contact window opening and is electrically connected to the substrate.
在本發明的一些實施例中，在第一導線的蓋層上形成第一蝕刻停止層，其中第一蝕刻停止層的材料和蓋層的材料不同。因此，第一蝕刻停止層和蓋層之間有一蝕刻選擇比，可以在形成接觸窗開口的時候，保護下方的蓋層以及導電層。 In some embodiments of the invention, a first etch stop layer is formed over the cap layer of the first wire, wherein the material of the first etch stop layer and the material of the cap layer are different. Therefore, there is an etching selectivity ratio between the first etch stop layer and the cap layer, and the underlying cap layer and the conductive layer can be protected when the contact opening is formed.
在本發明的一些實施例中，在開口中形成覆蓋開口的底部和側壁的保護層。藉由設置此保護層，可更進一步在形成接觸窗開口的時候，保護介電層、蓋層以及導電層，提升製程裕度。 In some embodiments of the invention, a protective layer covering the bottom and sidewalls of the opening is formed in the opening. By providing the protective layer, the dielectric layer, the cap layer and the conductive layer can be further protected when the contact opening is formed, thereby increasing the process margin.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
100‧‧‧基底 100‧‧‧Base
200‧‧‧第一導線 200‧‧‧First wire
210、910、910a、911、911a、912、912a、913、913a、914、914a‧‧‧導電層 210, 910, 910a, 911, 911a, 912, 912a, 913, 913a, 914, 914a‧‧‧ conductive layer
220‧‧‧蓋層 220‧‧‧ cover
230‧‧‧凹槽 230‧‧‧ Groove
230a‧‧‧頂角 230a‧‧‧Top angle
300‧‧‧第一隔離結構 300‧‧‧First isolation structure
310、410‧‧‧氧化層 310, 410‧‧‧ oxide layer
320、420‧‧‧高密度氧化層 320, 420‧‧‧ high-density oxide layer
400‧‧‧第二隔離結構 400‧‧‧Second isolation structure
500、600‧‧‧蝕刻停止材料層 500, 600‧‧‧ etching stop material layer
600a‧‧‧第一蝕刻停止層 600a‧‧‧First etch stop layer
604‧‧‧第二蝕刻停止層 604‧‧‧Second etch stop layer
602‧‧‧間隙 602‧‧‧ gap
700‧‧‧罩幕層 700‧‧‧ Cover layer
800‧‧‧圖案化光阻層 800‧‧‧ patterned photoresist layer
900‧‧‧第二導線 900‧‧‧second wire
902‧‧‧間隙 902‧‧‧ gap
920、920a‧‧‧蓋層 920, 920a‧‧‧ cover
1000‧‧‧介電層 1000‧‧‧ dielectric layer
1100‧‧‧開口 1100‧‧‧ openings
1100a‧‧‧接觸窗開口 1100a‧‧‧Contact window opening
1200‧‧‧中間層 1200‧‧‧ middle layer
1200a‧‧‧圖案化中間層 1200a‧‧‧ patterned intermediate layer
1300‧‧‧硬罩幕層 1300‧‧‧hard mask layer
1300a‧‧‧圖案化硬罩幕層 1300a‧‧‧ patterned hard mask layer
1400、1400a‧‧‧保護層 1400, 1400a‧‧ ‧ protective layer
1500‧‧‧導體層 1500‧‧‧ conductor layer
1500a‧‧‧接觸窗 1500a‧‧‧Contact window
R1‧‧‧第一區域 R1‧‧‧ first area
R2‧‧‧第二區域 R2‧‧‧ second area
D1‧‧‧第一方向 D1‧‧‧ first direction
D2‧‧‧第二方向 D2‧‧‧ second direction
dp1‧‧‧深度 Dp1‧‧ depth
圖1A至圖13A為圖1D至圖13D中線A-A’的剖面示意圖。 1A to 13A are schematic cross-sectional views of a line A-A' of Figs. 1D to 13D.
圖1B至圖13B為圖1D至圖13D中線B-B’的剖面示意圖。 1B to 13B are schematic cross-sectional views of line B-B' of Figs. 1D to 13D.
圖1C至圖13C為圖1D至圖13D中線C-C’的剖面示意圖。 1C to 13C are schematic cross-sectional views of line C-C' of Figs. 1D to 13D.
圖1D至圖13D為依照本揭露一些實施例的一種記憶體元件的製造過程的各種階段的上視圖。 1D-13D are top views of various stages of a fabrication process of a memory device in accordance with some embodiments of the present disclosure.
關於本發明記憶體元件的製造方法的實施例，請先參照圖1D，提供基底100。基底100具有多個第一區域R1和多個第二區域R2。第一區域R1和第二區域R2沿第一方向D1交錯排列。在一些實施例中，基底100為半導體材料，例如是矽或其他合適的材料。在一些實施例中，基底100為絕緣層上有矽(silicon on insulating layer，SOI)基底。在一些實施例中，基底100可以是合適的化合物半導體，例如是氮化鎵、砷化鎵或磷化銦。在一些實施例中，基底100可以是合適的合金半導體，例如是矽鍺、矽錫、砷化鋁鎵或砷磷化鎵。 Regarding an embodiment of the method of fabricating the memory device of the present invention, first referring to FIG. 1D, a substrate 100 is provided. The substrate 100 has a plurality of first regions R1 and a plurality of second regions R2. The first region R1 and the second region R2 are staggered in the first direction D1. In some embodiments, substrate 100 is a semiconductor material such as germanium or other suitable material. In some embodiments, substrate 100 is a silicon on insulating layer (SOI) substrate on an insulating layer. In some embodiments, substrate 100 can be a suitable compound semiconductor, such as gallium nitride, gallium arsenide, or indium phosphide. In some embodiments, substrate 100 can be a suitable alloy semiconductor such as germanium, antimony tin, aluminum gallium arsenide or gallium arsenide gallium phosphate.
請參照圖1A至圖1D，基底100中已形成多個第一隔離結構300以及多個第二隔離結構400。第一隔離結構300埋入於基底100中，並沿第一方向D1沿伸。第二隔離結構400埋入於兩相鄰第一隔離結構300之間的第一區域R1的基底100中。第一隔離結構300與第二隔離結構400可以分別為單層、雙層或多層。在第一隔離結構300與第二隔離結構400為雙層或是多層的實施例中，可以依需求使用相同或是相異的方法來形成，使所形成的各層隔離結構具有想要的特性。在一些實施例中，第一隔離結構300包括氧化層310和位於氧化層310上的高密度氧化層320；第二隔離結構400可以包括氧化層410和位於氧化層410上的高密度氧化層420。氧化層310、410和高密度氧化層320、420的材料例如是氧化矽。在一些實施例中，第一隔離結構300以及第二隔離結構400可以藉由淺溝渠隔離法來形成。更具體說，可以先在基底 100中形成溝渠，再於溝渠中填入氧化層與高密度氧化層。在一些實施例中，形成氧化層310、410的方法例如是使用電漿輔助化學氣相沈積法(Plasma-enhanced chemical vapor deposition，PECVD)在溝渠中填入氧化層；形成高密度氧化層320、420的方法例如是使用高密度電漿化學氣相沉積法(High-density plasma chemical vapor deposition，HDPCVD)在氧化層310、410上形成高密度氧化層。 Referring to FIGS. 1A through 1D , a plurality of first isolation structures 300 and a plurality of second isolation structures 400 have been formed in the substrate 100 . The first isolation structure 300 is buried in the substrate 100 and extends along the first direction D1. The second isolation structure 400 is buried in the substrate 100 of the first region R1 between the two adjacent first isolation structures 300. The first isolation structure 300 and the second isolation structure 400 may be a single layer, a double layer or a plurality of layers, respectively. In the embodiment in which the first isolation structure 300 and the second isolation structure 400 are double-layered or multi-layered, the same or different methods may be used as needed to make the formed isolation structures have desired characteristics. In some embodiments, the first isolation structure 300 includes an oxide layer 310 and a high density oxide layer 320 on the oxide layer 310; the second isolation structure 400 may include an oxide layer 410 and a high density oxide layer 420 on the oxide layer 410. . The material of the oxide layers 310, 410 and the high-density oxide layers 320, 420 is, for example, ruthenium oxide. In some embodiments, the first isolation structure 300 and the second isolation structure 400 may be formed by shallow trench isolation. More specifically, it can be on the substrate first. A trench is formed in 100, and an oxide layer and a high-density oxide layer are filled in the trench. In some embodiments, the method of forming the oxide layers 310, 410 is, for example, using a plasma-assisted chemical vapor deposition (PECVD) to fill an oxide layer in the trench; forming a high-density oxide layer 320, The method of 420 is, for example, forming a high-density oxide layer on the oxide layers 310, 410 using high-density plasma chemical vapor deposition (HDPCVD).
接著，在基底100上形成蝕刻停止材料層500。在一些實施例中，蝕刻停止材料層500為條狀，其沿著第一方向D1延伸，覆蓋第一隔離結構300及其兩側的部分基底100表面，並且覆蓋相鄰兩個第一隔離結構300之間的部分第二個隔離結構400及部分的基底100表面。蝕刻停止材料層500的材料例如是氧化矽，形成的方法例如是化學氣相沉積法，厚度例如是14nm至24nm之間。 Next, an etch stop material layer 500 is formed on the substrate 100. In some embodiments, the etch stop material layer 500 is strip-shaped extending along the first direction D1, covering the surface of the first isolation structure 300 and portions of the substrate 100 on both sides thereof, and covering adjacent two first isolation structures A portion of the second isolation structure 400 between the 300 and a portion of the surface of the substrate 100. The material of the etch stop material layer 500 is, for example, ruthenium oxide, and the formation method is, for example, chemical vapor deposition, and the thickness is, for example, between 14 nm and 24 nm.
在未被蝕刻停止材料層500覆蓋的各個基底100中均形成導電層210，各導電層210位於第一隔離結構300的兩側，並沿第一方向D1沿伸，且穿過第二隔離結構400。導電層210的形成方法例如是在基底100中形成沿著第一方向D1延伸的溝槽(未繪示)，再於溝槽中形成導電材料層。導電材料層覆蓋基底100表面，並且填入於溝槽中。導電材料層的材料包括金屬、金屬矽化物或其組合。導電材料層的材料例如是鎢(tungsten)或其他合適的材料。之後，進行化學機械研磨法及/或回蝕刻法，移除基底100上 部分的導電材料層以及溝槽中部分的導電材料層，以在溝槽中形成導電層210。導電層210的上表面低於基底100的表面。 Conductive layers 210 are formed in each of the substrates 100 not covered by the etch stop material layer 500. Each of the conductive layers 210 is located on both sides of the first isolation structure 300 and extends along the first direction D1 and passes through the second isolation structure. 400. The method for forming the conductive layer 210 is, for example, forming a trench (not shown) extending in the first direction D1 in the substrate 100, and forming a conductive material layer in the trench. A layer of conductive material covers the surface of the substrate 100 and is filled in the trench. The material of the layer of conductive material includes a metal, a metal halide, or a combination thereof. The material of the layer of electrically conductive material is, for example, tungsten or other suitable material. Thereafter, a chemical mechanical polishing method and/or an etch back method is performed to remove the substrate 100. A portion of the layer of conductive material and a portion of the layer of conductive material in the trench to form a conductive layer 210 in the trench. The upper surface of the conductive layer 210 is lower than the surface of the substrate 100.
接著，在基底100上形成蓋材料層220a。蓋材料層220a覆蓋蝕刻停止材料層500並且覆蓋導電層210。蓋材料層220a的材料包括介電材料。蓋材料層220a的材料與第一隔離結構300不同，且與第二隔離結構400不同。在第一隔離結構300材料為氧化矽的實施例中，蓋材料層220a的材料例如是氮化矽、氮氧化矽或其他合適的材料。蓋材料層220a的形成方法例如是化學氣相沉積法。 Next, a cap material layer 220a is formed on the substrate 100. The cover material layer 220a covers the etch stop material layer 500 and covers the conductive layer 210. The material of the cover material layer 220a includes a dielectric material. The material of the cover material layer 220a is different from the first isolation structure 300 and is different from the second isolation structure 400. In embodiments where the first isolation structure 300 material is yttria, the material of the cover material layer 220a is, for example, tantalum nitride, hafnium oxynitride or other suitable material. The method of forming the cap material layer 220a is, for example, a chemical vapor deposition method.
請繼續參照圖2A至圖2D，移除部分蓋材料層220a，留下溝槽中的蓋層220。蓋層220的上表面低於基底100的表面，而形成凹槽230。凹槽230的深度dp1(基底100的上表面以及蓋層220的上表面的高度差)的範圍例如是在5奈米至15奈米之間。在一些實例中，移除部分蓋材料層220a的方法例如是以蝕刻停止材料層500為停止層，先進行化學機械研磨製程，再進行回蝕刻製程，以移除蓋材料層220a。在另一些實例中，移除部分蓋材料層220a的方法例如是以蝕刻停止材料層500為停止層，進行回蝕刻製程，以移除蓋材料層220a。 With continued reference to FIGS. 2A-2D, a portion of the cover material layer 220a is removed leaving the cap layer 220 in the trench. The upper surface of the cap layer 220 is lower than the surface of the substrate 100 to form the recess 230. The depth dp1 of the groove 230 (the difference in height between the upper surface of the substrate 100 and the upper surface of the cap layer 220) is, for example, between 5 nm and 15 nm. In some examples, the method of removing a portion of the capping material layer 220a is, for example, using the etch stop material layer 500 as a stop layer, first performing a chemical mechanical polishing process, and then performing an etch back process to remove the capping material layer 220a. In other examples, the method of removing a portion of the capping material layer 220a is performed by, for example, etching the material layer 500 as a stop layer, and performing an etch back process to remove the capping material layer 220a.
至此，完成第一導線200。第一導線200包括導電層210以及位於其上方的蓋層220。第一導線200分別位於第一隔離結構300的兩側，並沿第一方向D1沿伸，且穿過第二隔離結構400。在一些實施例中，第一導線200例如是做為字元線。 At this point, the first wire 200 is completed. The first wire 200 includes a conductive layer 210 and a cap layer 220 positioned thereover. The first wires 200 are respectively located at two sides of the first isolation structure 300 and extend along the first direction D1 and pass through the second isolation structure 400. In some embodiments, the first wire 200 is, for example, a word line.
請參照圖3A至圖3D，在基底100上形成另一層蝕刻停止材料層，其與上述蝕刻停止材料層500共同組成蝕刻停止材料層600。另一層蝕刻停止材料層的材料可以與上述蝕刻停止材料層500相同或相異，但與蓋層220的材料不同。另一層蝕刻停止材料層的形成方法例如是以四乙氧基矽烷(tetraethyl orthosilicate，TEOS)為氣體源，進行化學氣相沉積製程。蝕刻停止層600的材料例如是氧化矽或其他合適的材料，或其組合。蝕刻停止材料層600填入凹槽230並覆蓋基底100、第一導線200、第一隔離結構300以及第二隔離結構400。蝕刻停止材料層600在凹槽230中的厚度範圍例如是在5nm至15nm之間且在基底100上的厚度範圍例如是在11nm至21nm之間。 Referring to FIGS. 3A through 3D, another layer of etch stop material is formed on the substrate 100, which together with the etch stop material layer 500 described above constitutes an etch stop material layer 600. The material of the other etch stop material layer may be the same as or different from the etch stop material layer 500 described above, but different from the material of the cap layer 220. Another method of forming the etch stop material layer is a chemical vapor deposition process using, for example, tetraethyl orthosilicate (TEOS) as a gas source. The material of the etch stop layer 600 is, for example, yttrium oxide or other suitable material, or a combination thereof. The etch stop material layer 600 fills the recess 230 and covers the substrate 100, the first conductive line 200, the first isolation structure 300, and the second isolation structure 400. The thickness of the etch stop material layer 600 in the recess 230 is, for example, between 5 nm and 15 nm and the thickness on the substrate 100 is, for example, between 11 nm and 21 nm.
請參照圖4A至圖4D，接著，圖案化蝕刻停止材料層600，以形成第一蝕刻停止層600a。第一蝕刻停止層600a沿著第一方向D1延伸。相鄰的兩個第一蝕刻停止層600a之間的間隙602暴露出相鄰第一導線200之間的高密度氧化層420(第二隔離結構400)以及基底100。圖案化蝕刻停止材料層600的方法例如是微影與蝕刻製程。蝕刻製程可以採用非等向性蝕刻，例如是電漿蝕刻。在移除部分的蝕刻停止材料層600時，也可能會同時移除部分的蓋層220、基底100以及第二隔離結構400，因此，間隙602也會暴露出部分蓋層220(第一隔離結構300)。 Referring to FIGS. 4A through 4D, next, the etch stop material layer 600 is patterned to form a first etch stop layer 600a. The first etch stop layer 600a extends along the first direction D1. A gap 602 between adjacent two first etch stop layers 600a exposes the high density oxide layer 420 (second isolation structure 400) and the substrate 100 between adjacent first wires 200. The method of patterning the etch stop material layer 600 is, for example, a lithography and etching process. The etching process can be an anisotropic etch, such as a plasma etch. When a portion of the etch stop material layer 600 is removed, a portion of the cap layer 220, the substrate 100, and the second isolation structure 400 may also be removed at the same time. Therefore, the gap 602 may also expose a portion of the cap layer 220 (the first isolation structure) 300).
請參照圖5A至圖5D，在基底100上形成導電層910和覆蓋導電層910的蓋層920。導電層910覆蓋間隙602所裸露的高 密度氧化層420(第二隔離結構400)、蓋層220(第一隔離結構300)以及基底100。導電層910可以是由單一導電材料層所構成；或者，導電層910可以由多層導電材料層所構成。在此實施例中，導電層910可以與其他區域的電晶體的製程整合。舉例來說，導電層910可以由導電層911、導電層912、導電層913以及導電層914所構成，其中導電層911的材料為鈦(Ti)、導電層912的材料為氮化鈦(TiN)、導電層913的材料為矽化鎢(WSi)、導電層914的材料為鎢，但本發明不限於此，其他合適的導電材料也可使用。導電層910可以藉由物理氣相沉積法或是化學氣相沉積法來形成。在一些實施例中，蓋層920的材料與停止材料層600不同。蓋層920的材料例如是氮化矽或氮氧化矽，形成的方法例如是化學氣相沉積法。 Referring to FIGS. 5A through 5D, a conductive layer 910 and a cap layer 920 covering the conductive layer 910 are formed on the substrate 100. The conductive layer 910 covers the exposed height of the gap 602 A density oxide layer 420 (second isolation structure 400), a cap layer 220 (first isolation structure 300), and a substrate 100. The conductive layer 910 may be composed of a single layer of conductive material; alternatively, the conductive layer 910 may be composed of a plurality of layers of conductive material. In this embodiment, the conductive layer 910 can be integrated with the process of transistors in other regions. For example, the conductive layer 910 may be composed of a conductive layer 911, a conductive layer 912, a conductive layer 913, and a conductive layer 914. The material of the conductive layer 911 is titanium (Ti), and the material of the conductive layer 912 is titanium nitride (TiN). The material of the conductive layer 913 is tungsten germanium (WSi), and the material of the conductive layer 914 is tungsten. However, the present invention is not limited thereto, and other suitable conductive materials may also be used. The conductive layer 910 can be formed by physical vapor deposition or chemical vapor deposition. In some embodiments, the material of the cap layer 920 is different than the stop material layer 600. The material of the cap layer 920 is, for example, tantalum nitride or hafnium oxynitride, and the formation method is, for example, chemical vapor deposition.
請參照圖6A至圖6D，圖案化蓋層920與導電層910，以形成第二導線900。在一些實施例中，第二導線900例如是位元線。第二導線900沿第二方向D2延伸，並且覆蓋第二區域R2上的第一蝕刻停止層600a、蓋層220(第一隔離結構300)以及基底100，其中第二方向D2和第一方向D1不同。在一些實施例中，第二方向D2和第一方向D1互相垂直。相鄰兩個第二導線900之間的間隙902裸露出第一區域R1上的第一蝕刻停止層600a、高密度氧化層420(第二隔離結構400)、蓋層220(第一隔離結構300)以及基底100。圖案化蓋層920與導電層910可以進行微影與蝕刻製程來實施。蝕刻製程例如是非等向性蝕刻製程。在一些 實施例中，第二導線900包括蓋層920a與導電層910a，其中導電層910a包括導電層911a、導電層912a、導電層913a、導電層914a。在另一些實施例中，在圖案化蓋層920與導電層910時，除了形成第二導線900之外，在基底100的另一區域還同時形成了閘極結構(未繪示)。閘極結構包括閘極以及蓋層。閘極結構的閘極是由導電層911、導電層912、導電層913以及導電層914圖案化後所形成所構成。閘極結構的蓋層位於閘極上，其是由蓋層920圖案化後所形成。 Referring to FIGS. 6A-6D, the cap layer 920 and the conductive layer 910 are patterned to form a second wire 900. In some embodiments, the second wire 900 is, for example, a bit line. The second wire 900 extends in the second direction D2 and covers the first etch stop layer 600a, the cap layer 220 (first isolation structure 300), and the substrate 100 on the second region R2, wherein the second direction D2 and the first direction D1 different. In some embodiments, the second direction D2 and the first direction D1 are perpendicular to each other. The gap 902 between the adjacent two second wires 900 exposes the first etch stop layer 600a on the first region R1, the high-density oxide layer 420 (the second isolation structure 400), and the cap layer 220 (the first isolation structure 300) And the substrate 100. The patterned cap layer 920 and the conductive layer 910 can be implemented by a photolithography and etching process. The etching process is, for example, an anisotropic etching process. In some In an embodiment, the second wire 900 includes a cap layer 920a and a conductive layer 910a, wherein the conductive layer 910a includes a conductive layer 911a, a conductive layer 912a, a conductive layer 913a, and a conductive layer 914a. In other embodiments, in the case of patterning the cap layer 920 and the conductive layer 910, in addition to forming the second wire 900, a gate structure (not shown) is simultaneously formed in another region of the substrate 100. The gate structure includes a gate and a cap layer. The gate of the gate structure is formed by patterning the conductive layer 911, the conductive layer 912, the conductive layer 913, and the conductive layer 914. The cap layer of the gate structure is located on the gate, which is formed by patterning the cap layer 920.
請參照圖7A至圖7D，在基底100、蓋層220、高密度氧化層420(第二隔離結構400)、蓋層920a以及第一蝕刻停止層600a上形成第二蝕刻停止層604。第二蝕刻停止層604還覆蓋第二導線900的側壁。之後，於蝕刻停止層604上形成介電層1000。介電層1000覆蓋第一區域R1，並且填入第二導線900之間的間隙902。第二蝕刻停止層604的材料與介電層1000的材料不同，且與第一蝕刻停止層600a不同。第二蝕刻停止層604的材料例如是氮化矽或氮氧化矽，形成的方法例如是以化學氣相沉積法。介電層1000的材料例如是氧化矽、旋塗式玻璃(SOG)、其他合適的材料，或其組合。形成介電層1000的方法例如是以化學氣相沉積法或是旋塗法。在形成介電層1000之後，還可進一步以第二蝕刻停止層604為停止層，進行化學機械研磨製程，以使介電層100具有平坦的表面。在一些實施例中，介電層1000的上表面和第二導線900上的第二蝕刻停止層604的上表面共平面，但本發明不 限於此。 Referring to FIGS. 7A-7D, a second etch stop layer 604 is formed over the substrate 100, the cap layer 220, the high density oxide layer 420 (second isolation structure 400), the cap layer 920a, and the first etch stop layer 600a. The second etch stop layer 604 also covers the sidewalls of the second wire 900. Thereafter, a dielectric layer 1000 is formed on the etch stop layer 604. The dielectric layer 1000 covers the first region R1 and fills the gap 902 between the second wires 900. The material of the second etch stop layer 604 is different from the material of the dielectric layer 1000 and is different from the first etch stop layer 600a. The material of the second etch stop layer 604 is, for example, tantalum nitride or hafnium oxynitride, and is formed by, for example, chemical vapor deposition. The material of the dielectric layer 1000 is, for example, yttria, spin on glass (SOG), other suitable materials, or a combination thereof. The method of forming the dielectric layer 1000 is, for example, a chemical vapor deposition method or a spin coating method. After the dielectric layer 1000 is formed, the second etch stop layer 604 may be further used as a stop layer, and a chemical mechanical polishing process may be performed to make the dielectric layer 100 have a flat surface. In some embodiments, the upper surface of the dielectric layer 1000 and the upper surface of the second etch stop layer 604 on the second wire 900 are coplanar, but the present invention does not Limited to this.
請參照圖8A至圖8D，在介電層1000上形成中間層1200和硬罩幕層1300。在一些實施例中，中間層1200的材料與介電層1000不同，例如中間層1200的材料是氧化矽或其他合適的材料，形成的方法例如是化學氣相沉積法。硬罩幕層1300的材料例如是多晶矽或其他合適的材料，形成的方法例如是化學氣相沉積法。 Referring to FIGS. 8A through 8D, an intermediate layer 1200 and a hard mask layer 1300 are formed on the dielectric layer 1000. In some embodiments, the material of the intermediate layer 1200 is different from the dielectric layer 1000. For example, the material of the intermediate layer 1200 is yttria or other suitable material, and the forming method is, for example, chemical vapor deposition. The material of the hard mask layer 1300 is, for example, polycrystalline germanium or other suitable material, and the method of formation is, for example, chemical vapor deposition.
請參照圖9A至圖9D，將硬罩幕層1300和中間層1200圖案化，以形成圖案化硬罩幕層1300a和圖案化中間層1200a。圖案化硬罩幕層1300a和圖案化中間層1200a例如是沿著第一方向D1延伸的條狀物。之後，以圖案化中間層1200a和圖案化硬罩幕層1300a為罩幕，對介電層1000進行非等向性蝕刻，以形成開口1100。在第一區域R1中，開口1100的底部裸露出第一蝕刻停止層600a。此外，在一些實施例中，由於相鄰兩個圖案化硬罩幕層1300a之間的間隙例如是沿著第一方向D1延伸且跨過第一區域R1與第二區域R2的溝渠，因此，在第二區域R2中，開口1100的底部裸露出蓋層920a。 Referring to FIGS. 9A-9D, the hard mask layer 1300 and the intermediate layer 1200 are patterned to form a patterned hard mask layer 1300a and a patterned intermediate layer 1200a. The patterned hard mask layer 1300a and the patterned intermediate layer 1200a are, for example, strips that extend along the first direction D1. Thereafter, the dielectric layer 1000 is anisotropically etched to form the opening 1100 with the patterned intermediate layer 1200a and the patterned hard mask layer 1300a as masks. In the first region R1, the bottom of the opening 1100 exposes the first etch stop layer 600a. Moreover, in some embodiments, since the gap between the adjacent two patterned hard mask layers 1300a is, for example, a trench extending along the first direction D1 and spanning the first region R1 and the second region R2, In the second region R2, the bottom of the opening 1100 exposes the cap layer 920a.
對介電層1000進行非等向性蝕刻製程時，可以多階段蝕刻製程來進行。在一些實施例中，進行第一階段蝕刻製程，是先以第二蝕刻停止層604為蝕刻停止層，選擇對於介電層1000與第二蝕刻停止層604之間具有良好蝕刻選擇比且對於介電層1000與蓋層920a之間具有高蝕刻選擇比的蝕刻劑，來移除圖案化硬罩幕層1300a所裸露的介電層1000。進行第二階段蝕刻製程，是移除 圖案化硬罩幕層1300a所裸露的第二蝕刻停止層604，以形成開口1100。在進行第二階段蝕刻製程時，在第一區域R1中，藉由第一蝕刻停止層600a的材料與第二蝕刻停止層604的材料不同，選擇對於第二蝕刻停止層604與第一蝕刻停止層600a之間具有高蝕刻選擇比的蝕刻劑，因此，在蝕刻第二蝕刻停止層604時可以第一蝕刻停止層600a做為蝕刻停止層，以避免下方的蓋層220被蝕刻或被蝕穿。換言之，在進行第二階段的蝕刻製程之後，在第一區域R1中，開口1100的底部裸露出第一蝕刻停止層600a，而不會裸露出蓋層220或甚至裸露出蓋層220下方的導電層210。此外，在一些實施例中，在進行第二階段蝕刻製程時，當所選擇的蝕刻劑對於第二蝕刻停止層604與蓋層920a之間沒有足夠高的蝕刻選擇比時，在第二區域R2中未被圖案化硬罩幕層1300a覆蓋的部分蓋層920a也會被蝕刻。由於蝕刻第二蝕刻停止層604的厚度相當薄，其遠比蓋層920a薄，因此，在第二區域R2的蓋層920a只有少許被蝕刻，而不會被蝕穿，因此，在第一區域R1的開口1100的深度較深；而在第二區域R2的開口1100的深度較淺。 When the dielectric layer 1000 is subjected to an anisotropic etching process, it can be performed by a multi-stage etching process. In some embodiments, the first-stage etching process is performed by first using the second etch stop layer 604 as an etch stop layer, and selecting a good etch selectivity ratio between the dielectric layer 1000 and the second etch stop layer 604 and An etchant having a high etch selectivity between the electrical layer 1000 and the cap layer 920a is used to remove the dielectric layer 1000 exposed by the patterned hard mask layer 1300a. Perform the second stage etching process, which is removed A second etch stop layer 604 exposed by the hard mask layer 1300a is patterned to form an opening 1100. During the second-stage etching process, in the first region R1, the material of the first etch stop layer 600a is different from the material of the second etch stop layer 604, and the second etch stop layer 604 and the first etch stop are selected. An etchant having a high etch selectivity between layers 600a, therefore, the first etch stop layer 600a can be used as an etch stop layer when etching the second etch stop layer 604 to prevent the underlying cap layer 220 from being etched or etched through. . In other words, after performing the etching process of the second stage, in the first region R1, the bottom of the opening 1100 exposes the first etch stop layer 600a without exposing the conductive layer under the cap layer 220 or even the exposed cap layer 220. Layer 210. In addition, in some embodiments, when the second stage etching process is performed, when the selected etchant does not have a sufficiently high etching selectivity ratio between the second etch stop layer 604 and the cap layer 920a, in the second region R2 A portion of the cap layer 920a that is not covered by the patterned hard mask layer 1300a is also etched. Since the thickness of the etched second etch stop layer 604 is relatively thin, which is much thinner than the cap layer 920a, the cap layer 920a in the second region R2 is only slightly etched without being etched, and therefore, in the first region The opening 1100 of R1 has a deeper depth; and the opening 1100 of the second region R2 has a shallower depth.
請參照圖10A至圖10D，在基底100上方形成保護層1400。保護層1400覆蓋開口1100的底部和側壁以及圖案化硬罩幕層1300a。保護層1400的材料與介電層1000不同，且與第一蝕刻停止層600a不同。保護層1400的材料例如是氮化矽、氮氧化矽或其他合適的材料。形成保護層1400的方法例如是以化學氣相沉積法。保護層1400的厚度範圍例如是3奈米至10奈米之間。 Referring to FIGS. 10A through 10D, a protective layer 1400 is formed over the substrate 100. The protective layer 1400 covers the bottom and sidewalls of the opening 1100 and the patterned hard mask layer 1300a. The material of the protective layer 1400 is different from the dielectric layer 1000 and is different from the first etch stop layer 600a. The material of the protective layer 1400 is, for example, tantalum nitride, hafnium oxynitride or other suitable material. The method of forming the protective layer 1400 is, for example, a chemical vapor deposition method. The thickness of the protective layer 1400 ranges, for example, from 3 nm to 10 nm.
請參照圖11A至圖11D，對保護層1400進行非等向性蝕刻製程，以在開口1100的側壁形成保護層1400a。若所形成的開口1100的位置發生偏移或尺寸過大時，開口1100的底面或側壁裸露的材料層(例如是高密度氧化層420)可能與後續欲移除的第一蝕刻停止層600a的材料相同或具有相似的蝕刻特性時，保護層1400a可以覆蓋開口1100的側壁與開口1100的部分底面，以在後續蝕刻製程中提供足夠的保護。 Referring to FIGS. 11A-11D , the protective layer 1400 is anisotropically etched to form a protective layer 1400a on the sidewall of the opening 1100 . If the position of the formed opening 1100 is offset or oversized, the exposed material layer of the bottom surface or sidewall of the opening 1100 (eg, the high density oxide layer 420) may be related to the material of the first etch stop layer 600a to be subsequently removed. When the same or have similar etch characteristics, the protective layer 1400a may cover the sidewalls of the opening 1100 and a portion of the bottom surface of the opening 1100 to provide sufficient protection during subsequent etching processes.
請參照圖11A至圖11D以及圖12A至圖12D，移除開口1100底部所裸露的第一蝕刻停止層600a，以形成多個接觸窗開口1100a。接觸窗開口1100a暴露出基底100的上表面以及部分凹槽230側壁所裸露的基底100。移除開口1100底部所裸露的第一蝕刻停止層600a的方法例如是進行選擇性蝕刻製程。在本發明中，由於第一蝕刻停止層600a的材料與蓋層220不同，因此第一蝕刻停止層600a與蓋層220之間有足夠的蝕刻選擇比，因此，第一蝕刻停止層600a可以在形成接觸窗開口1100a時，保護下方的蓋層220以及導電層210。 Referring to FIGS. 11A-11D and FIGS. 12A-12D, the first etch stop layer 600a exposed at the bottom of the opening 1100 is removed to form a plurality of contact opening 1100a. The contact window opening 1100a exposes the upper surface of the substrate 100 and the exposed substrate 100 of the sidewalls of the partial recess 230. The method of removing the exposed first etch stop layer 600a at the bottom of the opening 1100 is, for example, a selective etching process. In the present invention, since the material of the first etch stop layer 600a is different from the cap layer 220, there is a sufficient etching selectivity ratio between the first etch stop layer 600a and the cap layer 220. Therefore, the first etch stop layer 600a may be When the contact opening 1100a is formed, the underlying cap layer 220 and the conductive layer 210 are protected.
請繼續參照圖12A至圖12D，在圖案化硬罩幕層1300a上以及接觸窗開口1100a中形成導體層1500。導體層1500的材料例如是摻雜多晶矽或金屬，形成的方法例如是化學氣相沉積法或是物理氣相沉積法。 Referring to FIGS. 12A through 12D, a conductor layer 1500 is formed on the patterned hard mask layer 1300a and in the contact opening 1100a. The material of the conductor layer 1500 is, for example, doped polysilicon or metal, and the formation method is, for example, chemical vapor deposition or physical vapor deposition.
請繼續參照圖13A至圖13D，以圖案化中間層1200a為停止層，進行化學機械研磨製程，移除圖案化硬罩幕層1300a以 及其上方的導體層1500，以在接觸窗開口1100a中形成接觸窗1500a。接觸窗1500a與基底100電性連接。在形成接觸窗1500a之後，還包括形成與接觸窗1500a連接的電容器等製程，於此不再贅述。 Referring to FIG. 13A to FIG. 13D, the intermediate layer 1200a is patterned as a stop layer, and a chemical mechanical polishing process is performed to remove the patterned hard mask layer 1300a. And a conductor layer 1500 above it to form a contact window 1500a in the contact opening 1100a. The contact window 1500a is electrically connected to the substrate 100. After the contact window 1500a is formed, a process of forming a capacitor connected to the contact window 1500a is also included, and details are not described herein.
在本發明中，請參照圖2A至圖2D以及圖11A至圖11D，在第一導線200的蓋層220上形成凹槽230，之後再於凹槽230中形成第一蝕刻停止層600a。由於第一蝕刻停止層600a的材料和蓋層220的材料不同，因此，在後續形成接觸窗開口1100a時，第一蝕刻停止層600a和蓋層220之間有足夠的蝕刻選擇比，以保護其下方的蓋層220，避免蓋層220被蝕刻，藉此，即使蓋層中有空隙的存在，以本發明之製造方法仍能避免裸露出導電層210，因此可以減少或避免後續形成的接觸窗1500a與導電層210發生短路。 In the present invention, referring to FIGS. 2A to 2D and FIGS. 11A to 11D, a groove 230 is formed on the cap layer 220 of the first wire 200, and then a first etch stop layer 600a is formed in the groove 230. Since the material of the first etch stop layer 600a and the material of the cap layer 220 are different, when the contact opening 1100a is subsequently formed, there is a sufficient etching selectivity ratio between the first etch stop layer 600a and the cap layer 220 to protect it. The lower cap layer 220 prevents the cap layer 220 from being etched, whereby even if there is a void in the cap layer, the manufacturing method of the present invention can avoid the bare conductive layer 210, thereby reducing or avoiding the subsequently formed contact window. 1500a is short-circuited with the conductive layer 210.
再者，在本發明中，請參照圖10A至圖10D以及圖11A至圖11D，在本發明中，在移除第一蝕刻停止層600a之前，先形成覆蓋開口1100的底部和側壁的保護層1400a。藉由設置此保護層1400a，可更進一步在形成接觸窗開口1100a的時候，保護介電層1000、蓋層220以及導電層210，提升製程裕度。 Furthermore, in the present invention, referring to FIGS. 10A to 10D and FIGS. 11A to 11D, in the present invention, a protective layer covering the bottom and side walls of the opening 1100 is formed before the first etch stop layer 600a is removed. 1400a. By providing the protective layer 1400a, the dielectric layer 1000, the cap layer 220, and the conductive layer 210 can be further protected during the formation of the contact opening 1100a to improve the process margin.
請參照圖13A至圖13D，本發明的記憶體元件的接觸窗1500a穿過介電層1000與蝕刻停止層604。接觸窗1500a包覆凹槽230的頂角230a，而與基底100電性連接。換言之，接觸窗1500a與基底100的上表面以及蓋層220所裸露的基底100的側壁電性 連接。接觸窗1500a具有不同高度的兩個底面。更詳細地說，與蓋層220接觸的接觸窗1500a的一底面的高度較低；而與基底100上表面接觸的接觸窗1500a的另一底面的高度較高。在一實施例中，兩個底面的高度差的範圍為5奈米至15奈米。 Referring to FIGS. 13A-13D, the contact window 1500a of the memory device of the present invention passes through the dielectric layer 1000 and the etch stop layer 604. The contact window 1500a covers the top corner 230a of the recess 230 and is electrically connected to the substrate 100. In other words, the contact window 1500a and the upper surface of the substrate 100 and the sidewall of the substrate 100 exposed by the cap layer 220 are electrically connection. The contact window 1500a has two bottom surfaces of different heights. In more detail, the height of one bottom surface of the contact window 1500a in contact with the cap layer 220 is low; and the height of the other bottom surface of the contact window 1500a in contact with the upper surface of the substrate 100 is high. In one embodiment, the height difference between the two bottom surfaces ranges from 5 nanometers to 15 nanometers.
值得一提的是，在一些實施例中，接觸窗1500a的側壁上段及中段被保護層1400a環繞，接觸窗1500a的側壁下段的至少一部分被蝕刻停止層600a覆蓋。另一方面，此外，在另一些實施例中，接觸窗1500a的側壁上段及中段直接被介電層1000環繞，接觸窗1500a的側壁下段的至少一部分直接被蝕刻停止層600a覆蓋。 It is worth mentioning that in some embodiments, the upper and middle sections of the sidewall of the contact window 1500a are surrounded by the protective layer 1400a, and at least a portion of the lower section of the sidewall of the contact window 1500a is covered by the etch stop layer 600a. On the other hand, in addition, in other embodiments, the upper and middle sidewalls of the contact window 1500a are directly surrounded by the dielectric layer 1000, and at least a portion of the lower sidewall of the contact window 1500a is directly covered by the etch stop layer 600a.
綜合以上所述，在本發明中，將第一導線上的蓋層減薄，以形成第一蝕刻停止層，可以在形成接觸窗開口時，保護下方的蓋層以及導電層。另外，在接觸窗開口形成之前，先在開口中形成覆蓋開口的底部和側壁的保護層，可更進一步保護介電層、蓋層以及導電層，提升製程裕度。 In summary, in the present invention, the cap layer on the first wire is thinned to form a first etch stop layer, and the underlying cap layer and the conductive layer can be protected when the contact opening is formed. In addition, before the contact window opening is formed, a protective layer covering the bottom and the sidewall of the opening is formed in the opening, which further protects the dielectric layer, the cap layer and the conductive layer, thereby improving the process margin.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧基底 100‧‧‧Base
200‧‧‧第一導線 200‧‧‧First wire
210‧‧‧導電層 210‧‧‧ Conductive layer
220‧‧‧蓋層 220‧‧‧ cover
230‧‧‧凹陷 230‧‧‧ dent
230a‧‧‧頂角 230a‧‧‧Top angle
300‧‧‧第一隔離結構 300‧‧‧First isolation structure
310、410‧‧‧氧化層 310, 410‧‧‧ oxide layer
320、420‧‧‧高密度氧化層 320, 420‧‧‧ high-density oxide layer
400‧‧‧第二隔離結構 400‧‧‧Second isolation structure
600a‧‧‧第一蝕刻停止層 600a‧‧‧First etch stop layer
604‧‧‧第二蝕刻停止層 604‧‧‧Second etch stop layer
1000‧‧‧介電層 1000‧‧‧ dielectric layer
1100a‧‧‧接觸窗開口 1100a‧‧‧Contact window opening
1200a‧‧‧圖案化罩幕層 1200a‧‧‧ patterned mask layer
1400a‧‧‧保護層 1400a‧‧ ‧ protective layer
1500a‧‧‧接觸窗 1500a‧‧‧Contact window
Claims (12)
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| TW201106445A (en) * | 2009-08-11 | 2011-02-16 | Hynix Semiconductor Inc | Semiconductor device and method of fabricating the same |
| TW201230303A (en) * | 2010-11-30 | 2012-07-16 | Elpida Memory Inc | Semiconductor device and method of forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW201106445A (en) * | 2009-08-11 | 2011-02-16 | Hynix Semiconductor Inc | Semiconductor device and method of fabricating the same |
| TW201230303A (en) * | 2010-11-30 | 2012-07-16 | Elpida Memory Inc | Semiconductor device and method of forming the same |
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