TWI594349B - Ic carrier of semiconductor package and manufacturing method thereof - Google Patents
Ic carrier of semiconductor package and manufacturing method thereof Download PDFInfo
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- TWI594349B TWI594349B TW104140701A TW104140701A TWI594349B TW I594349 B TWI594349 B TW I594349B TW 104140701 A TW104140701 A TW 104140701A TW 104140701 A TW104140701 A TW 104140701A TW I594349 B TWI594349 B TW I594349B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明係關於一種載板及其製造方法，特別關於一種適用於中低腳數之積體電路封裝領域的半導體封裝載板及其製造方法。 The present invention relates to a carrier board and a method of fabricating the same, and more particularly to a semiconductor package carrier board suitable for use in the field of integrated circuit packages of medium and low pin counts and a method of fabricating the same.
隨著人類對提高生活便利性的需求下，各種電子化產品***性的急速擴張，而在電子產品組件製程上佔據舉足輕重地位之積體電路封裝技術也因應此需求所寄予的高速處理化、多功能化、積集化(Integrated)以及小型輕量化等多方面渴望，朝向微型化與高密度化發展。 With the demand for improved convenience of human beings, the explosion of various electronic products has rapidly expanded, and the integrated circuit packaging technology that plays a pivotal role in the manufacturing process of electronic components has also responded to the high-speed processing and multi-functionality of this demand. We are eager to achieve miniaturization and high density, and we are eager to integrate and integrate small size and light weight.
目前半導體封裝技術在中低腳數的封裝上主要是以引線框架(Lead frame)、四方扁平無腳封裝(Quad Flat No-lead Package,QFN)或晶圓級晶片封裝方式(WB CSP)為主，但若要應用於智慧型手機或穿戴式裝置所需求的小型、輕薄、低成本以及細間距等功能需求下，上述封裝用之載板或引線框架已面臨技術瓶頸。 At present, semiconductor packaging technology is mainly based on lead frame, quad flat no-lead package (QFN) or wafer level chip package (WB CSP). However, if it is to be applied to the functions of small size, light weight, low cost, and fine pitch required for smart phones or wearable devices, the carrier board or lead frame for the above package has faced a technical bottleneck.
舉例來說，在引線框架上的封裝製程架構上，其所使用的導線架厚度往往較大，再者，因為其無法形成較為精細的線路與現率間距，以及線路佈局(un-routable)，因此導線架無法對設置於其上之晶片具有電磁波防護效果。此外，現有的載板之介電材料是採用有玻璃纖維之核心層(CCL)或樹脂膠片(PP：Prepreg)，並用雷射鑽孔(laser via)作為電性連接，但雷射對玻璃纖維材進行鑽孔的加工產出慢，成本高，且孔徑不易微小化。再者，當介電材採用玻纖之BT、FR4、FR5或ABF等材料和防焊材料時，在薄型化的情況下，非常容易產生板翹，導致薄型化困難。 更者，由玻璃纖維組構成之介電材料也增加了細線路加工的難度與成本。 For example, the thickness of the leadframe used in the packaging process architecture on the lead frame tends to be large, and because it cannot form finer lines and current spacing, and un-routable, Therefore, the lead frame cannot have electromagnetic wave protection effect on the wafer disposed thereon. In addition, the dielectric material of the existing carrier plate is a core layer of glass fiber (CCL) or a resin film (PP: Prepreg), and a laser via is used as an electrical connection, but the laser is used for the glass fiber. The drilling of the material is slow in production, high in cost, and the aperture is not easily miniaturized. Further, when the dielectric material is made of a material such as BT, FR4, FR5 or ABF of glass fiber and a solder resist material, in the case of thinning, the warpage is very likely to occur, resulting in difficulty in thinning. Moreover, the dielectric material composed of the glass fiber group also increases the difficulty and cost of the fine line processing.
因此，各家封裝業者無不汲汲營營研究可符合目前中低腳數封裝結構市場所需的導線架。本發明係針對此一需求，提出一種嶄新的載板及其製造方法，以符合此需。 Therefore, various packaging companies have to conduct research to meet the lead frame required for the current low-to-medium package structure market. The present invention is directed to this need, and proposes a brand new carrier board and a method of manufacturing the same to meet this need.
本發明之主要目的在於提供一種半導體封裝載板及其製造方法，其兼具有可繞線，細線路間距與厚度薄之優點。 SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor package carrier and a method of fabricating the same, which have the advantages of being windable, having a fine line pitch and a thin thickness.
本發明之另一目的在於提供一種半導體封裝載板及其製造方法，其可符合中低腳數之積體電路封裝領域之體積輕薄與成本低廉的需求。 Another object of the present invention is to provide a semiconductor package carrier and a method of fabricating the same, which can meet the requirements of light weight and low cost in the field of integrated circuit packages with medium and low pin counts.
為達上述目的，本發明提供一種半導體封裝載板，其主要包括一模鑄介電層與一圖案化導體層。模鑄介電層具有至少一開口槽。而圖案化導體層是埋設於此模鑄介電層內，其中部分圖案化導體層自開口槽顯露出，形成上下兩端是開放端的是作為導電柱，其餘圖案化導體層因僅一端是開放端的是作為導線。 To achieve the above object, the present invention provides a semiconductor package carrier comprising a die cast dielectric layer and a patterned conductor layer. The die cast dielectric layer has at least one open slot. The patterned conductor layer is embedded in the die-cast dielectric layer, wherein a portion of the patterned conductor layer is exposed from the open trench, and the upper and lower ends are open ends as conductive pillars, and the remaining patterned conductor layers are open only at one end. The end is used as a wire.
另外，為達上述目的，本發明尚提供此種半導體封裝載板的製造方法，其首先於一暫時性載板之一表面形成一圖案化導體層；隨後，於此暫時性載板上形成一覆蓋該圖案化導體層之模鑄介電層；接續，於模鑄介電層上形成至少一開口槽，以顯露出部分圖案化導體層，其中開口槽即是作為一開放端；以及，最後移除該暫時性載板，以顯露出圖案化導體層之一側，作為另一開放端，並且顯露出部分之介電材料層。部分圖案化導體層自開口槽顯露出，形成上下兩端是開放端者係作為導電柱，而於圖案化導體層僅一端是開放端者係作為導線。 In addition, in order to achieve the above object, the present invention further provides a method for fabricating a semiconductor package carrier, which first forms a patterned conductor layer on a surface of a temporary carrier; subsequently, a temporary carrier is formed on the carrier. Covering the patterned dielectric layer of the patterned conductor layer; subsequently, forming at least one open trench on the die-cast dielectric layer to expose a portion of the patterned conductor layer, wherein the open trench is an open end; and, finally The temporary carrier is removed to reveal one side of the patterned conductor layer as another open end and a portion of the dielectric material layer is exposed. The partially patterned conductor layer is exposed from the open trench, and the upper and lower ends are open-ended as the conductive pillar, and the patterned conductor layer is open-ended only as one end.
10、50‧‧‧半導體封裝載板 10, 50‧‧‧ semiconductor package carrier
12‧‧‧模鑄介電層 12‧‧‧Molded dielectric layer
14‧‧‧圖案化導體層 14‧‧‧ patterned conductor layer
14a‧‧‧導電柱 14a‧‧‧conductive column
14b‧‧‧導線 14b‧‧‧Wire
16‧‧‧保護層 16‧‧‧Protective layer
18‧‧‧開口槽 18‧‧‧Open slot
20、60‧‧‧封裝結構 20, 60‧‧‧Package structure
22‧‧‧晶片 22‧‧‧ wafer
23‧‧‧連接凸塊 23‧‧‧Connecting bumps
24‧‧‧封膠層 24‧‧‧ Sealing layer
25‧‧‧固定膠 25‧‧‧Fixed glue
26‧‧‧錫球 26‧‧‧ solder balls
32‧‧‧金屬線材 32‧‧‧Metal wire
40‧‧‧暫時性載板 40‧‧‧ Temporary carrier board
42‧‧‧圖案化光阻層 42‧‧‧ patterned photoresist layer
422‧‧‧開孔 422‧‧‧opening
44‧‧‧導體材料 44‧‧‧Conductor materials
52‧‧‧導電層 52‧‧‧ Conductive layer
圖1所示為本發明第一實施例之半導體封裝載板的一示意圖。 1 is a schematic view showing a semiconductor package carrier of a first embodiment of the present invention.
圖2為圖1之半導體封裝載板應用於球柵陣列封裝之一實施例示意圖。 2 is a schematic diagram of an embodiment of the semiconductor package carrier of FIG. 1 applied to a ball grid array package.
圖3為圖1之半導體封裝載板應用於球柵陣列封裝之另一實施例示意圖。 3 is a schematic diagram of another embodiment of the semiconductor package carrier of FIG. 1 applied to a ball grid array package.
圖4A至圖4F為圖1所示之半導體封裝載板的製作步驟示意圖。 4A to 4F are schematic diagrams showing the steps of fabricating the semiconductor package carrier shown in FIG. 1.
圖4G為具有保護層之半導體封裝載板之一示意圖。 4G is a schematic diagram of a semiconductor package carrier with a protective layer.
圖5為本發明第二實施例之半導體封裝載板的一示意圖。 FIG. 5 is a schematic diagram of a semiconductor package carrier according to a second embodiment of the present invention.
圖6為圖5之半導體封裝載板應用於平面網格陣列封裝之一實施例示意圖。 6 is a schematic diagram of an embodiment of the semiconductor package carrier of FIG. 5 applied to a planar grid array package.
圖7為圖5之半導體封裝載板應用於平面網格陣列封裝之另一實施例示意圖。 7 is a schematic diagram of another embodiment of the semiconductor package carrier of FIG. 5 applied to a planar grid array package.
圖8A至圖8F為圖5所示之半導體封裝載板的製作步驟示意圖。 8A to 8F are schematic diagrams showing the steps of fabricating the semiconductor package carrier shown in FIG. 5.
以下將透過實施例來解釋本發明內容，本發明的實施例並非用以限制本發明須在如實施例所述之任何特定的環境、應用或特殊方式方能實施。因此，關於實施例之說明僅為闡釋本發明之目的，而非用以限制本發明。須說明者，以下實施例及圖式中，與本發明非直接相關之元件已省略而未繪示；且圖式中各元件間之尺寸關係僅為求容易瞭解，非用以限制實際比例。另外，以下實施例中，相同的元件將以相同的元件符號加以說明。 The present invention is not limited by the embodiment, and the embodiment of the present invention is not intended to limit the invention to any specific environment, application or special mode as described in the embodiments. Therefore, the description of the embodiments is merely illustrative of the invention and is not intended to limit the invention. It should be noted that, in the following embodiments and drawings, components that are not directly related to the present invention have been omitted and are not shown; and the dimensional relationships between the components in the drawings are merely for ease of understanding and are not intended to limit the actual ratio. In the following embodiments, the same elements will be described with the same element symbols.
本發明是一種兼具有體積小、厚度薄，成本低，且導線間距可以細微化等特性之載板，其可應用於中低腳數之積體電路封裝領域。請參照圖1所示，其係本發明之半導體封裝載板的第一實施例之示意圖。如圖1所示，半導體封裝載板10主要包括一模鑄介電層12以及至少一圖案化導體層14。圖案化導體層14係埋設於模鑄介電層12內，且圖案化導體層14包含有至少一第一導體部與至少一第二導體部。其中，第一導體部與第二導體部間係由模鑄介電層12隔離。模鑄介電層12具有至少一開口槽18，以顯露出第一導體部，使第一導體部呈現上下兩端皆為開放式，也就是第一導體部具有上下兩端顯露於模鑄介電層12外的開放端，使第一導體部可作為上下層電性傳遞之導電柱14a。而第二導體部僅一端開放式顯露於模鑄介電層12外，是作為導線14b，可做同一層的 線路布局(繞線)之用。另外，部分的導線14b亦可作為電性連接墊，以作為與電子元件連接之用途。 The invention is a carrier board which has the characteristics of small volume, thin thickness, low cost, and fine wire spacing, and can be applied to the field of integrated circuit package with medium and low pin count. Please refer to FIG. 1, which is a schematic view of a first embodiment of a semiconductor package carrier of the present invention. As shown in FIG. 1, the semiconductor package carrier 10 mainly includes a die cast dielectric layer 12 and at least one patterned conductor layer 14. The patterned conductor layer 14 is embedded in the die-cast dielectric layer 12, and the patterned conductor layer 14 includes at least one first conductor portion and at least one second conductor portion. The first conductor portion and the second conductor portion are separated by a die-cast dielectric layer 12. The die-cast dielectric layer 12 has at least one opening groove 18 to expose the first conductor portion, so that the first conductor portion has an open upper and lower ends, that is, the first conductor portion has upper and lower ends exposed to the die-casting medium. The open end outside the electrical layer 12 allows the first conductor portion to serve as a conductive post 14a for electrical transmission of the upper and lower layers. The second conductor portion is only open at one end and exposed outside the die-cast dielectric layer 12, and serves as the wire 14b, which can be used as the same layer. Line layout (winding). In addition, part of the wire 14b can also serve as an electrical connection pad for use in connection with electronic components.
於此，要說明的是，所謂的開放式係指圖案化導體層14未被模鑄介電層12覆蓋之部分。換言之，即顯露於模鑄介電層12的部分圖案化導體層14，不論是否再被其他元件覆蓋，皆稱之為開放式。 Here, it is to be noted that the so-called open type refers to a portion of the patterned conductor layer 14 that is not covered by the die-cast dielectric layer 12. In other words, the partially patterned conductor layer 14 exposed to the die-cast dielectric layer 12, whether or not it is covered by other components, is referred to as open.
上述之界定方式是意味著導電柱14a與導線14b實由單一圖案化導體層14所同步形成的，差異僅在於開口槽18之有無，來界定出此部分的圖案化導體層14是作為上下層電性傳遞之導電柱14a或是做為單一平面之電性傳遞的導線14b。此外，圖案化導體層14是埋設於模鑄介電層12內，所以模鑄介電層12之高度可以與圖案化導體層14極為近似，因為其僅需些許增加覆蓋住圖案化導體層14單一側之高度僅可。如此一來，整體載板之厚度將可以大幅縮小。 The above definition means that the conductive pillars 14a and the wires 14b are formed by the single patterned conductor layer 14 in synchronization with each other, except for the presence or absence of the opening grooves 18, to define the patterned conductor layer 14 as the upper and lower layers. The electrically conductive conductive post 14a is either a wire 14b that is electrically transmitted as a single plane. In addition, the patterned conductor layer 14 is embedded in the die-cast dielectric layer 12, so the height of the die-cast dielectric layer 12 can be very similar to that of the patterned conductor layer 14 because it only needs to be slightly covered to cover the patterned conductor layer 14. The height of one side is only available. As a result, the thickness of the overall carrier can be greatly reduced.
再者，圖案化導體層14自模鑄介電層12顯露於外的部分更形成有一保護層16，以避免顯露出的圖案化導體層14在常態環境下產生氧化反應。 Furthermore, the patterned conductor layer 14 is further formed with a protective layer 16 from the exposed portion of the die-cast dielectric layer 12 to prevent the exposed patterned conductor layer 14 from undergoing an oxidation reaction under a normal environment.
上述之半導體封裝載板10可應用於球柵陣列(BGA)封裝。舉例來說，如圖2所示，封裝結構20包含有一晶片22、一封膠層24以及至少一錫球26。晶片22係藉由至少一連接凸塊(Bump)23採覆晶接合(Flip-Chip)方式透過保護層16而與半導體封裝載板10中之導線14b電性連接。封膠層24係將晶片22與位於晶片22側之顯露於模鑄介電層12外之導電柱14a、導線14b及保護層16同時封圍，以防止濕氣由外部進入。錫球26係設置於導電柱14a未被封膠層24封圍之開口槽18，以作為電性接腳，來與後續之電路板(圖中未示)之電性接點連接。 The semiconductor package carrier 10 described above can be applied to a ball grid array (BGA) package. For example, as shown in FIG. 2, the package structure 20 includes a wafer 22, an adhesive layer 24, and at least one solder ball 26. The wafer 22 is electrically connected to the wires 14b of the semiconductor package carrier 10 through the protective layer 16 by at least one bump bump 23 in a Flip-Chip manner. The encapsulant layer 24 simultaneously encloses the wafer 22 and the conductive pillars 14a, the wires 14b and the protective layer 16 exposed on the wafer 22 side outside the die-cast dielectric layer 12 to prevent moisture from entering from the outside. The solder ball 26 is disposed on the open slot 18 of the conductive post 14a that is not enclosed by the sealant layer 24, and is used as an electrical pin to be connected to an electrical contact of a subsequent circuit board (not shown).
當然，如圖3所示，晶片22也可利用固定膠25暫時固定於半導體封裝載板10，再藉由金屬線材32採打線接合(wire bonding)方式透過保護層16而與半導體封裝載板10上之導電柱14a電性連接。因封裝過程係為一習知技術，於此將不再贅述。 Of course, as shown in FIG. 3, the wafer 22 can also be temporarily fixed to the semiconductor package carrier 10 by using the fixing glue 25, and then transmitted through the protective layer 16 by the wire bonding 32 to the semiconductor package carrier 10. The conductive pillars 14a are electrically connected. Since the packaging process is a conventional technique, it will not be described here.
再如圖1所示，半導體封裝載板10使用模鑄介電層12作為基材，以承載圖案化導體層14，並藉以絕緣隔離以及保護圖案化導體層14。模鑄介電層12之材質係可選用晶片封裝用之鑄模化合物(Molding Compound)，其例如但不限於具有酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之鑄模化合物，且鑄模化合物亦可包含適當之填充劑，例如是粉狀二氧化矽。 As further shown in FIG. 1, the semiconductor package carrier 10 uses a die-cast dielectric layer 12 as a substrate to carry the patterned conductor layer 14 and thereby insulate and protect the patterned conductor layer 14. The material of the die-cast dielectric layer 12 may be a mold compound for wafer encapsulation, such as, but not limited to, having a phenolic resin (Novolac-Based Resin), an epoxy resin (Epoxy-Based Resin), and a ruthenium resin. Silicone-Based Resin or other suitable mold compound, and the mold compound may also contain a suitable filler such as powdered cerium oxide.
於本實施例中，圖案化導體層14之材質係為金屬，例如但不限於選自銅、鐵、銀、鎳及其組合。 In the present embodiment, the material of the patterned conductor layer 14 is a metal such as, but not limited to, selected from the group consisting of copper, iron, silver, nickel, and combinations thereof.
請參閱圖4A至圖4F，其係圖1之半導體封裝載板10的製作步驟示意圖。首先如圖4A所示，提供一可分離式的暫時性載板40，並於此暫時性載板40表面上形成一圖案化光阻層42，其具有複數開孔422。圖案化光阻層42係應用曝光顯影技術所形成。在本實施例中，暫時性載板40之材質可以為鐵、鎳、銅金屬或與介電材料複合而製成，當然也可依據不同的技術需求進行任意變化。 Please refer to FIG. 4A to FIG. 4F , which are schematic diagrams showing the steps of fabricating the semiconductor package carrier 10 of FIG. 1 . First, as shown in FIG. 4A, a detachable temporary carrier 40 is provided, and a patterned photoresist layer 42 having a plurality of openings 422 is formed on the surface of the temporary carrier 40. The patterned photoresist layer 42 is formed using an exposure development technique. In this embodiment, the material of the temporary carrier 40 may be made of iron, nickel, copper metal or a composite material, and may of course be arbitrarily changed according to different technical requirements.
隨後，如圖4B所示，於圖案化光阻層42之該等開孔422中形成一導體材料44。於本實施例中，導體材料44之材質係為金屬，例如但不限於選自銅、鐵、銀、鎳及其組合，且依據不同的材質可應用電鍍技術、無電鍍(Electroless Plating)技術、濺鍍(Sputtering Coating)技術或蒸鍍(Thermal Coating)技術所形成。 Subsequently, as shown in FIG. 4B, a conductor material 44 is formed in the openings 422 of the patterned photoresist layer 42. In this embodiment, the material of the conductor material 44 is a metal, such as, but not limited to, selected from the group consisting of copper, iron, silver, nickel, and combinations thereof, and electroplating technology, electroless plating (Electroless Plating) technology may be applied according to different materials. Sputtering Coating technology or Thermal Coating technology.
接續，如圖4C所示，移除圖案化光阻層42即獲得先前所述之具有至少一第一導體部與至少一第二導體部之圖案化導體層14。隨後，如圖4D所示，利用鑄模技術形成一覆蓋圖案化導體層14之一模鑄介電層12。於本實施例中，模鑄介電層12係可應用真空壓模技術或是鑄模技術所形成。當應用鑄模技術時，模鑄介電層12之材質係可選用晶片封裝用之鑄模化合物，其例如但不限於具有酚醛基樹脂、環氧基樹脂、矽基樹脂或其他適當之鑄模化合物，且鑄模化合物亦可包含適當之填充劑，例如是粉狀二氧化矽。 Next, as shown in FIG. 4C, the patterned photoresist layer 42 is removed to obtain the patterned conductor layer 14 having at least one first conductor portion and at least one second conductor portion as previously described. Subsequently, as shown in FIG. 4D, a molded dielectric layer 12 covering one of the patterned conductor layers 14 is formed by a molding technique. In the present embodiment, the die-cast dielectric layer 12 can be formed using vacuum compression molding techniques or molding techniques. When the molding technique is applied, the material of the die-cast dielectric layer 12 may be a mold compound for wafer encapsulation, such as, but not limited to, having a phenolic resin, an epoxy resin, a ruthenium-based resin, or other suitable mold compound, and The mold compound may also contain a suitable filler such as powdered cerium oxide.
另外，當應用鑄模技術時，形成模鑄介電層12之步驟還可包括：提供一鑄模化合物，其中鑄模化合物具有樹脂及粉狀之二氧化矽；加熱鑄模化合物至液體狀態；注入呈液態之鑄模化合物於第三開孔中，並使鑄模化合物在高溫和高壓下包覆圖案化導體層；固化鑄模化合物，使鑄模化合物形成模鑄介電層12。 In addition, when the molding technique is applied, the step of forming the die-cast dielectric layer 12 may further include: providing a mold compound in which the mold compound has resin and powdered cerium oxide; heating the mold compound to a liquid state; and injecting into a liquid state The mold compound is in the third opening, and the mold compound is coated with the patterned conductor layer at a high temperature and a high pressure; the mold compound is cured to form the mold compound into the die-cast dielectric layer 12.
隨後，如圖4E所示，移除部分位於圖案化導體層14上之模鑄介電層12，形成數個開口槽18，以顯露出部分圖案化導體層14。此處所指的移除步驟，可選用磨削(grinding)、電漿(plasma)或反應離子式蝕刻(RIE)的方式來移除部分模鑄介電層12。 Subsequently, as shown in FIG. 4E, the portion of the die-cast dielectric layer 12 on the patterned conductor layer 14 is removed to form a plurality of open trenches 18 to expose portions of the patterned conductor layer 14. The removal step referred to herein may optionally remove the partially molded dielectric layer 12 by means of grinding, plasma or reactive ion etching (RIE).
最後，搭配圖4F所示，移除暫時性載板40，即獲得半導體封裝載板10。如該圖所示，移除暫時性載板40後，圖案化導體層14之另一側將顯露出來，以作為後續的電性連接用途，此時，部分圖案化導體層14之上下兩端顯露於模鑄介電層12，以作為導電柱14a，而另一部分圖案化導體層14僅一端顯露於模鑄介電層12外者係作為導線14b。 Finally, as shown in FIG. 4F, the temporary carrier 40 is removed, that is, the semiconductor package carrier 10 is obtained. As shown in the figure, after the temporary carrier 40 is removed, the other side of the patterned conductor layer 14 will be exposed for subsequent electrical connection purposes. At this time, the upper and lower ends of the partially patterned conductor layer 14 are partially patterned. The die-cast dielectric layer 12 is exposed as the conductive pillar 14a, and the other portion of the patterned conductor layer 14 is exposed at one end only to the die-cast dielectric layer 12 as the wire 14b.
此外，再如圖4G所示，為避免顯露出在常態環境下產生氧化反應，更可於顯露於模鑄介電層12外之圖案化導體層14表面上形成一保護層16。此保護層16可以是有機保焊膜(OSP)、Ni/Pd/Au鍍膜或Ni/Ag鍍膜。 In addition, as shown in FIG. 4G, in order to avoid the occurrence of an oxidation reaction in a normal environment, a protective layer 16 may be formed on the surface of the patterned conductor layer 14 exposed outside the die-cast dielectric layer 12. This protective layer 16 may be an organic solder resist film (OSP), a Ni/Pd/Au plating film, or a Ni/Ag plating film.
請參閱圖5，其係本發明第二實施例之半導體封裝載板50的示意圖。此實施例與第一實施例之差異在於半導體封裝載板50之模鑄介電層12之開口槽18內更填設有一導電層52，以使導電柱14a加上導電層52之高度與模鑄介電層12之高度約略一致。 Please refer to FIG. 5, which is a schematic diagram of a semiconductor package carrier 50 according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that a conductive layer 52 is further filled in the open trench 18 of the die-cast dielectric layer 12 of the semiconductor package carrier 50 to add the height and mode of the conductive pillar 14a to the conductive layer 52. The height of the cast dielectric layer 12 is approximately the same.
此時為避免顯露出在常態環境下產生氧化反應，同樣也可於顯露於模鑄介電層12外之導電柱14a、導線14b或導電層52表面上形成一保護層16。 At this time, in order to avoid the occurrence of an oxidation reaction in a normal environment, a protective layer 16 may be formed on the surface of the conductive pillar 14a, the wire 14b or the conductive layer 52 exposed outside the die-cast dielectric layer 12.
請圖6所示，其係圖5所示之半導體封裝載板50應用於平面網格陣列封裝的一實施例示意圖。如圖6所示，封裝結構60包含有一晶片22及一封膠層24。晶片22係藉由連接凸塊23採覆晶 接合方式透過保護層16而與半導體封裝載板50中顯露於外之導線14b電性連接。封膠層24係將晶片22與位於晶片側自該模鑄介電層12顯露外之導線14b封圍，以防止濕氣由外部進入。因封裝過程係為一習知技術，於此將不再贅述。當然，如圖7所示，晶片22也可藉由固定膠25暫時固定於半導體封裝載板50，再利用金屬線材32採打線接合方式透過保護層16來與半導體封裝載板50上之導電柱14a電性連接。 Please refer to FIG. 6 , which is a schematic diagram of an embodiment of the semiconductor package carrier 50 shown in FIG. 5 applied to a planar grid array package. As shown in FIG. 6, the package structure 60 includes a wafer 22 and an adhesive layer 24. The wafer 22 is covered by the connecting bump 23 The bonding method is electrically connected to the exposed wires 14b of the semiconductor package carrier 50 through the protective layer 16. The encapsulant layer 24 encloses the wafer 22 with the wires 14b on the wafer side that are exposed from the molded dielectric layer 12 to prevent moisture from entering from the outside. Since the packaging process is a conventional technique, it will not be described here. Of course, as shown in FIG. 7 , the wafer 22 can also be temporarily fixed to the semiconductor package carrier 50 by the fixing glue 25 , and then the conductive layer 16 can be used to pass through the protective layer 16 and the conductive pillar on the semiconductor package carrier 50 by using the metal wire 32 . 14a electrical connection.
請參閱圖8A至圖8F，其係本發明第二實施例之半導體封裝載板50的製作步驟示意圖。首先如圖8A所示，提供一可分離式的暫時性載板40，並於此暫時性載板40表面上形成一圖案化光阻層42，其具有複數開孔422。 Please refer to FIG. 8A to FIG. 8F , which are schematic diagrams showing the steps of fabricating the semiconductor package carrier 50 of the second embodiment of the present invention. First, as shown in FIG. 8A, a detachable temporary carrier 40 is provided, and a patterned photoresist layer 42 having a plurality of openings 422 is formed on the surface of the temporary carrier 40.
隨後，如圖8B所示，於圖案化光阻層42之開孔422形成一導體層，接續，移除圖案化光阻層42，以獲得一圖案化導體層14。隨後，如圖8C所示，形成一覆蓋圖案化導體層14之模鑄介電層12。 Subsequently, as shown in FIG. 8B, a conductor layer is formed on the opening 422 of the patterned photoresist layer 42, and the patterned photoresist layer 42 is removed to obtain a patterned conductor layer 14. Subsequently, as shown in FIG. 8C, a die-cast dielectric layer 12 covering the patterned conductor layer 14 is formed.
隨後，如圖8D所示，利用磨削(grinding)、電漿(plasma)或反應離子式蝕刻(RIE)的方式於模鑄介電層12上形成至少一開口槽18，以顯露出部分圖案化導體層14之表面。 Subsequently, as shown in FIG. 8D, at least one open trench 18 is formed on the die-cast dielectric layer 12 by means of grinding, plasma or reactive ion etching (RIE) to reveal a partial pattern. The surface of the conductor layer 14 is formed.
接續，如圖8E所示，於開口槽18內填入一導電層52，以使自開口槽18所露出之該部分圖案化導體層14之高度加上導電層52之高度後能夠與模鑄介電層12之高度約略一致。 Continuing, as shown in FIG. 8E, a conductive layer 52 is filled in the opening groove 18 so that the height of the portion of the patterned conductor layer 14 exposed from the opening groove 18 is increased by the height of the conductive layer 52. The height of the dielectric layer 12 is approximately the same.
最後，搭配圖8F所示，移除暫時性載板40，以形成半導體封裝載板50。如該圖所示，移除暫時性載板40後，圖案化導體層14之另一側將顯露出來，以作為後續的電性連接用途。此時為避免顯露出在常態環境下產生氧化反應，更可於顯露於模鑄介電層12外之圖案化導體層14以及導電層52表面上形成一保護層16。 Finally, as shown in FIG. 8F, the temporary carrier 40 is removed to form the semiconductor package carrier 50. As shown in the figure, after the temporary carrier 40 is removed, the other side of the patterned conductor layer 14 will be exposed for subsequent electrical connection purposes. At this time, in order to avoid the occurrence of an oxidation reaction in a normal environment, a protective layer 16 may be formed on the surface of the patterned conductor layer 14 and the conductive layer 52 exposed outside the die-cast dielectric layer 12.
在上述圖8A至圖8F中製程步驟的細節，如暫時性載板的材料，圖案化光阻層的形成方法等可承襲圖4A至圖4F所教示的內容，因此不再進行贅述。 The details of the process steps in the above-described FIGS. 8A to 8F, such as the material of the temporary carrier, the formation method of the patterned photoresist layer, and the like, can follow the teachings of FIGS. 4A to 4F, and thus will not be described again.
綜上所述，本發明提供一種嶄新的半導體封裝載板與其製作方法，其導電柱和導線是由圖案化導體層所同時形成，並利用一高度約略相近之模鑄介電層封圍，因為模鑄介電層之高度與導電柱或導線之高度相當近似，因此能夠減少載板整體厚度，並且因導電層的圖案化過程已經是一相當成熟的技術，因此線路間距也可以大幅縮小，並可以形成環繞式的導線佈局(routable)，進而提供晶片電磁上的防護。 In summary, the present invention provides a novel semiconductor package carrier and a method of fabricating the same, wherein the conductive pillars and wires are simultaneously formed by a patterned conductor layer and are enclosed by a die-cast dielectric layer having a height approximately The height of the die-cast dielectric layer is similar to the height of the conductive pillar or wire, so the overall thickness of the carrier can be reduced, and since the patterning process of the conductive layer is already a mature technology, the line pitch can be greatly reduced, and A wraparound wire layout can be formed to provide electromagnetic protection of the wafer.
本發明符合發明專利之要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士，爰依本案發明精神所作之等效修飾或變化，皆應包括於以下之申請專利範圍內。 The invention complies with the requirements of the invention patent, and proposes a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Any person who is familiar with the skill of the case, equivalent modifications or changes made in accordance with the spirit of the invention shall be included in the scope of the following patent application.
10‧‧‧半導體封裝載板 10‧‧‧Semiconductor package carrier
12‧‧‧模鑄介電層 12‧‧‧Molded dielectric layer
14‧‧‧圖案化導體層 14‧‧‧ patterned conductor layer
14a‧‧‧導電柱 14a‧‧‧conductive column
14b‧‧‧導線 14b‧‧‧Wire
16‧‧‧保護層 16‧‧‧Protective layer
18‧‧‧開口槽 18‧‧‧Open slot
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| TW200948232A (en) * | 2008-05-06 | 2009-11-16 | Kinsus Interconnect Tech Corp | Manufacturing method of leadless packaging substrate |
| TW201113999A (en) * | 2009-10-14 | 2011-04-16 | Advanced Semiconductor Eng | Package carrier, package structure and process of fabricating package carrier |
| TW201351515A (en) * | 2012-06-07 | 2013-12-16 | Subtron Technology Co Ltd | Package carrier and manufacturing method thereof |
| TW201535596A (en) * | 2014-01-17 | 2015-09-16 | Taiwan Semiconductor Mfg Co Ltd | Package-on-package device and methods of forming same |
| TW201541587A (en) * | 2014-04-21 | 2015-11-01 | Zhen Ding Technology Co Ltd | Chip package substrate, chip package structure and method for manufacturing the chip package substrate and the chip package structure |
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| TW200948232A (en) * | 2008-05-06 | 2009-11-16 | Kinsus Interconnect Tech Corp | Manufacturing method of leadless packaging substrate |
| TW201113999A (en) * | 2009-10-14 | 2011-04-16 | Advanced Semiconductor Eng | Package carrier, package structure and process of fabricating package carrier |
| TW201351515A (en) * | 2012-06-07 | 2013-12-16 | Subtron Technology Co Ltd | Package carrier and manufacturing method thereof |
| TW201535596A (en) * | 2014-01-17 | 2015-09-16 | Taiwan Semiconductor Mfg Co Ltd | Package-on-package device and methods of forming same |
| TW201541587A (en) * | 2014-04-21 | 2015-11-01 | Zhen Ding Technology Co Ltd | Chip package substrate, chip package structure and method for manufacturing the chip package substrate and the chip package structure |
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