TWI592866B - Methods for atomic writes in a ssd (solid state disk) system and apparatuses using the same - Google Patents

Methods for atomic writes in a ssd (solid state disk) system and apparatuses using the same Download PDF

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TWI592866B
TWI592866B TW105134399A TW105134399A TWI592866B TW I592866 B TWI592866 B TW I592866B TW 105134399 A TW105134399 A TW 105134399A TW 105134399 A TW105134399 A TW 105134399A TW I592866 B TWI592866 B TW I592866B
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周溱
苗寧忠
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上海寶存信息科技有限公司
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
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    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
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    • G06F3/0688—Non-volatile semiconductor memory arrays

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Description

固態硬碟系統的原子寫入方法以及使用該方法的裝置 Atom writing method for solid state hard disk system and device using the same

本發明關連於一種快閃記憶體裝置，特別是一種固態硬碟系統的原子寫入方法以及使用該方法的裝置。 The present invention relates to a flash memory device, and more particularly to an atomic writing method for a solid state hard disk system and a device using the same.

快閃記憶體裝置通常分為NOR快閃裝置與NAND快閃裝置。NOR快閃裝置為隨機存取裝置，而可於位址腳位上提供任何的位址，用以存取NOR快閃裝置的主裝置(host)，並及時地由NOR快閃裝置的資料腳位上獲得儲存於該位址上的資料。相反地，NAND快閃裝置並非隨機存取，而是序列存取。NAND快閃裝置無法像NOR快閃裝置一樣，可以存取任何隨機位址，主裝置反而需要寫入序列的位元組(bytes)的值到NAND快閃裝置中，用以定義請求命令(command)的類型(如，讀取、寫入、抹除等)，以及用在此命令上的位址。位址可指向一個頁面(在快閃記憶體中的一個寫入作業的最小資料塊)或一個區塊(在快閃記憶體中的一個抹除作業的最小資料塊)。實際上，NAND快閃裝置通常從記憶體單元(memory cells)上讀取或寫入完整的數頁資料。當一整頁的資料從陣列讀取到裝置中的緩存器(buffer)後，藉由使用提取訊號(strobe signal)順序地敲出(clock out)內容，讓主單元可逐位元組或字元組(words)存取資 料。 Flash memory devices are generally classified into NOR flash devices and NAND flash devices. The NOR flash device is a random access device, and any address can be provided at the address pin to access the host of the NOR flash device and timely by the data foot of the NOR flash device. The data stored on the address is obtained on the bit. Conversely, NAND flash devices are not random access, but sequential access. The NAND flash device cannot access any random address like the NOR flash device. Instead, the master device needs to write the value of the byte of the sequence to the NAND flash device to define the request command (command). Type (eg, read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest data block of a write job in flash memory) or a block (the smallest data block of an erase job in flash memory). In fact, NAND flash devices typically read or write complete pages of data from memory cells. When a full page of data is read from the array into a buffer in the device, the main unit can be bitwise or word by sequentially clocking out the content using a strobe signal. Tuple access material.

原子寫入是應用在儲存系統的重要規格，例如，資料庫系統。資料庫系統在資料完整(data integrity)上需要滿足原子性(atomicity)、一致性(consistency)、隔離性(isolation)及持續性(durability)的要求，簡稱為ACID。即使是遭遇到掉電(power loss)的非預期事件，資料庫的原子性都要確保每次更新是全部成功或者全部失敗。為滿足資料庫系統，固態硬碟系統的資料寫入也需要符合原子性的要求。因此，本發明提出一種固態硬碟系統的原子寫入方法以及使用該方法的裝置，用以滿足資料庫的原子性。 Atomic writing is an important specification applied to storage systems, for example, database systems. The database system needs to meet the requirements of atomicity, consistency, isolation, and durability in data integrity, referred to as ACID. Even in the event of an unexpected event of power loss, the atomicity of the database ensures that each update is all successful or all fails. In order to meet the database system, the data writing of the solid state hard disk system also needs to meet the atomic requirements. Accordingly, the present invention provides an atomic writing method for a solid state hard disk system and a device using the same to satisfy the atomicity of the database.

本發明的實施例提出一種固態硬碟系統的原子寫入方法，由處理單元執行，包含以下步驟。接收原子寫入命令，指示寫入少於一個頁面長度的資料至儲存單元。判斷上述資料將觸發緩存器中之跨頁面儲存時，填充虛擬資料至緩存器中之第一區域的所有可用子區域，以及儲存上述資料至緩存器中之第二區域。成功儲存上述資料至緩存器中之第二區域後，更新安全指標用以指向上述資料所儲存的第二區域的最後一個子區域的結束位址。 Embodiments of the present invention provide an atomic writing method for a solid state hard disk system, which is executed by a processing unit and includes the following steps. Receive atomic write command, indicating to write data less than one page length to the storage unit. Determining that the above data will trigger the cross-page storage in the buffer, fill the virtual data to all available sub-areas of the first area in the buffer, and store the above data to the second area in the buffer. After successfully storing the above data to the second area in the buffer, the security indicator is updated to point to the end address of the last sub-area of the second area stored in the above data.

本發明的實施例提出一種固態硬碟系統的原子寫入裝置，包含緩存控制器及處理單元。緩存控制器透過存取介面耦接至儲存單元。處理單元從主裝置接收原子寫入命令，指示寫入少於一個頁面長度的資料至儲存單元。處理單元判斷上述資料將觸發緩存器中之跨頁面儲存時，驅動緩存控制器填充 虛擬資料至緩存器中之第一區域的所有可用子區域，驅動緩存控制器儲存上述資料至緩存器中之第二區域。成功儲存上述資料至緩存器中之第二區域後，緩存控制器更新安全指標，用以指向上述資料所儲存的第二區域的最後一個子區域的結束位址。 Embodiments of the present invention provide an atomic writing device for a solid state hard disk system including a cache controller and a processing unit. The cache controller is coupled to the storage unit through an access interface. The processing unit receives an atomic write command from the primary device, instructing to write data of less than one page length to the storage unit. The processing unit determines that the above data will trigger the cross-page storage in the buffer, and the drive cache controller fills The virtual data is to all available sub-areas of the first area in the buffer, and the drive cache controller stores the above data to the second area in the buffer. After successfully storing the above data to the second area in the buffer, the cache controller updates the security indicator to point to the end address of the last sub-area of the second area stored in the above data.

10‧‧‧系統 10‧‧‧System

110‧‧‧處理單元 110‧‧‧Processing unit

120‧‧‧資料分配器 120‧‧‧Data distributor

130‧‧‧緩存控制器 130‧‧‧ Cache Controller

140‧‧‧掉電處理電路 140‧‧‧Power-down processing circuit

150‧‧‧存取介面 150‧‧‧Access interface

160‧‧‧主裝置 160‧‧‧Main device

170‧‧‧存取介面 170‧‧‧Access interface

CTRL‧‧‧控制訊號 CTRL‧‧‧ control signal

CMD1、...、CMD5‧‧‧命令 CMD1,..., CMD5‧‧‧ Order

DAT1、DAT2‧‧‧資料 DAT1, DAT2‧‧‧ data

170_0~170_j‧‧‧存取子介面 170_0~170_j‧‧‧Access subinterface

180‧‧‧儲存單元 180‧‧‧ storage unit

180_0_0、...、180_j_i‧‧‧儲存子單元 180_0_0,...,180_j_i‧‧‧Storage subunit

320_0_0、...、320_0_i‧‧‧晶片致能控制訊號 320_0_0,...,320_0_i‧‧‧ wafer enable control signal

400‧‧‧緩存器 400‧‧‧ Cache

400_0_0、...、400_0_i‧‧‧緩存器中的區域 400_0_0,...,400_0_i‧‧‧Area in the buffer

S510~S589‧‧‧方法步驟 S510~S589‧‧‧ method steps

610、640、660‧‧‧原子寫入的資料 610, 640, 660‧ ‧ atomic data

620、650a、650b‧‧‧非原子寫入的資料 620, 650a, 650b‧‧‧ non-atomic written data

630‧‧‧虛擬資料 630‧‧‧virtual information

Ps‧‧‧安全指標 Ps‧‧‧ Safety Indicators

第1圖係依據本發明實施例之快閃記憶體的系統架構示意圖。 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

第2圖係依據本發明實施例之存取介面與儲存單元的方塊圖。 2 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention.

第3圖係依據本發明實施例之一個存取子介面與多個儲存子單元的連接示意圖。 Figure 3 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention.

第4圖係依據本發明實施例的緩存器示意圖。 Figure 4 is a schematic diagram of a buffer in accordance with an embodiment of the present invention.

第5圖係依據本發明實施例的固態硬碟系統的原子寫入方法流程圖。 Fig. 5 is a flow chart showing an atomic writing method of a solid state hard disk system according to an embodiment of the present invention.

第6圖係依據本發明實施例的緩存器中的暫存資料示意圖。 Figure 6 is a schematic diagram of temporary storage data in a buffer according to an embodiment of the present invention.

第7A至7D圖係依據本發明實施例的掉電處理示意圖。 7A to 7D are schematic diagrams of power down processing according to an embodiment of the present invention.

以下說明係為完成發明的較佳實現方式，其目的在於描述本發明的基本精神，但並不用以限定本發明。實際的發明內容必須參考之後的權利要求範圍。 The following description is a preferred embodiment of the invention, which is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual inventive content must be referenced to the scope of the following claims.

必須了解的是，使用於本說明書中的”包含”、”包 括”等詞，係用以表示存在特定的技術特徵、數值、方法步驟、作業處理、元件以及/或組件，但並不排除可加上更多的技術特徵、數值、方法步驟、作業處理、元件、組件，或以上的任意組合。 It must be understood that the "include" and "packages" used in this specification "", etc., is used to mean that there are specific technical features, numerical values, method steps, work processes, components, and/or components, but does not exclude the addition of additional technical features, numerical values, method steps, and operational processing. A component, component, or any combination of the above.

於權利要求中使用如”第一”、"第二"、"第三"等詞係用來修飾權利要求中的元件，並非用來表示之間具有優先權順序，先行關係，或者是一個元件先於另一個元件，或者是執行方法步驟時的時間先後順序，僅用來區別具有相同名字的元件。 The words "first", "second", and "third" are used in the claims to modify the elements in the claims, and are not used to indicate a priority order, an advance relationship, or a component. Prior to another component, or the chronological order in which the method steps are performed, it is only used to distinguish components with the same name.

第1圖係依據本發明實施例之快閃記憶體的系統架構示意圖。快閃記憶體的系統架構10中包含處理單元110，用以寫入資料到儲存單元180中的指定位址，以及從儲存單元180中的指定位址讀取資料。詳細來說，處理單元110透過存取介面170寫入資料到儲存單元180中的指定位址，以及從儲存單元180中的指定位址讀取資料。處理單元110可使用多種方式實施，例如以專用硬體電路或通用硬體(例如，單一處理器、具平行處理能力的多處理器或其他具運算能力的處理器)，並且於載入及執行特定指令或軟體時實施如下所述的功能。處理單元110可包含運算邏輯單元(ALU,Arithmetic and Logic Unit)以及位移器(bit shifter)。運算邏輯單元負責執行布林運算(如AND、OR、NOT、NAND、NOR、XOR、XNOR等)，而位移器負責位移運算及位元旋轉。系統架構10使用數個電子訊號來協調處理單元110與儲存單元180間的資料與命令傳遞，包含資料線(data line)、時脈訊號(clock signal)與控制訊號(control signal)。資料線可用以傳遞命令、位址、讀出及寫入的資料；控制訊號線可用以傳遞晶片致能(chip enable,CE)、位址提取致能(address latch enable,ALE)、命令提取致能(command latch enable,CLE)、寫入致能(write enable,WE)等控制訊號。存取介面170可採用雙倍資料率(double data rate,DDR)通訊協定與儲存單元180溝通，例如，開放NAND快閃(open NAND flash interface,ONFI)、雙倍資料率開關(DDR toggle)或其他介面。處理單元110另可使用存取介面150透過指定通訊協定與主裝置160進行溝通，例如，通用序列匯流排(universal serial bus,USB)、先進技術附著(advanced technology attachment,ATA)、序列先進技術附著(serial advanced technology attachment,SATA)、快速周邊元件互聯(peripheral component interconnect express,PCI-E)或其他介面。 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention. The system architecture 10 of the flash memory includes a processing unit 110 for writing data to a specified address in the storage unit 180 and reading data from a specified address in the storage unit 180. In detail, the processing unit 110 writes the data to the specified address in the storage unit 180 through the access interface 170, and reads the data from the specified address in the storage unit 180. The processing unit 110 can be implemented in a variety of manners, such as dedicated hardware circuits or general purpose hardware (eg, a single processor, multi-processor with parallel processing capabilities, or other computing capable processor), and loaded and executed. The functions described below are implemented for specific instructions or software. Processing unit 110 may include an arithmetic logic unit (ALU, Arithmetic and Logic Unit) and a bit shifter. The arithmetic logic unit is responsible for performing Boolean operations (such as AND, OR, NOT, NAND, NOR, XOR, XNOR, etc.), while the shifter is responsible for displacement operations and bit rotation. The system architecture 10 uses a plurality of electronic signals to coordinate data and command transmission between the processing unit 110 and the storage unit 180, including a data line, a clock signal, and a control signal (control). Signal). The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transmit chip enable (CE), address latch enable (ALE), command extraction Control signals such as command latch enable (CLE) and write enable (WE). The access interface 170 can communicate with the storage unit 180 using a double data rate (DDR) protocol, such as an open NAND flash interface (ONFI), a double data rate switch (DDR toggle), or Other interface. The processing unit 110 can also use the access interface 150 to communicate with the main device 160 through a specified communication protocol, for example, a universal serial bus (USB), an advanced technology attachment (ATA), and an advanced technology. (serial advanced technology attachment, SATA), peripheral component interconnect express (PCI-E) or other interface.

儲存單元180可包含多個儲存子單元，每一個儲存子單元實施於一個晶粒(die)上，各自使用關聯的存取子介面與處理單元110進行溝通。第2圖係依據本發明實施例之存取介面與儲存單元的方塊圖。快閃記憶體10可包含j+1個存取子介面170_0至170_j，存取子介面又可稱為通道(channel)，每一個存取子介面連接i+1個儲存子單元。換句話說，i+1個儲存子單元共享一個存取子介面。例如，當快閃記憶體10包含4個通道(j=3)且每一個通道連接4個儲存單元(i=3)時，快閃記憶體10一共擁有16個儲存單元180_0_0至180_j_i。處理單元110可驅動存取子介面170_0至170_j中之一者，寫入資料至指定的儲存子單元。每個儲存子單元擁有獨立的晶片致能(CE,Chip Enable)控制訊 號。換句話說，當欲對指定的儲存子單元進行資料寫入時，需要驅動關聯的存取子介面致能此儲存子單元的晶片致能控制訊號。第3圖係依據本發明實施例之一個存取子介面與多個儲存子單元的連接示意圖。處理單元110可透過存取子介面170_0使用獨立的晶片致能控制訊號320_0_0至320_0_i來從連接的儲存子單元180_0_0至180_0_i中選擇出其中一者，接著，透過共享的資料線310_0寫入資料至選擇出的儲存子單元的指定位置。 The storage unit 180 can include a plurality of storage subunits, each of which is implemented on a die, each communicating with the processing unit 110 using an associated access sub-interface. 2 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention. The flash memory 10 may include j + 1 access sub-interfaces 170_0 to 170_j, the access sub-interfaces may also be referred to as channels, and each access sub-interface is connected to i + 1 storage sub-units. In other words, i + 1 storage subunits share an access subinterface. For example, when the flash memory 10 contains 4 channels ( j = 3 ) and each channel is connected to 4 storage units ( i = 3 ), the flash memory 10 has a total of 16 storage units 180_0_0 to 180_j_i. The processing unit 110 can drive one of the access sub-interfaces 170_0 to 170_j to write data to the designated storage sub-unit. Each storage subunit has a separate chip enable (CE, Chip Enable) control signal. In other words, when data is to be written to a specified storage subunit, it is necessary to drive the associated access subinterface to enable the wafer enable control signal of the storage subunit. Figure 3 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention. The processing unit 110 can select one of the connected storage sub-units 180_0_0 to 180_0_i through the access sub-interface 170_0 using the independent chip enable control signals 320_0_0 to 320_0_i, and then write the data through the shared data line 310_0 to Select the specified location of the storage subunit.

處理單元110可使用二個模式中之一者驅動存取介面170寫入資料，一為直接寫入(direct write)，另一為緩存寫入(buffered write)。當主裝置160發出的寫入命令(write command,CMD1)指示寫入超過一個頁面長度的資料時，處理單元110進入直接寫入模式。假設一個頁面的長度為16K位元組(bytes)：當處理單元110判斷主裝置160發出的寫入命令CMD1指示寫入超過16K位元組的資料時，使用直接寫入模式來寫入資料。於此須注意的是，如果寫入資料的長度不為頁面長度的倍數時(例如nxp的資料，其中n代表頁面數量，p代表一個頁面的資料長度)，不足的部分以虛擬資料(dummy data)填充。詳細來說，於直接寫入模式中，處理單元110發出控制訊號CTRL指示資料分配器(data dispatcher)120將資料DAT1直接傳送至存取介面170，並且發出命令CMD3驅動存取介面170把資料DAT1寫入至儲存單元180中的指定位址。當主裝置160發出的寫入命令CMD1指示寫入的資料長度少於一個頁面時，處理單元110進入緩存寫入模式。詳細來說，於緩存寫入模式中，處理單元 110發出控制訊號CTRL指示資料分配器120將資料DAT1傳送至緩存控制器130並且發出命令CMD2驅動緩存控制器130儲存資料DAT1至緩存器的指定區域。接著，當緩存器中的資料蒐集到一個頁面的長度後，處理單元110發出命令CMD2驅動緩存控制器130輸出緩存器中指定區域的資料DAT2至存取介面170，接著發出命令CMD3驅動存取介面170把資料DAT2寫入至儲存單元180中的指定位址。資料分配器120可以解多工器(de-multiplexer)實施，用以將存取介面150的資料線依據控制訊號CTRL耦接至緩存控制器130及存取介面170中之一者。第4圖係依據本發明實施例的緩存器示意圖。緩存器的區域配置相符於儲存單元180的設置。例如，緩存器包含多個區域400_0_0至400_0_i，每一個區域關連於第3圖所示的儲存子單元180_0_0至180_0_i。詳細來說，區域400_0_0暫存即將寫入至儲存子單元180_0_0中一個頁面的資料，區域400_0_1暫存即將寫入至儲存子單元180_0_1中一個頁面的資料，依此類推。每個區域可包含四個子區域，用以分別儲存四個單元(units)的資料，每個單元為固定長度，例如4K位元組。於此須注意的是，每個區域包含的子區域數目可依據儲存子單元的設計而調整，本發明並不因此受限。 The processing unit 110 can drive the access interface 170 to write data using one of two modes, one for direct write and the other for buffered write. When the write command (CMD1) issued by the host device 160 indicates that data exceeding one page length is written, the processing unit 110 enters the direct write mode. Assume that the length of one page is 16K bytes: When the processing unit 110 determines that the write command CMD1 issued by the host device 160 indicates that data of more than 16K bytes is written, the direct write mode is used to write data. It should be noted here that if the length of the written data is not a multiple of the page length (for example, nxp data, where n represents the number of pages, p represents the data length of a page), and the insufficient portion is dummy data (dummy data) )filling. In detail, in the direct write mode, the processing unit 110 issues a control signal CTRL to instruct the data dispatcher 120 to transfer the data DAT1 directly to the access interface 170, and issues a command CMD3 to drive the access interface 170 to the data DAT1. The write to the specified address in the storage unit 180. When the write command CMD1 issued by the host device 160 indicates that the length of the written data is less than one page, the processing unit 110 enters the buffer write mode. In detail, in the cache write mode, the processing unit 110 issues a control signal CTRL to instruct the data distributor 120 to transmit the data DAT1 to the cache controller 130 and issue a command CMD2 to drive the cache controller 130 to store the data DAT1 to the designated area of the buffer. Then, after the data in the buffer is collected to the length of one page, the processing unit 110 issues a command CMD2 to drive the cache controller 130 to output the data DAT2 of the designated area in the buffer to the access interface 170, and then issues a command CMD3 to drive the access interface. 170 writes the material DAT2 to the specified address in the storage unit 180. The data distributor 120 can be implemented as a de-multiplexer for coupling the data line of the access interface 150 to one of the cache controller 130 and the access interface 170 according to the control signal CTRL. Figure 4 is a schematic diagram of a buffer in accordance with an embodiment of the present invention. The area configuration of the buffer corresponds to the setting of the storage unit 180. For example, the buffer contains a plurality of regions 400_0_0 to 400_0_i, each of which is associated with the storage subunits 180_0_0 to 180_0_i shown in FIG. In detail, the area 400_0_0 temporarily stores data to be written to one page of the storage subunit 180_0_0, and the area 400_0_1 temporarily stores data to be written to one page of the storage subunit 180_0_1, and so on. Each zone may contain four sub-zones for storing data for four units, each of which is of fixed length, such as 4K bytes. It should be noted here that the number of sub-regions included in each region can be adjusted according to the design of the storage subunit, and the present invention is not limited thereby.

第5圖係依據本發明實施例的固態硬碟系統的原子寫入方法流程圖。於緩存寫入模式中，處理單元110載入並執行特定軟體程序(software routine)時實施此方法，用以將不足一個頁面的資料搬遷至緩存器400中的特定區域。首先，處理單元110透過存取介面150從主裝置160取得寫入命令 CMD1，包含是否為原子寫入(atomic write)的資訊(步驟S510)。當處理單元110判斷寫入命令CMD1為原子寫入時(步驟S520中”是”的路徑)，執行原子寫入程序(步驟S530至S570)，否則(步驟S520中”否”的路徑)，執行非原子寫入程序(步驟S581至S589)。 Fig. 5 is a flow chart showing an atomic writing method of a solid state hard disk system according to an embodiment of the present invention. In the cache write mode, the method is implemented when the processing unit 110 loads and executes a particular software routine to relocate less than one page of data to a particular area in the buffer 400. First, the processing unit 110 obtains a write command from the host device 160 through the access interface 150. CMD1 contains information on whether or not it is atomic write (step S510). When the processing unit 110 judges that the write command CMD1 is atomic write (the path of YES in step S520), the atomic write program is executed (steps S530 to S570), otherwise (the path of "NO" in step S520), execution is performed. The non-atomic writing program (steps S581 to S589).

非原子寫入程序反覆執行一個迴圈，用以逐區塊寫入緩存器400中的可用空間。於每一回合中，處理單元110指示資料分配器120將資料DAT1傳送至緩存控制器130，以及驅動緩存控制器130從緩存器中的下一個可用子區域儲存一個區塊的資料DAT1(步驟S581)，以及，於成功儲存資料後，緩存控制器130更新安全指標用以指向此子區域的結束位址(步驟S583)。於此須注意的是，安全指標可儲存於緩存控制器130中的一個寄存器(register)。安全指標的作用將於後續段落描述。接著，判斷是否蒐集完一個頁面的資料(步驟S585)。於步驟S585，處理單元110可判斷此子區域是否為一個區域的最後一個子區域，如果是，則代表蒐集完一個頁面的資料。當蒐集完一個頁面的資料(步驟S585中”是”的路徑)，處理單元110驅動緩存控制器130輸出此頁面的資料DAT2至存取介面170以及驅動存取介面170將此頁面的資料DAT2寫入儲存單元180中的指定位址，例如指定儲存子單元的指定區塊(步驟S587)，接著，判斷是否儲存完寫入命令CMD1指示的所有資料(步驟S589)。當尚未蒐集完一個頁面的資料(步驟S585中”否”的路徑)，處理單元110判斷是否儲存完寫入命令CMD1指示的所有資料(步驟S589)。當尚未儲存完寫入命令CMD1指示的所有資料時(步驟 S589中”否”的路徑)，繼續從緩存器中的下一個可用子區域儲存一個區塊的資料(步驟S581)；否則，結束整個處理。 The non-atomic write program repeatedly executes a loop for writing the free space in the buffer 400 block by block. In each round, the processing unit 110 instructs the data distributor 120 to transfer the material DAT1 to the cache controller 130, and drives the cache controller 130 to store the data DAT1 of one block from the next available sub-area in the buffer (step S581). And, after successfully storing the data, the cache controller 130 updates the security indicator to point to the end address of the sub-area (step S583). It should be noted here that the security indicator can be stored in a register in the cache controller 130. The role of safety indicators will be described in subsequent paragraphs. Next, it is judged whether or not the material of one page is collected (step S585). In step S585, the processing unit 110 may determine whether the sub-area is the last sub-area of an area, and if so, the data of the collected one page. When the data of one page is collected (the path of "YES" in step S585), the processing unit 110 drives the cache controller 130 to output the data DAT2 of the page to the access interface 170 and the drive access interface 170 to write the data DAT2 of the page. The specified address in the storage unit 180, for example, specifies a designated block of the storage subunit (step S587), and then, it is judged whether or not all the materials indicated by the write command CMD1 are stored (step S589). When the material of one page has not been collected (the path of NO in step S585), the processing unit 110 determines whether or not all the materials indicated by the write command CMD1 are stored (step S589). When all the data indicated by the write command CMD1 has not been stored (step The path of "NO" in S589) continues to store the data of one block from the next available sub-area in the buffer (step S581); otherwise, the entire process is ended.

原子寫入程序首先判斷寫入命令CMD1是否觸發跨頁面儲存(步驟S530)。於步驟S530，處理單元可判斷緩存器中目前區域中的可用子區域數目是否小於寫入命令CMD1指示的資料單元數目。若是，則代表若不做任何處理，寫入命令CMD1將使資料拆開儲存至緩存器中的二個區域。 The atomic write program first determines whether the write command CMD1 triggers cross-page storage (step S530). In step S530, the processing unit may determine whether the number of available sub-areas in the current area in the buffer is less than the number of data units indicated by the write command CMD1. If so, it means that if no processing is done, the write command CMD1 will cause the data to be unpacked and stored in the two areas in the buffer.

當判斷將觸發跨頁面儲存時(步驟S530中”是”的路徑)，處理單元110驅動緩存控制器130填充虛擬資料(dummy data)至目前區域的所有可用子區域(步驟S541)，驅動緩存控制器130輸出此頁面的資料DAT2至存取介面170以及驅動存取介面170將此頁面的資料DAT2寫入儲存單元180中的指定位址，例如指定儲存子單元的指定區塊(步驟S543)，以及指示資料分配器120將資料DAT1傳送至緩存控制器130，以及驅動緩存控制器130從緩存器中的下一個區域的第一個子區域開始儲存資料DAT1(步驟S545)，以及，於成功儲存資料後，緩存控制器130更新安全指標用以指向資料DAT1所儲存的最後一個子區域的結束位址(步驟S570)。 When it is judged that the cross-page storage will be triggered (the path of YES in step S530), the processing unit 110 drives the cache controller 130 to fill the dummy data to all available sub-regions of the current region (step S541), and drives the cache control. The device 130 outputs the data DAT2 of the page to the access interface 170 and the drive access interface 170 to write the data DAT2 of the page to a specified address in the storage unit 180, for example, designating a specified block of the storage subunit (step S543). And instructing the data distributor 120 to transfer the data DAT1 to the cache controller 130, and driving the cache controller 130 to store the data DAT1 from the first sub-area of the next area in the buffer (step S545), and to successfully store After the data, the cache controller 130 updates the security indicator to point to the end address of the last sub-area stored in the data DAT1 (step S570).

當判斷不觸發跨頁面儲存時(步驟S530中”否”的路徑)，指示資料分配器120將資料DAT1傳送至緩存控制器130，以及驅動緩存控制器130從緩存器中的目前區域的下一個可用子區域開始儲存資料DAT1(步驟S550)，以及，判斷是否蒐集完一個頁面的資料(步驟S561)。步驟S561的技術內容可參考步驟S585的說明，為求說明書簡潔，不再贅述。當蒐集完一個頁面 的資料(步驟S561中”是”的路徑)，處理單元110驅動緩存控制器130輸出此頁面的資料DAT2至存取介面170以及驅動存取介面170將此頁面的資料DAT2寫入儲存單元180中的指定位址(步驟S563)。當尚未蒐集完一個頁面的資料時(步驟S561中”否”的路徑)，緩存控制器130於成功儲存資料後更新安全指標用以指向資料DAT1所儲存的最後一個子區域的結束位址(步驟S570)。 When it is judged that the cross-page storage is not triggered (NO in step S530), the data distributor 120 is instructed to transfer the material DAT1 to the cache controller 130, and the drive cache controller 130 is driven from the next area of the current area in the buffer. The available sub-areas starts storing the data DAT1 (step S550), and judges whether or not the data of one page is collected (step S561). For the technical content of step S561, refer to the description of step S585. For the sake of brevity of the description, details are not described herein. When collecting a page The data (the path of "YES" in step S561), the processing unit 110 drives the cache controller 130 to output the data DAT2 of the page to the access interface 170 and the drive access interface 170 to write the data DAT2 of the page into the storage unit 180. The specified address (step S563). When the data of one page has not been collected (the path of NO in step S561), the cache controller 130 updates the security indicator to point to the end address of the last sub-area stored in the data DAT1 after successfully storing the data (steps) S570).

於步驟S543、S563及S587中更包含當此頁面的資料DAT2寫入儲存單元180中的指定位址後，清除安全指標。 In steps S543, S563, and S587, the security indicator is cleared after the data DAT2 of the page is written to the specified address in the storage unit 180.

以下舉出實例來說明如上所述的方法。假設主裝置160發出多個命令CMD1給處理單元110，希望依序原子寫入2個單元的資料、非原子寫入1個單元的資料、原子寫入2個單元的資料、非原子寫入3個單元的資料以及原子寫入2個單元的資料：第6圖係依據本發明實施例的緩存器中的暫存資料示意圖。為處理第一個命令，處理單元110執行步驟S550及S570，用以將2個單元的資料610寫入緩存器中第一個區域中的前二個子區域，並且將安全指標更新為指向第一個區域中的第二個子區域的結束位址。為處理第二個命令，處理單元110執行步驟S581及S583，用以將1個單元的資料620寫入緩存器中第一個區域中的第三個子區域，並且將安全指標更新為指向第一個區域中的第三個子區域的結束位址。為處理第三個命令，處理單元110執行步驟S530時發現此命令將觸發跨頁面儲存，接著，執行步驟S541及S543進行虛擬資料630的填充以及驅動緩存控制器130及存取介面170，用以將第一個區域中的資料610至630寫入儲存子單元180_0_0中的可用區塊，接著，執行步驟S545 及S570用以將2個單元的資料640寫入緩存器中第二個區域中的前二個子區域，並且將安全指標更新為指向第一個區域中的第二個子區域的結束位址。為處理第四個命令，處理單元110先執行步驟S581至S589的迴圈二次，用以將前2個單元的資料650a寫入緩存器中第二個區域中的後二個子區域，以及驅動緩存控制器130及存取介面170，用以將第二個區域中的資料640至640a寫入儲存子單元180_0_1中的可用區塊。之後，處理單元110先執行步驟S581至S589的迴圈一次，用以將餘下1個單元的資料650b寫入緩存器中第三個區域中的第一個子區域，並且將安全指標更新為指向第三個區域中的第一個子區域的結束位址。為處理第五個命令，處理單元110執行步驟S581及S583，用以將2個單元的資料660寫入緩存器中第三個區域中的第二至三個子區域，並且將安全指標更新為指向第三個區域中的第三個子區域的結束位址。 The following examples are given to illustrate the method as described above. It is assumed that the main device 160 issues a plurality of commands CMD1 to the processing unit 110, and it is desirable to write data of two units in sequence, non-atomic data of one unit, data of two units, and non-atomic writing. The data of the units and the data of the two units written by the atom: FIG. 6 is a schematic diagram of the temporary data in the buffer according to the embodiment of the present invention. To process the first command, the processing unit 110 performs steps S550 and S570 to write the data 610 of the two cells into the first two sub-regions in the first region of the buffer, and updates the security indicator to point to the first The ending address of the second subregion in the region. To process the second command, the processing unit 110 performs steps S581 and S583 to write the data 620 of one unit into the third sub-area in the first area of the buffer, and updates the security indicator to point to the first The end address of the third subregion in the region. To process the third command, the processing unit 110 executes step S530 and finds that the command will trigger cross-page storage. Then, steps S541 and S543 are performed to fill the virtual data 630 and drive the cache controller 130 and the access interface 170 for The data 610 to 630 in the first region are written into the available blocks in the storage subunit 180_0_0, and then, step S545 is performed. And S570 is configured to write the data 640 of the two units into the first two sub-areas in the second area of the buffer, and update the security indicator to point to the end address of the second sub-area in the first area. To process the fourth command, the processing unit 110 first performs the loops of steps S581 to S589 twice to write the data 650a of the first two cells into the last two sub-regions in the second region of the buffer, and to drive The cache controller 130 and the access interface 170 are configured to write the data 640 to 640a in the second area to the available blocks in the storage sub-unit 180_0_1. Thereafter, the processing unit 110 first performs the loop of steps S581 to S589 once to write the data 650b of the remaining one unit into the first sub-area of the third area in the buffer, and updates the security indicator to point. The end address of the first subregion in the third region. To process the fifth command, the processing unit 110 performs steps S581 and S583 to write the data 660 of the two cells into the second to third sub-regions of the third region in the buffer, and updates the security indicator to point. The ending address of the third subregion in the third region.

然而，快閃記憶體於運作時可能發生意外掉電，系統架構10中另包含掉電處理電路(power-loss handling circuit)140，用以持續偵測是否發生掉電的情況。一旦偵測到掉電，掉電處理電路140使用剩餘電量來發出命令CMD4驅動緩存控制器130，用以將儲存於目前區域中的開始位址至安全指標指向的位址間的資料輸出至存取介面170，並且，發出命令CMD5驅動存取介面170，用以寫入目前區域中的資料至相應儲存子單元中的可用區塊。 However, the flash memory may be accidentally powered down during operation, and the system architecture 10 further includes a power-loss handling circuit 140 for continuously detecting whether a power failure occurs. Once the power failure is detected, the power-down processing circuit 140 uses the remaining power to issue a command CMD4 to drive the cache controller 130 to output the data stored between the start address in the current area and the address pointed to by the security indicator to the memory. The interface 170 is fetched, and a command CMD5 is issued to drive the access interface 170 for writing data in the current area to the available blocks in the corresponding storage subunit.

以下舉出數個情境來說明如上所述的掉電處理。搭配參考第6圖所示的命令處理說明。第7A圖係依據本發明實 施例的掉電處理示意圖。於第一個情境中，於處理第二個命令期間，掉電處理電路140偵測到發生掉電的情況，發出命令CMD4驅動緩存控制器130，用以將第一個區域中的開始位址至安全指標Ps指向的位址間的資料610輸出至存取介面170，並且，發出命令CMD5驅動存取介面170，用以寫入資料610至儲存子單元180_0_0中的可用區塊，使得第一個命令指示的原子寫入可成功地執行。第7B圖係依據本發明實施例的掉電處理示意圖。於第二個情境中，於處理第三個命令指示的第二個單元的資料的原子寫入期間，掉電處理電路140偵測到發生掉電的情況，發出命令CMD4驅動緩存控制器130，但由於安全指標Ps還沒有被更新，因此第二個區域中的所有資料都不會輸出至存取介面170，使得第三個命令指示的原子寫入全部失敗。第7C圖係依據本發明實施例的掉電處理示意圖。於第三個情境中，於處理第四個命令指示的第二個單元的資料的非原子寫入期間，掉電處理電路140偵測到發生掉電的情況，發出命令CMD4驅動緩存控制器130，用以將第二個區域中的開始位址至安全指標Ps指向的位址間的資料640及650a_1輸出至存取介面170，並且，發出命令CMD5驅動存取介面170，用以寫入資料640及650a_1至儲存子單元180_0_1中的可用區塊，使得第三個命令指示的原子寫入可成功地執行。第7D圖係依據本發明實施例的掉電處理示意圖。於第四個情境中，於處理第五個命令期間，掉電處理電路140偵測到發生掉電的情況，發出命令CMD4驅動緩存控制器130，用以將第三個區域中的開始位址至安全指標Ps指向的位址間的資料650b輸出至存取介面170，並且， 發出命令CMD5驅動存取介面170，用以寫入資料650b至儲存子單元180_0_2中的可用區塊，使得第五個命令指示的原子寫入完全失敗。 Several scenarios are given below to illustrate the power down process as described above. Refer to the command processing instructions shown in Figure 6. Figure 7A is based on the present invention Schematic diagram of the power down process of the embodiment. In the first scenario, during the processing of the second command, the power-down processing circuit 140 detects that a power failure has occurred, and issues a command CMD4 to drive the cache controller 130 for starting the address in the first region. The data 610 to the address pointed to by the security indicator Ps is output to the access interface 170, and a command CMD5 is issued to drive the access interface 170 for writing the data 610 to the available block in the storage sub-unit 180_0_0, so that the first The atomic writes indicated by the commands can be successfully executed. FIG. 7B is a schematic diagram of power-down processing according to an embodiment of the present invention. In the second scenario, during the atomic write of the data of the second unit indicated by the third command, the power-down processing circuit 140 detects that a power failure has occurred, and issues a command CMD4 to drive the cache controller 130. However, since the security indicator Ps has not been updated, all the data in the second area is not output to the access interface 170, so that the atomic writes indicated by the third command all fail. FIG. 7C is a schematic diagram of power-down processing according to an embodiment of the present invention. In the third scenario, during the non-atomic writing of the data of the second unit indicated by the fourth command, the power-down processing circuit 140 detects that a power failure has occurred, and issues a command CMD4 to drive the cache controller 130. And outputting the data 640 and 650a_1 between the start address in the second area to the address pointed to by the security indicator Ps to the access interface 170, and issuing a command CMD5 to drive the access interface 170 for writing data. 640 and 650a_1 to the available blocks in the storage sub-unit 180_0_1 such that the atomic write indicated by the third command can be successfully executed. FIG. 7D is a schematic diagram of power-down processing according to an embodiment of the present invention. In the fourth scenario, during the processing of the fifth command, the power-down processing circuit 140 detects that a power failure has occurred, and issues a command CMD4 to drive the cache controller 130 to start the address in the third region. The data 650b between the addresses pointed to by the security indicator Ps is output to the access interface 170, and The command CMD5 is driven to access the interface 170 for writing the data 650b to the available block in the storage sub-unit 180_0_2 such that the atomic write indicated by the fifth command fails completely.

雖然第1至3圖中包含了以上描述的元件，但不排除在不違反發明的精神下，使用更多其他的附加元件，已達成更佳的技術效果。此外，雖然第5圖的處理步驟採用特定的順序來執行，但是在不違反發明精神的情況下，熟習此技藝人士可以在達到相同效果的前提下，修改這些步驟間的順序，所以，本發明並不侷限於僅使用如上所述的順序。 Although the above-described elements are included in FIGS. 1 to 3, it is not excluded that more other additional elements are used without departing from the spirit of the invention, and a better technical effect has been achieved. In addition, although the processing steps of FIG. 5 are performed in a specific order, without departing from the spirit of the invention, those skilled in the art can modify the order among the steps while achieving the same effect, so the present invention It is not limited to using only the order as described above.

雖然本發明使用以上實施例進行說明，但需要注意的是，這些描述並非用以限縮本發明。相反地，此發明涵蓋了熟習此技藝人士顯而易見的修改與相似設置。所以，申請權利要求範圍須以最寬廣的方式解釋來包含所有顯而易見的修改與相似設置。 Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements that are apparent to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest form to include all obvious modifications and similar arrangements.

S510~S589‧‧‧方法步驟 S510~S589‧‧‧ method steps

Claims (16)

一種固態硬碟系統的原子寫入方法，由一處理單元執行，包含：接收一原子寫入命令，指示寫入少於一頁面長度的一第一資料至一儲存單元；判斷上述資料將觸發一緩存器中之跨頁面儲存時，填充一虛擬資料至上述緩存器中之一第一區域的所有可用子區域；判斷上述資料將觸發一緩存器中之跨頁面儲存時，儲存上述第一資料至上述緩存器中之一第二區域；以及成功儲存上述第一資料至上述緩存器中之上述第二區域後，更新一安全指標用以指向上述第一資料所儲存的上述第二區域的最後一個子區域的結束位址。 An atomic writing method for a solid state hard disk system is executed by a processing unit, comprising: receiving an atomic write command, instructing to write a first data to a storage unit that is less than a page length; determining that the data triggers a When storing across the page in the buffer, filling a virtual data into all available sub-areas of one of the first areas of the buffer; determining that the data will trigger a cross-page storage in a buffer, storing the first data to a second area of the buffer; and after successfully storing the first data to the second area in the buffer, updating a security indicator for pointing to the last of the second area stored by the first data The end address of the subregion. 如申請專利範圍第1項所述的固態硬碟系統的原子寫入方法，其中，上述第一區域的長度組態為上述頁面長度，以及上述第二區域的長度組態為上述頁面長度。 The atomic writing method of the solid state hard disk system according to claim 1, wherein the length of the first area is configured as the length of the page, and the length of the second area is configured as the length of the page. 如申請專利範圍第1項所述的固態硬碟系統的原子寫入方法，其中，上述緩存器中之跨頁面儲存係指若不做任何處理，上述第一資料將拆開儲存至上述第一區域及上述第二區域。 The atomic writing method of the solid state hard disk system according to claim 1, wherein the cross-page storage in the buffer means that the first data is unpacked and stored to the first one if no processing is performed. Area and the above second area. 如申請專利範圍第1項所述的固態硬碟系統的原子寫入方法，更包含： 於填充上述虛擬資料至上述緩存器中之上述第一區域的所有可用子區域後，寫入上述第一區域的資料至上述儲存單元。 The atomic writing method of the solid state hard disk system according to claim 1, further comprising: After filling the virtual data to all available sub-areas of the first area in the buffer, writing the data of the first area to the storage unit. 如申請專利範圍第1項所述的固態硬碟系統的原子寫入方法，更包含：於成功儲存上述資料至上述緩存器中之上述第二區域前發生掉電，不寫入上述第一資料至上述儲存單元。 The atomic writing method of the solid state hard disk system according to claim 1, further comprising: powering down before successfully storing the data to the second area in the buffer, not writing the first data To the above storage unit. 如申請專利範圍第1項所述的固態硬碟系統的原子寫入方法，更包含：於成功儲存上述第一資料至上述緩存器中之上述第二區域後，接收一非原子寫入命令，指示寫入少於上述頁面長度的一第二資料至上述儲存單元；儲存上述第二資料至上述第二區域中接續於上述第一資料之後的一子區域。 The atomic writing method of the solid state hard disk system according to claim 1, further comprising: receiving a non-atomic write command after successfully storing the first data to the second region in the buffer, Instructing to write a second data that is less than the length of the page to the storage unit; storing the second data to a sub-area subsequent to the first data in the second area. 如申請專利範圍第6項所述的固態硬碟系統的原子寫入方法，更包含：於成功儲存上述第二資料至上述第二區域前發生掉電，將上述第二區域中的開始位址至上述安全指標指向的位址間的資料寫入上述儲存單元。 The atomic writing method of the solid state hard disk system according to claim 6, further comprising: generating a power failure before successfully storing the second data to the second area, and starting the address in the second area The data between the addresses pointed to by the above security indicators is written into the above storage unit. 如申請專利範圍第7項所述的固態硬碟系統的原子寫入方法，其中，上述第二區域中的開始位址至上述安全指標指向的位址間的資料包含上述第一資料。 The atomic writing method of the solid state hard disk system according to claim 7, wherein the data between the start address in the second area and the address pointed by the security indicator includes the first data. 一種固態硬碟系統的原子寫入裝置，包含：一緩存控制器，透過一存取介面耦接至一儲存單元；以及 一處理單元，從一主裝置接收一原子寫入命令，指示寫入少於一頁面長度的一第一資料至上述儲存單元；判斷上述資料將觸發上述緩存器中之跨頁面儲存時，驅動上述緩存控制器填充一虛擬資料至上述緩存器中之一第一區域的所有可用子區域；判斷上述資料將觸發一緩存器中之跨頁面儲存時，驅動上述緩存控制器儲存上述第一資料至上述緩存器中之一第二區域；其中，成功儲存上述第一資料至上述緩存器中之上述第二區域後，上述緩存控制器更新一安全指標用以指向上述第一資料所儲存的上述第二區域的最後一個子區域的結束位址。 An atomic writing device for a solid state hard disk system, comprising: a cache controller coupled to a storage unit through an access interface; a processing unit, receiving an atomic write command from a master device, instructing to write a first data of less than one page length to the storage unit; determining that the data triggers cross-page storage in the buffer, driving the above The cache controller fills a virtual data to all available sub-areas of one of the first areas of the buffer; determining that the data triggers a cross-page storage in a buffer, driving the cache controller to store the first data to the foregoing a second area of the buffer; wherein, after successfully storing the first data to the second area in the buffer, the cache controller updates a security indicator for pointing to the second stored in the first data The ending address of the last subregion of the region. 如申請專利範圍第9項所述的固態硬碟系統的原子寫入裝置，其中，上述緩存控制器包含上述緩存器，上述第一區域的長度組態為上述頁面長度，以及上述第二區域的長度組態為上述頁面長度。 The atomic writing device of the solid state hard disk system of claim 9, wherein the cache controller comprises the buffer, the length of the first area is configured as the length of the page, and the second area is The length is configured as the above page length. 如申請專利範圍第9項所述的固態硬碟系統的原子寫入裝置，其中，上述緩存器中之跨頁面儲存係指若不做任何處理，上述第一資料將拆開儲存至上述第一區域及上述第二區域。 The atomic writing device of the solid state hard disk system according to claim 9, wherein the cross-page storage in the buffer means that the first data is unpacked and stored to the first one if no processing is performed. Area and the above second area. 如申請專利範圍第9項所述的固態硬碟系統的原子寫入裝置，其中，於填充上述虛擬資料至上述緩存器中之上述第一區域的所有可用子區域後，上述處理單元驅動上述緩存控制器輸出上述第一區域的資料至上述存取介面，以及驅動上述存取介面寫入上述第一區域的資料至上述儲存單 元。 The atomic writing device of the solid state hard disk system of claim 9, wherein the processing unit drives the cache after filling the virtual data into all available sub-regions of the first region in the buffer The controller outputs the data of the first area to the access interface, and drives the access interface to write the data of the first area to the storage list yuan. 如申請專利範圍第9項所述的固態硬碟系統的原子寫入裝置，其中，於成功儲存上述資料至上述緩存器中之上述第二區域前發生掉電，不寫入上述第一資料至上述儲存單元。 The atomic writing device of the solid state hard disk system according to claim 9, wherein the power is lost before the storing of the data to the second area in the buffer, and the first data is not written The above storage unit. 如申請專利範圍第9項所述的固態硬碟系統的原子寫入裝置，其中，於成功儲存上述第一資料至上述緩存器中之上述第二區域後，上述處理單元從上述主裝置接收一非原子寫入命令，指示寫入少於上述頁面長度的一第二資料至上述儲存單元；驅動上述緩存控制器儲存上述第二資料至上述第二區域中接續於上述第一資料之後的一子區域。 The atomic writing device of the solid state hard disk system of claim 9, wherein the processing unit receives a first region from the buffer after successfully storing the first data to the second region in the buffer a non-atomic write command, instructing to write a second data that is less than the length of the page to the storage unit; driving the cache controller to store the second data to a second one of the second area that is subsequent to the first data region. 如申請專利範圍第14項所述的固態硬碟系統的原子寫入裝置，更包含：一掉電處理電路，耦接於上述緩存控制器及上述存取介面，於成功儲存上述第二資料至上述第二區域前偵測到發生掉電，驅動上述緩存控制器，用以輸出上述第二區域中的開始位址至上述安全指標指向的位址間的資料至上述存取介面；以及驅動上述存取介面，用以寫入上述第二區域中的開始位址至上述安全指標指向的位址間的資料至上述儲存單元。 The atomic writing device of the solid state hard disk system of claim 14, further comprising: a power down processing circuit coupled to the cache controller and the access interface to successfully store the second data to Detecting a power failure before detecting the second area, driving the cache controller to output data between the start address in the second area to the address pointed by the security indicator to the access interface; and driving the foregoing And an access interface for writing data between the start address in the second area to the address pointed by the security indicator to the storage unit. 如申請專利範圍第15項所述的固態硬碟系統的原子寫入裝置，其中，上述第二區域中的開始位址至上述安全指標指向的位址間的資料包含上述第一資料。 The atomic writing device of the solid state hard disk system according to claim 15, wherein the data between the start address in the second area and the address pointed by the security indicator includes the first data.
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