TWI589197B - Circuit structure - Google Patents
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- TWI589197B TWI589197B TW104139270A TW104139270A TWI589197B TW I589197 B TWI589197 B TW I589197B TW 104139270 A TW104139270 A TW 104139270A TW 104139270 A TW104139270 A TW 104139270A TW I589197 B TWI589197 B TW I589197B
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- 239000004020 conductor Substances 0.000 claims description 110
- 239000000758 substrate Substances 0.000 claims description 41
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 15
- 230000008054 signal transmission Effects 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
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Description
本發明係關於一種電路結構，特別是一種電路板的電路結構。The present invention relates to a circuit structure, and more particularly to a circuit board circuit structure.
隨著高速數位化通訊時代的來臨，高頻化電子產品、電腦高速訊號硬體和軟體的快速發展以及工作頻率增加與頻寬要求變高與積體電路快速發展，因而對於訊號的工作頻率與頻寬要求越來越高。當電信問題受到傳輸速度的提升伴隨而來，加上互連元件產品如連接器、線纜或印刷電路板縮小化使電路的佈局越來越緊密，造成訊號完整性(Signal Integrity, SI)、電磁干擾(Electromagnetic Interference, EMI)、電磁相容(Electromagnetic Compatibility, EMC)或是電源完整性(Power Integrity, PI)的設計優劣足以決定傳輸訊號品質優劣。With the advent of the high-speed digital communication era, the rapid development of high-frequency electronic products, computer high-speed signal hardware and software, as well as increased operating frequency and bandwidth requirements and rapid development of integrated circuits, thus the operating frequency of the signal The bandwidth requirements are getting higher and higher. When telecom problems are accompanied by an increase in transmission speed, coupled with the shrinking of interconnect components such as connectors, cables or printed circuit boards, the layout of the circuits is getting tighter, resulting in Signal Integrity (SI), The design of Electromagnetic Interference (EMI), Electromagnetic Compatibility (EMC) or Power Integrity (PI) is sufficient to determine the quality of the transmitted signal.
然而在以上各種問題中，又以訊號完整性的問題最為嚴重，因此在訊號傳遞的元件中訊號完整性的設計也成為一個極需解決的問題。進一步來說，當傳輸訊號的頻率愈來愈高，電路結構內用以傳輸訊號的導電線之阻抗(impedance)及導體柱之阻抗就愈需要相互匹配(match)，以令訊號在電路板中經由導體柱被傳遞時能不被破壞，進而有效的改善訊號的完整性。反之，當導體柱之阻抗與導電線之阻抗不匹配(mismatch)時，訊號在透過導體柱與導電線穿層傳遞時，容易因為傳輸路徑上的阻抗不同而造成訊號反射的問題，進而導致訊號不必要的傳輸消耗。當所傳遞的訊號速度愈快時，因訊號反射所衍生的訊號消耗的問題就愈加嚴重。However, in the above various problems, the problem of signal integrity is the most serious, so the design of signal integrity in the signal transmission component has become an extremely problem to be solved. Further, as the frequency of the transmitted signal becomes higher and higher, the impedance of the conductive line for transmitting the signal in the circuit structure and the impedance of the conductor post need to match each other so that the signal is in the circuit board. It can be transmitted without being damaged when it is transmitted through the conductor post, thereby effectively improving the integrity of the signal. Conversely, when the impedance of the conductor post is mismatched with the impedance of the conductive line, the signal is easily transmitted due to the impedance difference on the transmission path when transmitting through the conductor post and the conductive line, thereby causing the signal to be signaled. Unnecessary transmission consumption. As the speed of the transmitted signal is faster, the problem of signal consumption due to signal reflection becomes more serious.
鑒於以上的問題，本發明揭露一種電路結構，有助於改善導體柱之阻抗與導電線之阻抗不匹配的問題。In view of the above problems, the present invention discloses a circuit structure that contributes to the problem of improving the impedance mismatch between the impedance of the conductor post and the conductive line.
本發明所揭露的電路結構包含一基板、至少一導體柱、至少一第一導電線以及至少一第二導電線。基板具有相對的一第一表面和一第二表面。導體柱設置於基板。第一導電線設置於基板的第一表面，且第一導電線電性連接於導體柱。第二導電線設置於基板內，且第二導電線電性連接於導體柱。基板更具有鄰近導體柱的至少一第一穿孔。第一穿孔自基板的第一表面貫穿至第二表面。第一穿孔包含相連通的一第一穿孔段和一第二穿孔段。第一穿孔段較第二穿孔段更靠近基板的第一表面，且第二穿孔段的孔徑大於第一穿孔段的孔徑。The circuit structure disclosed in the present invention comprises a substrate, at least one conductor post, at least one first conductive line and at least one second conductive line. The substrate has a first surface and a second surface opposite to each other. The conductor post is disposed on the substrate. The first conductive line is disposed on the first surface of the substrate, and the first conductive line is electrically connected to the conductor post. The second conductive line is disposed in the substrate, and the second conductive line is electrically connected to the conductor post. The substrate further has at least one first perforation adjacent to the conductor post. The first perforation extends from the first surface of the substrate to the second surface. The first perforation includes a first perforated section and a second perforated section that are in communication. The first perforated section is closer to the first surface of the substrate than the second perforated section, and the aperture of the second perforated section is larger than the aperture of the first perforated section.
根據本發明所揭露的電路結構，第一穿孔中孔徑不等的第一穿孔段與第二穿孔段分別對應導體柱之上、下半部，藉此可讓導體柱之上半部之阻抗匹配於第一導電線之阻抗與第二導電線之阻抗，使得第一穿孔能有效減少訊號能量因阻抗不匹配所造成的能量損耗，進而維持訊號的完整性以改善訊號的傳輸品質。According to the circuit structure disclosed in the present invention, the first perforated section and the second perforated section of the first perforation having different apertures respectively correspond to the upper and lower half of the conductor post, thereby matching the impedance of the upper half of the conductor post. The impedance of the first conductive line and the impedance of the second conductive line enable the first through hole to effectively reduce the energy loss caused by the impedance mismatch of the signal energy, thereby maintaining the integrity of the signal to improve the transmission quality of the signal.
此外，由於第二穿孔段的孔徑大於第一穿孔段的孔徑，故導體柱下半部的阻抗會大於上半部的阻抗。藉此能夠有效避免訊號傳輸到導體柱下半部並轉而傳輸至阻抗較小之第二導電線，進而避免能量損失。In addition, since the aperture of the second perforated section is larger than the aperture of the first perforated section, the impedance of the lower half of the conductor post is greater than the impedance of the upper half. Thereby, the signal can be effectively prevented from being transmitted to the lower half of the conductor post and transferred to the second conductive line with less impedance, thereby avoiding energy loss.
以上之關於本揭露內容之說明及以下之實施方式之說明係用以示範與解釋本發明之精神與原理，並且提供本發明之專利申請範圍更進一步之解釋。The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.
以下在實施方式中詳細敘述本發明之詳細特徵以及優點，其內容足以使任何熟習相關技藝者了解本發明之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之實施例進一步詳細說明本發明之觀點，但非以任何觀點限制本發明之範疇。The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.
請同時參照圖1至圖4。圖1為根據本發明第一實施例之電路結構的俯視示意圖。圖2為圖1之電路結構沿線2-2剖切的剖切示意圖。圖3為圖1之電路結構的第一穿孔的俯視示意圖。圖4為圖3之第一穿孔的剖切示意圖。在本實施例中，電路結構1包含一基板10、一第一導體柱20、一第二導體柱30、二第一導電線40、二第二導電線50和多個接地柱60。接地柱60、導體柱20、30以及導電線40、50的數量並非用以限制本發明，其可視電路結構1的設計需求任意調整。Please refer to FIG. 1 to FIG. 4 at the same time. 1 is a top plan view showing a circuit structure in accordance with a first embodiment of the present invention. 2 is a cross-sectional view of the circuit structure of FIG. 1 taken along line 2-2. 3 is a top plan view of the first perforation of the circuit structure of FIG. 1. 4 is a cross-sectional view of the first perforation of FIG. 3. In this embodiment, the circuit structure 1 includes a substrate 10, a first conductor post 20, a second conductor post 30, two first conductive lines 40, two second conductive lines 50, and a plurality of ground posts 60. The number of grounding posts 60, conductor posts 20, 30, and conductive lines 40, 50 are not intended to limit the invention, and can be arbitrarily adjusted to the design requirements of the circuit structure 1.
基板10例如可以是多層電木板、多層玻璃纖維板或多層塑膠板。基板10具有相對的一第一表面110和一第二表面120。第一導體柱20和第二導體柱30設置於基板10並且相分離。詳細來說，第一導體柱20和第二導體柱30皆自基板10的第一表面110貫穿至第二表面120，並且第一導體柱20和第二導體柱30的二端皆自第一表面110顯露於外。在本實施例中，第一導體柱20和第二導體柱30皆可以是由實心柱狀的導體製成，但不限於此。在其他實施例中，第一導體柱和第二導體柱皆可以是由空心柱狀的導體製成，且於空心的導體柱內灌入膠體。The substrate 10 can be, for example, a multilayer electric wood board, a multi-layer fiberglass board or a multi-layer plastic board. The substrate 10 has a first surface 110 and a second surface 120 opposite to each other. The first conductor post 20 and the second conductor post 30 are disposed on the substrate 10 and are separated. In detail, both the first conductor post 20 and the second conductor post 30 penetrate from the first surface 110 of the substrate 10 to the second surface 120, and both ends of the first conductor post 20 and the second conductor post 30 are from the first Surface 110 is exposed. In the present embodiment, the first conductor post 20 and the second conductor post 30 may each be made of a solid cylindrical conductor, but are not limited thereto. In other embodiments, both the first conductor post and the second conductor post may be made of a hollow cylindrical conductor and filled with a colloid in the hollow conductor post.
二第一導電線40皆設置於基板10的第一表面110。二第一導電線40分別電性連接於第一導體柱20和第二導體柱30，並且第一導電線40與基板10電性絕緣。詳細來說，二第一導電線40分別電性連接於第一導體柱20和第二導體柱30位於第一表面110的此二端。在本實施例中，第一導電線40係為微帶線(Differential Microstrip Line)。The two first conductive lines 40 are all disposed on the first surface 110 of the substrate 10 . The first conductive lines 40 are electrically connected to the first conductor post 20 and the second conductor post 30, respectively, and the first conductive line 40 is electrically insulated from the substrate 10. In detail, the two first conductive lines 40 are electrically connected to the first conductor post 20 and the second conductor post 30 respectively at the two ends of the first surface 110. In this embodiment, the first conductive line 40 is a differential microstrip line.
二第二導電線50皆設置於基板10內部並且平行於第一導電線40。二第二導電線50分別電性連接於第一導體柱20和第二導體柱30之中段，並且第二導電線50與基板10電性絕緣。詳細來說，二第二導電線50分別和第一導體柱20以及第二導體柱30相接於一連接處A，且二連接處A皆介於基板10的第一表面110和第二表面120之間。在本實施例中，第二導電線50係為帶線(Stripline)。連接於第一導體柱20的第一導電線40和第二導電線50可以分別電連接至相異的二參考電位。連接於第二導體柱30的第一導電線40和第二導電線50亦可以分別電連接至相異的二參考電位。接地柱60例如可以是接地的多個金屬柱，其設置於基板10並且鄰近第一導體柱20、第二導體柱30和第一導電線40。The second conductive lines 50 are both disposed inside the substrate 10 and parallel to the first conductive line 40. The second conductive lines 50 are electrically connected to the middle of the first conductor post 20 and the second conductor post 30, respectively, and the second conductive line 50 is electrically insulated from the substrate 10. In detail, the second conductive lines 50 are respectively connected to the first conductor post 20 and the second conductor post 30 at a joint A, and the two joints A are located on the first surface 110 and the second surface of the substrate 10. Between 120. In the present embodiment, the second conductive line 50 is a strip line. The first conductive line 40 and the second conductive line 50 connected to the first conductor post 20 may be electrically connected to different two reference potentials, respectively. The first conductive line 40 and the second conductive line 50 connected to the second conductor post 30 may also be electrically connected to different two reference potentials, respectively. The grounding post 60 can be, for example, a plurality of grounded metal posts disposed on the substrate 10 and adjacent to the first conductor post 20, the second conductor post 30, and the first conductive line 40.
在本實施例中，基板10更具有鄰近第一導體柱20和第二導體柱30的二第一穿孔130和一第二穿孔140。第一穿孔130和第二穿孔140的製作方式例如可以是透過化學蝕刻製程處理基板10或是用鑽具加工基板10而形成。第二穿孔140介於二第一穿孔130之間。第一導體柱20介於其中一第一穿孔130和第二穿孔140之間，且第二導體柱30介於另一第一穿孔130和第二穿孔140之間。第一穿孔130和第二穿孔140數量並非用以限制本發明，其可視電路結構1的設計需求任意調整。二第一穿孔130以及第二穿孔140皆自基板10的第一表面110貫穿至第二表面120。In the embodiment, the substrate 10 further has two first through holes 130 and a second through hole 140 adjacent to the first conductor post 20 and the second conductor post 30. The first through hole 130 and the second through hole 140 may be formed by, for example, processing the substrate 10 by a chemical etching process or processing the substrate 10 with a drill. The second through hole 140 is interposed between the two first through holes 130. The first conductor post 20 is interposed between one of the first through holes 130 and the second through hole 140, and the second conductor post 30 is interposed between the other first through holes 130 and the second through holes 140. The number of first perforations 130 and second perforations 140 is not intended to limit the invention, and is arbitrarily adjusted in accordance with the design requirements of the circuit structure 1. The first through hole 130 and the second through hole 140 penetrate from the first surface 110 of the substrate 10 to the second surface 120.
第一穿孔130各包含相連通的一第一穿孔段131和一第二穿孔段132。第一穿孔段131較第二穿孔段132更靠近基板10的第一表面110。也就是說，如圖2所示，第一穿孔段131位於基板10的上半部，且第二穿孔段132位於基板10的下半部。此外，第二穿孔段132的孔徑大於第一穿孔段131的孔徑W1。詳細來說，如圖3和圖4所示，基板10可以具有四弧面150。其中二弧面150共同圍繞出其中一第一穿孔130的第二穿孔段132，另二弧面150則共同圍繞出另一第一穿孔130的第二穿孔段132。圍繞出第二穿孔段132的二弧面150彼此相連而於交接處形成朝第二穿孔段132的中心延伸的一第一凸出部151與一第二凸出部152。換言之，二弧面150投影於第二表面120的形狀近似於啞鈴形。The first perforations 130 each include a first perforated section 131 and a second perforated section 132 that are in communication. The first perforated section 131 is closer to the first surface 110 of the substrate 10 than the second perforated section 132. That is, as shown in FIG. 2, the first perforated section 131 is located in the upper half of the substrate 10, and the second perforated section 132 is located in the lower half of the substrate 10. Furthermore, the aperture of the second perforated section 132 is larger than the aperture W1 of the first perforated section 131. In detail, as shown in FIGS. 3 and 4, the substrate 10 may have a four-arc surface 150. The two arcuate faces 150 collectively surround the second perforated section 132 of one of the first perforations 130, and the other arcuate faces 150 collectively surround the second perforated section 132 of the other first perforation 130. A second curved surface 150 surrounding the second perforated section 132 is connected to each other to form a first protruding portion 151 and a second protruding portion 152 extending toward the center of the second perforated section 132 at the intersection. In other words, the shape of the two arcuate faces 150 projected onto the second surface 120 approximates a dumbbell shape.
第一凸出部151和第二凸出部152分別位於第二穿孔段132的相對二側。二第一凸出部151分別鄰近第一導體柱20和第二導體柱30。鄰近第一導體柱20的第一凸出部151介於第一導體柱20和其中一第二凸出部152之間。鄰近第二導體柱30的第一凸出部151則介於第二導體柱30和另一第二凸出部152之間。如圖3所示，定義一第一方向D1通過第一凸出部151與第二凸出部152，並且一第二方向D2正交於第一方向D1。在本實施例中，第二穿孔段132的孔徑可包含在第一方向D1上的孔徑W11以及在第二方向D2上的孔徑W22，且孔徑W22大於第二穿孔段132在第一方向D1上的孔徑W11。在本實施例中，孔徑W11以及孔徑W22皆大於第一穿孔段131的孔徑W1。The first protrusion 151 and the second protrusion 152 are respectively located on opposite sides of the second perforated section 132. The two first protrusions 151 are adjacent to the first conductor post 20 and the second conductor post 30, respectively. The first protrusion 151 adjacent to the first conductor post 20 is interposed between the first conductor post 20 and one of the second protrusions 152. The first protrusion 151 adjacent to the second conductor post 30 is between the second conductor post 30 and the other second protrusion 152. As shown in FIG. 3, a first direction D1 is defined to pass through the first protrusion 151 and the second protrusion 152, and a second direction D2 is orthogonal to the first direction D1. In this embodiment, the aperture of the second perforated section 132 may include an aperture W11 in the first direction D1 and an aperture W22 in the second direction D2, and the aperture W22 is greater than the second perforated section 132 in the first direction D1. The aperture W11. In the embodiment, the aperture W11 and the aperture W22 are both larger than the aperture W1 of the first perforated section 131.
在未具有穿孔的傳統電路結構中，因為導電線與導體柱的阻抗不匹配而產生訊號反射，進而導致不必要的能量損耗。此外，因導體柱上半部的阻抗與導體柱下半部的阻抗相近(導體柱下半部俗稱殘斷，Via Stub)，導致訊號能量容易漏損，進而使得傳輸到帶線的訊號能量大幅下降。In a conventional circuit structure without perforations, signal reflection occurs due to a mismatch in the impedance of the conductive lines and the conductor posts, resulting in unnecessary energy loss. In addition, because the impedance of the upper half of the conductor post is close to the impedance of the lower half of the conductor post (the lower half of the conductor post is commonly called Via Stub), the signal energy is easily leaked, and the signal energy transmitted to the line is greatly increased. decline.
在本實施例中，第一穿孔130的第一穿孔段131與第二穿孔140有助於提升第一導體柱20、第二導體柱30、二第一導電線40與二第二導電線50間的阻抗匹配度。再者，由於第二穿孔段132的孔徑W2大於第一穿孔段131的孔徑W1，故可透過第一穿孔130的第二穿孔段132與第二穿孔140來提升第一導體柱20之殘斷(下半部)、第二導體柱30之殘斷(下半部)的阻抗，以減少訊號漏損，進而改善訊號的完整性。In the embodiment, the first perforation section 131 and the second perforation 140 of the first through hole 130 help to lift the first conductor post 20 , the second conductor post 30 , the two first conductive lines 40 and the second second conductive lines 50 . The degree of impedance matching between. Moreover, since the aperture W2 of the second perforating section 132 is larger than the aperture W1 of the first perforating section 131, the second perforated section 132 and the second perforation 140 of the first perforation 130 can be passed through to improve the breakage of the first conductor post 20. (lower half), the impedance of the second conductor post 30 (lower half) to reduce signal leakage, thereby improving signal integrity.
在本實施例中，為了進一步能透過阻抗匹配的方式來提升訊號在電路結構1傳輸的完整性，電路結構1還可以有下列所述的改良。In the present embodiment, in order to further improve the integrity of the transmission of the signal in the circuit structure 1 by means of impedance matching, the circuit structure 1 can also be improved as described below.
在本實施例中，第二導電線50與導體柱20、30的連接處A至第一表面110的間距S1可以等於第二穿孔段132至第一表面110的最小間距S2。第二穿孔段132至第一表面110的最小間距S2即為第二穿孔段132鄰近第一表面110的一端至第一表面110的距離。In the present embodiment, the distance S1 between the junction A of the second conductive line 50 and the conductor posts 20, 30 to the first surface 110 may be equal to the minimum spacing S2 of the second perforated section 132 to the first surface 110. The minimum spacing S2 of the second perforated section 132 to the first surface 110 is the distance of the second perforated section 132 from one end of the first surface 110 to the first surface 110.
另外，如圖4所示，第一穿孔段131的長度L1可以小於等於第二穿孔段132的長度L2。藉此，第二穿孔段132的長度較為充足，以能有效加強導體柱上半部阻抗和導體柱下半部阻抗互相不匹配的程度，有助於加強第二穿孔段132減少訊號能量損失的影響。本實施例之第一穿孔段131的長度L1小於第二穿孔段132的長度L2，但本發明並不以此為限。在其他實施例中，第一穿孔段131的長度L1可以等於第二穿孔段132的長度L2，或是第一穿孔段131的長度L1可以大於第二穿孔段132的長度L2。In addition, as shown in FIG. 4, the length L1 of the first perforated section 131 may be less than or equal to the length L2 of the second perforated section 132. Thereby, the length of the second perforated section 132 is sufficient to effectively strengthen the impedance of the upper half of the conductor post and the impedance of the lower half of the conductor post to each other, which helps to strengthen the second perforated section 132 to reduce the signal energy loss. influences. The length L1 of the first perforated section 131 of the embodiment is smaller than the length L2 of the second perforated section 132, but the invention is not limited thereto. In other embodiments, the length L1 of the first perforated section 131 may be equal to the length L2 of the second perforated section 132, or the length L1 of the first perforated section 131 may be greater than the length L2 of the second perforated section 132.
此外，對於鄰近第一導體柱20的第一穿孔130而言，第一穿孔130之第一穿孔段131的中心O1與第一導體柱20的間距C1可以小於第二穿孔段132的中心O2與第一導體柱20的間距C2。對於鄰近第二導體柱30的第一穿孔130而言，第一穿孔段131的中心與第二導體柱30的間距亦可以小於第二穿孔段132的中心與第二導體柱30的間距。藉此，第一穿孔段131以及第二穿孔段132的空間配置較為合適，有助於使第一穿孔130減少訊號能量損失的效果較為顯著。In addition, for the first through hole 130 adjacent to the first conductor post 20, the distance C1 between the center O1 of the first perforated section 131 of the first through hole 130 and the first conductor post 20 may be smaller than the center O2 of the second perforated section 132. The pitch of the first conductor post 20 is C2. For the first through hole 130 adjacent to the second conductor post 30, the distance between the center of the first through hole segment 131 and the second conductor post 30 may also be smaller than the distance between the center of the second through hole segment 132 and the second conductor post 30. Thereby, the spatial arrangement of the first perforated section 131 and the second perforated section 132 is suitable, and the effect of reducing the signal energy loss of the first perforation 130 is more remarkable.
以下說明在本實施例的電路結構1中傳輸訊號與在傳統電路結構中傳輸訊號的能量損耗比較以及訊號完整性比較。請同時參照圖5至圖8。圖5為圖1之電路結構進行模擬測試之模擬電路之立體示意圖。圖6為傳統電路結構進行模擬測試之模擬電路之立體示意圖。圖7為對圖5和圖6之模擬電路結構輸入方形脈衝波所得到的波形-時間的圖表。圖8為對圖5和圖6之模擬電路結構輸入方形脈衝波所得到的訊號傳輸損耗-訊號頻率的圖表。The energy loss comparison and signal integrity comparison of the transmission signal in the circuit structure 1 of the present embodiment and the transmission signal in the conventional circuit structure will be described below. Please refer to FIG. 5 to FIG. 8 at the same time. FIG. 5 is a schematic perspective view of an analog circuit in which the circuit structure of FIG. 1 is subjected to simulation test. FIG. 6 is a schematic perspective view of an analog circuit in which a conventional circuit structure is subjected to analog test. Fig. 7 is a graph showing the waveform-time obtained by inputting a square pulse wave to the analog circuit configuration of Figs. 5 and 6. FIG. 8 is a graph showing the signal transmission loss-signal frequency obtained by inputting a square pulse wave to the analog circuit structure of FIGS. 5 and 6.
圖5和圖6分別繪示以電路結構1和傳統電路結構分別進行模擬測試之模擬電路之立體示意圖。相較圖1至圖4的電路結構1，由於接地柱60和基板10本體對阻抗的改變影響極小，故圖5在模擬電路結構1時省略接地柱60以及除了第一穿孔130和第二穿孔140之外之基板10的其他結構。同樣地，圖6在模擬傳統電路結構時也省略的基板和接地柱。由於電路結構1一般會使用於正常大氣環境下，因此在模擬電路結構1時以空氣柱做為第一穿孔130和第二穿孔140的等效物。圖1中的二第一穿孔段131等效於圖5中的二第一空氣柱P1，二第二穿孔段132等效於圖5中的二第二空氣柱P2，且第二穿孔140等效於圖5中的第三空氣柱P3。FIG. 5 and FIG. 6 are respectively schematic perspective views of an analog circuit for performing analog test respectively on the circuit structure 1 and the conventional circuit structure. Compared with the circuit structure 1 of FIG. 1 to FIG. 4, since the grounding post 60 and the substrate 10 have little influence on the impedance change, FIG. 5 omits the ground post 60 and the first through hole 130 and the second through hole in the analog circuit structure 1. Other structures of the substrate 10 other than 140. Similarly, Figure 6 also omits the substrate and ground posts when simulating a conventional circuit structure. Since the circuit structure 1 is generally used in a normal atmospheric environment, the air column is used as the equivalent of the first through hole 130 and the second through hole 140 in the analog circuit structure 1. The first first perforated section 131 in FIG. 1 is equivalent to the two first air columns P1 in FIG. 5, and the second second perforated section 132 is equivalent to the second second air column P2 in FIG. 5, and the second perforation 140 is equal to It is effective for the third air column P3 in FIG.
於圖5和圖6中，二導體柱20、30的外徑皆為18.0 釐米(mm)，二導體柱20、30的的長度皆為200.0 mm。各導電線40、50的阻抗皆為100歐姆(Ω)。導電線40、50與導體柱20、30連接處A至第一表面110的間距為99.0 mm，導電線40、50與導體柱20、30連接處至第二表面的間距為101.0 mm。於圖5中，第二空氣柱P2至第一表面的最小間距為99.0 mm。第一空氣柱P1的孔徑為36.0 mm，第二空氣柱P2在第一方向D1的孔徑為78.1 mm，第二空氣柱P2在第二方向D2的孔徑為128.0 mm，第三空氣柱P3的孔徑為65.8 mm。第一空氣柱P1的長度為99.0 mm，第二空氣柱P2的長度為101.0 mm，第三空氣柱P3的長度為200.0 mm。第一空氣柱P1的中心與導體柱的間距為39.1 mm，第二空氣柱P2的中心與導體柱的間距為78.2 mm。In FIGS. 5 and 6, the outer diameters of the two conductor posts 20, 30 are both 18.0 cm (mm), and the lengths of the two conductor posts 20, 30 are both 200.0 mm. The impedance of each of the conductive lines 40, 50 is 100 ohms (Ω). The pitch of the conductive lines 40, 50 from the junction A of the conductor posts 20, 30 to the first surface 110 is 99.0 mm, and the distance between the conductive lines 40, 50 and the junction of the conductor posts 20, 30 to the second surface is 101.0 mm. In FIG. 5, the minimum spacing of the second air column P2 to the first surface is 99.0 mm. The aperture of the first air column P1 is 36.0 mm, the aperture of the second air column P2 in the first direction D1 is 78.1 mm, the aperture of the second air column P2 in the second direction D2 is 128.0 mm, and the aperture of the third air column P3 It is 65.8 mm. The length of the first air column P1 is 99.0 mm, the length of the second air column P2 is 101.0 mm, and the length of the third air column P3 is 200.0 mm. The distance between the center of the first air column P1 and the conductor column is 39.1 mm, and the distance between the center of the second air column P2 and the conductor column is 78.2 mm.
進行模擬測試時，會從圖5和圖6中位於導體柱上方的導電線40輸入一方形脈衝波訊號，並且會從連接於導體柱中間的導電線50接收經過此模擬電路之輸出訊號。此外，還會模擬此方形脈衝波訊號行經此模擬電路時所產生的能量損耗。When performing the simulation test, a square pulse wave signal is input from the conductive wire 40 located above the conductor post in FIGS. 5 and 6, and the output signal passing through the analog circuit is received from the conductive wire 50 connected to the middle of the conductor post. In addition, the energy loss generated by the square pulse wave signal passing through the analog circuit is simulated.
參照圖7所示，其中圖表橫軸為輸入訊號後經過時間，縱軸為訊號電壓。理想的方形脈衝波係從輸入約0.3奈秒(nsec)後由0伏特(V)提升至1.0 V。對於圖6的模擬傳統電路而言，在輸入訊號約0.3 nsec後，由於導電柱和導電線間的阻抗不匹配以及部分訊號傳輸到導體柱下半部的影響，使得訊號在傳統電路傳輸時發生不必要的能量損耗，因此訊號從0 V提升至1.0 V的所需時間增加約0.3 nsec，進而接收到的訊號波形也相較輸入時的波形失真。Referring to FIG. 7, the horizontal axis of the graph is the elapsed time after the input signal, and the vertical axis is the signal voltage. The ideal square pulse wave system is boosted from 0 volts (V) to 1.0 V after the input is about 0.3 nanoseconds (nsec). For the analog conventional circuit of FIG. 6, after the input signal is about 0.3 nsec, the signal is generated during the transmission of the conventional circuit due to the impedance mismatch between the conductive post and the conductive line and the influence of the partial signal transmission to the lower half of the conductor post. Unnecessary energy loss, so the time required to increase the signal from 0 V to 1.0 V increases by about 0.3 nsec, and the received signal waveform is also distorted compared to the input waveform.
對於圖5模擬本實施例的電路結構1而言，第一空氣柱P1和第三空氣柱P3使導電柱阻抗匹配於導電線的阻抗。此外，第二空氣柱P2大幅增加導電柱下半部的阻抗。因此，這些空氣柱P1至P3有助於維持訊號在電路結構1中傳輸時的訊號完整性，避免發生能量損耗，因此訊號從0 V提升至1.0 V的所需時間趨近於0.3 nsec，進而接收到的訊號波形和輸入訊號的波形較為相近。For the circuit structure 1 of the present embodiment simulated in FIG. 5, the first air column P1 and the third air column P3 match the impedance of the conductive post to the impedance of the conductive line. In addition, the second air column P2 substantially increases the impedance of the lower half of the conductive post. Therefore, these air columns P1 to P3 help maintain the signal integrity of the signal transmitted in the circuit structure 1 and avoid energy loss, so the time required for the signal to rise from 0 V to 1.0 V approaches 0.3 nsec, and further The received signal waveform and the waveform of the input signal are similar.
參照圖8所示，其中圖表橫軸為輸入訊號頻率，縱軸為訊號傳輸損耗。當輸入訊號頻率較低(約4GHz~8GHz)時，電路結構1中傳輸訊號與在傳統電路結構中傳輸訊號的能量損耗差異較小，但仍能從圖表中看出電路結構1造成的能量損耗小於傳統電路結構造成的能量損耗。當輸入訊號頻率較高(大於12GHz)時，很明顯地訊號在傳統電路結構傳輸所產生的傳輸損耗遠大於訊號在電路結構1傳輸所產生的傳輸損耗。進一步來說，當輸入訊號頻率大約為13GHz時，傳統電路結構所造成的傳輸損耗與電路結構1所造成的傳輸損耗相差近六倍。藉由圖表展示的模擬結果，能清楚地得知本實施例的電路結構1確實提升了導體柱和導電線間的阻抗匹配，有效維持訊號完整性，降低訊號能量損失。上述訊號傳輸損耗即意指訊號由導電線40傳輸至導電線50過程的饋入損失(Insertion Loss)，其單位為分貝(dB)。Referring to FIG. 8, the horizontal axis of the graph is the input signal frequency, and the vertical axis is the signal transmission loss. When the input signal frequency is low (about 4 GHz to 8 GHz), the difference between the transmission signal of the circuit structure 1 and the energy loss of the signal transmitted in the conventional circuit structure is small, but the energy loss caused by the circuit structure 1 can still be seen from the graph. Less than the energy loss caused by the traditional circuit structure. When the input signal frequency is higher (greater than 12 GHz), it is obvious that the transmission loss caused by the transmission of the signal in the conventional circuit structure is much larger than the transmission loss caused by the transmission of the signal in the circuit structure 1. Further, when the input signal frequency is about 13 GHz, the transmission loss caused by the conventional circuit structure is nearly six times that of the transmission loss caused by the circuit structure 1. From the simulation results shown in the graph, it can be clearly seen that the circuit structure 1 of the present embodiment does improve the impedance matching between the conductor post and the conductive line, effectively maintaining signal integrity and reducing signal energy loss. The above signal transmission loss means the loss of the signal transmitted by the conductive line 40 to the conductive line 50, and the unit is decibel (dB).
第一實施例的導體柱、導電線以及穿孔的數量和相對位置關係並非用以限制本發明。請參照圖9，為根據本發明第二實施例之電路結構的俯視示意圖。第三實施例與第一實施例相似，故以下僅就相異處進行說明。本實施例和第一實施例的差異在於，本實施例的電路結構1未包含第二導體柱和第二穿孔，且電路結構1的二第一穿孔130分別位於第一導體柱20的相對二側。The number and relative positional relationship of the conductor posts, the conductive wires, and the perforations of the first embodiment are not intended to limit the present invention. Please refer to FIG. 9, which is a top plan view of a circuit structure according to a second embodiment of the present invention. The third embodiment is similar to the first embodiment, and therefore only the differences will be described below. The difference between this embodiment and the first embodiment is that the circuit structure 1 of the present embodiment does not include the second conductor post and the second through hole, and the two first through holes 130 of the circuit structure 1 are respectively located at the opposite sides of the first conductor post 20 side.
第一實施例的第二穿孔段從俯視示意圖來看近似啞鈴形，但本發明並不以此為限。請參照圖10，為根據本發明第三實施例之電路結構的俯視示意圖。第三實施例與第一實施例相似，故以下僅就相異處進行說明。本實施例和第一實施例的差異在於，本實施例的第二穿孔段為圓柱狀。也就是說，第二穿孔段132在第一方向D1上的孔徑W11等於第二穿孔段132在第二方向D2上的孔徑W22。The second perforated section of the first embodiment is approximately dumbbell shaped from a top view, but the invention is not limited thereto. Please refer to FIG. 10, which is a top plan view of a circuit structure according to a third embodiment of the present invention. The third embodiment is similar to the first embodiment, and therefore only the differences will be described below. The difference between this embodiment and the first embodiment is that the second perforated section of the embodiment has a cylindrical shape. That is, the aperture W11 of the second perforated section 132 in the first direction D1 is equal to the aperture W22 of the second perforated section 132 in the second direction D2.
綜上所述，本發明所揭露的電路結構中，第一穿孔的第一穿孔段有助於使第一導電線的阻抗分別與導體柱的阻抗相匹配。此外，第一穿孔的第二穿孔段有助於使第二導電線的阻抗與導體柱的阻抗相匹配。進一步來說，由於第二穿孔段的孔徑大於第一穿孔段的孔徑，而令導體柱上半部阻抗和導體柱下半部阻抗互相不匹配，有效避免訊號傳輸到導體柱下半部。藉此，第一穿孔能有效減少訊號能量因阻抗不匹配所造成的能量損失，進而改善訊號的完整性。In summary, in the circuit structure disclosed in the present invention, the first perforated section of the first perforation helps to match the impedance of the first conductive line with the impedance of the conductor post. Furthermore, the second perforated section of the first perforation helps to match the impedance of the second electrically conductive line to the impedance of the conductor post. Further, since the aperture of the second perforated section is larger than the aperture of the first perforated section, the impedance of the upper half of the conductor post and the impedance of the lower half of the conductor post do not match each other, thereby effectively preventing the signal from being transmitted to the lower half of the conductor post. Thereby, the first perforation can effectively reduce the energy loss caused by the impedance mismatch of the signal energy, thereby improving the integrity of the signal.
雖然本發明以前述之實施例揭露如上，然其並非用以限定本發明。在不脫離本發明之精神和範圍內，所為之更動與潤飾，均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.
1 電路結構 10 基板 110 第一表面 120 第二表面 130 第一穿孔 131 第一穿孔段 132 第二穿孔段 140 第二穿孔 150 弧面 151 第一凸出部 152 第二凸出部 20 第一導體柱 30 第二導體柱 40 第一導電線 50 第二導電線 60 接地柱 P1 第一空氣柱 P2 第二空氣柱 P3 第三空氣柱 D1 第一方向 D2 第二方向 W11 第二穿孔段在第一方向上的孔徑 W22 第二穿孔段在第二方向上的孔徑 A 第二導電線和導體柱的連接處 S1 第二導電線與導體柱的連接處至第一表面的間距 S2 第二穿孔段至第一表面的最小間距 L1 第一穿孔段的長度 L2 第二穿孔段的長度 O1 第一穿孔段的中心 O2 第二穿孔段的中心 C1 第一穿孔段的中心與導體柱的間距 C2 第二穿孔段的中心與導體柱的間距1 circuit structure 10 substrate 110 first surface 120 second surface 130 first perforation 131 first perforation section 132 second perforation section 140 second perforation 150 curved surface 151 first protrusion 152 second protrusion 20 first conductor Column 30 second conductor post 40 first conductive line 50 second conductive line 60 grounding pole P1 first air column P2 second air column P3 third air column D1 first direction D2 second direction W11 second perforated section at first Aperture W22 in the direction Aperture A of the second perforated section in the second direction A junction of the second conductive line and the conductor post S1 Second guide The distance from the junction of the wire to the conductor post to the first surface S2 The minimum distance L1 from the second perforation segment to the first surface L1 The length L2 of the first perforation segment The length O1 of the second perforation segment O1 The center O2 of the first perforation segment Second perforation The center of the segment C1 The distance between the center of the first perforated segment and the conductor column C2 The distance between the center of the second perforated segment and the conductor column
圖1為根據本發明第一實施例之電路結構的俯視示意圖。 圖2為圖1之電路結構沿線2-2剖切的剖切示意圖。 圖3為圖1之電路結構的第一穿孔的俯視示意圖。 圖4為圖3之第一穿孔的剖切示意圖。 圖5為圖1之電路結構進行模擬測試之模擬電路之立體示意圖。 圖6為傳統電路結構進行模擬測試之模擬電路之立體示意圖。 圖7為對圖5和圖6之模擬電路結構輸入方形脈衝波所得到的波形-時間的圖表。 圖8為對圖5和圖6之模擬電路結構輸入方形脈衝波所得到的訊號傳輸損耗-訊號頻率的圖表。 圖9為根據本發明第二實施例之電路結構的俯視示意圖。 圖10為根據本發明第三實施例之電路結構的俯視示意圖。1 is a top plan view showing a circuit structure in accordance with a first embodiment of the present invention. 2 is a cross-sectional view of the circuit structure of FIG. 1 taken along line 2-2. 3 is a top plan view of the first perforation of the circuit structure of FIG. 1. 4 is a cross-sectional view of the first perforation of FIG. 3. FIG. 5 is a schematic perspective view of an analog circuit in which the circuit structure of FIG. 1 is subjected to simulation test. FIG. 6 is a schematic perspective view of an analog circuit in which a conventional circuit structure is subjected to analog test. Fig. 7 is a graph showing the waveform-time obtained by inputting a square pulse wave to the analog circuit configuration of Figs. 5 and 6. FIG. 8 is a graph showing the signal transmission loss-signal frequency obtained by inputting a square pulse wave to the analog circuit structure of FIGS. 5 and 6. Figure 9 is a top plan view of a circuit structure in accordance with a second embodiment of the present invention. Figure 10 is a top plan view showing a circuit structure in accordance with a third embodiment of the present invention.
1 電路結構 10 基板 110 第一表面 130 第一穿孔 131 第一穿孔段 132 第二穿孔段 140 第二穿孔 150 弧面 20 第一導體柱 30 第二導體柱 40 第一導電線 50 第二導電線 60 接地柱1 circuit structure 10 substrate 110 first surface 130 first perforation 131 first perforation section 132 second perforation section 140 second perforation 150 curved surface 20 first conductor post 30 second conductor post 40 first conductive line 50 second conductive line 60 grounding post
Claims (10)
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| TW104139270A TWI589197B (en) | 2015-11-25 | 2015-11-25 | Circuit structure |
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| TW104139270A TWI589197B (en) | 2015-11-25 | 2015-11-25 | Circuit structure |
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|---|---|
| TW201720245A TW201720245A (en) | 2017-06-01 |
| TWI589197B true TWI589197B (en) | 2017-06-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104139270A TWI589197B (en) | 2015-11-25 | 2015-11-25 | Circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI589197B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102065632B (en) * | 2009-11-18 | 2013-03-20 | 三星电机株式会社 | Electromagnetic bandgap structure and printed circuit board comprising the same |
| CN103260348A (en) * | 2013-04-01 | 2013-08-21 | 广州兴森快捷电路科技有限公司 | High-speed PCB and difference via hole impedance control method |
| TW201517711A (en) * | 2013-08-08 | 2015-05-01 | Invensas Corp | Ultra high performance interposer |
| TWI510157B (en) * | 2014-07-09 | 2015-11-21 | 中原大學 | A transmission device for maintaining signal integrity |
-
2015
- 2015-11-25 TW TW104139270A patent/TWI589197B/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102065632B (en) * | 2009-11-18 | 2013-03-20 | 三星电机株式会社 | Electromagnetic bandgap structure and printed circuit board comprising the same |
| CN103260348A (en) * | 2013-04-01 | 2013-08-21 | 广州兴森快捷电路科技有限公司 | High-speed PCB and difference via hole impedance control method |
| TW201517711A (en) * | 2013-08-08 | 2015-05-01 | Invensas Corp | Ultra high performance interposer |
| TWI510157B (en) * | 2014-07-09 | 2015-11-21 | 中原大學 | A transmission device for maintaining signal integrity |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201720245A (en) | 2017-06-01 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |