TWI588714B - Timing controller and method for reducing inner noise of touch panel - Google Patents

Timing controller and method for reducing inner noise of touch panel Download PDF

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TWI588714B
TWI588714B TW105128224A TW105128224A TWI588714B TW I588714 B TWI588714 B TW I588714B TW 105128224 A TW105128224 A TW 105128224A TW 105128224 A TW105128224 A TW 105128224A TW I588714 B TWI588714 B TW I588714B
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level
signal
clock signal
time
switched
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TW105128224A
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TW201809994A (en
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蔡瑋霖
王義豪
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友達光電股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Position Input By Displaying (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

時序控制器及觸控面板的雜訊抑制方法Timing controller and touch panel noise suppression method

本發明係關於觸控領域之相關技術，尤其是有關於一種用於觸控面板的時序控制器及觸控面板的雜訊抑制方法。The present invention relates to related technologies in the field of touch, and more particularly to a method for suppressing noise of a timing controller for a touch panel and a touch panel.

藉由量測雜訊的耦合量，可知觸控面板在其內部二個互為反相的時脈訊號轉換位準時會產生較大的雜訊，因而影響了觸控面板的觸控功能。此問題雖可藉由分別對齊上述二個時脈訊號的上升緣（rising edge）與下降緣（falling edge）來獲得解決，然而有些種類的觸控面板卻無法採用這樣的方式來抑制雜訊，採用上述方式反而會無法造成面板無法正常動作。By measuring the coupling amount of the noise, it can be seen that the touch panel generates a large amount of noise when the two mutually inverted clock signal conversion levels are internal, thereby affecting the touch function of the touch panel. Although the problem can be solved by respectively aligning the rising edge and the falling edge of the above two clock signals, some types of touch panels cannot adopt such a method to suppress noise. In the above manner, the panel will not be able to operate normally.

本發明之一目的在提供一種時序控制器，其可產生補償訊號來抑制上述二個時脈訊號所造成的雜訊。It is an object of the present invention to provide a timing controller that can generate a compensation signal to suppress noise caused by the two clock signals.

本發明之另一目的在提供一種觸控面板的雜訊抑制方法。Another object of the present invention is to provide a noise suppression method for a touch panel.

本發明提出一種時序控制器，此時序控制器包括有第一訊號產生器、第二訊號產生器與補償訊號產生器。第一訊號產生器用以產生第一訊號，此第一訊號具有第一位準與第二位準。第二訊號產生器用以依據第一訊號產生第一時脈訊號以及第二時脈訊號，其中第一時脈訊號與第二時脈訊號互為反相。補償訊號產生器用以依據第一訊號產生補償訊號，此補償訊號具有第三位準與第四位準，且每當第一訊號由第一位準切換至第二位準，補償訊號產生器便於延遲達第一時間時與延遲達第二時間時分別切換一次補償訊號之位準。The invention provides a timing controller, which comprises a first signal generator, a second signal generator and a compensation signal generator. The first signal generator is configured to generate a first signal, where the first signal has a first level and a second level. The second signal generator is configured to generate the first clock signal and the second clock signal according to the first signal, wherein the first clock signal and the second clock signal are mutually inverted. The compensation signal generator is configured to generate a compensation signal according to the first signal, the compensation signal has a third level and a fourth level, and the compensation signal generator is convenient whenever the first signal is switched from the first level to the second level. The level of the compensation signal is switched once when the delay reaches the first time and when the delay reaches the second time.

本發明另提出一種觸控面板的雜訊抑制方法，此雜訊抑制方法包括有下列步驟：提供第一時脈訊號以及第二時脈訊號；以及提供補償訊號，並將補償訊號傳送至一觸控面板中，此補償訊號具有第一位準與第二位準，且每當第一時脈訊號或第二時脈訊號切換一次位準，補償訊號便於相同時間切換一次與第一時脈訊號或第二時脈訊號反向之位準。The present invention further provides a noise suppression method for a touch panel. The noise suppression method includes the following steps: providing a first clock signal and a second clock signal; and providing a compensation signal, and transmitting the compensation signal to a touch In the control panel, the compensation signal has a first level and a second level, and each time the first clock signal or the second clock signal is switched once, the compensation signal is convenient to switch once and the first clock signal at the same time. Or the second clock signal is reversed.

由於本發明之補償訊號在第一時脈訊號與第二時脈訊號之其中任一切換位準時也會切換一次位準，且補償訊號之高、低準位的切換方式與第一時脈訊號與第二時脈訊號二者之高、低準位的切換方式相反，因此本發明之補償訊號可以抑制或抵銷第一時脈訊號與第二時脈訊號於切換位準時所產生的雜訊，改善了觸控面板因受到雜訊而影響其觸控能力的問題。The compensation signal of the present invention also switches the level once when the first clock signal and the second clock signal are switched, and the switching mode of the high and low levels of the compensation signal and the first clock signal In contrast to the switching between the high and low levels of the second clock signal, the compensation signal of the present invention can suppress or cancel the noise generated when the first clock signal and the second clock signal are switched. Improves the problem that the touch panel affects its touch capability due to noise.

為了讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <RTIgt;

圖1繪有依照本發明一實施例之時序控制器的內部電路方塊。如圖1所示，時序控制器10係電性耦接觸控面板16，用以提供觸控面板16所需之控制訊號（詳後述）。此觸控面板16例如是低溫多晶矽觸控面板之類無法採用習知之雜訊抑制方法的觸控面板。此時序控制器10包括有振盪器15、第一訊號產生器11、第二訊號產生器13、補償訊號產生器12與電壓位準轉換器14。第一訊號產生器11用以依據振盪器15所提供的時脈訊號CK而產生第一訊號FS，此第一訊號FS例如是水平同步訊號（Horizontal sync，Hsync），但本發明並不以此為限。另外，當第一訊號產生器11內建有振盪器時，時序控制器10就可以不採用振盪器15。1 depicts an internal circuit block of a timing controller in accordance with an embodiment of the present invention. As shown in FIG. 1 , the timing controller 10 is electrically coupled to the control panel 16 for providing the control signals required by the touch panel 16 (described later). The touch panel 16 is, for example, a low-temperature polysilicon touch panel or the like which cannot adopt the conventional noise suppression method. The timing controller 10 includes an oscillator 15, a first signal generator 11, a second signal generator 13, a compensation signal generator 12, and a voltage level converter 14. The first signal generator 11 generates a first signal FS according to the clock signal CK provided by the oscillator 15. The first signal FS is, for example, a horizontal sync signal (Hsync), but the present invention does not Limited. In addition, when the first signal generator 11 has an internal oscillator, the timing controller 10 can not use the oscillator 15.

第二訊號產生器13用以依據第一訊號FS來產生觸控面板16中之閘極驅動電路（Gate driver）所需之二個互為反相的時脈訊號，以下分別稱為時脈訊號CLK以及時脈訊號XCLK。在此例中，時脈訊號CLK與XCLK二者的上升緣並無對齊，且二者的下降緣亦無對齊。較佳地，第二訊號產生器13還用以依據上述之第一訊號FS來產生閘極驅動電路所需之起始脈衝（Start pulse，SP），以利用此起始脈衝SP控制閘極驅動電路開始產生各閘極脈衝（Gate pulse）。補償訊號產生器12用以依據上述之第一訊號FS產生補償訊號TPC。至於電壓位準轉換器（Level shifter）14，其用以調整時脈訊號CLK、時脈訊號XCLK、起始脈衝SP以及補償訊號TPC的電壓位準，並將調整後的時脈訊號CLK、時脈訊號XCLK、起始脈衝SP以及補償訊號TPC傳送給觸控面板16。此外，由於電壓位準轉換器14係用以轉換訊號的電壓位準，因此時序控制器10可依實際的設計需求而決定是否採用。The second signal generator 13 is configured to generate two mutually inverted clock signals required by the gate driver in the touch panel 16 according to the first signal FS, which are respectively referred to as clock signals. CLK and clock signal XCLK. In this example, the rising edges of the clock signals CLK and XCLK are not aligned, and the falling edges of the two are not aligned. Preferably, the second signal generator 13 is further configured to generate a start pulse (SP) required by the gate driving circuit according to the first signal FS, to control the gate driving by using the starting pulse SP. The circuit begins to generate each gate pulse. The compensation signal generator 12 is configured to generate a compensation signal TPC according to the first signal FS. A voltage level shifter 14 is used to adjust the voltage level of the clock signal CLK, the clock signal XCLK, the start pulse SP, and the compensation signal TPC, and adjust the adjusted clock signal CLK, time. The pulse signal XCLK, the start pulse SP, and the compensation signal TPC are transmitted to the touch panel 16. In addition, since the voltage level converter 14 is used to convert the voltage level of the signal, the timing controller 10 can decide whether to adopt according to actual design requirements.

為了方便說明，以下將以水平同步訊號Hsync作為第一訊號FS為例，來說明本發明之補償訊號TPC為何可以抑制時脈訊號CLK與XCLK所造成的雜訊。請參照圖2，其係繪示水平同步訊號Hsync、時脈訊號CLK、時脈訊號XCLK與補償訊號TPC這四者之間的其中一種時序關係。如圖2所示，水平同步訊號Hsync具有位準L1與位準L2，在本實施例中位準L1大於位準L2，而補償訊號TPC具有位準L3與位準L4，且位準L3大於位準L4。此外，時間T2小於時間T1。For convenience of description, the following uses the horizontal synchronization signal Hsync as the first signal FS as an example to illustrate why the compensation signal TPC of the present invention can suppress the noise caused by the clock signals CLK and XCLK. Referring to FIG. 2, one of the timing relationships between the horizontal synchronization signal Hsync, the clock signal CLK, the clock signal XCLK, and the compensation signal TPC is shown. As shown in FIG. 2, the horizontal synchronization signal Hsync has a level L1 and a level L2. In this embodiment, the level L1 is greater than the level L2, and the compensation signal TPC has a level L3 and a level L4, and the level L3 is greater than Level L4. Furthermore, time T2 is less than time T1.

依圖2所示之時序關係，可知每當水平同步訊號Hsync由位準L1切換至位準L2時，補償訊號產生器12便於延遲達時間T2時將補償訊號TPC由位準L4切換至位準L3，並於延遲達時間T1時將補償訊號TPC由位準L3切換至位準L4。而由於當時脈訊號CLK或XCLK由邏輯高電位切換至邏輯低電位時，補償訊號TPC也由電位較低的位準L4切換至電位較高的位準L3，而當時脈訊號CLK或XCLK由邏輯低電位切換至邏輯高電位時，補償訊號TPC也會由電位較高的位準L3切換至電位較低的位準L4，因此補償訊號TPC所產生的雜訊可以抑制或部分抵銷時脈訊號CLK與XCLK於切換位準時所產生的雜訊。According to the timing relationship shown in FIG. 2, when the horizontal synchronization signal Hsync is switched from the level L1 to the level L2, the compensation signal generator 12 can facilitate the switching of the compensation signal TPC from the level L4 to the level when the delay reaches the time T2. L3, and the compensation signal TPC is switched from the level L3 to the level L4 when the delay reaches the time T1. However, since the pulse signal CLK or XCLK is switched from the logic high level to the logic low level, the compensation signal TPC is also switched from the lower potential level L4 to the higher potential level L3, while the pulse signal CLK or XCLK is logic. When the low potential is switched to the logic high level, the compensation signal TPC is also switched from the higher potential level L3 to the lower potential level L4, so the noise generated by the compensation signal TPC can suppress or partially cancel the clock signal. The noise generated by CLK and XCLK when switching the level.

請參照圖3，其係繪示水平同步訊號Hsync、時脈訊號CLK、時脈訊號XCLK與補償訊號TPC這四者之間的另一種時序關係。如圖3所示，水平同步訊號Hsync具有位準L1與位準L2，而補償訊號TPC具有位準L3與位準L4。此外，時間T2大於時間T1。Please refer to FIG. 3 , which illustrates another timing relationship between the horizontal synchronization signal Hsync, the clock signal CLK, the clock signal XCLK, and the compensation signal TPC. As shown in FIG. 3, the horizontal synchronization signal Hsync has a level L1 and a level L2, and the compensation signal TPC has a level L3 and a level L4. Furthermore, time T2 is greater than time T1.

依圖3所示之時序關係，可知每當水平同步訊號Hsync由位準L1切換至位準L2時，補償訊號產生器12便於延遲達時間T1時將補償訊號TPC由位準L3切換至位準L4，並於延遲達時間T2時將補償訊號TPC由位準L4切換至位準L3。而由於當時脈訊號CLK或XCLK由邏輯低電位切換至邏輯高電位時，補償訊號TPC也由電位較高的位準L3切換至電位較低的位準L4，而當時脈訊號CLK或XCLK由邏輯高電位切換至邏輯低電位時，補償訊號TPC也會由電位較低的位準L4切換至電位較高的位準L3，因此補償訊號TPC所產生的雜訊可以抑制或部分抵銷時脈訊號CLK與XCLK於切換位準時所產生的雜訊。當時脈訊號CLK之邏輯高電位與邏輯低電位之間的壓差、時脈訊號XCLK之邏輯高電位與邏輯低電位之間的壓差、補償訊號TPC之位準L3與L4之間的壓差皆為相同時，那麼理論上補償訊號TPC所產生的雜訊就可以完全抵銷時脈訊號CLK與XCLK於切換位準時所產生的雜訊。According to the timing relationship shown in FIG. 3, when the horizontal synchronization signal Hsync is switched from the level L1 to the level L2, the compensation signal generator 12 can facilitate the switching of the compensation signal TPC from the level L3 to the level when the delay reaches the time T1. L4, and the compensation signal TPC is switched from the level L4 to the level L3 when the delay reaches the time T2. Since the pulse signal CLK or XCLK is switched from logic low to logic high, the compensation signal TPC is also switched from the higher potential level L3 to the lower potential level L4, and the pulse signal CLK or XCLK is logic. When the high potential is switched to the logic low level, the compensation signal TPC is also switched from the lower potential level L4 to the higher potential level L3, so the noise generated by the compensation signal TPC can suppress or partially cancel the clock signal. The noise generated by CLK and XCLK when switching the level. The voltage difference between the logic high and logic low of the pulse signal CLK, the voltage difference between the logic high and the logic low of the clock signal XCLK, and the voltage difference between the level of the compensation signal TPC, L3 and L4 When they are all the same, then the noise generated by the theoretical compensation signal TPC can completely offset the noise generated when the clock signals CLK and XCLK are switched.

藉由圖2與圖3所示之時序關係，可知每當水平同步訊號Hsync由一位準（例如位準L1）切換至另一位準（例如位準L2）時，補償訊號產生器12便於延遲達時間T1時與延遲達時間T2時分別切換一次補償訊號TPC之位準。以另一觀點來看，每當時脈訊號CLK或XCLK切換一次位準，補償訊號產生器12便控制補償訊號TPC於相同時間切換一次與時脈訊號CLK或XCLK反向之位準。According to the timing relationship shown in FIG. 2 and FIG. 3, it can be seen that the compensation signal generator 12 is convenient whenever the horizontal synchronization signal Hsync is switched from one level (for example, level L1) to another level (for example, level L2). When the delay reaches the time T1 and the delay reaches the time T2, the level of the compensation signal TPC is switched once. From another point of view, each time the pulse signal CLK or XCLK is switched once, the compensation signal generator 12 controls the compensation signal TPC to switch the level opposite to the clock signal CLK or XCLK at the same time.

圖4係繪示時脈訊號CLK、時脈訊號XCLK、起始脈衝SP與補償訊號TPC這四者在觸控面板16中的其中一種布局方式。如圖4所示，觸控面板16區分有驅動電路布局區與顯示區，其中顯示區用以配置畫素陣列18，而驅動電路布局區則用以配置由多個移位暫存器（Shift register，SR）所構成的閘極驅動電路17。在圖4所示之例子中，時脈訊號CLK、時脈訊號XCLK、起始脈衝SP與補償訊號TPC這四者在觸控面板16中的傳送路徑皆位於閘極驅動電路17的左側，且補償訊號TPC的傳送路徑係與時脈訊號CLK、時脈訊號XCLK與起始脈衝SP這三者之其中任一的傳送路徑的間隔皆小於預設距離。然此僅是用以舉例，並非用以限制本發明，本領域之通常知識者應知，只要補償訊號TPC的傳送路徑係與時脈訊號CLK與時脈訊號XCLK二者之至少其中之一的傳送路徑的間隔小於預設距離，就可以抑制或抵銷預設距離內之時脈訊號CLK與XCLK於切換位準時所產生的雜訊。FIG. 4 illustrates one of the layouts of the clock signal CLK, the clock signal XCLK, the start pulse SP, and the compensation signal TPC in the touch panel 16. As shown in FIG. 4, the touch panel 16 is divided into a driving circuit layout area and a display area, wherein the display area is used to configure the pixel array 18, and the driving circuit layout area is configured to be configured by a plurality of shift registers (Shift). A gate drive circuit 17 composed of register, SR). In the example shown in FIG. 4, the transmission paths of the clock signal CLK, the clock signal XCLK, the start pulse SP, and the compensation signal TPC in the touch panel 16 are all located on the left side of the gate driving circuit 17, and The transmission path of the compensation signal TPC is separated from the transmission path of any one of the clock signal CLK, the clock signal XCLK and the start pulse SP by less than a preset distance. However, this is only an example and is not intended to limit the present invention. It should be understood by those skilled in the art that the transmission path of the compensation signal TPC is at least one of the clock signal CLK and the clock signal XCLK. When the interval of the transmission path is less than the preset distance, the noise generated when the clock signals CLK and XCLK within the preset distance are switched at the level can be suppressed or cancelled.

圖5為依照本發明一實施例之觸控面板的雜訊抑制方法的流程圖，請參照圖5，此方法包括有下列步驟：提供第一時脈訊號CLK以及第二時脈訊號XCLK（如步驟S51所示）；提供補償訊號TPC，並將補償訊號TPC傳送至一觸控面板16(如步驟S52所示)；以及每當第一時脈訊號CLK或第二時脈訊號XCLK切換一次位準，補償訊號TPC便於相同時間切換一次與第一時脈訊號CLK或第二時脈訊號XCLK反向之位準(如步驟S53所示)。FIG. 5 is a flowchart of a method for suppressing noise of a touch panel according to an embodiment of the present invention. Referring to FIG. 5, the method includes the following steps: providing a first clock signal CLK and a second clock signal XCLK (eg, Step S51); providing a compensation signal TPC, and transmitting the compensation signal TPC to a touch panel 16 (as shown in step S52); and switching the first clock signal CLK or the second clock signal XCLK once every time. The compensation signal TPC is convenient to switch the level opposite to the first clock signal CLK or the second clock signal XCLK at the same time (as shown in step S53).

綜上所述，由於本發明之補償訊號在第一時脈訊號與第二時脈訊號之其中任一切換位準時也會切換一次位準，且補償訊號之高、低準位的切換方式與第一時脈訊號與第二時脈訊號二者之高、低準位的切換方式相反，因此本發明之補償訊號可以抑制或抵銷第一時脈訊號與第二時脈訊號於切換位準時所產生的雜訊，改善了觸控面板因受到雜訊而影響其觸控能力的問題。In summary, the compensation signal of the present invention also switches the level once when any one of the first clock signal and the second clock signal is switched, and the switching mode of the high and low levels of the compensation signal is The switching mode of the first clock signal and the second clock signal are opposite to each other. Therefore, the compensation signal of the present invention can suppress or cancel the first clock signal and the second clock signal at the switching level. The generated noise improves the touch panel's ability to affect its touch capability due to noise.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技術者，在不脫離本發明之精神和範圍內，當可做些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

10‧‧‧時序控制器10‧‧‧Sequence Controller

11‧‧‧第一訊號產生器11‧‧‧First signal generator

12‧‧‧補償訊號產生器12‧‧‧Compensation signal generator

13‧‧‧第二訊號產生器13‧‧‧Second signal generator

14‧‧‧電壓位準轉換器14‧‧‧Voltage level converter

15‧‧‧振盪器15‧‧‧Oscillator

16‧‧‧觸控面板16‧‧‧Touch panel

17‧‧‧閘極驅動電路17‧‧‧ gate drive circuit

18‧‧‧畫素陣列18‧‧‧ pixel array

CK、CLK、XCLK‧‧‧時脈訊號CK, CLK, XCLK‧‧‧ clock signal

FS‧‧‧第一訊號FS‧‧‧first signal

Hsync‧‧‧水平同步訊號Hsync‧‧‧ horizontal sync signal

SP‧‧‧起始脈衝SP‧‧‧ starting pulse

TPC‧‧‧補償訊號TPC‧‧‧compensation signal

T1、T2‧‧‧時間T1, T2‧‧‧ time

L1、L2、L3、L4‧‧‧位準L1, L2, L3, L4‧‧‧

S51~S53‧‧‧步驟S51~S53‧‧‧Steps

圖1繪有依照本發明一實施例之時序控制器的內部電路方塊；      圖2係繪示水平同步訊號Hsync、時脈訊號CLK、時脈訊號XCLK與補償訊號TPC這四者之間的其中一種時序關係；      圖3係繪示水平同步訊號Hsync、時脈訊號CLK、時脈訊號XCLK與補償訊號TPC這四者之間的另一種時序關係；      圖4係繪示時脈訊號CLK、時脈訊號XCLK、起始脈衝SP與補償訊號TPC這四者在觸控面板16中的其中一種布局方式；      圖5為依照本發明一實施例之觸控面板的雜訊抑制方法的流程圖。1 is an internal circuit block of a timing controller according to an embodiment of the invention; FIG. 2 is a diagram showing one of a horizontal synchronization signal Hsync, a clock signal CLK, a clock signal XCLK, and a compensation signal TPC. Timing relationship; Figure 3 shows another timing relationship between the horizontal sync signal Hsync, the clock signal CLK, the clock signal XCLK and the compensation signal TPC; Figure 4 shows the clock signal CLK, clock signal One of the layouts of the XCLK, the start pulse SP and the compensation signal TPC in the touch panel 16; FIG. 5 is a flow chart of the noise suppression method of the touch panel according to an embodiment of the invention.

10‧‧‧時序控制器 10‧‧‧Sequence Controller

11‧‧‧第一訊號產生器 11‧‧‧First signal generator

12‧‧‧補償訊號產生器 12‧‧‧Compensation signal generator

13‧‧‧第二訊號產生器 13‧‧‧Second signal generator

14‧‧‧電壓位準轉換器 14‧‧‧Voltage level converter

15‧‧‧振盪器 15‧‧‧Oscillator

16‧‧‧觸控面板 16‧‧‧Touch panel

CK、CLK、XCLK‧‧‧時脈訊號 CK, CLK, XCLK‧‧‧ clock signal

FS‧‧‧第一訊號 FS‧‧‧first signal

SP‧‧‧起始脈衝 SP‧‧‧ starting pulse

TPC‧‧‧補償訊號 TPC‧‧‧compensation signal

Claims (11)

一種時序控制器，該時序控制器包括：一第一訊號產生器，用以產生一第一訊號，該第一訊號具有一第一位準與一第二位準；一第二訊號產生器，用以依據該第一訊號產生一第一時脈訊號以及一第二時脈訊號，其中該第一時脈訊號與該第二時脈訊號互為反相；以及一補償訊號產生器，用以依據該第一訊號產生一補償訊號，該補償訊號具有一第三位準與一第四位準，且每當該第一時脈訊號或該第二時脈訊號切換一次位準，該補償訊號便於相同時間切換一次與該第一時脈訊號或該第二時脈訊號反向之位準。 A timing controller includes: a first signal generator for generating a first signal, the first signal having a first level and a second level; and a second signal generator, And generating a first clock signal and a second clock signal according to the first signal, wherein the first clock signal and the second clock signal are mutually inverted; and a compensation signal generator for Generating a compensation signal according to the first signal, the compensation signal has a third level and a fourth level, and the compensation signal is switched every time the first clock signal or the second clock signal is switched once. It is convenient to switch the level opposite to the first clock signal or the second clock signal at the same time. 如申請專利範圍第1項所述之時序控制器，其中每當該第一訊號由該第一位準切換至該第二位準，該補償訊號產生器便於延遲達一第一時間時與延遲達一第二時間時分別切換一次該補償訊號之位準。 The timing controller of claim 1, wherein the compensation signal generator facilitates delaying to a first time and delay each time the first signal is switched from the first level to the second level. When the second time is reached, the level of the compensation signal is switched once. 如申請專利範圍第2項所述之時序控制器，其中該第三位準係大於該第四位準，該第二時間係小於該第一時間，且該補償訊號產生器係於延遲達該第二時間時將該補償訊號由該第四位準切換至該第三位準，並於延遲達該第一時間時將該補償訊號由該第三位準切換至該第四位準，其中當該補償訊號由該第四位準切換至該第三位準時，該第一時脈訊號或該第二時脈訊號係由邏輯高電位切換至邏輯低電位，而當該 補償訊號由該第三位準切換至該第四位準時，該第一時脈訊號或該第二時脈訊號係由邏輯低電位切換至邏輯高電位。 The timing controller of claim 2, wherein the third level is greater than the fourth level, the second time is less than the first time, and the compensation signal generator is delayed by the Switching the compensation signal from the fourth level to the third level at the second time, and switching the compensation signal from the third level to the fourth level when the delay reaches the first time, wherein When the compensation signal is switched from the fourth level to the third level, the first clock signal or the second clock signal is switched from a logic high level to a logic low level, and when When the compensation signal is switched from the third level to the fourth level, the first clock signal or the second clock signal is switched from a logic low level to a logic high level. 如申請專利範圍第2項所述之時序控制器，其中該第三位準係大於該第四位準，該第二時間係大於該第一時間，且該補償訊號產生器係於延遲達該第一時間時將該補償訊號由該第三位準切換至該第四位準，並於延遲達該第二時間時將該補償訊號由該第四位準切換至該第三位準，其中當該補償訊號由該第三位準切換至該第四位準時，該第一時脈訊號或該第二時脈訊號係由邏輯低電位切換至邏輯高電位，而當該補償訊號由該第四位準切換至該第三位準時，該第一時脈訊號或該第二時脈訊號係由邏輯高電位切換至邏輯低電位。 The timing controller of claim 2, wherein the third level is greater than the fourth level, the second time is greater than the first time, and the compensation signal generator is delayed by the Switching the compensation signal from the third level to the fourth level at the first time, and switching the compensation signal from the fourth level to the third level when the delay reaches the second time, wherein When the compensation signal is switched from the third level to the fourth level, the first clock signal or the second clock signal is switched from a logic low level to a logic high level, and when the compensation signal is When the four bits are switched to the third level, the first clock signal or the second clock signal is switched from a logic high level to a logic low level. 如申請專利範圍第1項所述之時序控制器，其更包括一振盪器，該振盪器用以提供一時脈至該第一訊號產生器，以使該第一訊號產生器據以產生該第一訊號。 The timing controller of claim 1, further comprising an oscillator, wherein the oscillator is configured to provide a clock to the first signal generator, so that the first signal generator generates the first A signal. 如申請專利範圍第1項所述之時序控制器，其更包括一電壓位準轉換器，該電壓位準轉換器用以調整該第一時脈訊號、該第二時脈訊號、以及該補償訊號的電壓位準。 The timing controller of claim 1, further comprising a voltage level converter, wherein the voltage level converter is configured to adjust the first clock signal, the second clock signal, and the compensation signal The voltage level. 一種觸控面板的雜訊抑制方法，其包括：提供一第一時脈訊號以及一第二時脈訊號；以及提供一補償訊號，並將該補償訊號傳送至一觸控面板中，該補償訊號具有一第一位準與一第二位準，且每當該第一時脈訊號或該第二時脈訊 號切換一次位準，該補償訊號便於相同時間切換一次與該第一時脈訊號或該第二時脈訊號反向之位準。 A noise suppression method for a touch panel includes: providing a first clock signal and a second clock signal; and providing a compensation signal, and transmitting the compensation signal to a touch panel, the compensation signal Having a first level and a second level, and each time the first clock signal or the second time pulse The number is switched once, and the compensation signal is convenient to switch the level opposite to the first clock signal or the second clock signal at the same time. 如申請專利範圍第7項所述之雜訊抑制方法，其更包括提供一第一訊號，並依據該第一訊號產生該第一時脈訊號以及該第二時脈訊號，其中該第一訊號具有一第三位準以及第四位準，且每當該第一訊號由該第三位準切換至該第四位準，便於延遲達一第一時間時與延遲達一第二時間時分別切換一次該補償訊號之位準。 The noise suppression method of claim 7, further comprising: providing a first signal, and generating the first clock signal and the second clock signal according to the first signal, wherein the first signal Having a third level and a fourth level, and each time the first signal is switched from the third level to the fourth level, the delay is up to a first time and the delay is up to a second time Switch the level of the compensation signal once. 如申請專利範圍第8項所述之雜訊抑制方法，其中該第一位準係大於該第二位準，該第二時間係小於該第一時間，且係於延遲達該第一時間時將該補償訊號由該第一位準切換至該第二位準，並於延遲達該第二時間時將該補償訊號由該第二位準切換至該第一位準，其中當該補償訊號由該第二位準切換至該第一位準時，該第一時脈訊號或該第二時脈訊號係由邏輯高電位切換至邏輯低電位，而當該補償訊號由該第一位準切換至該第二位準時，該第一時脈訊號或該第二時脈訊號係由邏輯低電位切換至邏輯高電位。 The method for suppressing noise according to claim 8, wherein the first level is greater than the second level, the second time is less than the first time, and the delay is up to the first time Switching the compensation signal from the first level to the second level, and switching the compensation signal from the second level to the first level when the delay reaches the second time, where the compensation signal When the second level is switched to the first level, the first clock signal or the second clock signal is switched from a logic high level to a logic low level, and when the compensation signal is switched by the first level Up to the second level, the first clock signal or the second clock signal is switched from a logic low level to a logic high level. 如申請專利範圍第8項所述之雜訊抑制方法，其中該第一位準係大於該第二位準，該第二時間係大於該第一時間，且係於延遲達該第一時間時將該補償訊號由該第一位準切換至該第二位準，並於延遲達該第二時間時將該補償訊號由該第二位準切換至該第一位準，其中當該補償訊號由該第一位準切換至該第二位準時，該第一時脈訊號或該第 二時脈訊號係由邏輯低電位切換至邏輯高電位，而當該補償訊號由該第二位準切換至該第一位準時，該第一時脈訊號或該第二時脈訊號係由邏輯高電位切換至邏輯低電位。 The method for suppressing noise according to claim 8, wherein the first level is greater than the second level, the second time is greater than the first time, and the delay is up to the first time Switching the compensation signal from the first level to the second level, and switching the compensation signal from the second level to the first level when the delay reaches the second time, where the compensation signal When the first level is switched to the second level, the first clock signal or the first The second clock signal is switched from a logic low level to a logic high level, and when the compensation signal is switched from the second level to the first level, the first clock signal or the second clock signal is logic The high potential switches to a logic low. 如申請專利範圍第7項所述之雜訊抑制方法，其中在該觸控面板中，該補償訊號的傳送路徑係與該第一時脈訊號與該第二時脈訊號二者之至少其中之一的傳送路徑的間隔小於一預設距離。 The method for suppressing noise according to claim 7, wherein in the touch panel, the transmission path of the compensation signal is at least one of the first clock signal and the second clock signal. The interval of one of the transmission paths is less than a predetermined distance.
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