TWI587377B - Method for forming semiconductor device structure - Google Patents
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Description
本揭露係關於一種半導體裝置結構的形成方法，且特別係關於一種溝槽式閘極金氧半場效電晶體(trench gate metal-oxide-semiconductor field effect transistor，trench gate MOSFET)的形成方法。 The present disclosure relates to a method of forming a semiconductor device structure, and more particularly to a method of forming a trench gate metal-oxide-semiconductor field effect transistor (trench gate MOSFET).
半導體產業持續地改善不同的電子組件之整合密度，藉由持續降低最小元件尺寸，讓更多組件能夠在給定的面積中整合。例如，被廣泛地應用在電力開關(power switch)元件之溝槽式閘極金氧半導體場效電晶體，便是利用垂直結構的設計，以提升功能密度。其利用晶片之背面作為汲極，而於晶片之正面製作多個電晶體之源極以及閘極。 The semiconductor industry continues to improve the integration density of different electronic components, allowing more components to be integrated in a given area by continuously reducing the minimum component size. For example, trench gate MOSFETs, which are widely used in power switch components, utilize vertical structure design to increase functional density. It uses the back side of the wafer as a drain, and the source and gate of a plurality of transistors are fabricated on the front side of the wafer.
然而，隨著半導體裝置的功能密度不斷提升，處理及製造半導體裝置的複雜度亦跟著增加。例如，因受限於傳統微影曝光機台的對準能力，導致溝槽式閘極金氧半導體場效電晶體的接觸結構之特徵尺寸無法縮小，因此無法有效地降低裝置之導通電阻(on resistance)。 However, as the functional density of semiconductor devices continues to increase, the complexity of processing and manufacturing semiconductor devices has also increased. For example, due to the alignment ability of the conventional lithography exposure machine, the contact size of the contact structure of the trench gate MOS field effect transistor cannot be reduced, so the on-resistance of the device cannot be effectively reduced (on Resistance).
在一些實施例中，提供一種半導體裝置結構的形成方法，包括：形成複數個溝槽於一基底中；形成內襯(lining) 於溝槽之一閘極介電層；以一閘極材料填充溝槽；回蝕刻閘極材料以暴露溝槽之上部；以一第一介電層再填充(refill)溝槽之上部且覆蓋溝槽之間的一基底表面；實行一第一化學機械研磨製程以部分地移除第一介電層，直到暴露溝槽之間的基底表面；以及利用形成於溝槽之上部的第一介電層作為一蝕刻遮罩，藉由暴露之基底表面，蝕刻基底以形成一自對準接觸(self-aligned contact)開口於溝槽之間。 In some embodiments, a method of forming a semiconductor device structure is provided, including: forming a plurality of trenches in a substrate; forming a liner a gate dielectric layer of the trench; filling the trench with a gate material; etching back the gate material to expose the upper portion of the trench; refilling the upper portion of the trench with a first dielectric layer and covering a substrate surface between the trenches; performing a first CMP process to partially remove the first dielectric layer until the substrate surface between the trenches is exposed; and utilizing a first dielectric layer formed over the trench The electrical layer acts as an etch mask by etching the substrate to form a self-aligned contact between the trenches by exposing the surface of the substrate.
在一些實施例中，亦提供一種半導體裝置結構的形成方法，包括：提供一基底，基底上形成有一墊層(pad layer)；形成複數個溝槽於基底中；等向性蝕刻溝槽之頂角以擴大溝槽之上部；形成內襯於溝槽之一閘極介電層；以一閘極材料填充溝槽；回蝕刻閘極材料以暴露擴大之溝槽之上部；以一介電層再填充(refill)擴大之溝槽之上部且覆蓋溝槽之間的一基底表面；實行一化學機械研磨製程.以部分地移除介電層，直到暴露溝槽之間的基底表面；以及利用形成於擴大之溝槽之上部的介電層作為一蝕刻遮罩，藉由暴露之基底表面，蝕刻基底以形成一自對準接觸開口於溝槽之間。 In some embodiments, a method of forming a semiconductor device structure is also provided, including: providing a substrate on which a pad layer is formed; forming a plurality of trenches in the substrate; and isotropically etching the top of the trench An angle to enlarge the upper portion of the trench; forming a gate dielectric layer lining the trench; filling the trench with a gate material; etching back the gate material to expose the upper portion of the enlarged trench; with a dielectric layer Refilling the upper portion of the enlarged trench and covering a substrate surface between the trenches; performing a chemical mechanical polishing process to partially remove the dielectric layer until the surface of the substrate between the trenches is exposed; A dielectric layer formed over the enlarged trench serves as an etch mask, and the substrate is etched to form a self-aligned contact opening between the trenches by exposing the surface of the substrate.
10、30、50、70‧‧‧半導體裝置結構的形成方法 10, 30, 50, 70‧‧‧Methods for forming semiconductor device structures
12~28、32~34、51~53、71~79‧‧‧半導體裝置結構的形成方法之步驟 12~28, 32~34, 51~53, 71~79‧‧‧ steps of the method for forming the structure of the semiconductor device
100‧‧‧基底 100‧‧‧Base
100A‧‧‧暴露的基底表面 100A‧‧‧ exposed substrate surface
102‧‧‧溝槽 102‧‧‧ trench
102A‧‧‧溝槽之上部 102A‧‧‧Top part of the trench
102B‧‧‧溝槽之上部的側壁 102B‧‧‧ sidewalls above the trench
102C‧‧‧溝槽之頂角 102C‧‧‧The top corner of the trench
104‧‧‧蝕刻製程 104‧‧‧ etching process
106‧‧‧閘極介電層 106‧‧‧gate dielectric layer
108‧‧‧閘極材料 108‧‧‧gate material
110‧‧‧主體區 110‧‧‧ Main area
112‧‧‧源極區 112‧‧‧ source area
114、114’‧‧‧介電層 114, 114'‧‧‧ dielectric layer
116‧‧‧化學機械研磨製程 116‧‧‧Chemical mechanical polishing process
118‧‧‧接觸開口 118‧‧‧Contact opening
120‧‧‧接觸阻障層 120‧‧‧Contact barrier
122‧‧‧導電材料 122‧‧‧Electrical materials
124‧‧‧接觸插塞結構 124‧‧‧Contact plug structure
402‧‧‧硬遮罩層 402‧‧‧hard mask layer
600A‧‧‧基底表面 600A‧‧‧ substrate surface
610‧‧‧等向性蝕刻製程 610‧‧‧Iotropic etching process
614、614’‧‧‧介電層 614, 614'‧‧‧ dielectric layer
810‧‧‧等向性蝕刻製程 810‧‧‧Iotropic etching process
812‧‧‧墊層 812‧‧‧ cushion
812a‧‧‧墊氧化層 812a‧‧‧Mat oxide layer
812b‧‧‧墊氮化層 812b‧‧‧Material Nitride
第1圖顯示根據一些實施例，半導體裝置結構的形成方法之流程圖；第2A圖至第2J圖顯示根據一些實施例，使用第1圖所示之方法所形成之半導體裝置結構在不同階段之剖面圖；第3圖顯示根據一些實施例，半導體裝置結構的形成方法 之流程圖；第4A圖至第4C圖顯示根據一些實施例，使用第3圖所示之方法所形成之半導體裝置結構在不同階段之剖面圖；第5圖顯示根據一些實施例，半導體裝置結構的形成方法之流程圖；第6A圖至第6F圖顯示根據一些實施例，使用第5圖所示之方法所形成之半導體裝置結構在不同階段之剖面圖；第7圖顯示根據一些實施例，半導體裝置結構的形成方法之流程圖；第8A圖至第8F圖顯示根據一些實施例，使用第7圖所示之方法所形成之半導體裝置結構在不同階段之剖面圖。 1 is a flow chart showing a method of forming a semiconductor device structure according to some embodiments; FIGS. 2A to 2J are diagrams showing the structure of a semiconductor device formed using the method shown in FIG. 1 at different stages, according to some embodiments. Sectional view; FIG. 3 shows a method of forming a semiconductor device structure in accordance with some embodiments FIG. 4A to FIG. 4C are cross-sectional views showing semiconductor device structures formed using the method illustrated in FIG. 3 at different stages, and FIG. 5 is a view showing a semiconductor device structure in accordance with some embodiments. A flow chart of a method of forming; FIGS. 6A-6F show cross-sectional views of semiconductor device structures formed using the method illustrated in FIG. 5 at different stages, in accordance with some embodiments; FIG. 7 shows, in accordance with some embodiments, A flowchart of a method of forming a semiconductor device structure; FIGS. 8A through 8F are cross-sectional views showing the structure of a semiconductor device formed using the method shown in FIG. 7 at different stages, in accordance with some embodiments.
以下將配合所附圖式詳述本發明之實施例，應注意的是，依照工業上的標準實施，所附圖示並未按照比例繪製，事實上，可能任意的放大或縮小元件的尺寸以便清楚表現出本發明的特徵。 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, which are to be considered in accordance with the The features of the invention are clearly shown.
以下公開許多不同的實施方法或是例子來實行本發明之不同特徵，以下描述具體的元件及其排列的例子以闡述本發明。當然這些僅是例子且不該以此限定本發明的範圍。例如，在描述中提及第一個元件形成於第二個元件上時，其可以包括第一個元件與第二個元件直接接觸的實施例，也可以包括有其它元件形成於第一個元件與第二個元件之間的實施例，其中第一個元件與第二個元件並未直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地 敘述本揭露，不代表所討論的不同實施例及/或結構之間有特定的關係。 The various features of the invention are set forth in the description of the various embodiments of the invention. Of course, these are only examples and should not limit the scope of the invention. For example, when the description refers to the first element being formed on the second element, it may include an embodiment in which the first element is in direct contact with the second element, and may include other elements formed on the first element. An embodiment between the second element and the second element is not in direct contact with the second element. In addition, repeated labels or labels may be used in different embodiments, which are simply and clearly The disclosure of the present disclosure does not imply a specific relationship between the various embodiments and/or structures discussed.
此外，其中可能用到與空間相關的用詞，像是“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些關係詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係，這些空間關係詞包括使用中或操作中的裝置之不同方位，以及圖示中所描述的方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。 In addition, space-related terms such as "below", "below", "lower", "above", "higher" and similar terms may be used. Words for convenience in describing the relationship between one element or feature(s) in the drawing and another element or feature(s), the spatial terminology includes different orientations of the device in operation or operation, and The orientation described. The device may be turned to a different orientation (rotated 90 degrees or other orientation), and the spatially related adjectives used therein may also be interpreted identically.
本發明提供之形成半導體裝置結構之方法採用高選擇性之化學機械研磨製搭配高選擇性之蝕刻製程，形成自對準接觸(self-aligned contact)結構。可使用於溝槽式閘極金氧半場效電晶體(trench gate MOSFET)，此方法有助於半導體裝置結構之關鍵尺寸微縮化，且亦可有效降低半導體裝置結構的導通電阻(on resistance)。 The method of forming a semiconductor device structure provided by the present invention employs a highly selective chemical mechanical polishing process in conjunction with a highly selective etching process to form a self-aligned contact structure. It can be used for trench gate MOSFETs, which contributes to the miniaturization of critical dimensions of semiconductor device structures and also effectively reduces the on resistance of semiconductor device structures.
第1圖顯示根據一些實施例，半導體裝置結構的形成方法10之流程圖。應理解的是，可於半導體裝置結構的形成方法10進行前、進行中及/或進行後提供額外的操作。在不同的實施例中，所述的一些階段可以被取代或刪除。可添加額外特徵於半導體裝置結構，在不同的實施例中，以下所述的一些特徵可以被取代或刪除。第2A圖至第2J圖顯示根據一些實施例，使用第1圖所示之方法10所形成之半導體裝置結構在不同階段之剖面圖。 FIG. 1 shows a flow chart of a method 10 of forming a semiconductor device structure in accordance with some embodiments. It should be understood that additional operations may be provided before, during, and/or after the forming method 10 of the semiconductor device structure. In various embodiments, some of the stages described may be replaced or deleted. Additional features may be added to the semiconductor device structure, and in various embodiments, some of the features described below may be replaced or deleted. 2A through 2J are cross-sectional views showing the structure of the semiconductor device formed using the method 10 shown in Fig. 1 at various stages, in accordance with some embodiments.
請參照第1及2A圖，半導體裝置結構的形成方法10 起始於步驟12，形成溝槽102於基板100中。基板100可包括：單晶結構、多晶結構或非晶結構的矽或鍺之元素半導體；氮化鎵(GaN)、碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)或銻化銦(indium antimonide)等化合物半導體；SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP或GaInAsP等合金半導體或其它合適的材料或前述組合。在一些實施例中，可利用一或多個微影及蝕刻製程形成溝槽102。 Referring to FIGS. 1 and 2A, a method of forming a semiconductor device structure 10 Beginning at step 12, trenches 102 are formed in substrate 100. The substrate 100 may include: a single crystal structure, a polycrystalline structure or an amorphous structure of germanium or germanium elemental semiconductor; gallium nitride (GaN), silicon carbide, gallium arsenic, gallium phosphide ( Alloy semiconductor such as gallium phosphide, indium phosphide, indium arsenide or indium antimonide; alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP or other suitable Material or combination of the foregoing. In some embodiments, the trenches 102 can be formed using one or more lithography and etching processes.
請參照第1及2B圖，在一些實施例中，半導體裝置結構的形成方法10可包含步驟14，進行蝕刻製程104以圓化(rounding)溝槽102之頂角102C。頂角102C位於溝槽102的頂部之兩側。經圓化之頂角102C使溝槽102的頂部寬度大於底部寬度，換言之，溝槽102具有經擴大的頂部。前述蝕刻製程可為乾蝕刻、濕蝕刻、其它合適的蝕刻製程或前述之組合。乾蝕刻例如可為反應離子蝕刻(reactive ion etch，RIE)或電漿蝕刻plasma etch)等。在一些實施例中，蝕刻製程104可為軟蝕刻(soft etch)製程，為一低能量/低損害的電漿蝕刻製程，對基板造成的損害較一般蝕刻製程小。 Referring to FIGS. 1 and 2B , in some embodiments, the method 10 of forming a semiconductor device structure can include the step 14 of performing an etching process 104 to round the apex angle 102C of the trench 102 . The top corners 102C are located on either side of the top of the trench 102. The rounded apex angle 102C causes the top width of the trench 102 to be greater than the bottom width, in other words, the trench 102 has an enlarged top. The foregoing etching process may be dry etching, wet etching, other suitable etching processes, or a combination of the foregoing. The dry etching may be, for example, reactive ion etch (RIE) or plasma etching (etch etch) or the like. In some embodiments, the etch process 104 can be a soft etch process, which is a low energy/low damage plasma etch process that causes less damage to the substrate than a typical etch process.
此外，在一些實施例中，可選擇性(optionally)順應地(conformally)形成犧牲氧化(sacrificial oxide)層(未繪示)於溝槽102上，接著再將其移除，以清除形成溝槽的步驟對基板造成之損害(例如，蝕刻製程產生的損害)。 Moreover, in some embodiments, a sacrificial oxide layer (not shown) may be formed conformally formed on the trench 102 and then removed to remove the trenches. The steps cause damage to the substrate (eg, damage from the etching process).
接著，請參照第1及2C圖，於步驟16中，形成內襯(lining)溝槽102之閘極介電層106。在一些實施例中，閘極介電 層106可包含介電材料，例如：氧化矽、氮化矽、氮氧化矽、高介電常數(high-k)介電材料、其它合適之介電材料或前述之組合。此高介電常數介電材料可為金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽化物、金屬的氮氧化物、金屬鋁酸鹽、鋯矽酸鹽、鋯鋁酸鹽。例如，此高介電常數介電材料可為LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfO2、HfO3、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba,Sr)TiO3(BST)、Al2O3或前述組合。 Next, referring to FIGS. 1 and 2C, in step 16, a gate dielectric layer 106 of a liner trench 102 is formed. In some embodiments, the gate dielectric layer 106 may comprise a dielectric material such as hafnium oxide, tantalum nitride, hafnium oxynitride, a high-k dielectric material, other suitable dielectric materials. Or a combination of the foregoing. The high-k dielectric material may be a metal oxide, a metal nitride, a metal halide, a transition metal oxide, a transition metal nitride, a transition metal telluride, a metal oxynitride, a metal aluminate, or a zirconium Acid salt, zirconium aluminate. For example, the high-k dielectric material may be LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfO 2 , HfO 3 , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO 3 (BST), Al 2 O 3 or a combination thereof.
在一些實施例中，可利用熱氧化(thermal oxidation)製程、化學氣相沉積(chemical vapor deposition,CVD)製程、旋轉塗佈(spin coating)、原子層沉積(atomic layer deposition,ALD)製程、其它合適的製程或前述之組合形成閘極介電層106。 In some embodiments, a thermal oxidation process, a chemical vapor deposition (CVD) process, a spin coating, an atomic layer deposition (ALD) process, or the like may be utilized. A suitable process or combination of the foregoing forms a gate dielectric layer 106.
接著，請參照第1及2D圖，於步驟18中，以閘極材料108填充溝槽102。閘極材料108可為非晶矽、多晶矽、金屬或前述之組合。在一些實施例中，可藉由沉積閘極材料108以覆蓋基板100及溝槽102，以及實行平坦化製程直到暴露溝槽102之間的基底100以填充溝槽102。 Next, referring to FIGS. 1 and 2D, in step 18, the trench 102 is filled with the gate material 108. The gate material 108 can be amorphous germanium, polycrystalline germanium, metal, or a combination of the foregoing. In some embodiments, trench 100 can be filled by depositing gate material 108 to cover substrate 100 and trench 102, and performing a planarization process until exposed substrate 100 between trenches 102.
在一些實施例中，可藉由化學氣相沉積(CVD)製程、旋轉塗佈製程、原子層沉積(ALD)製程、物理氣相沉積(PVD)製程、其它合適的製程或前述之組合沉積閘極材料108。再者，平坦化製程可包含化學機械研磨(chemical mechanical planarization,CMP)製程、機械拋光製程、蝕刻製程、其它合 適的製程或前述之組合。 In some embodiments, the deposition gate can be formed by a chemical vapor deposition (CVD) process, a spin coating process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination thereof. Pole material 108. Furthermore, the planarization process may include a chemical mechanical planarization (CMP) process, a mechanical polishing process, an etching process, and other processes. Suitable process or a combination of the foregoing.
此外，閘極材料108之頂部可更包括一金屬矽化物層(未繪示)。此金屬矽化物可包含矽化鎳(nickel silicide)、矽化鈷(cobalt silicide)、矽化鎢(tungsten silicide)、矽化鈦(titanium silicide)、矽化鉭(tantalum silicide)、矽化鉑(platinum silicide)、矽化鉺(erbium silicide)或前述之組合。 In addition, the top of the gate material 108 may further include a metal telluride layer (not shown). The metal halide may include nickel silicide, cobalt silicide, tungsten tanning, titanium silicide, tantalum silicide, platinum silicide, bismuth telluride (erbium silicide) or a combination of the foregoing.
請參照第1及2E~2F圖，於步驟20中，回蝕刻(etch back)閘極材料108以暴露溝槽102之上部102A。可接著實行步驟22，形成主體區110以及位於主體區110之上的源極區112於溝槽102之間的基底100中。主體區110可作為半導體裝置結構的通道(channel)區。在一些實施例中，主體區110可具有P型摻雜物(例如：硼或銦等)，源極區112可具有N型摻雜物(例如：磷或砷等)。 Referring to FIGS. 1 and 2E-2F, in step 20, the gate material 108 is etched back to expose the upper portion 102A of the trench 102. Step 22 may then be performed to form the body region 110 and the source region 112 over the body region 110 in the substrate 100 between the trenches 102. The body region 110 can serve as a channel region of a semiconductor device structure. In some embodiments, body region 110 can have a P-type dopant (eg, boron or indium, etc.), and source region 112 can have an N-type dopant (eg, phosphorus or arsenic, etc.).
可藉由離子佈植製程以形成主體區110及源極區112。源極區112的深度可大於溝槽102暴露之上部102A的深度。在一些實施例中，可先形成主體區110，再形成源極區112於主體區110上方。然而，在另一些實施例中，亦可先形成源極區112於基底100中，然後再以高能離子佈植形成主體區110於源極區112下方。 The body region 110 and the source region 112 may be formed by an ion implantation process. The depth of the source region 112 may be greater than the depth at which the trench 102 exposes the upper portion 102A. In some embodiments, the body region 110 can be formed first, and the source region 112 can be formed over the body region 110. However, in other embodiments, the source region 112 may be first formed in the substrate 100, and then the body region 110 may be formed under the source region 112 by high energy ion implantation.
在一些實施例中，可接著實行退火(annealing)製程以活化佈植的摻質以及減少主體區110及源極區112中的摻質擴散。在一些實施例中，退火製程可為快速熱退火(rapid thermal annealing,RTA)製程。 In some embodiments, an annealing process can then be performed to activate the implanted dopant and reduce dopant diffusion in the body region 110 and the source region 112. In some embodiments, the annealing process can be a rapid thermal annealing (RTA) process.
此外，應注意的是，形成主體區110以及源極區112 於溝槽102之間的基底100中之步驟亦可於其它階段實行，只要能夠確實地形成主體區及源極區即可。例如，亦可於實行化學機械研磨(CMP)製程直到暴露溝槽之間的基底表面之步驟(步驟26，詳述於後文)後，再形成主體區以及源極區於基底中。 In addition, it should be noted that the body region 110 and the source region 112 are formed. The steps in the substrate 100 between the trenches 102 can also be performed at other stages as long as the body region and the source region can be reliably formed. For example, the body region and the source region may be formed in the substrate after performing a chemical mechanical polishing (CMP) process until the step of exposing the surface of the substrate between the trenches (step 26, which is described later in detail).
接著，請參照第1及2G圖，於步驟24中，形成介電層114以再填充(refill)溝槽102之上部102A，且覆蓋溝槽102之間的基底100，包含溝槽102之間的基底100的頂部及側壁。介電層114可用以將閘極材料108與後續形成之導電元件電性絕緣。介電層114可為氧化矽、氮化矽、氮氧化矽、硼磷矽玻璃(borophosphosilicate glass,BPSG)、磷矽玻璃(phosphosilicate glass,PSG)、旋塗式玻璃(spin-on glass,SOG)、或其它合適之介電材料或前述之組合。 Next, referring to FIGS. 1 and 2G, in step 24, a dielectric layer 114 is formed to refill the upper portion 102A of the trench 102 and cover the substrate 100 between the trenches 102, including between the trenches 102. The top and side walls of the substrate 100. Dielectric layer 114 can be used to electrically insulate gate material 108 from subsequently formed conductive elements. The dielectric layer 114 may be yttrium oxide, tantalum nitride, yttrium oxynitride, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin-on glass (SOG). Or other suitable dielectric material or a combination of the foregoing.
在一些實施例中，可藉由化學氣相沉積(CVD)製程、旋轉塗佈、原子層沉積(ALD)製程、物理氣相沉積(PVD)製程或前述之組合形成介電層114。在一些實施例中，使用高密度電漿(high density plasma,HDP)沉積製程形成介電層114，如第2G圖所示。 In some embodiments, the dielectric layer 114 can be formed by a chemical vapor deposition (CVD) process, a spin coating, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or a combination of the foregoing. In some embodiments, the dielectric layer 114 is formed using a high density plasma (HDP) deposition process, as shown in FIG. 2G.
接著，請參照第1及2H圖，於步驟26中，實行化學機械研磨(CMP)製程116以部分地移除介電層114，直到暴露溝槽102之間的基底表面100A。在實行化學機械研磨製程116之後，仍有部分介電層114’存留於溝槽之上部102A。再者，化學機械研磨製程116亦部分地移除閘極介電層106。 Next, referring to FIGS. 1 and 2H, in step 26, a chemical mechanical polishing (CMP) process 116 is performed to partially remove the dielectric layer 114 until the substrate surface 100A between the trenches 102 is exposed. After the CMP process 116 is performed, a portion of the dielectric layer 114' remains in the trench upper portion 102A. Moreover, the CMP process 116 also partially removes the gate dielectric layer 106.
在此，可使用對於介電層114及基底100具有高選擇性的化學機械研磨製程116，以選擇性地移除介電層114而不 移除基底100。在一些實施例中，暴露的基底表面100A可位於基底100的高台(mesa)區，即基底100頂部凸出的區域，如第2H圖中虛線方塊標示之區域。 Here, a chemical mechanical polishing process 116 having high selectivity to the dielectric layer 114 and the substrate 100 can be used to selectively remove the dielectric layer 114 without The substrate 100 is removed. In some embodiments, the exposed substrate surface 100A can be located in the mesa region of the substrate 100, i.e., the region that protrudes from the top of the substrate 100, as indicated by the dashed squares in Figure 2H.
接著，請參照第1及2I圖，於步驟28中，利用形成於溝槽之上部102A的介電層114’作為蝕刻遮罩(etching mask)，藉由暴露的基底表面100A，蝕刻基底100以形成接觸開口118於溝槽102之間。換言之，接觸開口118是由仍存留於溝槽之上部102A的介電層114’所定義，因此所形成之接觸開口118為一自對準(self-aligned)接觸開口。再者，接觸開口118貫穿形成於基底110中的源極區112且延伸至主體區110。 Next, referring to FIGS. 1 and 2I, in step 28, the dielectric layer 114' formed on the upper portion 102A of the trench is used as an etching mask, and the substrate 100 is etched by the exposed substrate surface 100A. Contact openings 118 are formed between the trenches 102. In other words, the contact opening 118 is defined by a dielectric layer 114' that remains in the upper portion 102A of the trench, such that the contact opening 118 formed is a self-aligned contact opening. Moreover, the contact opening 118 extends through the source region 112 formed in the substrate 110 and extends to the body region 110.
在此，可使用對於介電層114及基底100具有高選擇性的蝕刻製程，以選擇性地蝕刻基底100而不蝕刻介電層114。在一些實施例中，前述蝕刻製程可為乾蝕刻，例如可為反應離子蝕刻(reactive ion etch，RIE)、電漿蝕刻、其它合適的非等向性蝕刻製程或前述之組合。 Here, an etching process having high selectivity to the dielectric layer 114 and the substrate 100 may be used to selectively etch the substrate 100 without etching the dielectric layer 114. In some embodiments, the foregoing etching process may be dry etching, such as reactive ion etch (RIE), plasma etching, other suitable anisotropic etching processes, or a combination thereof.
此外，之後可形成接觸阻障層120及導電材料122於接觸開口118中，以形成接觸插塞(plug)結構124，如第2J圖所示。接觸阻障層120的材料可包括鈷(Co)、鉭(Ta)、鈷鎢磷化物(CoWP)、鈦(Ti)、鉭化氮(TaN)、釕(Ru)或前述之組合。導電材料122可包括鋁(Al)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、氮化鈦(titanium nitride,TiN)、氮化鉭(tantalum nitride,TaN)、矽化鎳(nickel silicide,NiSi)、矽化鈷(cobalt silicide,CoSi)、碳化鉭(tantulum carbide,TaC)、矽氮化鉭(tantulum silicide nitride,TaSiN)、碳氮化鉭(tantalum carbide nitride,TaCN)、鋁化鈦 (titanium aluminide,TiAl)，鋁氮化鈦(titanium aluminide nitride,TiAlN)、其他合適的金屬或前述之組合。 In addition, contact barrier layer 120 and conductive material 122 may be formed in contact opening 118 to form a contact plug structure 124, as shown in FIG. 2J. The material of the contact barrier layer 120 may include cobalt (Co), tantalum (Ta), cobalt tungsten phosphide (CoWP), titanium (Ti), niobium nitride (TaN), ruthenium (Ru), or a combination thereof. The conductive material 122 may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), Nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN) Titanium aluminide (titanium aluminide, TiAl), titanium aluminide nitride (TiAlN), other suitable metals or a combination of the foregoing.
在一些實施例中，可藉由化學氣相沉積(CVD)製程、原子層沉積(ALD)製程、物理氣相沉積(PVD)製程或前述之組合形成接觸阻障層120及導電材料122。 In some embodiments, the contact barrier layer 120 and the conductive material 122 may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or a combination thereof.
第3圖顯示根據另一些實施例，半導體裝置結構的形成方法30之流程圖。第4A圖至第4C圖顯示根據一些實施例，使用第3圖所示之方法30所形成之半導體裝置結構在不同階段之剖面圖。第4A~4C圖中與第2A~2J圖相同的元件符號代表與第2A~2J圖相同或相似的元件，於此便不再贅述。 FIG. 3 shows a flow chart of a method 30 of forming a semiconductor device structure in accordance with further embodiments. 4A through 4C are cross-sectional views showing the structure of the semiconductor device formed using the method 30 shown in Fig. 3 at various stages, in accordance with some embodiments. The same component symbols as in FIGS. 2A to 2J in FIGS. 4A to 4C represent the same or similar components as those in FIGS. 2A to 2J, and will not be described again.
請參照第3及4A圖，半導體裝置結構的形成方法30起始於步驟32，形成圖案化的硬遮罩層402於基底100上。圖案化的硬遮罩層402可用以定義後續將形成之溝槽102的位置。硬遮罩402可由氧化矽、氮化矽、氮氧化矽、碳化矽、其它合適的材料或前述之組合所形成。硬遮罩層402可具有單層或多層結構。 Referring to FIGS. 3 and 4A, the method 30 for forming a semiconductor device structure begins at step 32 by forming a patterned hard mask layer 402 on the substrate 100. The patterned hard mask layer 402 can be used to define the location of the trenches 102 that will be subsequently formed. The hard mask 402 may be formed of tantalum oxide, tantalum nitride, tantalum oxynitride, tantalum carbide, other suitable materials, or a combination of the foregoing. The hard mask layer 402 can have a single layer or a multilayer structure.
在一些實施例中，可藉由化學氣相沉積(CVD)製程、原子層沉積(ALD)製程、熱氧化(thermal oxidation)製程、物理氣相沉積(PVD)製程、其它合適的製程或前述之組合形成硬遮罩層402。化學氣相沉積製程例如可為低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)製程或電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)製程等。再者，可藉由一或多個微影及蝕刻製程以圖案化硬遮罩層402。 In some embodiments, it may be by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, a physical vapor deposition (PVD) process, other suitable processes, or the foregoing. The hard mask layer 402 is formed in combination. The chemical vapor deposition process may be, for example, a low-pressure chemical vapor deposition (LPCVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. Furthermore, the hard mask layer 402 can be patterned by one or more lithography and etching processes.
接著，請參照第3及4B圖，於步驟34中，以經圖案化之硬遮罩層402作為蝕刻遮罩，進行蝕刻製程以移除部分的基底100，使溝槽102具有錐形輪廓(tapered profile)。如第4B圖所示，溝槽102之側壁為傾斜的，經蝕刻之溝槽102的頂部寬度大於底部寬度，換言之，溝槽102具有經擴大的頂部。在一些實施例中，前述蝕刻製程可為乾蝕刻、濕蝕刻、其它合適的蝕刻製程或前述之組合。乾蝕刻例如可為反應離子蝕刻(reactive ion etch，RIE)或電漿蝕刻等。 Next, referring to FIGS. 3 and 4B, in step 34, the patterned hard mask layer 402 is used as an etch mask, and an etching process is performed to remove a portion of the substrate 100 so that the trench 102 has a tapered outline ( Tapered profile). As shown in FIG. 4B, the sidewalls of the trenches 102 are sloped, and the top width of the etched trenches 102 is greater than the bottom width, in other words, the trenches 102 have enlarged tops. In some embodiments, the foregoing etching process can be dry etching, wet etching, other suitable etching processes, or a combination of the foregoing. The dry etching may be, for example, reactive ion etching (RIE) or plasma etching.
接著，移除硬遮罩層402後，可接續半導體裝置結構的形成方法10之步驟16~28以完成方法30，即，形成內襯溝槽102之閘極介電層106(步驟16)；以閘極材料108填充溝槽102(步驟18)；回蝕刻閘極材料108以暴露溝槽之上部102A(步驟20)；形成主體區110以及源極區112於溝槽之間的基底中(步驟22)；形成介電層114以再填充溝槽之上部102A且覆蓋溝槽之間的基底(步驟24)；實行化學機械研磨製程116以部分地移除介電層114，直到暴露溝槽之間的基底表面(步驟26)；利用於溝槽之上部102A的介電層114’作為蝕刻遮罩，蝕刻基底100以形成接觸開口118於溝槽102之間(步驟28)。利用方法30所形成之半導體裝置結構如第4C圖所示，具有由形成於溝槽之上部102A的介電層114’所定義之自對準接觸開口118。 After the hard mask layer 402 is removed, the method 30 of the semiconductor device structure forming method 10 can be continued to complete the method 30, that is, the gate dielectric layer 106 of the liner trench 102 is formed (step 16); The trench 102 is filled with a gate material 108 (step 18); the gate material 108 is etched back to expose the trench upper portion 102A (step 20); the body region 110 and the source region 112 are formed in the substrate between the trenches ( Step 22) forming a dielectric layer 114 to refill the trench upper portion 102A and covering the substrate between the trenches (step 24); performing a chemical mechanical polishing process 116 to partially remove the dielectric layer 114 until the trench is exposed The substrate surface is interposed (step 26); the dielectric layer 114' is utilized as an etch mask for the upper portion 102A of the trench, and the substrate 100 is etched to form a contact opening 118 between the trenches 102 (step 28). The semiconductor device structure formed by method 30, as shown in FIG. 4C, has a self-aligned contact opening 118 defined by a dielectric layer 114' formed over the upper portion 102A of the trench.
第5圖顯示根據另一些實施例，半導體裝置結構的形成方法50之流程圖。第6A圖至第6F圖顯示根據一些實施例，使用第5圖所示之方法50所形成之半導體裝置結構在不同階段之剖面圖。第6A~6F圖中與第2A~2J圖相同的元件符號代表與 第2A~2J圖相同或相似的元件，於此便不再贅述。 FIG. 5 shows a flow chart of a method 50 of forming a semiconductor device structure in accordance with further embodiments. 6A through 6F are cross-sectional views showing the structure of the semiconductor device formed using the method 50 shown in Fig. 5 at various stages, in accordance with some embodiments. The symbolic symbols in Figure 6A~6F are the same as those in Figures 2A~2J. The same or similar elements of Figures 2A to 2J are not described herein.
請參照第5圖，半導體裝置結構的形成方法50接續半導體裝置結構的形成方法10之步驟20(第2E圖)但未進行圓化溝槽頂角之步驟，即，形成溝槽102於基板100中(步驟12)；形成內襯溝槽102之閘極介電層106(步驟16)；以閘極材料108填充溝槽102(步驟18)；回蝕刻閘極材料108以暴露溝槽之上部102A(步驟20)。於此，形成之半導體裝置結構如第6A圖所示，經回蝕刻的閘極材料108暴露溝槽之上部102A。 Referring to FIG. 5, the method 50 for forming a semiconductor device structure follows the step 20 of the method 10 for forming a semiconductor device structure (FIG. 2E) but does not perform the step of rounding the apex angle of the trench, that is, forming the trench 102 on the substrate 100. Medium (step 12); forming a gate dielectric layer 106 of the liner trench 102 (step 16); filling the trench 102 with the gate material 108 (step 18); etching back the gate material 108 to expose the upper portion of the trench 102A (step 20). Here, the formed semiconductor device structure is as shown in FIG. 6A, and the etched gate material 108 exposes the upper portion 102A of the trench.
接著，請參照第5及6B圖，於步驟51中，藉由高密度電漿(HDP)沉積製程形成介電層614於溝槽之上部102A以及溝槽102之間的基底表面600A之上。介電層614並未完全地填滿溝槽之上部102A。在一些實施例中，形成於基底表面600A之上的介電層614具有傾斜的邊緣，其並未與溝槽102之側壁對齊。 Next, referring to FIGS. 5 and 6B, in step 51, a dielectric layer 614 is formed over the trench top portion 102A and the trench surface 102 between the trenches 102 by a high density plasma (HDP) deposition process. Dielectric layer 614 does not completely fill trench upper portion 102A. In some embodiments, the dielectric layer 614 formed over the substrate surface 600A has a sloped edge that is not aligned with the sidewalls of the trench 102.
再者，介電層614亦部份地形成於溝槽之上部102A之側壁102B上。由於高密度電漿(HDP)沉積製程具有主要係沉積於溝槽的底部及頂部之特性，因此形成於溝槽之側壁102B上的介電層614之厚度遠小於形成於溝槽之上部102A以及基底表面600A之上的介電層614之厚度。 Moreover, the dielectric layer 614 is also partially formed on the sidewall 102B of the upper portion 102A of the trench. Since the high density plasma (HDP) deposition process has characteristics mainly deposited on the bottom and top of the trench, the thickness of the dielectric layer 614 formed on the sidewall 102B of the trench is much smaller than that formed on the upper portion 102A of the trench and The thickness of the dielectric layer 614 over the substrate surface 600A.
接著，請參照第5及6C圖，於步驟53中，以回蝕刻部分地移除介電層614，以暴露溝槽之頂角102C。如第6C圖所示，形成於溝槽之上部102A之側壁102B上的介電層614完全地被移除，然而一部分的介電層614’仍存留於溝槽之上部102A及基底表面600A之上。在一些實施例中，可藉由乾蝕刻、濕蝕刻、 其它合適的蝕刻製程或前述之組合移除介電層614。乾蝕刻例如可為反應離子蝕刻(RIE)或電漿蝕刻等。 Next, referring to FIGS. 5 and 6C, in step 53, the dielectric layer 614 is partially removed by etch back to expose the top corner 102C of the trench. As shown in FIG. 6C, the dielectric layer 614 formed on the sidewall 102B of the upper portion 102A of the trench is completely removed, but a portion of the dielectric layer 614' remains on the trench upper portion 102A and the substrate surface 600A. on. In some embodiments, dry etching, wet etching, The dielectric layer 614 is removed by other suitable etching processes or combinations of the foregoing. The dry etching may be, for example, reactive ion etching (RIE) or plasma etching.
接著，請參照第5及6D圖，於步驟55中，利用剩餘的介電層614’作為蝕刻遮罩(etching mask)，等向性地蝕刻(isotropically etch)溝槽102以擴大溝槽之上部102A。如第6D圖所示，等向性蝕刻製程610移除溝槽之頂角102C及鄰近溝槽之上部102A的部分閘極介電層106及基底100。經擴大的溝槽之上部102A的寬度大於溝槽102之原始寬度，換言之，擴大的溝槽之上部102A使得溝槽102的頂部寬度大於底部寬度。 Next, referring to FIGS. 5 and 6D, in step 55, the remaining dielectric layer 614' is used as an etching mask, and the trench 102 is isotropically etched to enlarge the upper portion of the trench. 102A. As shown in FIG. 6D, the isotropic etch process 610 removes the top corner 102C of the trench and a portion of the gate dielectric layer 106 and substrate 100 adjacent the upper portion 102A of the trench. The expanded trench upper portion 102A has a width greater than the original width of the trench 102, in other words, the enlarged trench upper portion 102A is such that the top width of the trench 102 is greater than the bottom width.
此外，在一些實施例中，可選擇性(optionally)進行化學機械研磨製程，以部分地移除剩餘的介電層614’，直到暴露溝槽102之間的基底表面600A，而溝槽之上部102A中的介電層614'則仍然保留、未被移除，如第6E圖所示。 Moreover, in some embodiments, a chemical mechanical polishing process can be selectively performed to partially remove the remaining dielectric layer 614' until the substrate surface 600A between the trenches 102 is exposed, while the upper portion of the trenches The dielectric layer 614' in 102A remains and is not removed, as shown in Figure 6E.
接著，可接續半導體裝置結構的形成方法10之步驟22~28以完成方法50，即，形成主體區110以及源極區112於溝槽之間的基底中(步驟22)；形成介電層114以再填充溝槽之上部102A且覆蓋溝槽之間的基底(步驟24)；實行化學機械研磨製程116以部分地移除介電層114，直到暴露溝槽之間的基底表面(步驟26)；利用於溝槽之上部102A的介電層114’作為蝕刻遮罩，蝕刻基底100以形成接觸開口118於溝槽102之間(步驟28)。利用方法50所形成之半導體裝置結構如第6F圖所示，具有由形成於溝槽之上部102A的介電層114’所定義之自對準接觸開口118。 Next, steps 22-28 of the method 10 of forming the semiconductor device structure can be continued to complete the method 50, that is, forming the body region 110 and the source region 112 in the substrate between the trenches (step 22); forming the dielectric layer 114 Refilling the upper portion 102A of the trench and covering the substrate between the trenches (step 24); performing a chemical mechanical polishing process 116 to partially remove the dielectric layer 114 until the surface of the substrate between the trenches is exposed (step 26) The dielectric layer 114' is utilized as an etch mask for the upper portion 102A of the trench to etch the substrate 100 to form a contact opening 118 between the trenches 102 (step 28). The semiconductor device structure formed by method 50, as shown in Fig. 6F, has a self-aligned contact opening 118 defined by a dielectric layer 114' formed over the upper portion 102A of the trench.
第7圖顯示根據另一些實施例，半導體裝置結構的 形成方法70之流程圖。第8A圖至第8F圖顯示根據一些實施例，使用第7圖所示之方法70所形成之半導體裝置結構在不同階段之剖面圖。第8A~8F圖中與第2A~2J圖相同的元件符號代表與第2A~2J圖相同或相似的元件，於此便不再贅述。 Figure 7 shows the structure of a semiconductor device according to further embodiments. A flow chart of method 70 is formed. 8A through 8F are cross-sectional views showing the structure of the semiconductor device formed using the method 70 shown in Fig. 7, at various stages, in accordance with some embodiments. The same component symbols as in FIGS. 2A to 2J in FIGS. 8A to 8F represent the same or similar components as those in FIGS. 2A to 2J, and will not be described again.
請參照第7及8A圖，半導體裝置結構的形成方法70起始於步驟71，提供具有墊層(pad layer)812形成於其上之基底100。墊層812可具有單層或多層結構，墊層812可由氧化物、氮化物、其它合適的材料或前述之組合所形成，例如，氧化矽、氮化矽、氮氧化矽等。如第8A圖所示，在一些實施例中，墊層812具有墊氧化層812a及形成於墊氧化層812a之上的墊氮化層812b。在另一些實施例中，墊層812僅具有墊氧化層812a之單層結構。 Referring to FIGS. 7 and 8A, the method 70 for forming a semiconductor device structure begins at step 71 by providing a substrate 100 having a pad layer 812 formed thereon. The bedding layer 812 can have a single layer or a multi-layer structure, and the pad layer 812 can be formed of an oxide, a nitride, other suitable materials, or a combination of the foregoing, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, and the like. As shown in FIG. 8A, in some embodiments, the pad layer 812 has a pad oxide layer 812a and a pad nitride layer 812b formed over the pad oxide layer 812a. In other embodiments, the pad layer 812 has only a single layer structure of the pad oxide layer 812a.
在一些實施例中，可藉由化學氣相沉積(CVD)製程、熱氧化製程、其它合適的製程或前述之組合形成墊層812。化學氣相沉積製程例如可為低壓化學氣相沉積(LPCVD)製程或電漿增強化學氣相沉積(PECVD)製程等。 In some embodiments, the underlayer 812 can be formed by a chemical vapor deposition (CVD) process, a thermal oxidation process, other suitable processes, or a combination of the foregoing. The chemical vapor deposition process may be, for example, a low pressure chemical vapor deposition (LPCVD) process or a plasma enhanced chemical vapor deposition (PECVD) process.
接著，請參照第7及8B圖，於步驟73中，形成溝槽102於基板100中。如第8B圖所示，溝槽102貫穿墊氧化層812a以及墊氮化層812b，並延伸於基板100之中。可利用一或多個微影及蝕刻製程形成溝槽102。 Next, referring to FIGS. 7 and 8B, in step 73, the trench 102 is formed in the substrate 100. As shown in FIG. 8B, the trench 102 penetrates the pad oxide layer 812a and the pad nitride layer 812b and extends into the substrate 100. The trenches 102 can be formed using one or more lithography and etching processes.
接著，請參照第7及8C圖，於步驟75中，進行一後拉(pull-back)蝕刻製程802以部分地移除鄰接溝槽102之墊層812，以暴露溝槽之頂角102C，使得溝槽102延伸至墊層812中。在一些實施例中，後拉蝕刻製程802僅移除鄰接溝槽102之部分 的墊氧化層812a，而未移除墊氮化層812b，墊層812因而具有一內縮部(indented portion)。再者，後拉蝕刻製程802可包含濕蝕刻、其它合適的蝕刻製程或前述之組合。 Next, referring to FIGS. 7 and 8C, in step 75, a pull-back etching process 802 is performed to partially remove the pad layer 812 of the adjacent trench 102 to expose the top corner 102C of the trench. The trench 102 is caused to extend into the pad layer 812. In some embodiments, the post-etch etch process 802 removes only portions of the adjacent trenches 102. The pad oxide layer 812a does not remove the pad nitride layer 812b, and the pad layer 812 thus has an indented portion. Moreover, the post-etch etch process 802 can include wet etching, other suitable etching processes, or a combination of the foregoing.
接著，請參照第7及8D圖，於步驟77中，等向性地蝕刻(isotropically etch)溝槽之頂角102C以擴大溝槽之上部102A。如第8D圖所示，以墊層812作為蝕刻遮罩，等向性蝕刻製程810移除溝槽之頂角102C及鄰近溝槽之上部102A的部分基底100。經擴大的溝槽之上部102A的寬度大於溝槽102之原始寬度，換言之，擴大的溝槽之上部102A始得溝槽102整體的頂部寬度大於底部寬度。再者，在一些實施例中，墊層812的氧化層812a之內縮部的邊緣與經擴大之溝槽之上部102A的外部邊界(outer boundary)對齊。 Next, referring to FIGS. 7 and 8D, in step 77, the apex angle 102C of the trench is isotropically etched to enlarge the upper portion 102A of the trench. As shown in FIG. 8D, with the pad layer 812 as an etch mask, the isotropic etch process 810 removes the top corners 102C of the trench and portions of the substrate 100 adjacent the upper portion 102A of the trench. The expanded trench upper portion 102A has a width greater than the original width of the trench 102, in other words, the enlarged trench upper portion 102A begins with the trench top 102 as a whole having a top width greater than the bottom width. Moreover, in some embodiments, the edge of the constricted portion of the oxide layer 812a of the pad layer 812 is aligned with the outer boundary of the enlarged trench upper portion 102A.
接著，請參照第7及8E圖，於步驟79中，移除墊層812，暴露擴大的溝槽之上部102A。可藉由化學機械研磨製程、研磨製程、蝕刻製程、其它合適的製程或前述之組合移除墊層812。之後，可接續半導體裝置結構的形成方法10之步驟16~28以完成方法70，即，形成內襯溝槽102之閘極介電層106(步驟16)；以閘極材料108填充溝槽102(步驟18)；回蝕刻閘極材料108以暴露溝槽之上部102A(步驟20)；形成主體區110以及源極區112於溝槽之間的基底中(步驟22)；形成介電層114以再填充溝槽之上部102A且覆蓋溝槽之間的基底(步驟24)；實行化學機械研磨製程116以部分地移除介電層114，直到暴露溝槽之間的基底表面(步驟26)；利用於溝槽之上部102A的介電層114’作為蝕刻遮罩，蝕刻基底100以形成接觸開口118於溝槽102之間(步驟 28)。利用方法70所形成之半導體裝置結構如第8F圖所示，具有由形成於溝槽之上部102A的介電層114’所定義之自對準接觸開口118。 Next, referring to FIGS. 7 and 8E, in step 79, the underlayer 812 is removed to expose the enlarged trench upper portion 102A. The underlayer 812 can be removed by a chemical mechanical polishing process, a polishing process, an etching process, other suitable processes, or a combination of the foregoing. Thereafter, steps 16-28 of the method 10 of forming the semiconductor device structure can be continued to complete the method 70, ie, forming the gate dielectric layer 106 of the liner trench 102 (step 16); filling the trench 102 with the gate material 108. (Step 18); etching back the gate material 108 to expose the trench upper portion 102A (step 20); forming the body region 110 and the source region 112 in the substrate between the trenches (step 22); forming the dielectric layer 114 Refilling the upper portion 102A of the trench and covering the substrate between the trenches (step 24); performing a chemical mechanical polishing process 116 to partially remove the dielectric layer 114 until the surface of the substrate between the trenches is exposed (step 26) Using the dielectric layer 114' on the upper portion 102A of the trench as an etch mask, etching the substrate 100 to form a contact opening 118 between the trenches 102 (steps) 28). The semiconductor device structure formed by method 70, as shown in Fig. 8F, has a self-aligned contact opening 118 defined by a dielectric layer 114' formed over the upper portion 102A of the trench.
綜上所述，本發明實施例之半導體裝置結構的形成方法係利用高選擇性之化學機械研磨製使介電層暴露一特定之基底表面，例如位於基底之高台(mesa)區的表面，並利用高選擇性之蝕刻製程藉由此特定之基底表面，形成自對準接觸(self-aligned contact)開口於基底中。 In summary, the method for forming a semiconductor device structure according to an embodiment of the present invention utilizes highly selective chemical mechanical polishing to expose a dielectric layer to a specific substrate surface, such as a surface of a mesa region of the substrate, and A self-aligned contact opening is formed in the substrate by a highly selective etching process by means of the particular substrate surface.
本發明實施例之半導體裝置結構的形成方法可克服習知利用微影曝光機台形成接觸開口可能造成之對準失誤(misalignment)。此外，亦可縮小接觸結構之關鍵尺寸及有效地降低裝置之導通電阻(on resistance)。 The method for forming a semiconductor device structure according to an embodiment of the present invention can overcome the misalignment that may be caused by forming a contact opening by using a lithography exposure machine. In addition, the critical dimensions of the contact structure can be reduced and the on resistance of the device can be effectively reduced.
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.
100‧‧‧基底 100‧‧‧Base
106‧‧‧閘極介電層 106‧‧‧gate dielectric layer
108‧‧‧閘極材料 108‧‧‧gate material
110‧‧‧主體區 110‧‧‧ Main area
112‧‧‧源極區 112‧‧‧ source area
114’‧‧‧介電層 114’‧‧‧Dielectric layer
118‧‧‧接觸開口 118‧‧‧Contact opening
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| TW200739695A (en) * | 2006-02-10 | 2007-10-16 | Fairchild Semiconductor | Low resistance gate for power MOSFET applications and method of manufacture |
| TW200845229A (en) * | 2007-02-15 | 2008-11-16 | Fairchild Semiconductor | Integrated hydrogen anneal and gate oxidation for improved gate oxide integrity |
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| TW201507153A (en) * | 2012-07-13 | 2015-02-16 | Ubiq Semiconductor Corp | Trench gate MOSFET |
| CN104769723A (en) * | 2014-12-04 | 2015-07-08 | 冯淑华 | Groove power semiconductor MOSFET |
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| TW200739695A (en) * | 2006-02-10 | 2007-10-16 | Fairchild Semiconductor | Low resistance gate for power MOSFET applications and method of manufacture |
| TW200845229A (en) * | 2007-02-15 | 2008-11-16 | Fairchild Semiconductor | Integrated hydrogen anneal and gate oxidation for improved gate oxide integrity |
| US20100308400A1 (en) * | 2008-06-20 | 2010-12-09 | Maxpower Semiconductor Inc. | Semiconductor Power Switches Having Trench Gates |
| TW201507153A (en) * | 2012-07-13 | 2015-02-16 | Ubiq Semiconductor Corp | Trench gate MOSFET |
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