TWI587302B - Memory programming methods and memory devices - Google Patents
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本發明係有關於數位記憶體裝置，特別係有關於編輯能夠執行錯誤更正碼(ECC)之非及閘快閃式記憶體。 The present invention relates to digital memory devices, and more particularly to editing and non-gate flash memory capable of performing error correction codes (ECC).
因為非及閘快閃式記憶體顯著的成本優勢，已經使其變得越來越流行。再者，非及閘快閃式記憶體目前可於許多不同的介面取得，從傳統的非及閘介面至低針腳數之序列周邊介面。然而，非及閘快閃式記憶體易受損毀區塊的影響而偶而讀取錯誤，使得損毀區塊管理以及錯誤更正碼的處理通常皆是使用於這種類型的記憶體。 Because of the significant cost advantages of non-gate flash memory, it has become more and more popular. Furthermore, non-gate flash memory is currently available in many different interfaces, from traditional non-gate interfaces to sequential peripheral interfaces with low pin counts. However, the error of the non-gate flash memory is easily damaged and the error is read, so that the management of the damaged block and the processing of the error correction code are generally used for this type of memory.
在編輯操作中之錯誤更正碼以及損毀區塊管理的一種實現，係描述於由台灣新竹華邦電子於2013年11月26日所公開之W25N01GV之初步版本B，其為具有雙/四序列周邊匯流排以及連續讀取之3V 1G位元串列SLC非及閘快閃式記憶體。該編輯操作允許一字節至2112字節(即一頁面)之資料於先前抹除(FFh)之記憶體位址上編輯。由寫入致能指令開始之一編輯操作包括兩個步驟：(1)載入編輯檔案至資料緩衝器；以及(2)從資料緩衝器傳送資料至特定記憶體頁面。 An error correction code in the editing operation and an implementation of the damaged block management are described in the preliminary version B of W25N01GV published by Hsinchu Huabang Electronics of Taiwan on November 26, 2013, which has a dual/four sequence periphery. The bus and the continuously read 3V 1G bit are serially connected to the SLC non-gate flash memory. This editing operation allows data from one byte to 2112 bytes (i.e., one page) to be edited on the memory address of the previous erase (FFh). One of the editing operations initiated by the write enable command includes two steps: (1) loading the edit file into the data buffer; and (2) transferring the data from the data buffer to the particular memory page.
載入編輯資料至資料緩衝器之指令的一範例，係為由驅動/CS針腳至低邏輯位準而開始之載入編輯資料指令， 隨後在16位元欄位址以及8位元虛擬時脈之後的指令碼「02h」中移動，並且至少一字節之資料。 An example of an instruction to load an edit data to a data buffer is to load an edit data instruction starting from a drive /CS pin to a low logic level. Then move in the 16-bit field address and the instruction code "02h" after the 8-bit virtual clock, and at least one byte of data.
將資料緩衝器之資料傳送至特定記憶體頁面之指令之一範例，係為由驅動/CS針腳至低邏輯位準而開始之編輯執行指令，隨後在8位元虛擬時脈以及16位元頁面位址之後的指令碼「10h」中移動。驅動/CS針腳至高邏輯位準而完成指令週期之後，自定時編碼執行指令開始計時時間區間tPP，時間區間tPP係為時間密集任務之所需，時間密集任務如頁面編程、一次性編程鎖定以及故障區塊管理。時間區間tPP通常約為250微秒，但最長可為700微秒。當編程執行週期進行時，讀取狀態暫存器指令可作為確認忙碌位元之狀態，忙碌位元在編程執行週期時係為邏輯1，而在編程執行週期完成且裝置準備好接收指令時時，忙碌位元變為邏輯0。當編程執行週期完成時，在狀態暫存器中之寫入致能閂鎖位元被清除為邏輯0。 An example of an instruction to transfer data from a data buffer to a particular memory page is an edit execution instruction that begins with a drive/CS pin to a low logic level, followed by an 8-bit virtual clock and a 16-bit page. Move in the command code "10h" after the address. After the drive/CS pin reaches the high logic level and completes the instruction cycle, the self-timed code execution instruction starts the time interval tPP, which is required for time-intensive tasks, such as page programming, one-time program locking, and failure. Block management. The time interval tPP is typically about 250 microseconds, but can be as long as 700 microseconds. When the program execution cycle is in progress, the read status register instruction can be used to confirm the status of the busy bit, the busy bit is set to logic 1 during the program execution cycle, and when the program execution cycle is completed and the device is ready to receive the instruction. The busy bit becomes logic 0. When the program execution cycle is completed, the write enable latch bit in the status register is cleared to logic 0.
若內部錯誤更正碼被啟動，該頁面之資料的所有字元組以及額外的64字元組段落(備用區域)被接受，但指定為在額外的64字元組段落中之錯誤更正碼的字元組將由錯誤更正碼計算所覆寫。 If the internal error correction code is activated, all the character groups of the page's material and the extra 64-character paragraph (alternate area) are accepted, but the word is specified as an error correction code in the extra 64-character paragraph. The tuple will be overwritten by the error correction code calculation.
若另一頁面要被編程時，另一編程操作會經由在另一讀取編程資料指令以及另一編程執行指令之後而發出另一寫入致能指令而執行。 If another page is to be programmed, another programming operation is performed by issuing another write enable command after another read program data instruction and another program execution instruction.
根據本發明之一實施例，本發明提出一種記憶體編程方法，適用於利用一記憶體裝置之一資料暫存器以及一快 取暫存器作為一非及閘快閃式記憶體陣列之一頁面緩衝器，而將來自於一資料匯流排之一編程資料之頁面編程至上述記憶體裝置之上述非及閘快閃式記憶體陣列，包括：將來自上述資料匯流排之上述編程資料之一第一頁面儲存於上述快取暫存器；對儲存於上述快取暫存器之上述編程資料之上述第一頁面執行一錯誤更正碼操作，而建立經上述錯誤更正碼操作處理之上述第一頁面於上述快取暫存器；從上述快取暫存器將經上述錯誤更正碼操作處理之上述第一頁面儲存於上述資料暫存器；將經上述錯誤更正碼操作處理之上述第一頁面自上述資料暫存器編程至上述非及閘快閃式記憶體陣列；在與編程上述第一頁面步驟相重疊之時間中，自上述資料匯流排將上述編程資料之一第二資料頁面儲存於上述快取暫存器；以及在與編程上述第一頁面步驟相重疊之時間中，對儲存於上述快取暫存器之上述編程資料之上述第二頁面進行上述錯誤更正碼操作，而建立經上述錯誤更正碼操作處理之上述第二頁面於上述快取暫存器。 According to an embodiment of the present invention, the present invention provides a memory programming method suitable for utilizing a data buffer of a memory device and a fast The scratchpad is used as a page buffer of a non-gate flash memory array, and a page from a programming data of a data bus is programmed to the non-gate flash memory of the memory device. The body array includes: storing a first page of the programming data from the data bus in the cache register; performing an error on the first page of the programming data stored in the cache register Correcting the code operation, and establishing the first page processed by the error correction code operation in the cache register; and storing, by the cache register, the first page processed by the error correction code operation on the data a temporary register; the first page processed by the error correction code operation is programmed from the data register to the non-gate flash memory array; in a time overlapping with the step of programming the first page, And storing, in the data bus, a second data page of the programming data in the cache register; and overlapping with the step of programming the first page , The second page of said program information is stored in the register cache the above ECC the above operation, by establishing the above-described error correction code and the second page of the above-described operation process in the cache register.
根據本發明之另一實施例，本發明提出一種記憶體裝置，包括：一非及閘快閃式記憶體陣列、一列解碼器、一資料暫存器、一快取暫存器、一錯誤更正碼電路、一欄解碼器以及一控制電路。上述列解碼器耦接至上述非及閘快閃式記憶體陣列。上述資料暫存器耦接至上述非及閘快閃式記憶體陣列。上述快取暫存器耦接至上述資料暫存器。上述錯誤更正碼電路耦接至上述快取暫存器。上述欄解碼器耦接至上述快取暫存器。上述控制電路耦接至上述列解碼器、上述欄解碼器、上 述資料暫存器、上述快取暫存器以及上述錯誤更正碼電路，其中上述控制電路包括用以執行以下功能之複數邏輯以及暫存器元件：將一編程資料之一第一頁面儲存於上述快取暫存器；利用上述錯誤更正碼電路對儲存於上述快取暫存器之上述編程資料之上述第一頁面執行一錯誤更正碼操作，以建立上述快取暫存器中之經過上述錯誤更正碼操作之上述第一頁面；在與編程上述非及閘快閃式記憶體陣列相重疊之時間中，將上述編程資料之一第二頁面儲存於上述快取暫存器；以及在與編程上述非及閘快閃式記憶體陣列相重疊之時間中，對儲存於上述快取暫存器之上述編程資料之上述第二頁面執行上述錯誤更正碼操作，以建立經上述錯誤更正碼操作之上述第二頁面於上述快取暫存器。 According to another embodiment of the present invention, the present invention provides a memory device including: a non-gate flash memory array, a column decoder, a data register, a cache register, and an error correction. A code circuit, a column decoder and a control circuit. The column decoder is coupled to the non-gate flash memory array. The data register is coupled to the non-gate flash memory array. The cache register is coupled to the data register. The error correction code circuit is coupled to the cache register. The above column decoder is coupled to the cache register. The control circuit is coupled to the column decoder, the column decoder, and the foregoing The data register, the cache register, and the error correction code circuit, wherein the control circuit includes a plurality of logic and a register element for performing the following functions: storing a first page of a programming data in the above Cache the scratchpad; using the error correction code circuit to perform an error correction code operation on the first page of the programming data stored in the cache register to establish the error in the cache register Correcting the first page of the code operation; storing a second page of the programming data in the cache register in a time overlapping with programming the non-gate flash memory array; and programming in During the time when the non-gate flash memory array overlaps, the error correction code operation is performed on the second page of the programming data stored in the cache register to establish the error correction code operation. The second page is in the cache register.
100‧‧‧非及閘快閃式記憶體裝置 100‧‧‧ Non-gate flash memory device
110‧‧‧資料匯流排 110‧‧‧ data bus
120‧‧‧錯誤更正碼電路 120‧‧‧Error correction code circuit
130‧‧‧頁面緩衝器 130‧‧‧Page Buffer
132‧‧‧快取暫存器 132‧‧‧ cache register
134‧‧‧資料暫存器 134‧‧‧data register
140‧‧‧非及閘快閃式記憶體陣列 140‧‧‧ Non-gate flash memory array
142‧‧‧第一頁面 142‧‧‧ first page
144‧‧‧第二頁面 144‧‧‧ second page
150‧‧‧第一箭頭 150‧‧‧First arrow
152‧‧‧第二箭頭 152‧‧‧second arrow
154‧‧‧第三箭頭 154‧‧‧third arrow
156‧‧‧第四箭頭 156‧‧‧fourth arrow
158‧‧‧第五箭頭 158‧‧‧ fifth arrow
510‧‧‧快取暫存器 510‧‧‧ cache register
520‧‧‧資料暫存器 520‧‧‧data register
530‧‧‧非及閘快閃式記憶體陣列 530‧‧‧ Non-gate flash memory array
540‧‧‧快取忙碌位元 540‧‧‧Quick busy bits
561‧‧‧第一載入編程資料指令 561‧‧‧First Load Programming Data Instructions
562‧‧‧第一快取編程執行指令 562‧‧‧First cache programming execution instruction
563‧‧‧第二載入編程資料指令 563‧‧‧Second load programming data instruction
564‧‧‧第二快取編程執行指令 564‧‧‧Second cache programming execution instruction
600‧‧‧非及閘快閃式記憶體 600‧‧‧ Non-gate flash memory
622‧‧‧輸入/輸出控制 622‧‧‧Input/Output Control
623‧‧‧狀態暫存器 623‧‧‧Status Register
624‧‧‧連續頁面讀取位址暫存器 624‧‧‧Continuous page read address register
625‧‧‧命令暫存器 625‧‧‧Command Register
626‧‧‧位址暫存器 626‧‧‧ address register
627‧‧‧查找表暫存器 627‧‧‧ lookup table register
630‧‧‧控制邏輯 630‧‧‧Control logic
631‧‧‧連續頁面讀取故障區塊邏輯 631‧‧‧Continuous page read fault block logic
632‧‧‧連續頁面讀取故障區塊暫存器 632‧‧‧Continuous page read fault block register
633‧‧‧高電壓產生器 633‧‧‧High voltage generator
634‧‧‧列解碼器 634‧‧‧ column decoder
635‧‧‧通電偵測器 635‧‧‧Power Detector
636‧‧‧欄解碼器 636‧‧‧ column decoder
638‧‧‧頁面緩衝器 638‧‧‧Page Buffer
640‧‧‧非及閘快閃式記憶體陣列 640‧‧‧ Non-gate flash memory array
642‧‧‧使用者可定址區域 642‧‧‧User addressable area
644‧‧‧冗餘區塊區域 644‧‧‧Redundant block area
646‧‧‧查找表資訊區塊 646‧‧‧Search Table Information Block
647‧‧‧緩衝器模式旗標 647‧‧‧Buffer mode flag
648‧‧‧ECC-E旗標 648‧‧‧ECC-E flag
650‧‧‧第一錯誤更正碼狀態位元 650‧‧‧First error correction code status bit
651‧‧‧第二錯誤更正碼狀態位元 651‧‧‧ second error correction code status bit
652‧‧‧忙碌位元 652‧‧‧ busy bits
653‧‧‧快取忙碌位元 653‧‧‧ Cache busy bits
654‧‧‧串列位元 654‧‧‧ tandem bits
CLK‧‧‧時脈信號 CLK‧‧‧ clock signal
/CS‧‧‧反相之晶片選擇信號 /CS‧‧‧Inverted wafer selection signal
DI‧‧‧串列資料輸入信號 DI‧‧‧ serial data input signal
DO‧‧‧串列資料輸出信號 DO‧‧‧Sliced data output signal
/WP‧‧‧反相之寫入保護信號 /WP‧‧‧Inverted write protection signal
/HOLD‧‧‧反相之維持信號 /HOLD‧‧‧Reverse sustain signal
VCC‧‧‧電源線 VCC‧‧‧ power cord
GND‧‧‧接地端 GND‧‧‧ ground terminal
200~274‧‧‧步驟流程 200~274‧‧‧Step process
301-305、307-310、401-405、407-410‧‧‧時間序列 301-305, 307-310, 401-405, 407-410‧‧‧ time series
306、312、406、412‧‧‧頁面編程 306, 312, 406, 412‧‧‧ page programming
第1圖係顯示根據本發明之一實例所述之非及閘快閃式記憶體裝置之方塊圖；第2A、2B圖係顯示根據本發明之一實施例所述之編程操作之流程圖；第3圖係顯示根據本發明之一實施例所述之利用快取編程執行技術之編程操作之時序圖；第4圖係顯示根據本發明之一實施例所述之利用編程執行技術之編程操作之時序圖；第5圖係顯示根據本發明之一實施例所述之利用非及閘記憶體裝置之特定資源在編程操作時使用快取編程執行技 術之示意圖；第6圖係顯示根據本發明之一實施例所述之串列非及閘快閃式記憶體之功能性方塊圖。 1 is a block diagram showing a non-gate flash memory device according to an example of the present invention; and FIGS. 2A and 2B are flowcharts showing a programming operation according to an embodiment of the present invention; 3 is a timing diagram showing a programming operation using a cache program execution technique according to an embodiment of the present invention; and FIG. 4 is a diagram showing a program operation using a program execution technique according to an embodiment of the present invention. a timing diagram; FIG. 5 is a diagram showing the use of a cache programming execution technique during a program operation using a specific resource of a non-NAND memory device according to an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6 is a functional block diagram showing a tandem NAND flash memory according to an embodiment of the present invention.
快速讀取以及編程的效能係為非閘極快閃式記憶體裝置所令人滿意的地方。快速編程效能可利用快取編程執行技術而達成，快取編程執行技術係如第1圖所示之用以解釋目的之簡化型式。非及閘快閃式記憶體裝置100包括非及閘快閃式記憶體陣列140、頁面緩衝器130以及錯誤更正碼電路120。故障區塊管理電路也可包含於第1圖，但為了清楚說明本發明之目的而予以省略。非及閘快閃式記憶體陣列140具有用於數位儲存之許多頁面(如第1圖所示之第一頁面142以及第二頁面144)，也面緩衝器130具有兩個非常快的暫存器，分別為快取暫存器132以及資料暫存器134。為了達到快速編程的目的，在資料匯流排110之初始資料可被載入致快取暫存器132(第一箭頭150)。此後，來自快取暫存器132之資料可因錯誤更正電路120所實現之特殊錯誤更正碼演算法所要求，而被複製至錯誤更正碼電路120(第二箭頭152)，以便計算錯誤更正碼。錯誤更正碼被寫入至快取暫存器(第三箭頭154)，特別是寫入至儲存於快取暫存器132之資料頁面的備用區域。此後，快取暫存器132中被錯誤更正碼處理過的資料可被複製至資料暫存器(第四箭頭156)。非及閘快閃式記憶體陣列140(以第一頁面142作為說明)可以資料暫存器134中經錯誤更正碼處理之資料而編程，並使用任何合適的查找表技術用以故障區塊管理。 Fast read and programmed performance is a good place for non-gate flash memory devices. Fast programming performance can be achieved using the cache programming execution technique, which is a simplified version for explanatory purposes as shown in Figure 1. The NAND flash memory device 100 includes a NAND flash memory array 140, a page buffer 130, and an error correction code circuit 120. The fault block management circuit may also be included in Fig. 1, but will be omitted for the purpose of clearly illustrating the present invention. The non-gate flash memory array 140 has a number of pages for digital storage (such as the first page 142 and the second page 144 shown in FIG. 1), and the buffer 130 has two very fast temporary stores. The cacher is respectively a cache register 132 and a data register 134. For fast programming purposes, the initial data in the data bus 110 can be loaded into the cache register 132 (first arrow 150). Thereafter, the data from cache register 132 may be copied to error correction code circuit 120 (second arrow 152) as required by the special error correction code algorithm implemented by error correction circuit 120 to calculate the error correction code. . The error correction code is written to the cache register (third arrow 154), particularly to the spare area of the data page stored in the cache register 132. Thereafter, the data processed by the error correction code in the cache register 132 can be copied to the data register (fourth arrow 156). The non-gate flash memory array 140 (described on the first page 142) can be programmed in the data buffer 134 via error correction code processing and used any suitable lookup table technique for fault block management. .
有利的是，在快取暫存器132中錯誤更正碼處理過之資料複製至資料暫存器134(第四箭頭156)，快取暫存器132可用於其他操作。有利的是，當編程資料之第一頁面正被編程至非及閘快閃式記憶體陣列140時(第五箭頭158)，編程資料之第二頁面可被載入至非及閘快閃式記憶體裝置100以及錯誤更正碼處理(第一箭頭150、第二箭頭152以及第三箭頭154)。 Advantageously, the error corrected code processed data in the cache register 132 is copied to the data register 134 (fourth arrow 156), and the cache register 132 can be used for other operations. Advantageously, when the first page of programming data is being programmed to the non-gate flash memory array 140 (fifth arrow 158), the second page of programming data can be loaded into the non-gate flash The memory device 100 and error correction code processing (first arrow 150, second arrow 152, and third arrow 154).
第2A、2B圖係顯示根據本發明之一實例之執行第1圖所示之技巧之編程操作200之流程圖。接收且執行讀取致能指令(步驟202)，隨後接收並執行一載入編程資料指令(步驟204而放置編程資料至快取暫存器132(第1圖)。完全載入編程資料指令所需之總時間係為可變的，且根據許多不同的因素而改變，如使用之序列周邊介面協議(例如，單一、雙或四位元)以及操作頻率，但由在適當時候可發出快取編程執行指令之控制器將其列入考慮。由非及閘快閃式記憶體裝置100接收快取編程執行指令(步驟206)，快取編程執行指令執行許多內部操作且回應有限數目之指令。舉例來說，非及閘快閃式記憶體裝置100可設定裝置忙碌位元以及快取忙碌位元(步驟208)、執行錯誤更正碼處理(步驟210)、自快取暫存器132複製資料至資料暫存器134(步驟212)、重設快取忙碌位元(步驟214)以及自快取暫存器132初始編程非及閘快閃式記憶體陣列140之頁面(步驟216)。 2A, 2B are flowcharts showing a programming operation 200 for performing the technique shown in Fig. 1 in accordance with an example of the present invention. Receiving and executing the read enable instruction (step 202), then receiving and executing a load programming data instruction (step 204 and placing the programming data to the cache register 132 (FIG. 1). Fully loading the programming data instruction The total time required is variable and varies according to many different factors, such as the sequence peripheral interface protocol used (eg, single, dual or quad, and operating frequency, but can be issued by caching at the appropriate time) The controller that programs the execution instructions takes this into account. The cache program execution instructions are received by the non-gate flash memory device 100 (step 206), which performs a number of internal operations and responds to a limited number of instructions. For example, the non-gate flash memory device 100 can set the device busy bit and the cache busy bit (step 208), perform error correction code processing (step 210), and copy data from the cache register 132. To the data register 134 (step 212), reset the cache busy bit (step 214), and initially program the page of the non-gate flash memory array 140 from the cache register 132 (step 216).
在快取忙碌位元設定之後(步驟208)，非及閘快閃式記憶體裝置100可回應讀取狀態暫存器指令(步驟220)，以便記憶體控制器(圖中未顯示)可偵測是否快取忙碌位元被清除(步驟214)。若快取忙碌位元被清除(重設)且有更多編程非及閘 快閃式記憶體陣列之需求(步驟222為是)，編程操作可與第2B圖所示之許多操作一同進行。若沒有進一步對非及閘快閃式記憶體陣列編程之需求(步驟272為否)，其他操作可在忙碌位元被清除後而執行(步驟224)。 After the cache busy bit setting (step 208), the non-gate flash memory device 100 can respond to the read status register instruction (step 220) so that the memory controller (not shown) can detect It is determined if the cache busy bit is cleared (step 214). If the cache busy bit is cleared (reset) and there are more programming gates The need for a flash memory array (YES in step 222), the programming operation can be performed in conjunction with many of the operations shown in FIG. 2B. If there is no further need for programming the non-gate flash memory array (NO in step 272), other operations may be performed after the busy bit is cleared (step 224).
當頁面編程正在進行中，非及閘快閃式記憶體裝置100可與頁面編程並列執行許多其他操作，改善編程操作之整體吞吐量。非及閘快閃式記憶體裝置100可被致能而於頁面編程至寫入致能指令、載入編程資料指令以及快取編程執行指令時，以下列方式回應，即使當裝置忙碌位元被設定時亦如此。 When page programming is in progress, the non-gate flash memory device 100 can perform many other operations in parallel with page programming to improve the overall throughput of the programming operation. The non-gate flash memory device 100 can be enabled to respond in the following manners when page programming to write enable instructions, load programming data instructions, and cache programming execution instructions, even when the device busy bit is The same is true when setting.
如第2B圖所示，確認連續位元(步驟226)以決定是否編程操作係用於特定的頁面或是用於連續編程操作。在前述的事件中(步驟226為否)，接收以及執行寫入致能指令(步驟230)、接收以及執行載入編程資料指令(步驟232)而放置編程資料至快取暫存器132(第1圖)以及由非及閘快閃式記憶體裝置100接收快取編程執行指令(步驟234)。在後來的事件中(步驟226為是)，接收或執行寫入致能指令(步驟240)、接收或執行載入編程資料指令(步驟242)而放置編程資料至快取暫存器132(第1圖)以及由非及閘快閃式記憶體裝置100接收第二快取編程執行指令(步驟244)。第二快取編程執行不需要指定頁面位址，因為在執行連續編程時，頁面位址係為內部決定。有利的是，非及閘快閃式記憶體裝置100可執行許多內部操作來回硬第二快取編程執行指令，儘管編程正在執行以回應第一快取編程執行指令。舉例來說，非及閘快閃式記憶體裝置100可設定裝置忙碌位元以及快取忙碌位元(步驟250)，且執行錯誤更正碼 程序(步驟252)。 As shown in FIG. 2B, successive bits are asserted (step 226) to determine if the programming operation is for a particular page or for a continuous programming operation. In the foregoing event (NO in step 226), receiving and executing the write enable command (step 230), receiving and executing the load programming data instruction (step 232), and placing the programming data to the cache register 132 (the first) 1) and receiving a cache programming execution instruction by the non-gate flash memory device 100 (step 234). In a later event (YES in step 226), receiving or executing a write enable command (step 240), receiving or executing a load programming data instruction (step 242), placing programming data into cache register 132 (step 1) and receiving a second cache programming execution instruction by the non-gate flash memory device 100 (step 244). The second cache program execution does not require a page address to be specified because the page address is internally determined when performing continuous programming. Advantageously, the NAND flash memory device 100 can perform a number of internal operations to the hard second cache programming execution instructions, although programming is being performed in response to the first cache programming execution instructions. For example, the non-gate flash memory device 100 can set the device busy bit and the cache busy bit (step 250), and execute the error correction code. Program (step 252).
不論是否非及閘快閃式記憶體陣列之頁面編程正在執行，非及閘快閃式記憶體裝置100可回應讀取狀態暫存器指令(步驟270)，以便記憶體控制器(圖中並未顯示)可偵測是否暫存器忙碌位元是否清除(重置)。當非及閘快閃式記憶體陣列之頁面編程完成時，那時許多其他內部操作可能繼續進行；舉例來說，自快取暫存器132複製資料至資料暫存器134(步驟254)，重設快取忙碌位元(步驟256)、自快取暫存器132初始編程非及閘快閃式記憶體陣列140之更多頁面(步驟258)以及若沒有接收到寫入致能指令，則重設寫入致能閂鎖位元以及裝置忙碌位元(步驟260)。若快取忙碌位元被清除且非及閘快閃式記憶體陣列有其他編程之需求時(步驟272為是)，與步驟226一同開始之許多操作會被重複。若沒有其他編程非及閘快閃式記憶體陣列之需求時(步驟272為否)，其他操作可在忙碌位元清除後而執行(步驟274)。 Regardless of whether or not the page programming of the gate flash memory array is being performed, the non-gate flash memory device 100 can respond to the read status register instruction (step 270) for the memory controller (in the figure Not shown) It can detect whether the scratchpad busy bit is cleared (reset). When the page programming of the non-gate flash memory array is completed, then many other internal operations may continue at that time; for example, the self-cache register 132 copies the data to the data register 134 (step 254), Resetting the cache busy bit (step 256), initializing the more pages of the non-gate flash memory array 140 from the cache register 132 (step 258) and if no write enable command is received, The write enable latch bit and the device busy bit are then reset (step 260). If the cache busy bit is cleared and the non-gate flash memory array has other programming requirements (YES in step 272), many of the operations initiated with step 226 are repeated. If there is no other need to program the non-gate flash memory array (NO in step 272), other operations may be performed after the busy bit is cleared (step 274).
使用快取編程執行技術之編程操作200之吞吐量相對於標準編程執行技術之優點，可利用比較代表前者之第3圖之時序圖以及代表後者之第4圖之時序圖而瞭解。時間序列301-305(第3圖)以及時間序列401-405(第4圖)並非為本質上相異。然而，對於標準編程執行技術，時間序列407-410係為等待頁面編程406之完成後才發生。相反的且有利的是，當頁面編程306發生時，快取編程執行技術之時間序列307-310也正在發生，因此這些操作所使用之時間隱藏於頁面編程306所使用之時間之下。多頁面編程事件之吞吐量之優點顯而易見，對於 快取編程執行技術，編程頁面312與編程頁面306之間隔僅為自快取暫存器132傳輸編程資料至資料暫存器134所需之時間(時間序列311)，其中對於標準編程執行技術，編程頁面412落後編程頁面406不僅僅只是自快取暫存器132傳輸編程資料至資料暫存器134所需之時間(時間序列411)，而是分別對應讀取致能指令、載入編程資料指令、編程執行指令以及錯誤更正碼計算之時間序列407-410。 The throughput of the programming operation 200 using the cache programming execution technique can be understood by comparing the timing diagram representing the former FIG. 3 with the timing diagram representing the fourth diagram of the latter, with respect to the advantages of the standard programming execution technique. Time series 301-305 (Fig. 3) and time series 401-405 (Fig. 4) are not essentially different. However, for standard programming execution techniques, time series 407-410 occur only after waiting for completion of page programming 406. Conversely and advantageously, when page programming 306 occurs, the time series 307-310 of the cache programming execution technique are also occurring, so the time used for these operations is hidden below the time used by page programming 306. The advantages of the throughput of multi-page programming events are obvious, for The cache programming execution technique, the interval between the programming page 312 and the programming page 306 is only the time required to transfer the programming data from the cache register 132 to the data register 134 (time series 311), wherein for standard programming execution techniques, The programming page 412 behind the programming page 406 is not only the time required for the transfer of the programming data from the cache register 132 to the data register 134 (time series 411), but corresponding to the read enable command and the load programming data, respectively. The time series 407-410 of instructions, programming execution instructions, and error correction code calculations.
效能增進的原因係為在大多編程操作時，本質上完權利用非及閘快閃式記憶體裝置100之資源所產生的。如第5圖所示，資料暫存器520以及非及閘快閃式記憶體陣列530並非一開始就被第一載入編程資料指令(LPD)561以及第一快取編程執行指令(CPE)562所採用。然而，在清除快取忙碌位元540且回應第二載入編程資料指令(RSR(CB)LPD)563以及第二快取編程執行指令(CPE)564之後，在使用資料暫存器520以及非及閘快閃式記憶體陣列530進行頁面編程(CPE-1(PR))的時候，在此同時，快取暫存器510被用以接收編程資料(LPD-2)，隨後用以錯誤更正碼處理(CPE-2(ECC))。本質上的完全利用持續至隨後的載入編程資料以及快取編程執行指令序列，不論是依序或是對指定的頁面。 The reason for the performance improvement is that in most programming operations, the rights are essentially generated by the resources of the non-gate flash memory device 100. As shown in FIG. 5, the data buffer 520 and the non-gate flash memory array 530 are not initially loaded by the first load programming data instruction (LPD) 561 and the first cache programming execution instruction (CPE). 562 adopted. However, after clearing the cache busy bit 540 and responding to the second load programming data instruction (RSR(CB)LPD) 563 and the second cache program execution instruction (CPE) 564, the data register 520 is used and When the gate flash memory array 530 performs page programming (CPE-1 (PR)), at the same time, the cache register 510 is used to receive the programming data (LPD-2), and then used for error correction. Code processing (CPE-2 (ECC)). Intrinsic full utilization continues until the subsequent load programming data and the cache programming execution instruction sequence, either sequentially or on the specified page.
快取編程執行技術可與許多其他技術合併使用，以實現具有快讀取以及包括快速連續讀取之快編程能力之非及閘快閃式記憶體裝置。第6圖係顯示根據本發明之一實例所述之能夠提供跨頁面邊界以及自邏輯連續記憶體位置之連續讀取而不需等待時間之串列非及閘快閃式記憶體600之功能方 塊圖。錯誤更正碼程序以及利用故障區塊查找表之故障區塊管理，可在記憶體裝置之晶片上實現，也就是在相同的晶粒上之額外的電路，或者是實現於記憶體裝置之命令以及控制邏輯中且與命令以及控制邏輯之其他功能緊緊地整合在一起，隨著使用快取編程執行技術之快速操作而致能快速且有效率的連續讀取操作。合適的非及閘快閃式記憶體架構係詳細地描述於，例如Gupta於2014年3月4日公開之美國專利編號8,667,368之標題為「Method and Apparatus for Reading NAND Flash Memory」、Michael於2013年12月26日公開之美國專利公開號2013/0346671之標題為「On-Chip Bad Block Management for NAND Flash Memory」以及Jigour於2013年3月13日申請之美國專利申請號13/799,215之標題為「NAND Flash Memory」，在此謹將上述所有的參考文獻之內容併入至此。 The cache programming implementation technique can be used in conjunction with many other techniques to implement a non-gate flash memory device with fast read and fast programming capabilities including fast sequential reads. Figure 6 is a diagram showing the functional side of a tandem NAND flash memory 600 capable of providing continuous reading across page boundaries and from logical contiguous memory locations without waiting for time, in accordance with an embodiment of the present invention. Block diagram. The error correction code program and the fault block management using the fault block lookup table can be implemented on the wafer of the memory device, that is, an additional circuit on the same die, or a command implemented in the memory device and The control logic is tightly integrated with the commands and other functions of the control logic, enabling fast and efficient continuous read operations with the fast operation of the cache programming execution technique. A suitable non-sliding flash memory architecture is described in detail in, for example, U.S. Patent No. 8,667,368 issued to Gupta on March 4, 2014, entitled "Method and Apparatus for Reading NAND Flash Memory", Michael in 2013. U.S. Patent Publication No. 2013/034667, issued on Dec. 26, entitled "On-Chip Bad Block Management for NAND Flash Memory", and U.S. Patent Application Serial No. 13/799,215, filed on March 13, 2013, entitled NAND Flash Memory, the contents of all of the above references are incorporated herein by reference.
串列非及閘快閃式記憶體600包括非及閘快閃式記憶體以及相關的頁面緩衝器638。非及閘快閃式記憶體陣列640包括字元(列)線以及位元(欄)線，且配置為使用者可定址區域642、冗餘區塊區域644以及查找表資訊區塊646。任何所需之快閃式記憶體單元技術可用於非及閘快閃式記憶體陣列640之快閃式記憶體單元。串列非及閘快閃式記憶體600可包括許多其他電路來支持記憶體編程、抹除以及讀取，如列解碼器634、欄解碼器636、輸入/輸出控制622、狀態暫存器623、連續頁面讀取(continuous page read,CPR)位址暫存器(CPR BB ADDR REG)624、命令暫存器625、位址暫存器626、查找表暫存器627、控制邏輯630、連續頁面讀取故障區塊邏輯(CPR BB LOGIC)631、連續頁面讀取故障區塊暫存器(BB REG)632以及高電壓產生器(HV GEN)633。列解碼器634在使用者控制之下，在某些實施例中係為在內部控制之下，選擇使用者可定址區域642之列；並在內部控制之下選擇冗餘區塊區域644以及查找表資訊區塊646之列。電源係藉由電源線VCC以及接地端GND，提供至整個串列非及閘快閃式記憶體600之所有電路(圖中為顯示)。當非及閘快閃記憶體600可以任何所預支方式封裝，且可具有任何型式之介面，包括一班非及閘快閃式記憶體介面，第6圖之控制邏輯630事例地實現序列周邊介面/快速通道互聯(SPI/QPI)協定，包括多輸入輸出序列周邊介面介面。其他關於序列周邊介面/快速通道互聯介面之細節以及記憶體之各種電路，可參考Jigour於2009年7月7日發行之美國專利號7,558,900之標題為「Serial Flash Semiconductor Memory」，以及前述華邦電子於2013年11月26日中華民國台灣新竹所提出之初步版本B中，具有二/四串列周邊介面以及連續讀取之3V 1G位元串列單層式NAND快閃式記憶體之W25N01GV，在此將其全部內容引用於此。 The serial non-gate flash memory 600 includes a non-gate flash memory and an associated page buffer 638. The NAND flash memory array 640 includes a word (column) line and a bit (column) line, and is configured as a user addressable area 642, a redundant block area 644, and a lookup table information block 646. Any desired flash memory cell technology can be used for the flash memory cell of the non-gate flash memory array 640. The serial NAND flash memory 600 can include a number of other circuits to support memory programming, erasing, and reading, such as column decoder 634, column decoder 636, input/output control 622, and state register 623. Continuous page read (CPR) address register (CPR BB ADDR REG) 624, command register 625, address register 626, lookup table register 627, control logic 630, continuous Page Read Fault Block Logic (CPR BB LOGIC) 631, continuous page read fault block register (BB REG) 632 and high voltage generator (HV GEN) 633. Column decoder 634 is under user control, in some embodiments, under internal control, selects a column of user addressable regions 642; and selects redundant block regions 644 and looks under internal control Table information block 646. The power supply is supplied to all circuits (shown in the figure) of the entire serial non-gate flash memory 600 by the power line VCC and the ground GND. When the non-gate flash memory 600 can be packaged in any pre-fed manner and can have any type of interface, including a non-gate flash memory interface, the control logic 630 of FIG. 6 implements a sequence peripheral interface. / Fast Track Interconnect (SPI/QPI) protocol, including multiple input and output sequence peripheral interface. For additional details on the serial interface/fast channel interface and the various circuits of the memory, refer to Jurour's US Patent No. 7,558,900, issued July 7, 2009, entitled "Serial Flash Semiconductor Memory", and the aforementioned Winbond Electronics. In the preliminary version B proposed by Hsinchu, Taiwan, on November 26, 2013, the W25N01GV has a two/four serial peripheral interface and a continuously read 3V 1G bit tandem single-layer NAND flash memory. All of its contents are hereby incorporated by reference.
若模式需要切換，可提供緩衝器模式旗標647。可提供緩衝器模式旗標647代表狀態暫存器623之一位元。位於控制邏輯630之通電偵測器635，用以初始化在通電時特定模式之設定以及預設頁面之載入。 If the mode needs to be switched, a buffer mode flag 647 can be provided. A buffer mode flag 647 can be provided to represent one bit of the state register 623. A power-on detector 635 at control logic 630 is used to initialize the setting of a particular mode upon power up and the loading of a preset page.
忙碌位元652係為唯讀裝置忙碌位元，當裝置通電或執行不同指令(包括頁面資料讀取指令以及連續讀取指令)時，忙碌位元652設定為邏輯1狀態。此時，裝置忽略除了特定 指令(如讀取狀態暫存器、讀取JEDEC識別指令及用以快取編程執行技術之目的、載入編程資料指令)之其他指令。當執行指令完成時，忙碌位元652被清除至邏輯0狀態，代表裝置準備好接收其他指令。忙碌位元652可作為狀態暫存器623之部分。 The busy bit 652 is a read-only device busy bit. When the device is powered on or executes different instructions (including a page data read command and a continuous read command), the busy bit 652 is set to a logic 1 state. At this point, the device ignores the specific Instructions (such as read status register, read JEDEC identification instructions, and instructions for fast programming execution techniques, load programming data instructions). When the execution of the instruction is completed, the busy bit 652 is cleared to a logic 0 state, indicating that the device is ready to receive other instructions. Busy bit 652 can be part of state register 623.
當頁面緩衝器638之快取暫存器在執行載入編程資料指令或快取編程執行指令時被使用，為唯讀快取忙碌位元之快取忙碌位元653被設定為邏輯1狀態。當頁面緩衝器638之快取暫存器不再忙碌時，快取忙碌位元653被清除為邏輯0狀態，代表快取暫存器準備好接受其他指令。快取忙碌位元653可作為狀態暫存器623之一部分。 When the cache buffer of the page buffer 638 is used in executing the load programming data instruction or the cache programming execution instruction, the cache busy bit 653 for the read-only cache busy bit is set to the logic 1 state. When the cache buffer of page buffer 638 is no longer busy, cache busy bit 653 is cleared to a logic 0 state, indicating that the cache register is ready to accept other instructions. The cache busy bit 653 can be part of the status register 623.
頁面緩衝器638示例性地包括單頁資料暫存器(圖中並未顯示)、單頁快取暫存器(圖中並未顯示)以及用以自資料暫存器複製資料至快取暫存器之閘的一頁(圖中並未顯示)。任何合適的閂鎖或記憶體技術可用於資料暫存器以及快取暫存器，任何適合的閘技術可用以自資料暫存器複製資料至快取暫存器。資料暫存器以及快取暫存器可安排於任何期望數目之各部份，例如這些閘皆以此方式接線以及用來控制資料的複製。舉例來說，資料暫存器以及快取暫存器可安排於個別對應DR-0以及DR-1與CR-0以及CR-1之部分，並利用由對應控制線控制之閘所對應之群組而交替操作。頁面緩衝器638之資料暫存器以及快取暫存器可操作於一般方式，該一般方式相當適合藉由施加相同控制信號至對應的閘控制線之快取編程執行技術，且可交替操作這種技術而進行藉由施加適當時脈的控制信號至閘控制線之連續讀取。舉例來說，在兩部份實施中，其中一頁 係為2K字元組，半頁(1K)之閘可藉由一控制線而被控制，另一半之半頁(1K)之閘可藉由另一控制線而被控制，因此安排資料暫存器以及快取暫存器於兩個半頁(1K)可當作兩個半頁方式操作或是一個單頁(2K)方式操作。因為兩個部份交替操作，頁面緩衝器638之兩部份實施可稱為「乒乓」緩衝器。錯誤更正碼電路(圖中並未顯示)可根據ECC-E旗標(ECC-E)648之狀態，而對快取暫存器之內容執行錯誤更正碼程序。第一錯誤更正碼狀態位元(ECC-0)650以及第二錯誤更正碼狀態位元(ECC-1)651可用以代表錯誤更正碼程序之狀態，在完成讀取操作後可用以確認資料的完整性。若有需要，ECC-E旗標648、第一錯誤更正碼狀態位元(ECC-0)650及第二錯誤更正碼狀態位元(ECC-1)651可作部份狀態暫存器623。 The page buffer 638 illustratively includes a single page data register (not shown), a single page cache register (not shown), and a copy data from the data register to the cache. A page of the gate of the register (not shown). Any suitable latch or memory technology can be used for the data buffer and the cache register, and any suitable gate technique can be used to copy data from the data buffer to the cache register. The data register and the cache register can be arranged in any desired number of parts, for example, the gates are wired in this manner and used to control the copying of the data. For example, the data register and the cache register can be arranged in the respective DR-0 and DR-1 and CR-0 and CR-1 parts, and the group corresponding to the gate controlled by the corresponding control line is used. Group and alternate operations. The data buffer of the page buffer 638 and the cache register are operable in a general manner, which is quite suitable for the cache programming execution technique by applying the same control signal to the corresponding gate control line, and can alternately operate this The technique performs a continuous reading of the gate control line by applying a control signal of the appropriate clock. For example, in a two-part implementation, one of the pages It is a 2K character group, the half page (1K) gate can be controlled by one control line, and the other half of the half page (1K) gate can be controlled by another control line, so the data is temporarily stored. The cache and the cache register can be operated as two half-page operations or one single-page (2K) mode in two half pages (1K). Because the two parts operate alternately, the two portions of page buffer 638 can be referred to as a "ping-pong" buffer. The error correction code circuit (not shown) can perform an error correction code procedure on the contents of the cache register according to the state of the ECC-E flag (ECC-E) 648. The first error correction code status bit (ECC-0) 650 and the second error correction code status bit (ECC-1) 651 can be used to represent the status of the error correction code program, which can be used to confirm the data after the read operation is completed. Integrity. If desired, the ECC-E flag 648, the first error correction code status bit (ECC-0) 650, and the second error correction code status bit (ECC-1) 651 can be used as a partial status register 623.
可使用不同尺寸之頁面緩衝器，及/或若有需要也可將頁面緩衝器分割為兩個以上之部份或分割為不相等尺寸之部分，而不影響快取編程執行技術之效用。再者，邏輯性的以及物理性的非及閘快閃式記憶體陣列之差異，並不影響本發明在此所述之教示。舉例來說，物理性的陣列在一字元線上可具有二頁面(偶數頁面為2KB，奇數頁面為2KB)，因此一字元線可為4KB之非及閘位元單元。為說明清楚起見，在此之說明以及圖式係根據邏輯性的非及閘快閃式記憶體陣列。錯誤更正電路邏輯上可視為具有提供快取暫存器之一半(CR-0部份)之內容錯誤更正的ECC-0部份，以及提供快取暫存器之另一半(CR-1部份)之內容錯誤更正之ECC-1部份。各種的ECC演算法都能使用，包括如漢明錯誤更正演算法、BCH ECC algorithm、 Reed-Solomon ECC algorithm以及其他演算法。為求詳細說明，當兩個邏輯性ECC部份ECC-0以及ECC-1分別作為CR-0以及CR-1之接口，兩個物理性的ECC區塊或單一物理性區塊可用以接口CR-0以及CR-1。將資料暫存器以及快取暫存器劃分為複數區塊且對複數區塊執行錯誤更正碼程序之方式係用以說明之舉例，若有需要也可使用其他技術。 Different sizes of page buffers can be used, and/or the page buffer can be split into more than two parts or divided into unequal sizes if desired, without affecting the utility of the cache programming implementation technique. Moreover, the differences between the logical and physical non-gate flash memory arrays do not affect the teachings of the present invention as described herein. For example, a physical array can have two pages on a word line (2KB for even pages and 2KB for odd pages), so a word line can be a 4KB non-gate cell. For the sake of clarity, the description and drawings herein are based on a logical NAND flash memory array. The error correction circuit can be logically viewed as having an ECC-0 portion that provides error correction for one half of the cache register (CR-0 portion) and provides the other half of the cache register (CR-1 portion) ) The content of the error corrected ECC-1 part. Various ECC algorithms can be used, including such as Hamming error correction algorithm, BCH ECC algorithm, Reed-Solomon ECC algorithm and other algorithms. For detailed explanation, when two logical ECC parts ECC-0 and ECC-1 are respectively used as interfaces of CR-0 and CR-1, two physical ECC blocks or a single physical block can be used as interface CR. -0 and CR-1. The manner in which the data register and the cache register are divided into complex blocks and the error correction code procedure is performed on the complex blocks is used to illustrate the examples, and other techniques may be used if necessary.
當組織與運作非及閘快閃式記憶體600來執行各種讀取操作，包括在單一平面上之非及閘架構中連續頁面讀取操作以及晶粒上錯誤更正碼程序，該非及閘架構僅作說明解釋之用，而其變形亦可被預期。要知道，2KB頁面尺寸以及特定區塊尺寸之實施例係用以說明解釋之用，若有需要可做修改。再者，特定尺寸參考並非依字面上所限制，因為實際的頁面尺寸會根據設計考量而有所不同；舉例來說，該項目包括2048字元組之主要區域以及額外的64KB備用區域，其中備用區域用以儲存錯誤更正碼以及其他資訊，例如中介資料。以相同的方式，1KB代表1024字元組主要區域以及32字元組備用區域。當在此之描述係根據單一平面架構以利詳細說明，在此所教示者也可相同應用至多平面架構。當使用多個物理性平面時，會共用一或多字組線以便記憶體系統能同時服務多個輸入/輸出之要求。每一平面提供一頁面之資料，且包括為一頁尺寸的對應之資料暫存器以及為一頁尺寸的對應之快取暫存器。在此所述之技術可分別應用至每一平面，使得每一資料暫存器以及快取暫存器係劃分為多個部份，或可應用至多個平面，使得每一資料暫存器以及快取暫存器之本身係為多頁面資料暫存器以及 快取暫存器之一部分。 When the non-gate flash memory 600 is organized and operated to perform various read operations, including sequential page read operations in a non-gate architecture on a single plane and on-die error correction code procedures, the non-AND gate architecture is only For explanation purposes, and its deformation can also be expected. It should be understood that the embodiment of the 2KB page size and the specific block size is used for explanation purposes and can be modified if necessary. Furthermore, the specific size reference is not literally limited, as the actual page size will vary depending on design considerations; for example, the project includes a major area of 2048 characters and an additional 64KB spare area, where The area is used to store error correction codes and other information, such as mediation information. In the same way, 1 KB represents the 1024-character main area and the 32-character spare area. The description herein is equally applicable to a multi-planar architecture, as described herein in terms of a single planar architecture. When multiple physical planes are used, one or more word lines are shared so that the memory system can simultaneously serve multiple input/output requirements. Each plane provides a page of information, and includes a corresponding data buffer for one page size and a corresponding cache register for one page size. The techniques described herein can be applied to each plane separately, such that each data register and cache register are divided into multiple parts, or can be applied to multiple planes, such that each data register and The cache register itself is a multi-page data register and Cache one part of the scratchpad.
第6圖也顯示用於串列周邊介面之反相之晶片選擇信號/CS、時脈信號CLK、串列資料輸入信號DI、串列資料輸出信號DO、反相之寫入保護信號/WP以及反相之維持信號/HOLD。標準的串列周邊介面快閃式介面隨著可選的反相之寫入保護信號/WP以及反相之維持信號/HOLD，提供反相之晶片選擇信號/CS、時脈信號CLK、串列資料輸入信號DI以及串列資料輸出信號DO。當在標準串列周邊介面中的一位元串列資料匯流排(資料輸入經由串列資料輸入信號DI，而資料輸出經由串列資料輸出信號DO)提供簡單介面以及與啟動於單一串列周邊介面模式之許多控制器之相容性時，其限制了達到更高的吞吐量之可能性。多位元串列周邊介面之介面因而加入，並額外地支援雙通道(二位元介面)及/或四通道(四位元介面)以增加讀取之吞吐量。第11圖也顯示雙通道串列周邊介面以及四通道串列周邊介面操作之額外的資料匯流排信號，也就是藉由選擇性地重新定義I/O(0),I/O(1),I/O(2),and I/O(3)這四根腳位之功能。在一說明之實施例之四通道串列周邊介面讀取操作(其他實施例中亦可考慮)，可利用一位元標準串列周邊介面經由I/O(0)而給出適當的讀取指令，但位址以及輸出資料之介面可為四通道(也就是四位元資料匯流排)。與在標準串列周邊介面讀取操作中輸出一位元之資料相比，四通道串列周邊介面讀取操作可在一時脈週期內輸出四位元之資料，因而四通道串列周邊介面讀取操作可提供四倍高的讀取吞吐量。在此之四通道串列周邊介面讀取操作僅用於說明之用，在此之教示也可相同 地應用至其他操作模式，包括但不限於單一串列周邊匯流排、雙通道串列周邊匯流排、四周邊介面以及雙倍傳輸速率等讀取模式。在四周邊介面協定中，完整介面(操作碼、位址以及資料輸出)係以四位元為基礎。在雙倍傳輸速率協定中，輸出資料係提供於時脈信號CLK之正觸發緣以及負觸發緣，而非如單一傳輸速率讀取模式中，僅於時脈信號CLK之負觸發緣提供輸出資料。 Figure 6 also shows the wafer selection signal /CS, the clock signal CLK, the serial data input signal DI, the serial data output signal DO, the inverted write protection signal /WP for the inversion of the serial peripheral interface, and Inverted sustain signal / HOLD. The standard serial peripheral interface flash interface provides inverted chip select signal /CS, clock signal CLK, serial with the optional inverted write protection signal /WP and inverted sustain signal /HOLD The data input signal DI and the serial data output signal DO. When a one-bit serial data bus in the standard serial peripheral interface (data input via the serial data input signal DI and data output via the serial data output signal DO) provides a simple interface and starts with a single serial periphery When the compatibility of many controllers of the interface mode limits the possibility of achieving higher throughput. The multi-bit serial interface of the peripheral interface is thus added, and additionally supports dual channel (two bit interface) and/or four channel (four bit interface) to increase the throughput of reading. Figure 11 also shows the additional data bus signal for the dual channel serial peripheral interface and the four channel serial peripheral interface operation, that is, by selectively redefining I/O(0), I/O(1), I/O(2), and I/O(3) are functions of the four feet. The four-channel serial peripheral interface read operation (which may also be considered in other embodiments) in an illustrative embodiment may utilize a one-element standard serial peripheral interface to provide appropriate reading via I/O (0). The instruction, but the interface of the address and output data can be four channels (that is, four-bit data bus). Compared with the data of one bit output in the standard serial peripheral interface read operation, the four-channel serial peripheral interface read operation can output four-bit data in one clock cycle, thus the four-channel serial peripheral interface read The fetch operation provides four times the read throughput. The four-channel serial peripheral interface read operation here is for illustrative purposes only, and the teachings herein may be the same. The application is applied to other modes of operation, including but not limited to a single serial peripheral bus, a dual channel serial bus, a four peripheral interface, and a double transfer rate. In the four-perimeter interface agreement, the complete interface (opcode, address, and data output) is based on four bits. In the double transfer rate protocol, the output data is provided in the positive trigger edge and the negative trigger edge of the clock signal CLK, instead of in the single transfer rate read mode, the output data is provided only on the negative trigger edge of the clock signal CLK. .
快取編程執行技術可包括故障區塊管理。要被編程之頁面的位址被取得後，存放在位址暫存器626。編程程序藉由在查找表暫存器627中查找之動作，而繼續判斷位址暫存器626中之位址是否符合在查找表暫存器627中之任何邏輯區塊位址。因為查找表暫存器627可為能夠利用控制邏輯630於本地存取之一快速靜態存取記憶體，該查找之動作可快速執行而不會顯著影響編程時間。若沒有找到任何符合的對象，邏輯區塊位址則用以編程記憶體之一頁。若找到符合的對象時，則指出故障區塊，並且使用替代區塊之PBA而非位址暫存器626之邏輯區塊位址來編程所欲編程之頁面。一旦取得正確的頁面位址，實際的頁面編程程序以及確認編程錯誤之程序會以任何所欲的方式執行。根據本發明之一實施例，一合適的技巧係為一般編程驗證操作，該編程驗證操作通常在狀態暫存器中設定通過/失敗位元。在確認編程錯誤後，若有需要會執行故障區塊管理。故障區塊管理可以各種方式執行，例如在使用者控制下藉由主機或控制器而執行、半自動地回應由主機或控制器所標記之故障區塊、經由非及閘快閃式記憶體裝置之控制邏輯自動 地執行、或以任何其他合適的方式。 The cache programming execution technique may include fault block management. After the address of the page to be programmed is obtained, it is stored in the address register 626. The programming program continues to determine if the address in the address register 626 matches any of the logical block addresses in the lookup table register 627 by looking up the lookup in the lookup table register 627. Because the lookup table register 627 can be a fast static access memory that can be accessed locally by the control logic 630, the lookup action can be performed quickly without significantly affecting the programming time. If no matching object is found, the logical block address is used to program one page of memory. If a matching object is found, the fault block is indicated and the page to be programmed is programmed using the PBA of the substitute block instead of the logical block address of the address register 626. Once the correct page address is obtained, the actual page programming program and the program that confirms the programming error will be executed in any desired way. In accordance with an embodiment of the present invention, a suitable technique is a general program verify operation that typically sets pass/fail bits in a state register. After confirming the programming error, the fault block management will be performed if necessary. Fault block management can be performed in various ways, such as by a host or controller under user control, semi-automatically responding to a fault block marked by the host or controller, via a non-gate flash memory device. Control logic automatically Execute, or in any other suitable manner.
因為使用者可能在沒有助益到故障區塊的情況下跨越實體區塊邊界而編程，故對於串列編程操作時之編程吞吐量之維持，故障區塊管理係特別有用。使用者可藉由設定串列位元(SEQ)654，而啟動串列編程模式。 Fault block management is particularly useful for maintaining programming throughput during serial programming operations because the user may program across physical block boundaries without benefiting the faulty block. The user can initiate the serial programming mode by setting the serial bit (SEQ) 654.
本發明之敘述包括其在此所提之應用以及優點僅為說明之用，並非用以限制本發明於申請專利範圍中之範圍。在此所述之實施例之變形以及修改皆為可能，且該領域具有通常知識者也都知道實際替代以及等同於本發明之各種元件，可經由研究本專利說明書而得。舉例來說，儘管在此所述之許多實施例係用於串列非及閘快閃式記憶體，在此所述之特定技巧例如通電順序、模式選擇以及跨越頁面邊界與自邏輯性地連續記憶體位址而不用等待時間連續資料輸出等，可用於並列非及閘快閃式記憶體。再者，在此所給訂之特定數值係為說明之用，若有需要可自行修改。語彙如「第一」以及「第二」等，係為區別語彙而非解釋為隱含一順序或一整體之特定部份。這些或其他在此所述之實施例之變形以及調整，包括在此所述之實施例之替代以及等同物，可在不悖離本發明之範圍以及精神下得到，包括本發明以下所述之申請專利範圍。 The description of the present invention is intended to be illustrative, and is not intended to limit the scope of the invention. Variations and modifications of the embodiments described herein are possible, and those skilled in the art will be aware of the actual substitutions and equivalents to the various elements of the invention, which may be obtained by studying the present specification. For example, although many of the embodiments described herein are for serial non-gate flash memory, the specific techniques described herein, such as power-on sequence, mode selection, and logical continuity across page boundaries. The memory address can be used for parallel non-gate flash memory without waiting for continuous data output. Furthermore, the specific numerical values given herein are for illustrative purposes and may be modified as needed. The vocabulary such as "first" and "second" are used to distinguish vocabulary rather than to imply a specific order or a specific part of a whole. Variations and modifications of these or other embodiments described herein, including alternatives and equivalents to the embodiments described herein, may be made without departing from the scope and spirit of the invention, including the following Apply for a patent scope.
200~274‧‧‧步驟流程 200~274‧‧‧Step process
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI646430B (en) * | 2017-08-31 | 2019-01-01 | 華邦電子股份有限公司 | Byte programming method and page programming method |
| US10593407B2 (en) | 2017-08-31 | 2020-03-17 | Winbond Electronics Corp. | Fast programming methods for flash memory devices |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10566040B2 (en) * | 2016-07-29 | 2020-02-18 | Micron Technology, Inc. | Variable page size architecture |
| JP2018049387A (en) * | 2016-09-20 | 2018-03-29 | 東芝メモリ株式会社 | Memory system and processor system |
| US10956318B2 (en) * | 2018-06-19 | 2021-03-23 | Macronix International Co., Ltd. | Overlapping ranges of pages in memory systems |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003249082A (en) * | 2001-12-19 | 2003-09-05 | Toshiba Corp | Semiconductor integrated circuit |
| US20090024904A1 (en) * | 2007-07-19 | 2009-01-22 | Micron Technology, Inc. | Refresh of non-volatile memory cells based on fatigue conditions |
| US20100103734A1 (en) * | 2008-10-24 | 2010-04-29 | Gerrit Jan Hemink | Programming non-volatile memory with high resolution variable initial programming pulse |
| US20130336060A1 (en) * | 2012-06-13 | 2013-12-19 | Winbond Electronics Corp. | Memory device and redundancy method thereof |
| TW201403605A (en) * | 2012-07-02 | 2014-01-16 | Winbond Electronics Corp | Method and apparatus for reading NAND flash memory |
| TW201419295A (en) * | 2012-11-14 | 2014-05-16 | Winbond Electronics Corp | On-chip bad block management for NAND flash memory |
| US20140258811A1 (en) * | 2013-03-11 | 2014-09-11 | Macronix International Co., Ltd. | Storage scheme for built-in ecc operations |
-
2014
- 2014-12-09 TW TW103142740A patent/TWI587302B/en active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003249082A (en) * | 2001-12-19 | 2003-09-05 | Toshiba Corp | Semiconductor integrated circuit |
| US20090024904A1 (en) * | 2007-07-19 | 2009-01-22 | Micron Technology, Inc. | Refresh of non-volatile memory cells based on fatigue conditions |
| US20100103734A1 (en) * | 2008-10-24 | 2010-04-29 | Gerrit Jan Hemink | Programming non-volatile memory with high resolution variable initial programming pulse |
| US20130336060A1 (en) * | 2012-06-13 | 2013-12-19 | Winbond Electronics Corp. | Memory device and redundancy method thereof |
| TW201403605A (en) * | 2012-07-02 | 2014-01-16 | Winbond Electronics Corp | Method and apparatus for reading NAND flash memory |
| TW201419295A (en) * | 2012-11-14 | 2014-05-16 | Winbond Electronics Corp | On-chip bad block management for NAND flash memory |
| US20140258811A1 (en) * | 2013-03-11 | 2014-09-11 | Macronix International Co., Ltd. | Storage scheme for built-in ecc operations |
| TW201435893A (en) * | 2013-03-11 | 2014-09-16 | Macronix Int Co Ltd | Storage scheme for built-in ECC operations |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI646430B (en) * | 2017-08-31 | 2019-01-01 | 華邦電子股份有限公司 | Byte programming method and page programming method |
| US10593407B2 (en) | 2017-08-31 | 2020-03-17 | Winbond Electronics Corp. | Fast programming methods for flash memory devices |
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|---|---|
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