TWI586229B - Adjustable an in-line band rejection structure - Google Patents
Adjustable an in-line band rejection structure Download PDFInfo
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本發明係有關一種可調控線內帶拒結構，尤指一種可以藉由簡化電路結構設計而降低成本的線內帶拒結構技術。 The present invention relates to an adjustable in-line tape rejection structure, and more particularly to an in-line tape rejection structure technique which can reduce cost by simplifying circuit structure design.
隨著科技發展日新月異，智慧型的穿戴裝置越來越普及，電機設備與電子產品在使用過程中可能產生電磁輻射，以致干擾其他電氣設備的正常運作，甚至影響到人體的健康。由於現代的電子產品，功能越來越強大，操作速度也越來越快，連帶電子線路也越來越密集與複雜，致使電磁干擾(EMI)和電磁相容(EMC)問題已經變成了電路設計上的主要挑戰。 With the rapid development of science and technology, smart wearable devices are becoming more and more popular. Electromagnetic equipment and electronic products may generate electromagnetic radiation during use, which may interfere with the normal operation of other electrical equipment and even affect the health of the human body. Due to the increasingly powerful functions of modern electronic products, the operation speed is getting faster and faster, and the associated electronic circuits are becoming more and more dense and complex, resulting in electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems becoming circuit design. The main challenge.
依據所知，目前解決電磁干擾和電磁相容(EMI/EMC)常見的方法大致包括有：在I/O端加上濾波電容、使用濾波器(Filter)、屏蔽法(Shielding)以及擴展頻譜法(Spread Spectrum)等技術手段；或者是透過整合接地、佈線、搭接等層面菶等技術手段，雖然上述該等習知技術可以解決電磁干擾和電磁相容(EMI/EMC)的問題，惟，上述該等習知技術之電路結構設計過於複雜，以致製造加工成本較高，因此，如何開發出一種電路結構設計簡單，以降低製造加工成本的線內帶拒結構技術，實已成為相關技術領域業者所急欲解決與挑戰的重要課題。 According to the knowledge, the current common methods for solving electromagnetic interference and electromagnetic compatibility (EMI/EMC) include: adding filter capacitors at the I/O end, using filters, shielding methods, and spread spectrum methods. (Spread Spectrum) and other technical means; or through the integration of grounding, wiring, lapping and other technical means, although these above-mentioned techniques can solve electromagnetic interference and electromagnetic compatibility (EMI / EMC) problems, but The circuit structure design of the above-mentioned conventional technologies is too complicated, so that the manufacturing and processing costs are high. Therefore, how to develop an in-line tape repelling structure technology with simple circuit structure design to reduce the manufacturing processing cost has become a related technical field. The important issues that the industry is eager to solve and challenge.
依據目前所知，尚未發現具備電路結構簡單以降低製造加工成本之線內帶拒結構技術的專利或是論文被提出，且基於電子產業的迫切需求下，本發明人等乃經不斷的努力研發之下，終於研發出一套有別於上述文獻之技術概念的本發明。 According to the current knowledge, no patents or papers have been found that have an in-line rejection structure technology with a simple circuit structure to reduce manufacturing processing costs, and the inventors have continuously developed efforts based on the urgent needs of the electronics industry. Under the circumstance, a set of inventions different from the technical concept of the above documents was finally developed.
本發明主要目的，在於提供一種電路結構設計更為簡單而易於實現的可調控線內帶拒結構，主要是利用電容或電感、傳輸線之電氣長度與傳輸線阻抗會使電路在工作頻率點上達到帶通或帶拒特性的濾波功能，以解決電磁干擾和電磁相容的問題，並可藉由調變電容或電感大小來調整帶拒濾波器的工作頻率。達成上述目的功效所採用之技術手段，係於基板覆設包括第一導電區塊、第二導電區塊、第一傳輸線及第二傳輸線，其中該第一傳輸線一端連接第一導電區塊的頂部內側緣，其另端連接第二導電區塊的頂部內側緣；第二傳輸線一端連接第二導電區塊的底部內側緣，其末端延伸靠近至第一導電區塊的底部內側緣，且具有一間隙，並於第一導電區塊的底部內側緣與第二傳輸線末端之間電性連接有一電容或是電感。 The main object of the present invention is to provide a controllable in-line strip rejection structure which is simpler and easier to implement, and mainly utilizes a capacitor or an inductor, and the electrical length of the transmission line and the transmission line impedance cause the circuit to reach the operating frequency point. Passing or rejecting the filtering function to solve the problem of electromagnetic interference and electromagnetic compatibility, and adjusting the operating frequency of the reject filter by adjusting the size of the capacitor or the inductor. The technical means for achieving the above-mentioned purpose is that the substrate covering comprises a first conductive block, a second conductive block, a first transmission line and a second transmission line, wherein one end of the first transmission line is connected to the top of the first conductive block The inner edge is connected to the top inner edge of the second conductive block; the second end of the second transmission line is connected to the bottom inner edge of the second conductive block, and the end thereof extends close to the bottom inner edge of the first conductive block, and has a The gap is electrically connected to a capacitor or an inductor between the bottom inner edge of the first conductive block and the end of the second transmission line.
10‧‧‧基板 10‧‧‧Substrate
20‧‧‧第一導電區塊 20‧‧‧First conductive block
21‧‧‧第二導電區塊 21‧‧‧Second conductive block
22‧‧‧訊號輸入埠 22‧‧‧Signal input埠
23‧‧‧訊號輸出埠 23‧‧‧Signal output埠
30‧‧‧第一傳輸線 30‧‧‧First transmission line
40‧‧‧第二傳輸線 40‧‧‧second transmission line
50‧‧‧電路元件 50‧‧‧ circuit components
C‧‧‧電容 C‧‧‧ capacitor
L‧‧‧電感 L‧‧‧Inductance
圖1係本發明具體的電路結構示意圖。 1 is a schematic diagram of a specific circuit structure of the present invention.
圖2係本發明電路實施示意圖。 2 is a schematic diagram of the implementation of the circuit of the present invention.
圖3係本發明於不同傳輸線尺寸與頻率對照的jX值示意圖。 Figure 3 is a schematic illustration of jX values for different transmission line sizes and frequencies in accordance with the present invention.
圖4係本發明於電路模擬與實際測量的帶拒頻率比對示意圖。 4 is a schematic diagram of the rejection frequency comparison between the circuit simulation and the actual measurement according to the present invention.
圖5係本發明實體電路的結構實施示意圖。 Fig. 5 is a schematic view showing the structure of a physical circuit of the present invention.
圖6係本發明於電路模擬與另一實際測量的帶拒頻率比對示意圖。 Figure 6 is a schematic illustration of the rejection ratio of the circuit simulation with another actual measurement of the present invention.
圖7係本發明另一實體電路的結構實施示意圖。 Figure 7 is a block diagram showing the structure of another physical circuit of the present invention.
為讓 貴審查委員能進一步瞭解本發明整體的技術特徵與達成本發明目的之技術手段，玆以具體實施例並配合圖式加以詳細說明：簡言之，本發明係以傳輸線串聯一個電路元件50(例如電感；或是電容)，再並聯一條傳輸線來設計新型的帶具濾波電路，並利用傳輸線矩陣與S參數推導分析，再利Microwave Office來驗證其分析的正確性，並用IE3D來模擬電路。電路結構是以線寬為50歐姆的情況下去設計的，最後以雕刻機實現電路於厚度之FR4基板上，再利用向量網路分析儀量測結果。電路模擬與實際量測結果，與理論皆在0~4GHz量測頻率範圍內具有一致性。 In order to allow the reviewing committee to further understand the technical features of the present invention and the technical means for achieving the object of the present invention, it will be described in detail by way of specific embodiments and drawings: in short, the present invention is a circuit component 50 connected in series by a transmission line. (such as inductors; or capacitors), and then parallel a transmission line to design a new type of filter circuit, and use the transmission line matrix and S-parameter derivation analysis, and then Microwave Office to verify the correctness of the analysis, and use IE3D to simulate the circuit. The circuit structure is designed with a line width of 50 ohms. Finally, the engraving machine is used to realize the circuit on the FR4 substrate of thickness, and the vector network analyzer is used to measure the result. The circuit simulation and actual measurement results are consistent with the theory in the 0~4GHz measurement frequency range.
請配合參看圖1、5及圖7所示，為達成本發明主要目的之具體實施例，係於基板10覆設包括一第一導電區塊20、一與第一導電區塊20形成左右對稱的第二導電區塊21、一第一傳輸線30及一第二傳輸線40；其中，第一傳輸線30一端連接第一導電區塊20的頂部內側緣，其另端連接第二導電區塊21的頂部內側緣；第二傳輸線40一端連接第二導電區塊21的底部內側緣，其末端延伸靠近至第一導電區塊20的底部內側緣而具有一間隙，並於第一導電區塊20的底部內側緣與第二傳輸線40末端之間電性連接有一電路元件50，此電路元件50可為電容C；或是電感L，據此以形成一帶具濾波電路。 Referring to FIG. 1 , FIG. 5 and FIG. 7 , in order to achieve the main purpose of the present invention, the substrate 10 is covered with a first conductive block 20 and a left and right symmetrical with the first conductive block 20 . a second conductive block 21, a first transmission line 30 and a second transmission line 40; wherein the first transmission line 30 has one end connected to the top inner edge of the first conductive block 20 and the other end of which is connected to the second conductive block 21 a top inner edge; the second transmission line 40 is connected to the bottom inner edge of the second conductive block 21 at one end, and the end thereof extends close to the bottom inner edge of the first conductive block 20 to have a gap, and is in the first conductive block 20 A circuit component 50 is electrically connected between the bottom inner edge and the end of the second transmission line 40. The circuit component 50 can be a capacitor C or an inductor L, thereby forming a tape filter circuit.
具體而言，請參看圖5、7所示之第一導電區塊20與第二導電區塊21皆呈矩形第一導電區塊20接設有一訊號輸入埠22，第二導電區 塊21接設有一訊號輸出埠23；而第一導電區塊20及第二導電區塊21的特性組抗皆為50歐姆，第一導電區塊20及第二導電區塊21的長度L3皆為0.587cm，線寬則皆為0.310801cm。 Specifically, the first conductive block 20 and the second conductive block 21 shown in FIG. 5 and FIG. 7 are rectangular, and the first conductive block 20 is connected with a signal input port 22, and the second conductive block 21 is connected. A signal output 埠23 is provided; and the characteristic resistance of the first conductive block 20 and the second conductive block 21 is 50 ohms, and the lengths L 3 of the first conductive block 20 and the second conductive block 21 are both 0.587. Cm, the line width is 0.310801cm.
請配合參看圖1、5所示的實施例中，第一傳輸線30與第二傳輸線40皆呈長矩形，且上述電路元件50為電容C，此電容C之電容值則是介於0.18~0.23pF之間；至於第一傳輸線30的長度L1為1.2cm，寬度W1為0.1257cm，阻抗Z1=80Ω，電氣長度θ1=61.5752°；第二傳輸線40的長度L2為1.15cm，寬度W2為0.0717586CM，阻抗Z1=100Ω，電氣長度θ2=59.0096°；較佳的，上述電容值為0.2pF，電容C誤差值在±0.1pF左右。 Referring to the embodiment shown in FIG. 1 and FIG. 5, the first transmission line 30 and the second transmission line 40 are both long rectangular, and the circuit component 50 is a capacitor C, and the capacitance of the capacitor C is between 0.18 and 0.23. Between pF; as for the length L 1 of the first transmission line 30 is 1.2 cm, the width W 1 is 0.1257 cm, the impedance Z 1 = 80 Ω, the electrical length θ 1 = 61.5752 °; the length L 2 of the second transmission line 40 is 1.15 cm, The width W 2 is 0.0717586 CM, the impedance Z 1 =100 Ω, and the electrical length θ 2 = 59.0096°; preferably, the capacitance value is 0.2 pF, and the capacitance C error value is about ±0.1 pF.
除此之外，再請參看圖1、7所示的實施例中，第一傳輸線30與第二傳輸線40皆呈長矩形；電路元件50為電感L，此電感L之電感值介於14.5~16.5nH之間；至於第一傳輸線30的長度L1為2.5cm，寬度W1為0.1257cm，阻抗Z1=80Ω，電氣長度θ1=128.2817°；第二傳輸線40的長度L2為2.45cm，寬度W2為0.0717586CM，阻抗Z1=100Ω，電氣長度θ2=125.7161°；較佳的，上述電感L的電感值為15nH，電感L誤差值在±0.75nH左右。 In addition, referring to the embodiment shown in FIG. 1 and FIG. 7, the first transmission line 30 and the second transmission line 40 are both long rectangular; the circuit component 50 is the inductance L, and the inductance of the inductance L is between 14.5. 16.5nH; as for the first transmission line 30, the length L 1 is 2.5cm, the width W 1 is 0.1257cm, the impedance Z 1 =80Ω, the electrical length θ 1 =128.2817°; the length L 2 of the second transmission line 40 is 2.45cm The width W 2 is 0.0717586 CM, the impedance Z 1 =100 Ω, and the electrical length θ 2 =125.7161°; preferably, the inductance L of the inductor L is 15 nH, and the inductance L error value is about 0.75 nH.
進一步而言，本發明是採用濾波器如參考文獻[1](Filter)的方式來解決電磁干擾和電磁相容(EMI/EMC)的問題。如圖1所示為本發明具體的電路結構示意，係使用電容C或電感L串連一條第一傳輸線30，再並聯一條第二傳輸線40，並且在電路設計上是以50歐姆線的寬度來進行設計，於此，無論是在應用上或是設計上都更加實用便利，本發明只需要一個電感L或電容C再利用並聯結構如參考文獻[8]即可做出一個濾波器，因此， 本發明電路設計結構確實非常的簡單。於是，本發明針對此並聯電路結構進行其電氣特性的分析與瞭解後，發現可以利用電容C、電感L、第一傳輸線30、第二傳輸線40之電氣長度(θ)與傳輸線阻抗(Z)會使電路在工作頻率點上達到帶通或帶拒特性，並且還可以利用改變電容C或電感L的大小，來調整帶拒濾波器的工作頻率。電路使用Microwave Office進行模擬，再以IE3D模擬軟體設計電路，並利用雕刻機實現電路，再以向量網路分析儀量測電路特性。 Further, the present invention solves the problems of electromagnetic interference and electromagnetic compatibility (EMI/EMC) by using a filter such as Reference [1] (Filter). 1 is a schematic diagram of a specific circuit structure of the present invention. A first transmission line 30 is connected in series with a capacitor C or an inductor L, and a second transmission line 40 is connected in parallel, and the circuit design is 50 ohm line width. Designing, here, whether it is more practical or convenient in application or design, the present invention only needs one inductor L or capacitor C and then uses a parallel structure such as reference [8] to make a filter, therefore, The circuit design structure of the present invention is indeed very simple. Therefore, the present invention analyzes and understands the electrical characteristics of the parallel circuit structure, and finds that the electrical length (θ) and the transmission line impedance (Z) of the capacitor C, the inductor L, the first transmission line 30, and the second transmission line 40 can be utilized. The circuit can be bandpass or stripped at the operating frequency point, and the operating frequency of the band reject filter can also be adjusted by changing the size of the capacitor C or the inductor L. The circuit is simulated using Microwave Office, and then the circuit is designed with IE3D analog software, and the circuit is implemented by an engraving machine, and then the circuit characteristics are measured by a vector network analyzer.
圖2所示為本發明所提出的電路結構，分別由一條第一傳輸線30跟另一條與電容C或電感L串接的第二傳輸線40，並聯後兩端各與訊號輸入埠22及訊號輸出埠23相連接。傳輸線之ABCD參數矩陣如(1)式，電容C或電感L串接的傳輸線之ABCD參數矩陣如(2)式：
再把ABCD轉換成Y參數，Y1、Y2合併後就可以得到完整的Y參數如(3)式。 Then convert ABCD into Y parameter, and Y 1 and Y 2 can be combined to obtain complete Y parameters such as (3).
再把Y參數轉成S參數，S11=S22如(4)式、S12=S21如(5)式。 Then, the Y parameter is converted into an S parameter, and S 11 = S 22 is as shown in the formula (4) and S 12 = S 21 as in the equation (5).
△Y如(10)式。 △ Y is as in (10).
△Y=(Y o +Y 11)(Y o +Y 22)-Y 12 Y 21 (6) △Y=( Y o + Y 11 )( Y o + Y 22 )- Y 12 Y 21 (6)
利用以上分析之公式來設計帶拒濾波器，設計帶拒濾波器之條件為|S11|等於1、|S21|等於0。將(5)式等於0，整理後得到(7)式。 Using the above analytical formula to design the rejection filter, the condition for designing the rejection filter is |S 11 | equal to 1, |S 21 | equal to zero. The formula (5) is equal to 0, and the formula (7) is obtained after finishing.
其中工作頻率f=2.45GHz，傳輸線阻抗Z1=80Ω、Z2=100Ω，特性阻抗(Z0)為50Ω的Port，給定傳輸線長度利用θ=β l來計算θ1、θ2，求出θ1、θ2後就可以算出jX的值，jX值為阻抗在虛軸的電抗值，Z1長度給定1.2cm、Z2長度給定1.15cm，知道工作頻率和長度後就可以求出θ1=61.5752°、θ2=59.0096°，由(7)式可以求出jX=-303.1314。jX為負表示使用的原件為電容C，改變Z1、Z2長度為2.5cm、2.45cm，其餘的不變，知道工作頻率和長度後就可以求出θ1=128.2817°、θ2=125.7161°，由(7)式可以求出jX=246.6557。jX值為正則使用電感L。 The working frequency f=2.45 GHz, the transmission line impedance Z 1 =80 Ω, Z 2 =100 Ω, the characteristic impedance (Z 0 ) is 50 Ω Port, and the θ 1 and θ 2 are calculated by using θ=β l for a given transmission line length. After θ 1 and θ 2 , the value of jX can be calculated. The jX value is the reactance value of the impedance on the imaginary axis. The length of Z 1 is 1.2 cm and the length of Z 2 is 1.15 cm. After knowing the working frequency and length, it can be obtained. θ 1 =61.5752° and θ 2 =59.0096°, and jX=-303.1314 can be obtained from the formula (7). If jX is negative, the original used is capacitor C, and the lengths of Z 1 and Z 2 are changed to 2.5 cm and 2.45 cm. The rest are unchanged. After knowing the operating frequency and length, θ 1 =128.2817° and θ 2 =125.7161 can be obtained. °, jX=246.6557 can be obtained from the formula (7). The jX value is positive and the inductance L is used.
圖3所示為利用公式(7)來計算jX值後在把不同長度下與不同頻率下所作的整理圖，給定的條件Z1=80Ω、Z2=100Ω、頻率1~3GHz、Z1長度分為6種(1.2、1.5、1.7、2.0、2.2、2.5)、Z2長度也分為6種(1.15、1.45、1.65、1.95、2.15、2.45)單位為cm，峰對峰值定為1000、-1000，圖3可以清楚的表示在那些長度和頻率下是使用電容C或電感L。 Figure 3 shows the alignment of different lengths and different frequencies after calculating the jX value using equation (7). Given conditions Z 1 = 80 Ω, Z 2 = 100 Ω, frequency 1 to 3 GHz, Z 1 The length is divided into 6 types (1.2, 1.5, 1.7, 2.0, 2.2, 2.5), and the length of Z 2 is also divided into 6 types (1.15, 1.45, 1.65, 1.95, 2.15, 2.45). The unit is cm, and the peak-to-peak value is set to 1000. -1000, Figure 3 clearly shows the use of capacitor C or inductor L at those lengths and frequencies.
在本發明的實驗例中，圖4是利用Microwave Office軟體進行可行性模擬、IE3D設計電路模擬和實作後實際測量的比較圖，給定的條件：工作頻率f=2.45GHz，傳輸線阻抗Z1=80Ω、Z2=100Ω，特性阻抗(Z0)為50Ω的Port，Z1、Z2的長度分別為1.2cm、1.15cm，θ1=61.5752°、θ2=59.0096°，jX=-303.1314轉換成電容C=0.2143pF，實際是使用0.2pF的電容C，電容C誤差值在±0.1pF。在Microwave Office模擬的|S11|=-0.000020093dB、|S21|=-53.635dB，在IE3D模擬的|S11|=-0.2603dB、|S21|=-16.14dB，實作測量的|S11|=-0.537195dB、|S21|=-11.004254dB，頻率都為2.45GHz。 In the experimental example of the present invention, FIG. 4 is a comparison diagram of the feasibility simulation, the IE3D design circuit simulation and the actual measurement after the implementation using the Microwave Office software, given conditions: operating frequency f=2.45 GHz, transmission line impedance Z 1 =80Ω, Z 2 =100Ω, the characteristic impedance (Z 0 ) is 50Ω Port, the lengths of Z 1 and Z 2 are 1.2cm, 1.15cm, θ 1 =61.5752°, θ 2 =59.0096°, jX=-303.1314 Converted to a capacitor C = 0.2143pF, the actual use of a capacitor C of 0.2pF, the capacitance C error value is ± 0.1pF. |S 11 |=-0.000020093dB, |S 21 |=-53.635dB in Microwave Office simulation, |S 11 |=-0.2603dB, |S 21 |=-16.14dB in IE3D simulation, for measurement | S 11 |=-0.537195dB, |S 21 |=-11.004254dB, and the frequency is 2.45 GHz.
接著，推導出理論值與IE3D模擬結果後，再以雕刻機實現電路，如圖5所示。本發明板材係使用雙面FR4基板10，介電常數為4.3，厚度為1.6mm。電容值於計算時給定為0.2143pF，實際使用0.2pF電容C誤差值在±0.1pF。圖6與圖4雷同，但圖6是jX為電感性的比較圖，給定的條件：工作頻率f=2.45GHz，傳輸線阻抗Z1=80Ω、Z2=100Ω，特性阻抗(Z0)為50Ω的Port，Z1、Z2的長度分別為2.5cm、2.45cm，θ1=128.2817°、θ2=125.7161°，jX=246.6557轉換成電感L=16.023nH，實際是使用15nH的電感L，電感L誤差值在±0.75nH。最後推導出理論值與IE3D模擬結果後，再以雕刻機實現電路，如圖5所示。板材係使用雙面FR4基板10，介電常 數為4.3，厚度為1.6mm。電感值於計算時給定為16.023nH，實際使用15nH電感誤差值在±0.75nH。 Next, after deriving the theoretical value and the IE3D simulation result, the circuit is implemented by an engraving machine, as shown in FIG. The sheet material of the present invention uses a double-sided FR4 substrate 10 having a dielectric constant of 4.3 and a thickness of 1.6 mm. The capacitance value is given as 0.2143pF when calculated, and the actual used 0.2pF capacitor C error value is ±0.1pF. Figure 6 is the same as Figure 4, but Figure 6 is a comparison diagram of jX inductive. Given conditions: operating frequency f = 2.45 GHz, transmission line impedance Z 1 = 80 Ω, Z 2 = 100 Ω, characteristic impedance (Z 0 ) is 50Ω Port, Z 1 , Z 2 lengths are 2.5cm, 2.45cm, θ 1 =128.2817°, θ 2 =125.7161°, jX=246.6557 is converted into inductance L=16.023nH, actually using 15nH inductor L, The inductance L error value is ±0.75nH. Finally, after deriving the theoretical value and the IE3D simulation result, the circuit is realized by the engraving machine, as shown in Fig. 5. The sheet was a double-sided FR4 substrate 10 having a dielectric constant of 4.3 and a thickness of 1.6 mm. The inductance value is given as 16.023nH in the calculation, and the actual 15nH inductance error is ±0.75nH.
綜上所述，本發明根據比較結果可以發現實際電路與IE3D所模擬出來的結果相似。由此可知，上述所推導出來的理論值符合實際電路之電路特性，證明推導的理論和模擬結果之正確性；因此，藉由上述具體實施例的說明，本發明確實具有電路結構設計更為簡單而易於實現特點，主要是利用電容或電感、傳輸線之電氣長度與傳輸線阻抗會使電路在工作頻率點上達到帶通或帶拒特性的濾波功能來解決電磁干擾和電磁相容的問題，並可藉由調變電容或電感大小來調整帶拒濾波器的工作頻率。 In summary, according to the comparison result, the present invention can find that the actual circuit is similar to the result simulated by IE3D. It can be seen that the theoretical values derived above conform to the circuit characteristics of the actual circuit, and prove the correctness of the theoretical and simulation results. Therefore, the invention has a simple circuit structure design by the description of the above specific embodiments. The easy-to-implement feature is mainly to use the capacitance or inductance, the electrical length of the transmission line and the transmission line impedance to make the circuit achieve the band-pass or rejection function filtering function at the working frequency point to solve the electromagnetic interference and electromagnetic compatibility problems, and The operating frequency of the reject filter is adjusted by modulating the capacitance or the size of the inductor.
以上所述，僅為本發明之一種可行實施例，並非用以限定本發明之專利範圍，舉凡依據下列請求項所述之內容、特徵以及其發明技術概念而為之簡易變化的等效實施，皆應包含於本發明之專利範圍內。本發明所具體界定於請求項之結構特徵，未見於同類物品，且具實用性與進步性，已符合發明專利要件，爰依法具文提出申請，謹請 鈞局依法核予專利，以維護本申請人合法之權益。 The above is only one possible embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent implementation of the content, the features and the technical concept of the invention as described in the following claims, All should be included in the scope of the patent of the present invention. The invention is specifically defined in the structural features of the request item, is not found in the same kind of articles, and has practicality and progress, has met the requirements of the invention patent, and has filed an application according to law, and invites the bureau to approve the patent according to law to maintain the present invention. The legal rights of the applicant.
[1] E. M. T. Jones, and J. T. Bolljahn, “COupled-Strip-Transmission-Line Filters and Directional Couplers,” IEEETrans. Microwave Theory Tech., vol. 4, no. 2, pp. 75-81, April 1956 [1] E. M. T. Jones, and J. T. Bolljahn, “COupled-Strip-Transmission-Line Filters And Directional Couplers,” IEEE Trans. Microwave Theory Tech., vol. 4, no. 2, pp. 75-81, April 1956
[2] Jyh-Wen Sheen,” A Compact Semi-Lumped Low-Pass Filter for Harmonics and Spurious Suppression,” IEEE Microwave and Guided Wave Letters, Vol. 10, No. 3, March 2000 [2] Jyh-Wen Sheen, “A Compact Semi-Lumped Low-Pass Filter for Harmonics and Spurious Suppression,” IEEE Microwave and Guided Wave Letters, Vol. 10, No. 3, March 2000
[3] Roberta Dozio, Martin J. Burke,” Second and Third Order Analogue High-Pass Filters for Diagnostic Quality ECG,” ISSC 2009, UCD, June 10-11th [3] Roberta Dozio, Martin J. Burke, “Second and Third Order Analogue High-Pass Filters for Diagnostic Quality ECG,” ISSC 2009, UCD, June 10-11 th
[4] M. Moradian, and H. Oraizi, “Optimum design of microstrip parallel coupled-line band-pass filters for multi-spuriouspass-band suppression,” IET Microw. Antennas Propag., Vol.1, No.2, April 2007, pp.488-495. [4] M. Moradian, and H. Oraizi, “Optimum design of microstrip parallel coupled-line band-pass filters for multi-spuriouspass-band suppression,” IET Microw. Antennas Propag., Vol.1, No.2, April 2007, pp.488-495.
[5] R. N. Bates, “Design of microstrip spur-line band-stop filter”, IEEE J. Microwave, Optics and Acoustics, vol. 1, no. 6, pp.209-214, Nov. 1977. [5] R. N. Bates, “Design of microstrip spur-line band-stop filter”, IEEE J. Microwave, Optics and Acoustics, vol. 1, no. 6, pp. 209-214, Nov. 1977.
[6] Jae-Gon Lee, and Jeong-Hae Lee, “Parallel Coupled Bandstop Filter Using Double Negative Coupled Transmission Line,” IEEE Microwaveand Wireless Components Letters, VOL.17, NO.4, April 2007, pp.283-285. [6] Jae-Gon Lee, and Jeong-Hae Lee, “Parallel Coupled Bandstop Filter Using Double Negative Coupled Transmission Line,” IEEE Microwave and Wireless Components Letters, VOL.17, NO.4, April 2007, pp.283-285.
[7] Bao-Xin Wang, Qing-Yuan Wang, and Rong-Jun Liu, “A Band-Stop Filter with Far Spurious Stop Bands,” Art of Miniaturizing RF and Microwave Passive Components, 2008. IMWS 2008. IEEE MTT-S International Microwave Workshop Series on, December 2008, pp.164-166. [7] Bao-Xin Wang, Qing-Yuan Wang, and Rong-Jun Liu, “A Band-Stop Filter with Far Spurious Stop Bands,” Art of Miniaturizing RF and Microwave Passive Components, 2008. IMWS 2008. IEEE MTT-S International Microwave Workshop Series on, December 2008, pp. 164-166.
[8] Yan-Guo Hu Xu、Jan-Dong Tseng，“Analysis and applications of parallel connected transmission line structure”，National Symposium on Telecommunications，pp.1163-1168，2004. (in Chinese) [8] Yan-Guo Hu Xu, Jan-Dong Tseng, "Analysis and applications of parallel connected transmission line structure", National Symposium on Telecommunications, pp. 1163-1168, 2004. (in Chinese)
[9] C. Nguyen and K. Chang, "On the analysis and design of spurline bandstop filters," IEEE Trans. Microwave TheoryTech., Vol. 33, No. 12, pp. 1416-1421, Dec. 1985. [9] C. Nguyen and K. Chang, "On the analysis and design of spurline bandstop filters," IEEE Trans. Microwave TheoryTech., Vol. 33, No. 12, pp. 1416-1421, Dec. 1985.
[10] C. Nguyen and K. Chang: "Analysis and design of spurlinebandstop filters", IEEE International MicrowaveSymposium, pp. 445-448, Jun. 1985. [10] C. Nguyen and K. Chang: "Analysis and design of spurlinebandstop filters", IEEE International Microwave Symposium, pp. 445-448, Jun. 1985.
20‧‧‧第一導電區塊 20‧‧‧First conductive block
21‧‧‧第二導電區塊 21‧‧‧Second conductive block
30‧‧‧第一傳輸線 30‧‧‧First transmission line
40‧‧‧第二傳輸線 40‧‧‧second transmission line
50‧‧‧電路元件 50‧‧‧ circuit components
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| US7256666B2 (en) * | 2002-12-27 | 2007-08-14 | Mitsubishi Denki Kabushiki Kaisha | Band rejection filter with attenuation poles |
| US7321276B2 (en) * | 2005-06-30 | 2008-01-22 | Harris Stratex Networks, Inc. | Independently adjustable combined harmonic rejection filter and power sampler |
| US7336323B2 (en) * | 2005-09-27 | 2008-02-26 | Chemimage Corporation | Liquid crystal filter with tunable rejection band |
| TWI324851B (en) * | 2007-01-04 | 2010-05-11 | Univ Nat Kaohsiung Applied Sci | A universal current-mode filter |
| TWI347029B (en) * | 2008-04-15 | 2011-08-11 | Nat Univ Chung Cheng |
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| US7256666B2 (en) * | 2002-12-27 | 2007-08-14 | Mitsubishi Denki Kabushiki Kaisha | Band rejection filter with attenuation poles |
| US7321276B2 (en) * | 2005-06-30 | 2008-01-22 | Harris Stratex Networks, Inc. | Independently adjustable combined harmonic rejection filter and power sampler |
| US7336323B2 (en) * | 2005-09-27 | 2008-02-26 | Chemimage Corporation | Liquid crystal filter with tunable rejection band |
| TWI324851B (en) * | 2007-01-04 | 2010-05-11 | Univ Nat Kaohsiung Applied Sci | A universal current-mode filter |
| TWI347029B (en) * | 2008-04-15 | 2011-08-11 | Nat Univ Chung Cheng |
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