TWI585571B - Clock signal generation circuit, memory storage device and clock signal generation method - Google Patents
Clock signal generation circuit, memory storage device and clock signal generation method Download PDFInfo
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Description
本發明是有關於一種振盪電路，且特別是有關於一種時脈訊號產生電路、記憶體儲存裝置及時脈訊號產生方法。The present invention relates to an oscillating circuit, and more particularly to a clock signal generating circuit, a memory storage device, and a clock signal generating method.
數位相機、行動電話與MP3播放器在這幾年來的成長十分迅速，使得消費者對儲存媒體的需求也急速增加。由於可複寫式非揮發性記憶體模組（例如，快閃記憶體）具有資料非揮發性、省電、體積小，以及無機械結構等特性，所以非常適合內建於上述所舉例的各種可攜式多媒體裝置中。Digital cameras, mobile phones and MP3 players have grown very rapidly in recent years, and the demand for storage media has increased rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, it is very suitable for various built-in examples. Portable multimedia device.
在電路系統中，普遍設置有振盪電路以提供時脈訊號。其中，電阻(resistor)電容(capacitor)振盪電路(簡稱為RC振盪電路)是較為常見的振盪電路。然而，一般的高頻(例如，頻率高於10兆赫(Mega Hertz, MHz))RC振盪電路產生的時脈訊號之頻率容易受到於環境溫度變化的影響。In circuit systems, an oscillating circuit is generally provided to provide a clock signal. Among them, a resistor (capacitor) oscillation circuit (referred to as an RC oscillation circuit) is a relatively common oscillation circuit. However, the frequency of the clock signal generated by a general high frequency (for example, a frequency higher than 10 MHz (Mega Hertz, MHz)) RC oscillator circuit is susceptible to changes in ambient temperature.
本發明提供一種時脈訊號產生電路、記憶體儲存裝置及時脈訊號產生方法，可降低溫度變化對時脈訊號的影響。The invention provides a clock signal generation circuit and a memory storage device timely pulse signal generation method, which can reduce the influence of temperature changes on the clock signal.
本發明的一範例實施例提供一種時脈訊號產生電路，其包括阻抗電路、振盪電路及控制電路。所述阻抗電路提供參考阻抗。所述振盪電路響應於第二時脈訊號產生第一時脈訊號。所述控制電路經由第一路徑耦接至所述阻抗電路並且經由第二路徑耦接至所述振盪電路。此外，所述控制電路維持第一路徑上的第一電氣特性與所述第二路徑上的第二電氣特性於一預定條件以調整所述第一時脈訊號的頻率。An exemplary embodiment of the present invention provides a clock signal generating circuit including an impedance circuit, an oscillating circuit, and a control circuit. The impedance circuit provides a reference impedance. The oscillating circuit generates a first clock signal in response to the second clock signal. The control circuit is coupled to the impedance circuit via a first path and to the oscillating circuit via a second path. Moreover, the control circuit maintains the first electrical characteristic on the first path and the second electrical characteristic on the second path to a predetermined condition to adjust the frequency of the first clock signal.
在本發明的一範例實施例中，所述第一電氣特性包括第一電流值，所述第二電氣特性包括第二電流值，所述控制電路維持所述第一路徑上的所述第一電氣特性與所述第二路徑上的所述第二電氣特性於所述預定條件的操作包括：維持所述第一電流值與所述第二電流值於第一條件。In an exemplary embodiment of the invention, the first electrical characteristic includes a first current value, the second electrical characteristic includes a second current value, and the control circuit maintains the first on the first path The operation of the electrical characteristic and the second electrical characteristic on the second path to the predetermined condition includes maintaining the first current value and the second current value at a first condition.
在本發明的一範例實施例中，所述第一電氣特性更包括第一電壓值，所述第二電氣特性更包括第二電壓值，所述控制電路維持所述第一路徑上的所述第一電氣特性與所述第二路徑上的所述第二電氣特性於所述預定條件的操作更包括：維持所述阻抗電路於所述第一路徑上的所述第一電壓值與所述振盪電路於所述第二路徑上的所述第二電壓值於第二條件。In an exemplary embodiment of the present invention, the first electrical characteristic further includes a first voltage value, the second electrical characteristic further includes a second voltage value, and the control circuit maintains the The operation of the first electrical characteristic and the second electrical characteristic on the second path to the predetermined condition further comprises: maintaining the first voltage value of the impedance circuit on the first path and the The second voltage value of the oscillating circuit on the second path is in a second condition.
在本發明的一範例實施例中，所述控制電路包括第一控制電路與第二控制電路。所述第一控制電路具有第一輸入端、第二輸入端及輸出端，其中所述第一輸入端耦接至所述第一路徑，所述第二輸入端耦接至所述第二路徑。所述第二控制電路具有輸入端、第一輸出端及第二輸出端，其中所述第二控制電路的所述輸入端耦接至所述第一控制電路的所述輸出端，所述第一輸出端耦接至所述第一路徑，所述第二輸出端耦接至所述第二路徑。In an exemplary embodiment of the invention, the control circuit includes a first control circuit and a second control circuit. The first control circuit has a first input end, a second input end, and an output end, wherein the first input end is coupled to the first path, and the second input end is coupled to the second path . The second control circuit has an input end, a first output end, and a second output end, wherein the input end of the second control circuit is coupled to the output end of the first control circuit, An output is coupled to the first path, and a second output is coupled to the second path.
在本發明的一範例實施例中，所述第一控制電路包括運算放大器，其接收所述第一輸入端的第一電壓與所述第二輸入端的第二電壓並於所述輸出端輸出控制電壓。In an exemplary embodiment of the present invention, the first control circuit includes an operational amplifier that receives a first voltage of the first input terminal and a second voltage of the second input terminal, and outputs a control voltage at the output terminal. .
在本發明的一範例實施例中，所述第二控制電路包括第一電晶體與第二電晶體。所述第一電晶體從所述第一控制電路的所述輸出端接收控制電壓並於所述第一輸出端輸出第一電流。所述第二電晶體從所述第一控制電路的所述輸出端接收所述控制電壓並於所述第二輸出端輸出第二電流。In an exemplary embodiment of the invention, the second control circuit includes a first transistor and a second transistor. The first transistor receives a control voltage from the output of the first control circuit and outputs a first current at the first output. The second transistor receives the control voltage from the output of the first control circuit and outputs a second current at the second output.
在本發明的一範例實施例中，所述第二電晶體的第二總數多於所述第一電晶體的第一總數。所述第二總數與所述第一總數的比值正相關於所述第二電流的第二電流值與所述第一電流的第一電流值的比值。In an exemplary embodiment of the invention, the second total number of the second transistors is greater than the first total number of the first transistors. The ratio of the second total to the first total is positively related to a ratio of a second current value of the second current to a first current value of the first current.
在本發明的一範例實施例中，所述振盪電路包括彼此串接的多個充/放電電路，所述多個充/放電電路的至少其中之一響應於所述第二電氣特性調整所述第一時脈訊號的所述頻率。In an exemplary embodiment of the present invention, the oscillating circuit includes a plurality of charge/discharge circuits connected in series with each other, at least one of the plurality of charge/discharge circuits adjusting the responsive to the second electrical characteristic The frequency of the first clock signal.
在本發明的一範例實施例中，所述多個充/放電電路中的第一充/放電電路包括第一開關單元、第二開關單元及充/放電單元，其中所述第一開關單元的第一端耦接所述第二路徑，所述第二開關單元的第一端耦接所述第一開關單元的第二端，所述充/放電單元的第一端耦接所述第一開關單元的所述第二端與所述第二開關單元的所述第一端。In an exemplary embodiment of the present invention, the first charging/discharging circuit of the plurality of charging/discharging circuits includes a first switching unit, a second switching unit, and a charging/discharging unit, wherein the first switching unit The first end is coupled to the second path, the first end of the second switch unit is coupled to the second end of the first switch unit, and the first end of the charge/discharge unit is coupled to the first end The second end of the switch unit and the first end of the second switch unit.
在本發明的一範例實施例中，所述第一開關單元與所述第二開關單元用以控制所述充/放電單元的充/放電路徑。In an exemplary embodiment of the invention, the first switching unit and the second switching unit are configured to control a charging/discharging path of the charging/discharging unit.
本發明的另一範例實施例提供一種記憶體儲存裝置，其包括連接介面單元、可複寫式非揮發性記憶體模組及記憶體控制電路單元。所述連接介面單元用以耦接至主機系統。所述記憶體控制電路單元耦接至所述連接介面單元與所述可複寫式非揮發性記憶體模組，其中所述連接介面單元包括時脈訊號產生電路，其中所述時脈訊號產生電路維持第一路徑上的第一電氣特性與第二路徑上的第二電氣特性於預定條件以調整所述時脈訊號產生電路產生的第一時脈訊號的頻率，其中所述第一路徑耦接至阻抗電路，其提供參考阻抗，其中所述第二路徑耦接至振盪電路，其響應於第二時脈訊號產生所述第一時脈訊號。Another exemplary embodiment of the present invention provides a memory storage device including a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to be coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the connection interface unit comprises a clock signal generation circuit, wherein the clock signal generation circuit Maintaining a first electrical characteristic on the first path and a second electrical characteristic on the second path to a predetermined condition to adjust a frequency of the first clock signal generated by the clock signal generating circuit, wherein the first path is coupled The impedance circuit provides a reference impedance, wherein the second path is coupled to the oscillating circuit, and the first clock signal is generated in response to the second clock signal.
在本發明的一範例實施例中，所述時脈訊號產生電路包括所述阻抗電路、所述振盪電路及控制電路，其中所述控制電路經由所述第一路徑耦接至所述阻抗電路並且經由所述第二路徑耦接至所述振盪電路，其中所述第一路徑上的所述第一電氣特性與所述第二路徑上的所述第二電氣特性是由所述控制電路所控制。In an exemplary embodiment of the present invention, the clock signal generating circuit includes the impedance circuit, the oscillating circuit, and a control circuit, wherein the control circuit is coupled to the impedance circuit via the first path and Coupling to the oscillating circuit via the second path, wherein the first electrical characteristic on the first path and the second electrical characteristic on the second path are controlled by the control circuit .
在本發明的一範例實施例中，所述時脈訊號產生電路包括第一控制電路與第二控制電路。所述第一控制電路具有第一輸入端、第二輸入端及輸出端，其中所述第一輸入端耦接至所述第一路徑，所述第二輸入端耦接至所述第二路徑。所述第二控制電路具有輸入端、第一輸出端及第二輸出端，其中所述輸入端耦接至所述第一控制電路的所述輸出端，所述第一輸出端耦接至所述第一路徑，所述第二輸出端耦接至所述第二路徑。In an exemplary embodiment of the invention, the clock signal generating circuit includes a first control circuit and a second control circuit. The first control circuit has a first input end, a second input end, and an output end, wherein the first input end is coupled to the first path, and the second input end is coupled to the second path . The second control circuit has an input end, a first output end, and a second output end, wherein the input end is coupled to the output end of the first control circuit, and the first output end is coupled to the The first path is coupled to the second path.
本發明的另一範例實施例提供一種時脈訊號產生方法，其用於記憶體儲存裝置，所述時脈訊號產生方法包括：由所述記憶體儲存裝置的阻抗電路提供參考阻抗；由所述記憶體儲存裝置的振盪電路響應於第二時脈訊號產生第一時脈訊號；維持所述記憶體儲存裝置中耦接至所述阻抗電路的第一路徑上的第一電氣特性與所述記憶體儲存裝置中耦接至所述振盪電路的第二路徑上的第二電氣特性於預定條件；以及根據所述第一電氣特性與所述第二電氣特性調整所述第一時脈訊號的頻率。Another exemplary embodiment of the present invention provides a clock signal generating method for a memory storage device, wherein the clock signal generating method includes: providing a reference impedance by an impedance circuit of the memory storage device; An oscillating circuit of the memory storage device generates a first clock signal in response to the second clock signal; maintaining a first electrical characteristic and the memory on the first path of the memory storage device coupled to the impedance circuit a second electrical characteristic coupled to the second path of the oscillating circuit in the bulk storage device is at a predetermined condition; and adjusting a frequency of the first clock signal according to the first electrical characteristic and the second electrical characteristic .
在本發明的一範例實施例中，所述第一電氣特性包括第一電流值，所述第二電氣特性包括第二電流值，而維持所述第一路徑上的所述第一電氣特性與所述第二路徑上的所述第二電氣特性於所述預定條件的步驟包括：維持所述第一電流值與所述第二電流值於第一條件。In an exemplary embodiment of the invention, the first electrical characteristic includes a first current value, and the second electrical characteristic includes a second current value while maintaining the first electrical characteristic on the first path The step of the second electrical characteristic on the second path to the predetermined condition includes maintaining the first current value and the second current value at a first condition.
在本發明的一範例實施例中，所述第一電氣特性更包括第一電壓值，所述第二電氣特性更包括第二電壓值，而維持所述第一路徑上的所述第一電氣特性與所述第二路徑上的所述第二電氣特性於所述預定條件的步驟更包括：維持所述阻抗電路於所述第一路徑上的所述第一電壓值與所述振盪電路於所述第二路徑上的所述第二電壓值於第二條件。In an exemplary embodiment of the present invention, the first electrical characteristic further includes a first voltage value, and the second electrical characteristic further includes a second voltage value while maintaining the first electrical on the first path The step of: the characteristic and the second electrical characteristic on the second path to the predetermined condition further comprises: maintaining the first voltage value of the impedance circuit on the first path and the oscillating circuit The second voltage value on the second path is in a second condition.
基於上述，所述控制電路經由第一路徑耦接用於提供參考阻抗的阻抗電路並經由第二路徑耦接用於產生第一時脈訊號的振盪電路。此外，所述控制電路會將所述第一路徑上的第一電氣特性與所述第二路徑上的第二電氣特性維持於一預定條件，藉以調整第一時脈訊號的頻率。在這樣的電路架構下，溫度變化對振盪電路產生的時脈訊號之影響可被減少。Based on the above, the control circuit is coupled to the impedance circuit for providing the reference impedance via the first path and coupled to the oscillating circuit for generating the first clock signal via the second path. In addition, the control circuit maintains the first electrical characteristic on the first path and the second electrical characteristic on the second path to a predetermined condition, thereby adjusting the frequency of the first clock signal. Under such a circuit architecture, the effect of temperature changes on the clock signal generated by the oscillating circuit can be reduced.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
以下提出多個範例實施例來說明本發明，然而本發明不僅限於所例示的多個範例實施例。又範例實施例之間也允許有適當的結合。在本案說明書全文(包括申請專利範圍)中所使用的「耦接」一詞可指任何直接或間接的連接手段。舉例而言，若文中描述第一裝置耦接於第二裝置，則應該被解釋成該第一裝置可以直接連接於該第二裝置，或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。此外，「訊號」一詞可指至少一電流、電壓、電荷、溫度、資料、或任何其他一或多個訊號。The following examples are presented to illustrate the invention, but the invention is not limited to the illustrated exemplary embodiments. Also suitable combinations are allowed between the example embodiments. The term "coupled" as used throughout the specification (including the scope of the patent application) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other one or more signals.
圖1是根據本發明的一範例實施例所繪示的時脈訊號產生電路的示意圖。FIG. 1 is a schematic diagram of a clock signal generating circuit according to an exemplary embodiment of the invention.
請參照圖1，時脈訊號產生電路10包括阻抗電路11、振盪電路12及控制電路13。控制電路13經由路徑141(亦稱為第一路徑)耦接至阻抗電路11並經由路徑142(亦稱為第二路徑)耦接至振盪電路12，其中路徑141與路徑142皆為導電路徑，且路徑141與路徑142上還可耦接其他未繪示於圖1中的電子元件。阻抗電路11用以提供一個參考阻抗(impedance)。振盪電路12用以接收時脈訊號CLK_2(亦稱為第二時脈訊號)並響應於時脈訊號CLK_2產生另一時脈訊號CLK_1(亦稱為第一時脈訊號)。控制電路13會控制路徑141上的電氣特性(亦稱為第一電氣特性)與路徑142上的電氣特性(亦稱為第二電氣特性)以調整時脈訊號CLK_1的頻率。例如，控制電路13會將第一電氣特性與第二電氣特性維持於一預定條件，藉以將時脈訊號CLK_1的頻率維持於一預定頻率。此外，所述時脈訊號CLK_1的頻率指的是時脈訊號CLK_1中脈波(pulse)的振盪頻率。Referring to FIG. 1, the clock signal generating circuit 10 includes an impedance circuit 11, an oscillating circuit 12, and a control circuit 13. The control circuit 13 is coupled to the impedance circuit 11 via a path 141 (also referred to as a first path) and coupled to the oscillating circuit 12 via a path 142 (also referred to as a second path), wherein the path 141 and the path 142 are both conductive paths. The path 141 and the path 142 may also be coupled to other electronic components not shown in FIG. The impedance circuit 11 is used to provide a reference impedance. The oscillating circuit 12 is configured to receive the clock signal CLK_2 (also referred to as the second clock signal) and generate another clock signal CLK_1 (also referred to as the first clock signal) in response to the clock signal CLK_2. The control circuit 13 controls the electrical characteristics (also referred to as the first electrical characteristic) on the path 141 and the electrical characteristics (also referred to as the second electrical characteristic) on the path 142 to adjust the frequency of the clock signal CLK_1. For example, the control circuit 13 maintains the first electrical characteristic and the second electrical characteristic at a predetermined condition to maintain the frequency of the clock signal CLK_1 at a predetermined frequency. In addition, the frequency of the clock signal CLK_1 refers to the oscillation frequency of the pulse in the clock signal CLK_1.
在一範例實施例中，第一電氣特性可為一個電流值(亦稱為第一電流值)，並且第二電氣特性亦可為一個電流值(亦稱為第二電流值)。例如，第一電流值為路徑141上的電流(亦稱為第一電流)的電流值，而第二電流值為路徑142上的電流(亦稱為第二電流)的電流值。例如，第一電流是控制電路13經由路徑141提供至阻抗電路11，而第二電流是控制電路13經由路徑142提供至振盪電路12。In an exemplary embodiment, the first electrical characteristic may be a current value (also referred to as a first current value), and the second electrical characteristic may also be a current value (also referred to as a second current value). For example, the first current value is the current value of the current on path 141 (also referred to as the first current) and the second current value is the current value of the current on path 142 (also referred to as the second current). For example, the first current is supplied to the impedance circuit 11 via the path 141 and the second current is supplied to the oscillating circuit 12 via the path 142.
在一範例實施例中，控制電路13會將第一電流值與第二電流值維持於一個特定條件(亦稱為第一條件)以調整時脈訊號CLK_1的頻率。例如，控制電路13可將第二電流值調整為第一電流值的N倍(或者，將第一電流值調整為第二電流值的1/N倍)，其中N為大於1的數值。例如，N可為大於1的整數。對應於不同的N值，提供至振盪電路12的第二電氣特性(例如，第二電流值)也會相應地改變，使得振盪電路12產生的時脈訊號CLK_1之頻率會相應地調整。In an exemplary embodiment, the control circuit 13 maintains the first current value and the second current value under a specific condition (also referred to as a first condition) to adjust the frequency of the clock signal CLK_1. For example, the control circuit 13 may adjust the second current value to N times the first current value (or adjust the first current value to 1/N times the second current value), where N is a value greater than one. For example, N can be an integer greater than one. Corresponding to different values of N, the second electrical characteristic (e.g., the second current value) supplied to the oscillating circuit 12 is also changed accordingly, so that the frequency of the clock signal CLK_1 generated by the oscillating circuit 12 is adjusted accordingly.
在一範例實施例中，第一電氣特性亦可為一個電壓值(亦稱為第一電壓值)，並且第二電氣特性亦可為一個電壓值(亦稱為第二電壓值)。例如，第一電壓值為阻抗電路11在路徑141上的電壓(亦稱為第一電壓)的電壓值，而第二電壓值為振盪電路12在路徑142上的電壓(亦稱為第二電壓)的電壓值。In an exemplary embodiment, the first electrical characteristic may also be a voltage value (also referred to as a first voltage value), and the second electrical characteristic may also be a voltage value (also referred to as a second voltage value). For example, the first voltage value is the voltage value of the voltage of the impedance circuit 11 on the path 141 (also referred to as the first voltage), and the second voltage value is the voltage of the oscillation circuit 12 on the path 142 (also referred to as the second voltage). The voltage value.
在一範例實施例中，控制電路13會將第一電壓值與第二電壓值維持於另一個特定條件(亦稱為第二條件)以調整時脈訊號CLK_1的頻率。例如，控制電路13可將第二電壓值調整為與第一電壓值相等或為第一電壓值的一預定倍數，或者將第一電壓值調整為與第二電壓值相等或為第二電壓值的一預定倍數。透過將第一電壓值與第二電壓值維持於第二條件，阻抗電路11所提供的參考阻抗即可用來調節振盪電路12產生的時脈訊號CLK_1的頻率。In an exemplary embodiment, the control circuit 13 maintains the first voltage value and the second voltage value under another specific condition (also referred to as a second condition) to adjust the frequency of the clock signal CLK_1. For example, the control circuit 13 may adjust the second voltage value to be equal to the first voltage value or a predetermined multiple of the first voltage value, or adjust the first voltage value to be equal to the second voltage value or to be the second voltage value. a predetermined multiple. By maintaining the first voltage value and the second voltage value in the second condition, the reference impedance provided by the impedance circuit 11 can be used to adjust the frequency of the clock signal CLK_1 generated by the oscillation circuit 12.
須注意的是，上述關於電氣特性(例如，電流及/或電壓)的控制操作可以是連續(或漸進式)的。例如，在上述將第一電流值與第二電流值維持於第一條件的操作中，第一電流值與第二電流值皆可能是變動的，而控制電路13會持續地嘗試將第一電流值與第二電流值維持於第一條件。類似地，在上述將第一電壓值與第二電壓值維持於第二條件的操作中，第一電壓值與第二電壓值亦可能是變動的，而控制電路13也會持續地嘗試將第一電壓值與第二電壓值維持於第二條件。在一範例實施例中，上述關於電氣特性的控制操作亦可以視為是對於電氣特性的鎖定操作。It should be noted that the above described control operations regarding electrical characteristics (eg, current and/or voltage) may be continuous (or progressive). For example, in the above operation of maintaining the first current value and the second current value in the first condition, both the first current value and the second current value may be varied, and the control circuit 13 continuously tries to apply the first current. The value and the second current value are maintained at the first condition. Similarly, in the above operation of maintaining the first voltage value and the second voltage value in the second condition, the first voltage value and the second voltage value may also be varied, and the control circuit 13 will continuously try to A voltage value and a second voltage value are maintained in the second condition. In an exemplary embodiment, the above control operation regarding electrical characteristics can also be considered as a locking operation for electrical characteristics.
圖2是根據本發明的另一範例實施例所繪示的時脈訊號產生電路的示意圖。FIG. 2 is a schematic diagram of a clock signal generating circuit according to another exemplary embodiment of the present invention.
請參照圖2，阻抗電路11包括阻抗元件21，其用以提供路徑141上的參考阻抗，其中此阻抗元件21可為一具有電阻值、電抗值或兩者皆有之元件。控制電路13包含控制電路(亦稱為第二控制電路)22與控制電路(亦稱為第一控制電路)23。控制電路22主要是用於將路徑141上的第一電流值與路徑142上的第二電流值維持於上述第一條件。控制電路23主要是用於將路徑141上的第一電壓值與路徑142上的第二電壓值維持於上述第二條件。在本範例實施例中，控制電路22對於電流的控制以及控制電路23對於電壓的控制是會相互影響的。然而，在另一範例實施例中，控制電路22與控制電路23亦可以是獨立運作的，而不會彼此影響。Referring to FIG. 2, the impedance circuit 11 includes an impedance element 21 for providing a reference impedance on the path 141. The impedance element 21 can be an element having a resistance value, a reactance value, or both. The control circuit 13 includes a control circuit (also referred to as a second control circuit) 22 and a control circuit (also referred to as a first control circuit) 23. The control circuit 22 is primarily for maintaining the first current value on the path 141 and the second current value on the path 142 at the first condition described above. Control circuit 23 is primarily used to maintain the first voltage value on path 141 and the second voltage value on path 142 at the second condition described above. In the present exemplary embodiment, the control of the current by the control circuit 22 and the control of the voltage by the control circuit 23 affect each other. However, in another exemplary embodiment, the control circuit 22 and the control circuit 23 may also operate independently without affecting each other.
在本範例實施例中，控制電路22具有輸出端(亦稱為第一輸出端)221、輸出端(亦稱為第二輸出端)222及輸入端223。控制電路23具有輸入端(亦稱為第一輸入端)231、輸入端(亦稱為第二輸入端)232及輸出端233。控制電路23的輸出端233耦接至控制電路22的輸入端223。控制電路23的輸入端231與控制電路22的輸出端221皆耦接至路徑141。控制電路23的輸入端232與控制電路22的輸出端222皆耦接至路徑142。In the present exemplary embodiment, the control circuit 22 has an output (also referred to as a first output) 221, an output (also referred to as a second output) 222, and an input 223. The control circuit 23 has an input (also referred to as a first input) 231, an input (also referred to as a second input) 232, and an output 233. The output 233 of the control circuit 23 is coupled to the input 223 of the control circuit 22. Both the input 231 of the control circuit 23 and the output 221 of the control circuit 22 are coupled to the path 141. Both the input 232 of the control circuit 23 and the output 222 of the control circuit 22 are coupled to the path 142.
在本範例實施例中，響應於輸入端231的第一電壓與輸入端232的第二電壓，控制電路23會從輸出端233輸出控制電壓至控制電路22的輸入端223。響應於輸入端223的控制電壓，控制電路22會從輸出端221輸出第一電流至路徑141並且從輸出端222輸出第二電流至路徑142。第一電流會經由路徑141流向阻抗元件21，而第二電流會經由路徑142流向振盪電路12中的充/放電電路24~26。In the present exemplary embodiment, in response to the first voltage of input 231 and the second voltage of input 232, control circuit 23 outputs a control voltage from output 233 to input 223 of control circuit 22. In response to the control voltage at input 223, control circuit 22 outputs a first current from output 221 to path 141 and a second current from output 222 to path 142. The first current flows to the impedance element 21 via the path 141, and the second current flows to the charge/discharge circuits 24-26 in the oscillating circuit 12 via the path 142.
在本範例實施例中，振盪電路12包含彼此串接的充/放電電路24~26，其串接方式如圖2所示。充/放電電路24用以接收時脈訊號CLK_2。經過充/放電電路24~26執行連續的充/放電操作之後，充/放電電路26會產生時脈訊號CLK_1。須注意的是，充/放電電路24~26的至少其中之一會響應於路徑142上的電氣特性(即，第二電氣特性)來調整時脈訊號CLK_1的頻率。例如，當路徑142上的電流值(即，第二電流值)上升時，充/放電電路24~26會根據上升的電流值來增加時脈訊號CLK_1的頻率。或者，當路徑142上的電流值下降時，充/放電電路24~26會根據下降的電流值來減少時脈訊號CLK_1的頻率。In the present exemplary embodiment, the oscillating circuit 12 includes charging/discharging circuits 24-26 connected in series with each other, as shown in FIG. The charging/discharging circuit 24 is configured to receive the clock signal CLK_2. After the charge/discharge circuits 24 to 26 perform continuous charge/discharge operations, the charge/discharge circuit 26 generates the clock signal CLK_1. It should be noted that at least one of the charge/discharge circuits 24-26 will adjust the frequency of the clock signal CLK_1 in response to the electrical characteristics (ie, the second electrical characteristic) on the path 142. For example, when the current value (ie, the second current value) on the path 142 rises, the charge/discharge circuits 24-26 increase the frequency of the clock signal CLK_1 according to the rising current value. Alternatively, when the current value on the path 142 decreases, the charge/discharge circuits 24 to 26 reduce the frequency of the clock signal CLK_1 according to the decreased current value.
須注意的是，雖然圖2所示的振盪電路12中彼此串接的充/放電電路的總數為3個，然而，在其他未提及的範例實施例中，振盪電路12中彼此串接的充/放電電路的總數還可以是5個、7個、9個或更多，只要可以產生所需的時脈訊號CLK_1即可。It should be noted that although the total number of charge/discharge circuits connected in series to each other in the oscillating circuit 12 shown in FIG. 2 is three, in other unmentioned exemplary embodiments, the oscillating circuits 12 are connected in series with each other. The total number of charge/discharge circuits may also be five, seven, nine or more as long as the desired clock signal CLK_1 can be generated.
在本範例實施例中，振盪電路12中彼此串接的充/放電電路中的第一者(例如，充/放電電路24)會從振盪電路12中彼此串接的充/放電電路中的最後一者(例如，充/放電電路26)接收時脈訊號CLK_1作為輸入的時脈訊號CLK_2。須注意的是，在另一範例實施例中，充/放電電路24的輸入端與充/放電電路26的輸出端之間還可以耦接其他未提及的電子元件。In the present exemplary embodiment, the first one of the charge/discharge circuits serially connected to each other in the oscillation circuit 12 (for example, the charge/discharge circuit 24) may be the last of the charge/discharge circuits serially connected to each other from the oscillation circuit 12. One (eg, charge/discharge circuit 26) receives clock signal CLK_1 as the input clock signal CLK_2. It should be noted that in another exemplary embodiment, other unmentioned electronic components may be coupled between the input end of the charging/discharging circuit 24 and the output end of the charging/discharging circuit 26.
圖3是根據本發明的另一範例實施例所繪示的時脈訊號產生電路的示意圖。FIG. 3 is a schematic diagram of a clock signal generating circuit according to another exemplary embodiment of the present invention.
請參照圖3，阻抗電路11包含至少一個阻抗單元R1，其提供上述參考阻抗。例如，阻抗電路11可包含至少一個電阻。控制電路22包括電晶體(亦稱為第一電晶體)PM1與電晶體(亦稱為第二電晶體)PM2。例如，電晶體PM1與PM2皆為P型金屬氧化物半導體場效電晶體(P-type Metal-Oxide-Semiconductor Field-Effect Transistor, PMOS)。電晶體PM1用以提供第一電流至路徑141。電晶體PM2用以提供第二電流至路徑142。控制電路23包括運算放大器OPA，其耦接至電晶體PM1與PM2。Referring to FIG. 3, the impedance circuit 11 includes at least one impedance unit R1 that provides the above reference impedance. For example, the impedance circuit 11 can include at least one resistor. The control circuit 22 includes a transistor (also referred to as a first transistor) PM1 and a transistor (also referred to as a second transistor) PM2. For example, the transistors PM1 and PM2 are both P-type Metal-Oxide-Semiconductor Field-Effect Transistors (PMOS). The transistor PM1 is used to provide a first current to the path 141. The transistor PM2 is used to provide a second current to the path 142. The control circuit 23 includes an operational amplifier OPA coupled to the transistors PM1 and PM2.
運算放大器OPA會接收路徑141上的第一電壓與路徑142上的第二電壓並輸出控制電壓至電晶體PM1與PM2。響應於運算放大器OPA輸出的控制電壓，電晶體PM1與電晶體PM2會被導通並且分別輸出具有第一電流值的第一電流與具有第二電流值的第二電流。此外，運算放大器OPA會使路徑141上的第一電壓之第一電壓值與路徑142上的第二電壓之第二電壓值相互逼近(或者使第一電壓值與第二電壓值的比值維持在一預設值)。須注意的是，雖然圖3僅呈現出一個電晶體PM1與一個電晶體PM2，然而，實際上電晶體PM1與PM2的總數皆可以是多個。The operational amplifier OPA receives the first voltage on path 141 and the second voltage on path 142 and outputs a control voltage to transistors PM1 and PM2. In response to the control voltage output by the operational amplifier OPA, the transistor PM1 and the transistor PM2 are turned on and respectively output a first current having a first current value and a second current having a second current value. In addition, the operational amplifier OPA maintains a first voltage value of the first voltage on the path 141 and a second voltage value of the second voltage on the path 142 to each other (or maintains a ratio of the first voltage value to the second voltage value at a preset value). It should be noted that although FIG. 3 only shows one transistor PM1 and one transistor PM2, in reality, the total number of transistors PM1 and PM2 may be plural.
在一範例實施例中，電晶體PM2的總數(亦稱為第二總數)會多於電晶體PM1的總數(亦稱為第一總數)。第二總數與第一總數的比值會正相關於路徑142上的第二電流值與路徑141上的第一電流值的比值。例如，若電晶體PM2的總數為電晶體PM1之總數的N倍(即，第二總數與第一總數的比值為N)，則路徑142上的第二電流值也約為路徑141上的第一電流值的N倍。換言之，藉由在控制電路22中配置(或導通)特定數量的電晶體PM1與PM2，路徑142上的電氣特性(即，第二電氣特性)可相應被決定。In an exemplary embodiment, the total number of transistors PM2 (also referred to as the second total) may be greater than the total number of transistors PM1 (also referred to as the first total). The ratio of the second total to the first total will be positively related to the ratio of the second current value on path 142 to the first current value on path 141. For example, if the total number of transistors PM2 is N times the total number of transistors PM1 (ie, the ratio of the second total to the first total is N), then the second current value on path 142 is also approximately the same on path 141. N times the value of a current. In other words, by configuring (or turning on) a particular number of transistors PM1 and PM2 in control circuit 22, the electrical characteristics (i.e., the second electrical characteristic) on path 142 can be determined accordingly.
在圖3的範例實施例中，振盪電路12亦稱為切換電容式環型振盪器。以下以振盪電路12中的充/放電電路24作為範例進行說明，而充/放電電路25與26具有相同或相似於充/放電電路24的電路結構。In the exemplary embodiment of FIG. 3, the oscillating circuit 12 is also referred to as a switched capacitor ring oscillator. Hereinafter, the charging/discharging circuit 24 in the oscillation circuit 12 will be described as an example, and the charging/discharging circuits 25 and 26 have the same or similar circuit configuration as the charging/discharging circuit 24.
請參照圖3，充/放電電路24包括開關單元(亦稱為第一開關單元)31、開關單元(亦稱為第二開關單元)31及充/放電單元33。例如，開關單元31包含至少一電晶體PM3，開關單元32包含至少一電晶體PM4，並且充/放電單元33包含至少一個電容單元C1。電晶體PM3與PM4皆例如為P型金屬氧化物半導體場效電晶體。此外，在另一範例實施例中，所述開關單元亦可為其他類型的開關元件，而不限於P型金屬氧化物半導體場效電晶體。Referring to FIG. 3, the charge/discharge circuit 24 includes a switch unit (also referred to as a first switch unit) 31, a switch unit (also referred to as a second switch unit) 31, and a charge/discharge unit 33. For example, the switching unit 31 includes at least one transistor PM3, the switching unit 32 includes at least one transistor PM4, and the charging/discharging unit 33 includes at least one capacitor unit C1. Both of the transistors PM3 and PM4 are, for example, P-type metal oxide semiconductor field effect transistors. In addition, in another exemplary embodiment, the switching unit may also be other types of switching elements, and is not limited to a P-type metal oxide semiconductor field effect transistor.
在本範例實施例中，開關單元31的第一端(例如，電晶體PM3的源極)耦接至路徑142。開關單元31的第二端(例如，電晶體PM3的汲極)耦接至開關單元32的第一端(例如，電晶體PM4的汲極)。充/放電單元33的第一端耦接至開關單元31的第二端與開關單元32的第一端。此外，開關單元32的第二端與充/放電單元33的第二端皆耦接至參考電壓(或接地電壓)。In the present exemplary embodiment, the first end of the switching unit 31 (eg, the source of the transistor PM3) is coupled to the path 142. The second end of the switching unit 31 (eg, the drain of the transistor PM3) is coupled to the first end of the switching unit 32 (eg, the drain of the transistor PM4). The first end of the charging/discharging unit 33 is coupled to the second end of the switching unit 31 and the first end of the switching unit 32. In addition, the second end of the switching unit 32 and the second end of the charging/discharging unit 33 are both coupled to a reference voltage (or a ground voltage).
在本範例實施例中，開關單元31與開關單元32用以控制充/放電單元33的充/放電路徑。例如，當開關單元31關閉而開關單元32開啟時，充/放電單元33會使用路徑142上的電流(即，第二電流)來充電。或者，當開關單元31開啟而開關單元32關閉時，充/放電單元33會放電。In the present exemplary embodiment, the switching unit 31 and the switching unit 32 are used to control the charging/discharging path of the charging/discharging unit 33. For example, when the switching unit 31 is turned off and the switching unit 32 is turned on, the charging/discharging unit 33 charges using the current on the path 142 (ie, the second current). Alternatively, when the switching unit 31 is turned on and the switching unit 32 is turned off, the charging/discharging unit 33 is discharged.
圖4A與圖4B是根據本發明的一範例實施例所繪示的充/放電路徑的示意圖。4A and 4B are schematic diagrams of charge/discharge paths according to an exemplary embodiment of the invention.
請參照圖4A，在本範例實施例中，電晶體PM3可等效為開關單元41，並且電晶體PM4可等效為開關單元42。響應於時脈訊號CLK_2的電壓低V L，電晶體PM3會被導通(即，開關單元41被關閉)並且電晶體PM4不會被導通(即，開關單元42被開啟)。此時，路徑142上的電流(即，第二電流)會沿著充電路徑401對電容單元C1進行充電。充電後，電容單元C1的第一端會處於電壓高V H。 Referring to FIG. 4A, in the present exemplary embodiment, the transistor PM3 may be equivalent to the switching unit 41, and the transistor PM4 may be equivalent to the switching unit 42. In response to the voltage of the clock signal CLK_2 being low V L , the transistor PM3 is turned on (ie, the switching unit 41 is turned off) and the transistor PM4 is not turned on (ie, the switching unit 42 is turned on). At this time, the current on the path 142 (ie, the second current) charges the capacitor unit C1 along the charging path 401. After charging, the first end of the capacitor unit C1 will be at a high voltage V H .
請參照圖4B，響應於時脈訊號CLK_2的電壓高V H，電晶體PM3不會被導通(即，開關單元41被開啟)並且電晶體PM4會被導通(即，開關單元42被關閉)。此時，電容單元C1會沿著放電路徑402進行放電。放電後，電容單元C1的第一端從電壓高V H變為電壓低V L。 Referring to Figure 4B, the response to a clock signal CLK_2 higher voltage V H, the transistor PM3 is not turned on (i.e., the switching unit 41 is turned on) and the transistor PM4 is turned on (i.e., the switching unit 42 is turned off). At this time, the capacitor unit C1 is discharged along the discharge path 402. After discharging, the first end of the capacitor unit C1 changes from a voltage high V H to a voltage low V L .
換言之，響應於充/放電電路24的輸入端(即，時脈訊號CLK_2)處於電壓低，充/放電電路24的輸出端會處於電壓高，充/放電電路25的輸出端會處於電壓低，並且充/放電電路26的輸出端(即，時脈訊號CLK_1)會處於電壓高。然後，響應於充/放電電路24的輸入端(即，時脈訊號CLK_2)處於電壓高，充/放電電路24的輸出端會處於電壓低，充/放電電路25的輸出端會處於電壓高，並且充/放電電路26的輸出端(即，時脈訊號CLK_1)會處於電壓低。因此，具有多個脈波的時脈訊號CLK_1即可被輸出。In other words, in response to the input of the charging/discharging circuit 24 (ie, the clock signal CLK_2) being at a low voltage, the output of the charging/discharging circuit 24 is at a high voltage, and the output of the charging/discharging circuit 25 is at a low voltage. And the output of the charging/discharging circuit 26 (i.e., the clock signal CLK_1) is at a high voltage. Then, in response to the input terminal of the charging/discharging circuit 24 (ie, the clock signal CLK_2) being at a high voltage, the output of the charging/discharging circuit 24 is at a low voltage, and the output of the charging/discharging circuit 25 is at a high voltage. And the output of the charge/discharge circuit 26 (i.e., the clock signal CLK_1) is at a low voltage. Therefore, the clock signal CLK_1 having a plurality of pulse waves can be output.
此外，當路徑142上的第二電流值上升時，振盪電路12中至少部分充/放電單元(例如，充/放電單元33)的充/放電效率會被提高，從而時脈訊號CLK_1的頻率會增加。反之，當路徑142上的第二電流值下降時，振盪電路12中至少部分充/放電單元的充/放電效率會被降低，從而時脈訊號CLK_1的頻率會減少。藉此，即便振盪電路12中的至少部分開關單元(或，電晶體)之切換頻率受到溫度變化影響，透過阻抗電路11在路徑141上提供的參考阻抗以及控制電路13對於電氣特性的控制(例如，電壓與電流的維持或鎖定)，路徑142上的第二電氣特性(例如，第二電流值)可自動地被調整，從而時脈訊號CLK_1的頻率可被維持在特定頻率。In addition, when the second current value on the path 142 rises, the charging/discharging efficiency of at least a portion of the charging/discharging unit (for example, the charging/discharging unit 33) in the oscillation circuit 12 is increased, so that the frequency of the clock signal CLK_1 is increased. increase. Conversely, when the second current value on the path 142 decreases, the charging/discharging efficiency of at least a portion of the charging/discharging unit in the oscillating circuit 12 is lowered, so that the frequency of the clock signal CLK_1 is reduced. Thereby, even if the switching frequency of at least part of the switching unit (or transistor) in the oscillating circuit 12 is affected by the temperature change, the reference impedance provided by the impedance circuit 11 on the path 141 and the control of the electrical characteristics of the control circuit 13 (for example) The voltage and current are maintained or locked. The second electrical characteristic (eg, the second current value) on path 142 can be automatically adjusted so that the frequency of clock signal CLK_1 can be maintained at a particular frequency.
圖5是根據本發明的一範例實施例所繪示的時脈訊號產生電路的等效電路示意圖。FIG. 5 is an equivalent circuit diagram of a clock signal generating circuit according to an exemplary embodiment of the invention.
請參照圖5，n1表示控制電路53中電晶體PM1的總數(即，第一總數)。n2表示控制電路53中電晶體PM2的總數(即，第二總數)。v1表示路徑141上的電壓值(即，第一電壓值)。v2表示路徑142上的電壓值(即，第二電壓值)。i1表示路徑141上的電流值(即，第一電流值)。i2表示路徑142上的電流值(即，第二電流值)。f表示振盪電路52產生的時脈訊號CLK_1的頻率，其可等效為振盪電路52中用來切換充/放電路徑之開關單元的切換頻率。C表示振盪電路52中某一充/放電單元的電容值。R表示阻抗電路51提供的參考阻抗值。假設n2與n1的比值是N(即，n2/n1=N)，以下方程式(1)~(4)可被推導。Referring to FIG. 5, n1 represents the total number of transistors PM1 (ie, the first total number) in the control circuit 53. N2 represents the total number of transistors PM2 in the control circuit 53 (i.e., the second total number). V1 represents the voltage value on the path 141 (ie, the first voltage value). V2 represents the voltage value on the path 142 (ie, the second voltage value). I1 represents the current value on the path 141 (ie, the first current value). I2 represents the current value on the path 142 (ie, the second current value). f represents the frequency of the clock signal CLK_1 generated by the oscillation circuit 52, which is equivalent to the switching frequency of the switching unit of the oscillation circuit 52 for switching the charge/discharge path. C represents the capacitance value of a certain charge/discharge unit in the oscillation circuit 52. R represents the reference impedance value supplied from the impedance circuit 51. Assuming that the ratio of n2 to n1 is N (ie, n2/n1=N), the following equations (1) to (4) can be derived.
i1=v1/R (1)I1=v1/R (1)
i2=C×v2×f (2)I2=C×v2×f (2)
由於v1=v2，可推導出方程式(3):Since v1=v2, equation (3) can be derived:
i2=N×i1 (3)I2=N×i1 (3)
綜合方程式(1)~(3)，可獲得方程式(4):By combining equations (1) to (3), equation (4) can be obtained:
f=N/(R×C) (4)f=N/(R×C) (4)
根據方程式(4)，振盪電路53中開關單元之切換頻率並沒有影響到時脈訊號CLK_1的頻率。因此，即便環境溫度發生變化而影響到振盪電路53中開關單元之切換效率，振盪電路53仍可以持續產生具有穩定頻率的時脈訊號CLK_1。According to the equation (4), the switching frequency of the switching unit in the oscillation circuit 53 does not affect the frequency of the clock signal CLK_1. Therefore, even if the ambient temperature changes to affect the switching efficiency of the switching unit in the oscillation circuit 53, the oscillation circuit 53 can continue to generate the clock signal CLK_1 having a stable frequency.
須注意的是，根據方程式(4)，振盪電路52產生的時脈訊號CLK_1的頻率f會受到N、C及R的影響。因此，透過設定N(即，控制電路53中電晶體PM1之總數與電晶體PM2之總數的比值)、C(即，振盪電路52中某一充/放電單元的電容值)及R(阻抗電路51提供的參考阻抗值)，振盪電路52產生的時脈訊號CLK_1的頻率f可線性地被決定。It should be noted that, according to equation (4), the frequency f of the clock signal CLK_1 generated by the oscillating circuit 52 is affected by N, C, and R. Therefore, by setting N (that is, the ratio of the total number of the transistors PM1 in the control circuit 53 to the total number of the transistors PM2), C (that is, the capacitance value of a certain charge/discharge unit in the oscillation circuit 52) and R (impedance circuit) The reference impedance value provided by 51), the frequency f of the clock signal CLK_1 generated by the oscillation circuit 52 can be linearly determined.
在一範例實施例中，電晶體PM1之總數與電晶體PM2之總數皆是固定的且皆被導通，以輸出第一電流與第二電流。然而，在另一範例實施例中，電晶體PM1及/或電晶體PM2中部分的電晶體不會被導通。此時，第一電流會由電晶體PM1中被導通者輸出，並且第二電流會由電晶體PM2中被導通者輸出。藉此，上述參數N(即，電晶體PM1中被導通者之總數與電晶體PM2中被導通者之總數的比值)即可以動態地被調整。此外，參數R與C也可以動態地被調整。In an exemplary embodiment, the total number of transistors PM1 and the total number of transistors PM2 are both fixed and turned on to output the first current and the second current. However, in another exemplary embodiment, a portion of the transistors in the transistor PM1 and/or the transistor PM2 are not turned on. At this time, the first current is outputted by the conductive person in the transistor PM1, and the second current is outputted by the conductive person in the transistor PM2. Thereby, the above parameter N (i.e., the ratio of the total number of conductive persons in the transistor PM1 to the total number of conductive persons in the transistor PM2) can be dynamically adjusted. In addition, the parameters R and C can also be dynamically adjusted.
圖6是根據本發明的一範例實施例所繪示的控制電路的示意圖。FIG. 6 is a schematic diagram of a control circuit according to an exemplary embodiment of the invention.
請參照圖6，在本範例實施例中，控制電路63更包括多個開關單元SW(1)~SW(M)，其分別串接在運算放大器OPA的輸出端與電晶體PM2(1)~PM2(M)之間。當要將n2與n1的比值設定為N時，開關單元SW(1)~SW(N)會被關閉(或導通)，並且開關單元SW(N+1)~SW(M)會被開啟(或不導通)，如圖6所示。藉此，電晶體PM2(1)~PM2(N)可接收到來自運算放大器OPA的控制電壓並對應地輸出第二電流至路徑142。換言之，控制電路63可動態地或自動地調整開關單元SW(1)~SW(M)中被關閉(或導通)者的數量，從而改變時脈訊號CLK_1的頻率。此外，圖6的開關機制亦可以套用至對電晶體PM1中導通者的數量控制，在此便不贅述。Referring to FIG. 6, in the exemplary embodiment, the control circuit 63 further includes a plurality of switch units SW(1)~SW(M) connected in series with the output terminal of the operational amplifier OPA and the transistor PM2(1)~ Between PM2(M). When the ratio of n2 to n1 is to be set to N, the switching units SW(1) to SW(N) are turned off (or turned on), and the switching units SW(N+1)~SW(M) are turned on ( Or not, as shown in Figure 6. Thereby, the transistors PM2(1) to PM2(N) can receive the control voltage from the operational amplifier OPA and correspondingly output the second current to the path 142. In other words, the control circuit 63 can dynamically or automatically adjust the number of turned off (or turned on) of the switching units SW(1) to SW(M), thereby changing the frequency of the clock signal CLK_1. In addition, the switching mechanism of FIG. 6 can also be applied to the number control of the conductive person in the transistor PM1, which will not be described here.
一般來說，時脈訊號產生電路10可設置於任意電子裝置中，以提供其操作所需的時脈訊號。須注意的是，在一範例實施例中，時脈訊號產生電路10是被設置於記憶體儲存裝置中，以提供時脈訊號給記憶體儲存裝置使用。例如，記憶體儲存裝置(亦稱，記憶體儲存系統)包括可複寫式非揮發性記憶體模組(rewritable non-volatile memory module)與控制器(亦稱，控制電路)。通常記憶體儲存裝置是與主機系統一起使用，以使主機系統可將資料寫入至記憶體儲存裝置或從記憶體儲存裝置中讀取資料。In general, the clock signal generating circuit 10 can be disposed in any electronic device to provide a clock signal required for its operation. It should be noted that, in an exemplary embodiment, the clock signal generating circuit 10 is disposed in the memory storage device to provide a clock signal to the memory storage device. For example, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). Typically, the memory storage device is used with a host system to enable the host system to write data to or read data from the memory storage device.
圖7是根據本發明的一範例實施例所繪示的主機系統、記憶體儲存裝置及輸入/輸出(I/O)裝置的示意圖。圖8是根據本發明的另一範例實施例所繪示的主機系統、記憶體儲存裝置及I/O裝置的示意圖。FIG. 7 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 8 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention.
請參照圖7與圖8，主機系統711一般包括處理器7111、隨機存取記憶體(random access memory, RAM)7112、唯讀記憶體(read only memory, ROM)7113及資料傳輸介面7114。處理器7111、隨機存取記憶體7112、唯讀記憶體7113及資料傳輸介面7114皆耦接至系統匯流排(system bus)7110。Referring to FIG. 7 and FIG. 8 , the host system 711 generally includes a processor 7111, a random access memory (RAM) 7112, a read only memory (ROM) 7113, and a data transmission interface 7114. The processor 7111, the random access memory 7112, the read-only memory 7113, and the data transmission interface 7114 are all coupled to a system bus 7110.
在本範例實施例中，主機系統711是透過資料傳輸介面7114與記憶體儲存裝置710耦接。例如，主機系統711可經由資料傳輸介面7114將資料儲存至記憶體儲存裝置710或從記憶體儲存裝置710中讀取資料。此外，主機系統711是透過系統匯流排110與I/O裝置12耦接。例如，主機系統711可經由系統匯流排110將輸出訊號傳送至I/O裝置712或從I/O裝置712接收輸入訊號。In the exemplary embodiment, the host system 711 is coupled to the memory storage device 710 through the data transmission interface 7114. For example, the host system 711 can store data to or read data from the memory storage device 710 via the data transfer interface 7114. In addition, the host system 711 is coupled to the I/O device 12 through the system bus bar 110. For example, host system 711 can transmit output signals to or receive input signals from I/O device 712 via system bus.
在本範例實施例中，處理器7111、隨機存取記憶體7112、唯讀記憶體7113及資料傳輸介面7114可設置在主機系統711的主機板820上。資料傳輸介面7114的數目可以是一或多個。透過資料傳輸介面7114，主機板820可以經由有線或無線方式耦接至記憶體儲存裝置710。記憶體儲存裝置710可例如是隨身碟8201、記憶卡8202、固態硬碟(Solid State Drive, SSD)8203或無線記憶體儲存裝置8204。無線記憶體儲存裝置8204可例如是近距離無線通訊(Near Field Communication, NFC)記憶體儲存裝置、無線傳真(WiFi)記憶體儲存裝置、藍牙(Bluetooth)記憶體儲存裝置或低功耗藍牙記憶體儲存裝置(例如，iBeacon)等以各式無線通訊技術為基礎的記憶體儲存裝置。此外，主機板820也可以透過系統匯流排7110耦接至全球定位系統(Global Positioning System, GPS)模組8205、網路介面卡8206、無線傳輸裝置8207、鍵盤8208、螢幕8209、喇叭8210等各式I/O裝置。例如，在一範例實施例中，主機板820可透過無線傳輸裝置8207存取無線記憶體儲存裝置8204。In the exemplary embodiment, the processor 7111, the random access memory 7112, the read-only memory 7113, and the data transmission interface 7114 may be disposed on the motherboard 820 of the host system 711. The number of data transmission interfaces 7114 may be one or more. The motherboard 820 can be coupled to the memory storage device 710 via a data transmission interface 7114 via a wired or wireless connection. The memory storage device 710 can be, for example, a flash drive 8201, a memory card 8202, a solid state drive (SSD) 8203, or a wireless memory storage device 8204. The wireless memory storage device 8204 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory. A memory storage device based on various wireless communication technologies, such as a storage device (for example, iBeacon). In addition, the motherboard 820 can also be coupled to the Global Positioning System (GPS) module 8205, the network interface card 8206, the wireless transmission device 8207, the keyboard 8208, the screen 8209, the speaker 8210, and the like through the system bus 7110. I/O device. For example, in an exemplary embodiment, the motherboard 820 can access the wireless memory storage device 8204 via the wireless transmission device 8207.
在一範例實施例中，所提及的主機系統為可實質地與記憶體儲存裝置配合以儲存資料的任意系統。雖然在上述範例實施例中，主機系統是以電腦系統來作說明，然而，圖9是根據本發明的另一範例實施例所繪示的主機系統與記憶體儲存裝置的示意圖。請參照圖9，在另一範例實施例中，主機系統931也可以是數位相機、攝影機、通訊裝置、音訊播放器、視訊播放器或平板電腦等系統，而記憶體儲存裝置930可為其所使用的安全數位(Secure Digital, SD)卡932、小型快閃(Compact Flash, CF)卡933或嵌入式儲存裝置934等各式非揮發性記憶體儲存裝置。嵌入式儲存裝置934包括嵌入式多媒體卡(embedded Multi Media Card, eMMC)9341及/或嵌入式多晶片封裝(embedded Multi Chip Package, eMCP)儲存裝置9342等各類型將記憶體模組直接耦接於主機系統的基板上的嵌入式儲存裝置。In an exemplary embodiment, the host system referred to is any system that can substantially cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is illustrated by a computer system, FIG. 9 is a schematic diagram of the host system and the memory storage device according to another exemplary embodiment of the present invention. Referring to FIG. 9, in another exemplary embodiment, the host system 931 can also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 930 can be used for Various non-volatile memory storage devices such as a Secure Digital (SD) card 932, a Compact Flash (CF) card 933, or an embedded storage device 934 are used. The embedded storage device 934 includes an embedded multimedia card (eMMC) 9341 and/or an embedded multi-chip package (eMCP) storage device 9342, and the like, directly coupling the memory module to the memory module. An embedded storage device on the base of the host system.
圖10是根據本發明的一範例實施例所繪示的記憶體儲存裝置的概要方塊圖。FIG. 10 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.
請參照圖10，記憶體儲存裝置710包括連接介面單元1002、記憶體控制電路單元1004與可複寫式非揮發性記憶體模組1006。Referring to FIG. 10, the memory storage device 710 includes a connection interface unit 1002, a memory control circuit unit 1004, and a rewritable non-volatile memory module 1006.
連接介面單元1002用以將記憶體儲存裝置710耦接至主機系統711。在本範例實施例中，連接介面單元1002是相容於序列先進附件(Serial Advanced Technology Attachment, SATA)標準。然而，必須瞭解的是，本發明不限於此，連接介面單元1002亦可以是符合並列先進附件(Parallel Advanced Technology Attachment, PATA)標準、電氣和電子工程師協會(Institute of Electrical and Electronic Engineers, IEEE)1394標準、高速周邊零件連接介面(Peripheral Component Interconnect Express, PCI Express)標準、通用序列匯流排(Universal Serial Bus, USB)標準、SD介面標準、超高速一代(Ultra High Speed-I, UHS-I)介面標準、超高速二代(Ultra High Speed-II, UHS-II)介面標準、記憶棒(Memory Stick, MS)介面標準、MCP介面標準、MMC介面標準、eMMC介面標準、通用快閃記憶體(Universal Flash Storage, UFS)介面標準、eMCP介面標準、CF介面標準、整合式驅動電子介面(Integrated Device Electronics, IDE)標準或其他適合的標準。連接介面單元1002可與記憶體控制電路單元1004封裝在一個晶片中，或者連接介面單元1002是佈設於一包含記憶體控制電路單元1004之晶片外。The connection interface unit 1002 is configured to couple the memory storage device 710 to the host system 711. In the present exemplary embodiment, the connection interface unit 1002 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 1002 may also be a Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394. Standard, high-speed Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface Standard, Ultra High Speed II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal flash memory (Universal) Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 1002 can be packaged in a wafer with the memory control circuit unit 1004, or the connection interface unit 1002 can be disposed outside a wafer including the memory control circuit unit 1004.
記憶體控制電路單元1004用以執行以硬體型式或韌體型式實作的多個邏輯閘或控制指令並且根據主機系統711的指令在可複寫式非揮發性記憶體模組1006中進行資料的寫入、讀取與抹除等運作。The memory control circuit unit 1004 is configured to execute a plurality of logic gates or control commands implemented in a hard type or a firmware type and perform data in the rewritable non-volatile memory module 1006 according to an instruction of the host system 711. Write, read, and erase operations.
可複寫式非揮發性記憶體模組1006是耦接至記憶體控制電路單元1004並且用以儲存主機系統711所寫入之資料。可複寫式非揮發性記憶體模組1006可以是單階記憶胞(Single Level Cell, SLC)NAND型快閃記憶體模組(即，一個記憶胞中可儲存1個位元的快閃記憶體模組)、多階記憶胞(Multi Level Cell, MLC)NAND型快閃記憶體模組(即，一個記憶胞中可儲存2個位元的快閃記憶體模組)、複數階記憶胞(Triple Level Cell，TLC)NAND型快閃記憶體模組(即，一個記憶胞中可儲存3個位元的快閃記憶體模組)、其他快閃記憶體模組或其他具有相同特性的記憶體模組。The rewritable non-volatile memory module 1006 is coupled to the memory control circuit unit 1004 and used to store data written by the host system 711. The rewritable non-volatile memory module 1006 can be a single-level memory cell (SLC) NAND-type flash memory module (ie, one memory cell can store one bit of flash memory). Module), Multi Level Cell (MLC) NAND flash memory module (ie, a flash memory module that can store 2 bits in a memory cell), and complex memory cells ( Triple Level Cell, TLC) NAND flash memory module (ie, a flash memory module that can store 3 bits in a memory cell), other flash memory modules, or other memory with the same characteristics Body module.
在一範例實施例中，時脈訊號產生電路10是配置在連接介面單元1002中，以提供用來對來自主機系統711之資料訊號進行取樣或產生欲傳輸至主機系統711之資料訊號的時脈訊號CLK_1。In an exemplary embodiment, the clock signal generating circuit 10 is disposed in the connection interface unit 1002 to provide a clock for sampling data signals from the host system 711 or generating data signals to be transmitted to the host system 711. Signal CLK_1.
圖11是根據本發明的一範例實施例所繪示的連接介面單元的示意圖。FIG. 11 is a schematic diagram of a connection interface unit according to an exemplary embodiment of the invention.
請參照圖11，連接介面單元1002包括時脈訊號產生電路1100與取樣電路1102。時脈訊號產生電路1100具有與時脈訊號產生電路10相同或相似的電路結構。時脈訊號產生電路1100會產生時脈訊號CLK_1。取樣電路1102會從時脈訊號產生電路1100接收時脈訊號CLK_1並從主機系統711接收資料訊號DATA_1。然後，取樣電路1102會基於時脈訊號CLK_1來對資料訊號DATA_1進行取樣並輸出取樣資料DATA_2。例如，取樣電路1102可直接使用時脈訊號CLK_1來取樣資料訊號DATA_1。或者，取樣電路1102也可以根據時脈訊號CLK_1來產生具有不同相位的至少一時脈訊號並使用此至少一時脈訊號來取樣資料訊號DATA_1。Referring to FIG. 11 , the connection interface unit 1002 includes a clock signal generation circuit 1100 and a sampling circuit 1102 . The clock signal generating circuit 1100 has the same or similar circuit configuration as the clock signal generating circuit 10. The clock signal generating circuit 1100 generates a clock signal CLK_1. The sampling circuit 1102 receives the clock signal CLK_1 from the clock signal generating circuit 1100 and receives the data signal DATA_1 from the host system 711. Then, the sampling circuit 1102 samples the data signal DATA_1 based on the clock signal CLK_1 and outputs the sample data DATA_2. For example, the sampling circuit 1102 can directly sample the data signal DATA_1 using the clock signal CLK_1. Alternatively, the sampling circuit 1102 may generate at least one clock signal having different phases according to the clock signal CLK_1 and use the at least one clock signal to sample the data signal DATA_1.
須注意的是，在其他未提及的範例實施例中，時脈訊號產生電路10亦可以例如是配置在記憶體控制電路單元1004或可複寫式非揮發性記憶體模組1006中，本發明不加以限制。It should be noted that, in other exemplary embodiments that are not mentioned, the clock signal generating circuit 10 can also be configured, for example, in the memory control circuit unit 1004 or the rewritable non-volatile memory module 1006. No restrictions.
圖12是根據本發明的一範例實施例所繪示的時脈訊號產生方法的流程圖。FIG. 12 is a flowchart of a method for generating a clock signal according to an exemplary embodiment of the invention.
請參照圖12，在步驟S1201中，由記憶體儲存裝置的阻抗電路提供參考阻抗。在步驟S1202中，由記憶體儲存裝置的振盪電路響應於第二時脈訊號產生第一時脈訊號。在步驟S1203中，維持記憶體儲存裝置中耦接至阻抗電路的第一路徑上的第一電氣特性與記憶體儲存裝置中耦接至振盪電路的第二路徑上的第二電氣特性於一預定條件。在步驟S1204中，根據第一電氣特性與第二電氣特性調整第一時脈訊號的頻率。Referring to FIG. 12, in step S1201, a reference impedance is provided by an impedance circuit of the memory storage device. In step S1202, the first clock signal is generated by the oscillation circuit of the memory storage device in response to the second clock signal. In step S1203, maintaining a first electrical characteristic of the first path of the memory storage device coupled to the impedance circuit and a second electrical characteristic of the second path of the memory storage device coupled to the oscillating circuit for a predetermined condition. In step S1204, the frequency of the first clock signal is adjusted according to the first electrical characteristic and the second electrical characteristic.
然而，圖12中各步驟已詳細說明如上，在此便不再贅述。值得注意的是，圖12中各步驟可以實作為多個程式碼或是電路，本發明不加以限制。此外，圖12的方法可以搭配以上範例實施例使用，也可以單獨使用，本發明不加以限制。However, the steps in Fig. 12 have been described in detail above, and will not be described again here. It should be noted that the steps in FIG. 12 can be implemented as multiple codes or circuits, and the present invention is not limited. In addition, the method of FIG. 12 may be used in combination with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.
綜上所述，本發明的控制電路會經由第一路徑耦接用於提供參考阻抗的阻抗電路並經由第二路徑耦接用於產生第一時脈訊號的振盪電路。藉此，透過將所述第一路徑上的第一電氣特性與所述第二路徑上的第二電氣特性維持於一預定條件，控制電路可調整第一時脈訊號的頻率。特別是，在這樣的電路架構下，溫度變化對振盪電路產生的時脈訊號之影響可被減少。In summary, the control circuit of the present invention couples an impedance circuit for providing a reference impedance via a first path and an oscillating circuit for generating a first clock signal via a second path. Thereby, the control circuit can adjust the frequency of the first clock signal by maintaining the first electrical characteristic on the first path and the second electrical characteristic on the second path at a predetermined condition. In particular, under such a circuit architecture, the effect of temperature changes on the clock signal generated by the oscillating circuit can be reduced.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10、1100‧‧‧時脈訊號產生電路
11、51‧‧‧阻抗電路
12、52‧‧‧振盪電路
13、53、63‧‧‧控制電路
141、142‧‧‧路徑
CLK_1、CLK_2‧‧‧時脈訊號
21‧‧‧阻抗元件
R1‧‧‧阻抗單元
22‧‧‧第二控制電路
221、222、233‧‧‧輸出端
231、232、223‧‧‧輸入端
23‧‧‧第一控制電路
OPA‧‧‧運算放大器
24、25、26‧‧‧充/放電電路
31、32、41、42、SW(1)~SW(M)‧‧‧開關單元
PM1、PM2、PM3、PM4、PM2(1)~PM(M)‧‧‧電晶體
33‧‧‧充/放電單元
C1‧‧‧電容單元
401‧‧‧充電路徑
402‧‧‧放電路徑
710、930‧‧‧記憶體儲存裝置
711、931‧‧‧主機系統
7110‧‧‧系統匯流排
7111‧‧‧處理器
7112‧‧‧隨機存取記憶體
7113‧‧‧唯讀記憶體
7114‧‧‧資料傳輸介面
712‧‧‧輸入/輸出(I/O)裝置
820‧‧‧主機板
8201‧‧‧隨身碟
8202‧‧‧記憶卡
8203‧‧‧固態硬碟
8204‧‧‧無線記憶體儲存裝置
8205‧‧‧全球定位系統模組
8206‧‧‧網路介面卡
8207‧‧‧無線傳輸裝置
8208‧‧‧鍵盤
8209‧‧‧螢幕
8210‧‧‧喇叭
932‧‧‧SD卡
933‧‧‧CF卡
934‧‧‧嵌入式儲存裝置
9341‧‧‧嵌入式多媒體卡
9342‧‧‧嵌入式多晶片封裝儲存裝置
1002‧‧‧連接介面單元
1004‧‧‧記憶體控制電路單元
1006‧‧‧可複寫式非揮發性記憶體模組
1102‧‧‧取樣電路
S1201‧‧‧步驟(由記憶體儲存裝置的阻抗電路提供參考阻抗)
S1202‧‧‧步驟(由記憶體儲存裝置的振盪電路響應於第二時脈訊號產生第一時脈訊號)
S1203‧‧‧步驟(維持記憶體儲存裝置中耦接至所述阻抗電路的第一路徑上的第一電氣特性與記憶體儲存裝置中耦接至所述振盪電路的第二路徑上的第二電氣特性於一預定條件)
S1204‧‧‧步驟(根據第一電氣特性與第二電氣特性調整第一時脈訊號的頻率)10, 1100‧‧‧ clock signal generation circuit
11, 51‧‧‧ impedance circuit
12, 52‧‧‧Oscillation circuit
13, 53, ‧ ‧ ‧ control circuit
141, 142‧‧ path
CLK_1, CLK_2‧‧‧ clock signal
21‧‧‧ impedance components
R1‧‧‧impedance unit
22‧‧‧Second control circuit
221, 222, 233‧‧ ‧ output
231, 232, 223‧‧‧ input
23‧‧‧First control circuit
OPA‧‧‧Operational Amplifier
24, 25, 26‧‧‧charge/discharge circuits
31, 32, 41, 42, SW (1) ~ SW (M) ‧ ‧ switch unit
PM1, PM2, PM3, PM4, PM2(1)~PM(M)‧‧‧O crystal
33‧‧‧charge/discharge unit
C1‧‧‧Capacitor unit
401‧‧‧Charging path
402‧‧‧discharge path
710, 930‧‧‧ memory storage device
711, 931‧‧‧ host system
7110‧‧‧System Bus
7111‧‧‧ processor
7112‧‧‧ Random access memory
7113‧‧‧Reading memory
7114‧‧‧Data transmission interface
712‧‧‧Input/Output (I/O) devices
820‧‧‧ motherboard
8201‧‧‧USB
8202‧‧‧ memory card
8203‧‧‧ Solid State Drive
8204‧‧‧Wireless memory storage device
8205‧‧‧Global Positioning System Module
8206‧‧‧Network Interface Card
8207‧‧‧Wireless transmission
8208‧‧‧ keyboard
8209‧‧‧ screen
8210‧‧‧ Speaker
932‧‧‧SD card
933‧‧‧CF card
934‧‧‧Embedded storage device
9341‧‧‧Embedded multimedia card
9342‧‧‧Embedded multi-chip package storage device
1002‧‧‧Connecting interface unit
1004‧‧‧Memory Control Circuit Unit
1006‧‧‧Rewritable non-volatile memory module
1102‧‧‧Sampling circuit
S1201‧‧‧ steps (providing reference impedance from the impedance circuit of the memory storage device)
S1202‧‧‧ steps (the first clock signal is generated by the oscillation circuit of the memory storage device in response to the second clock signal)
S1203. The steps of maintaining a first electrical characteristic coupled to the first path of the impedance circuit in the memory storage device and a second path coupled to the second path of the oscillating circuit in the memory storage device Electrical characteristics under a predetermined condition)
S1204‧‧‧ steps (adjusting the frequency of the first clock signal according to the first electrical characteristic and the second electrical characteristic)
圖1是根據本發明的一範例實施例所繪示的時脈訊號產生電路的示意圖。 圖2是根據本發明的另一範例實施例所繪示的時脈訊號產生電路的示意圖。 圖3是根據本發明的另一範例實施例所繪示的時脈訊號產生電路的示意圖。 圖4A與圖4B是根據本發明的一範例實施例所繪示的充/放電路徑的示意圖。 圖5是根據本發明的一範例實施例所繪示的時脈訊號產生電路的等效電路示意圖。 圖6是根據本發明的一範例實施例所繪示的控制電路的示意圖。 圖7是根據本發明的一範例實施例所繪示的主機系統、記憶體儲存裝置及輸入/輸出(I/O)裝置的示意圖。 圖8是根據本發明的另一範例實施例所繪示的主機系統、記憶體儲存裝置及I/O裝置的示意圖。 圖9是根據本發明的另一範例實施例所繪示的主機系統與記憶體儲存裝置的示意圖。 圖10是根據本發明的一範例實施例所繪示的記憶體儲存裝置的概要方塊圖。 圖11是根據本發明的一範例實施例所繪示的連接介面單元的示意圖。 圖12是根據本發明的一範例實施例所繪示的時脈訊號產生方法的流程圖。FIG. 1 is a schematic diagram of a clock signal generating circuit according to an exemplary embodiment of the invention. FIG. 2 is a schematic diagram of a clock signal generating circuit according to another exemplary embodiment of the present invention. FIG. 3 is a schematic diagram of a clock signal generating circuit according to another exemplary embodiment of the present invention. 4A and 4B are schematic diagrams of charge/discharge paths according to an exemplary embodiment of the invention. FIG. 5 is an equivalent circuit diagram of a clock signal generating circuit according to an exemplary embodiment of the invention. FIG. 6 is a schematic diagram of a control circuit according to an exemplary embodiment of the invention. FIG. 7 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 8 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention. FIG. 9 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. FIG. 10 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention. FIG. 11 is a schematic diagram of a connection interface unit according to an exemplary embodiment of the invention. FIG. 12 is a flowchart of a method for generating a clock signal according to an exemplary embodiment of the invention.
10‧‧‧時脈訊號產生電路 10‧‧‧clock signal generation circuit
11‧‧‧阻抗電路 11‧‧‧impedance circuit
12‧‧‧振盪電路 12‧‧‧Oscillation circuit
13‧‧‧控制電路 13‧‧‧Control circuit
141、142‧‧‧路徑 141, 142‧‧ path
CLK_1、CLK_2‧‧‧時脈訊號 CLK_1, CLK_2‧‧‧ clock signal
Claims (24)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| TW105135862A TWI585571B (en) | 2016-11-04 | 2016-11-04 | Clock signal generation circuit, memory storage device and clock signal generation method |
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| Application Number | Priority Date | Filing Date | Title |
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| TW105135862A TWI585571B (en) | 2016-11-04 | 2016-11-04 | Clock signal generation circuit, memory storage device and clock signal generation method |
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| Publication Number | Publication Date |
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| TWI585571B true TWI585571B (en) | 2017-06-01 |
| TW201818186A TW201818186A (en) | 2018-05-16 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7429898B2 (en) * | 2005-11-09 | 2008-09-30 | Fujifilm Corporation | Clock signal generating circuit, semiconductor integrated circuit and method for controlling a frequency division ratio |
| US20120153999A1 (en) * | 2010-12-17 | 2012-06-21 | Kwan-Dong Kim | Clock signal generation circuit |
| US20120249201A1 (en) * | 2011-03-31 | 2012-10-04 | Hynix Semiconductor Inc. | Clock signal generation circuit |
| TW201624977A (en) * | 2014-09-03 | 2016-07-01 | 微軟技術授權有限責任公司 | Multi-phase clock generation |
| TW201627793A (en) * | 2015-01-20 | 2016-08-01 | 三星電子股份有限公司 | Clock generator with stability during PVT variations and on-chip oscillator having the same |
-
2016
- 2016-11-04 TW TW105135862A patent/TWI585571B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7429898B2 (en) * | 2005-11-09 | 2008-09-30 | Fujifilm Corporation | Clock signal generating circuit, semiconductor integrated circuit and method for controlling a frequency division ratio |
| US20120153999A1 (en) * | 2010-12-17 | 2012-06-21 | Kwan-Dong Kim | Clock signal generation circuit |
| US20120249201A1 (en) * | 2011-03-31 | 2012-10-04 | Hynix Semiconductor Inc. | Clock signal generation circuit |
| TW201624977A (en) * | 2014-09-03 | 2016-07-01 | 微軟技術授權有限責任公司 | Multi-phase clock generation |
| TW201627793A (en) * | 2015-01-20 | 2016-08-01 | 三星電子股份有限公司 | Clock generator with stability during PVT variations and on-chip oscillator having the same |
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| TW201818186A (en) | 2018-05-16 |
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