TWI582601B - Configurable serial interface - Google Patents

Configurable serial interface Download PDF

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TWI582601B
TWI582601B TW102135874A TW102135874A TWI582601B TW I582601 B TWI582601 B TW I582601B TW 102135874 A TW102135874 A TW 102135874A TW 102135874 A TW102135874 A TW 102135874A TW I582601 B TWI582601 B TW I582601B
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voltage
serial
node
input
pin
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TW201428501A (en
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安格柏罕Ｈ
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線性科技股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

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Description

可配置式串列介面 Configurable serial interface

本發明一般而言相關於電子領域，且更詳言之為相關於串列介面。 The present invention is generally related to the field of electronics and, more particularly, to the serial interface.

近年來，存在對於提升積體電路使用彈性的努力，而使積體電路能被使用在不同的系統中。例如，可在複雜的訊號處理系統中使用可配置式串列介面，例如核發給Cassis等人的歐洲專利EP0619548號(「Cassis案」)所示。Cassis案使用模式配置接腳，模式配置接腳在串列周邊介面(SPI)模式中被連接至SPI的晶片選擇訊號(為低態有效)。因此，在接腳為高時，沒有SPI周邊被致動。在Cassis案中，使模式配置接腳浮接或將模式配置接腳連接至地，選擇I2C模式，I2C模式一般稱為「雙線介面(two-wire interface)」，其中存在對於兩個I2C位址的選擇。 In recent years, there has been an effort to improve the flexibility of use of integrated circuits, so that integrated circuits can be used in different systems. For example, a configurable serial interface can be used in a complex signal processing system, such as shown in European Patent EP0619548 ("Cassis") issued to Cassis et al. The Cassis case uses a mode configuration pin that is connected to the SPI chip select signal in the Serial Peripheral Interface (SPI) mode (valid for low). Therefore, when the pin is high, no SPI periphery is actuated. In the case of Cassis, the mode configuration pin is floated or the mode configuration pin is connected to the ground, and the I 2 C mode is selected. The I 2 C mode is generally called a "two-wire interface", where there is The choice of two I 2 C addresses.

在另一範例中，來自Analog Devices公司的AD5161裝置亦具有由配置接腳(亦即在規格表中所稱的DIS)切換的可配置式串列介面。例如，在DIS接腳被連接為低時，串列介面位於SPI模式中。在DIS接腳被連接為高時，串列介面 位於I2C模式中。可使用四個額外串列介面接腳來提供SPI模式中的串列資料輸出(SDO)、串列資料輸入(SDI)、時脈(CLK)以及晶片選擇(/CS)功能性。這些接腳中的三個接腳被使用於I2C模式中，以提供串列資料輸入/輸出(SDA)與串列時脈輸入(SCL)功能性以及位址選擇(AD0)。例如，在I2C模式中，第四個串列介面接腳不具有功能性。總和而言，對可配置式串列介面使用了五個接腳，而這五個接腳僅允許對於兩個I2C位址的選擇。 In another example, the AD5161 device from Analog Devices also has a configurable serial interface that is switched by a configuration pin (ie, a DIS referred to in the specification table). For example, when the DIS pin is tied low, the serial interface is in SPI mode. When the DIS pin is tied high, the serial interface is in I 2 C mode. Four additional serial interface pins can be used to provide serial data output (SDO), serial data input (SDI), clock (CLK), and wafer select (/CS) functionality in SPI mode. Three of these pins are used in I 2 C mode to provide serial data input/output (SDA) and serial clock input (SCL) functionality as well as address selection (AD0). For example, in the I 2 C mode, the fourth serial interface pin is not functional. In summary, five pins are used for the configurable serial interface, and these five pins only allow selection of two I 2 C addresses.

在又另一範例中，由NXP公司製造的PCA9502裝置具有由配置接腳(亦即規格表中所稱的I2C/SPI)切換的可配置式串列介面。在I2C/SPI接腳被連接為低時，串列介面位於SPI模式中。在I2C/SPI接腳被連接為高時，串列介面位於I2C模式中。例如，使用四個額外串列介面接腳以提供SPI模式中的SO、SI、SCLK、/CS功能性。在I2C模式中使用這些接腳以提供SDA與SCL功能性以及兩個位址選擇接腳(例如A0與A1)。總和而言，對可配置式串列介面使用了五個接腳，而藉由將A0與A1連接至各種其他接腳，這五個接腳允許對於十六個I2C模式位址的選擇。 In yet another example, a PCA9502 device manufactured by NXP has a configurable serial interface that is switched by a configuration pin (ie, I 2 C/SPI as referred to in the spec sheet). When the I 2 C/SPI pin is tied low, the serial interface is in SPI mode. When the I 2 C/SPI pin is tied high, the serial interface is in I 2 C mode. For example, four additional serial interface pins are used to provide SO, SI, SCLK, /CS functionality in SPI mode. These pins are used in I 2 C mode to provide SDA and SCL functionality as well as two address select pins (eg, A0 and A1). In summary, five pins are used for the configurable serial interface, and by connecting A0 and A1 to various other pins, these five pins allow selection of sixteen I 2 C mode addresses. .

在連接至一匯流排的裝置由實質上不同的獨立電壓源來供電時，可產生困難(例如引入不相容的邏輯位準)。例如，若周邊裝置為以12V源執行的電壓供應控制器，同時匯流排主控器為由3.3V供應的微控制器或特定應用積體電路(ASIC)，則可產生困難且解決方案需要相當多的電路設計支出。有鑑於此，核發給Cheng的美國專利第7,804,339號討 論這些關於不相容邏輯位準的困難中的一些。 Difficulties can arise (e.g., introducing incompatible logic levels) when the devices connected to a bus are powered by substantially different independent voltage sources. For example, if the peripheral device is a voltage supply controller that is executed with a 12V source, and the busbar master is a microcontroller or an application-specific integrated circuit (ASIC) supplied by 3.3V, it can cause difficulties and the solution needs to be quite More circuit design expenditures. In view of this, U.S. Patent No. 7,804,339 issued to Cheng Some of these difficulties regarding incompatible logic levels.

前述的先前技術作法具有數個缺點。例如在Cassis案中，配置系統在系統電力開啟(power up)可為功能性危害，其中在一短暫時間週期內晶片選擇線可為未定義。再者，Cassis案未提供任何處理不相容匯流排電壓情境的解決方案，在不相容匯流排電壓情境中積體電路具有可配置式串列介面，且可配置式串列介面以與匯流排主控器供應電壓實質上不同的供應電壓來執行。 The foregoing prior art practices have several drawbacks. For example, in the Cassis case, configuring the system to power up the system can be a functional hazard, where the wafer selection line can be undefined for a short period of time. Furthermore, the Cassis case does not provide any solution for dealing with incompatible bus voltage scenarios where the integrated circuit has a configurable serial interface and a configurable serial interface to communicate with the confluence The row masters supply voltages that are supplied at substantially different supply voltages.

對於上文討論的AD5161裝置，即使AD5161裝置中在SDO/SDA接腳上的開集極輸出驅動器可緩解獨立供應電壓情境中的一些議題，但卻花費相當大的成本。例如在SPI配置中，需要外部上拉(pull-up)電阻器(例如，上拉電阻器經受額外的功率消耗，並裝載連接至匯流排的所有裝置的輸出驅動器)。再者，外部上拉電阻器帶來已知存在於I2C通訊中的速度損失(或速度/功率權衡)。因此，此作法僅提供了有缺陷的SPI介面。另外，先前技術(諸如AD5161)的傳統可配置式串列介面浪費了一個接腳以容納I2C模式。此接腳若被用於提升I2C位址數量，則為較佳的。 For the AD5161 device discussed above, even the open collector output driver on the SDO/SDA pin in the AD5161 device can alleviate some of the issues in the independent supply voltage scenario, but at a considerable cost. For example, in an SPI configuration, an external pull-up resistor is required (eg, the pull-up resistor is subject to additional power consumption and loads the output drivers of all devices connected to the busbar). Furthermore, external pull-up resistors introduce speed losses (or speed/power tradeoffs) that are known to exist in I 2 C communication. Therefore, this approach only provides a flawed SPI interface. In addition, the conventional configurable serial interface of prior art (such as the AD5161) wasted a pin to accommodate the I 2 C mode. This pin is preferred if it is used to increase the number of I 2 C addresses.

對於上文討論的PCA9502裝置，PCA9502裝置使用基於將A1與A0接腳以多種方式連接至兩個供應(VDD與VSS)的或串列通訊接腳(SCL/SDA)的任意者的I2C模式位址選擇方案，來提供對於上至十六個I2C位址的選擇。然而在許多應用中，將位址選擇接腳連接至串列通訊接腳，產生潛在的功能性危害。 For the PCA9502 device discussed above, the PCA9502 device uses I 2 C based on any of the two supply (VDD and VSS) or serial communication pins (SCL/SDA) that connect the A1 and A0 pins in multiple ways. A mode address selection scheme to provide a choice of up to sixteen I 2 C addresses. However, in many applications, the address selection pin is connected to the serial communication pin, creating a potential functional hazard.

再者，PCA9502裝置藉由提供全推/拉驅動器級，避免SPI模式中串列輸出減慢。「高」訊號係由裝置的VDD接腳來供應。有鑑於此，PCA9502在SPI模式中可無法在PCA9502的串列輸出上，驅動較PCA9502自身供應電壓VDD高或低的「高」訊號。 Furthermore, the PCA9502 device avoids slowing down the serial output in SPI mode by providing a full push/pull driver stage. The "high" signal is supplied by the VDD pin of the device. In view of this, the PCA9502 cannot drive a "high" signal higher or lower than the PCA9502's own supply voltage VDD on the serial output of the PCA9502 in SPI mode.

AD5161裝置與PCA9502裝置兩者，在他們的串列介面連接至另一裝置(諸如作為匯流排主控器的微控制器或特定應用積體電路(ASIC))，且該另一裝置的供應電壓實質上不同於AD5161或PCA9502各別的供應電壓時，可遭遇到困難。例如，雜訊容忍限度(noise margin)可下降到損害串列匯流排通訊的程度。在PCA9502的供應電壓相當高於此種ASIC的供應電壓時(且若使用在期望最高速度的SPI模式中時)，可在ASIC中致動可造成超量電流與毀滅性閂鎖效應(latch-up)的寄生二極體。 Both the AD5161 device and the PCA9502 device are connected in their serial interface to another device (such as a microcontroller or an application specific integrated circuit (ASIC) as a busbar master), and the supply voltage of the other device Difficulties can be encountered when it is substantially different from the individual supply voltages of the AD5161 or PCA9502. For example, the noise margin can be reduced to the extent that the serial bus communication is compromised. When the supply voltage of the PCA9502 is quite higher than the supply voltage of this ASIC (and if used in the SPI mode where the highest speed is expected), actuation in the ASIC can cause excessive current and catastrophic latch-up (latch- Up) Parasitic diodes.

因此，如演示於AD5161與PCA9502中之實施可配置式串列介面的現存做法，具有許多缺點。有鑑於此，Cheng案甚至不嘗試使用可配置式串列介面。更確切而言，Cheng案甚至強調在此種系統中不相容電力供應所帶來的挑戰。 Therefore, the existing practice of implementing a configurable serial interface as demonstrated in the AD5161 and PCA9502 has a number of disadvantages. In view of this, the Cheng case does not even try to use the configurable serial interface. Rather, the Cheng case even highlights the challenges posed by incompatible power supplies in such systems.

有鑑於上文所述，將期望具有完全與I2C及SPI串列匯流排系統相容的可配置式串列介面。亦將期望具有容納數種積體電路供應電壓組合的可配置式串列介面。亦將期望具有容納可連接至串列匯流排之其他裝置的可能實質上不同的供應電壓，同時保持最佳的雜訊抗擾性(noise immunity)。將進一步期望具有使用低接腳數並在數種配置(例如諸如SPI 與I2C)中有效率地使用所有這些接腳的可配置式串列介面。所期望的這些特徵對於具有用於數位電路、但由高於數位電路之供應電壓供電的串列介面的積體電路(IC)而言特別有用。例如，一些應用包含不同的智慧型切換模式電力供應IC、電力與能源計量IC、以及供應監測或排序IC。 In view of the above, it would be desirable to have a configurable serial interface that is fully compatible with the I 2 C and SPI serial bus systems. It would also be desirable to have a configurable serial interface that accommodates a combination of several integrated circuit supply voltages. It would also be desirable to have a potentially substantially different supply voltage that accommodates other devices that can be connected to the tandem busbar while maintaining optimal noise immunity. It would be further desirable to have a configurable serial interface that uses low pin counts and efficiently uses all of these pins in several configurations, such as, for example, SPI and I 2 C. These desired features are particularly useful for integrated circuits (ICs) having a serial interface for digital circuitry but powered by supply voltages above the digital circuitry. For example, some applications include different smart switching mode power supply ICs, power and energy metering ICs, and supply monitoring or sequencing ICs.

從一個態樣來看，本發明提供一種可配置式串列介面，可配置式串列介面包含：配置節點；一或更多個輸入節點，一或更多個輸入節點之每一者耦接至各別的串列匯流排；一或更多個輸出節點，一或更多個輸出節點之每一者耦接至各別的串列匯流排；至少一個驅動器，至少一個驅動器經配置以驅動各別的輸出節點；電壓偵測電路，電壓偵測電路耦接至配置節點，且電壓偵測電路可操作以偵測在配置節點處的電壓，其中：可配置式串列介面可操作以基於在配置節點處偵測到的電壓來設定串列匯流排作業模式；且在至少一個串列匯流排作業模式中，配置節點經配置為模式選擇輸入以及對於輸出節點之至少一個驅動器的電力源兩者。 In one aspect, the present invention provides a configurable serial interface, the configurable serial interface comprising: a configuration node; one or more input nodes, each of the one or more input nodes coupled To each of the serial bus bars; one or more output nodes, each of the one or more output nodes being coupled to a respective serial bus; at least one driver, at least one driver configured to drive a respective output node; a voltage detection circuit, the voltage detection circuit is coupled to the configuration node, and the voltage detection circuit is operable to detect a voltage at the configuration node, wherein: the configurable serial interface is operable to be based Setting a voltage detected at the node to set the serial bus operation mode; and in at least one serial bus operation mode, the configuration node is configured as a mode selection input and a power source for at least one driver of the output node By.

從另一個態樣來看，本發明提供一種配置串列介面的方法，串列介面具有至少一個輸出驅動器，方法包含以下步驟：決定在配置接腳處的電壓；在所決定的電壓位於第一範圍內時，進入第一串列匯流排作業模式，第一串列匯流排作業模式包含：使用在配置接腳處的電壓作為模式選擇輸入；以及使用在配置接腳處的電壓作為對於至少一個輸出驅動器的電力供應；以及在所決定的電壓位於第二範圍內時， 進入第二串列匯流排作業模式中，第二串列匯流排作業模式包含：配置輸出驅動器為開汲極。 Viewed from another aspect, the present invention provides a method of configuring a serial interface, the serial interface having at least one output driver, the method comprising the steps of: determining a voltage at a configuration pin; the first determined voltage is at the first Within the range, entering the first serial bus operation mode, the first serial bus operation mode includes: using the voltage at the configuration pin as a mode selection input; and using the voltage at the configuration pin as at least one Outputting the power supply to the driver; and when the determined voltage is within the second range, In the second serial bus operation mode, the second serial bus operation mode includes: configuring the output driver to be an open drain.

102‧‧‧積體電路 102‧‧‧Integrated circuit

104‧‧‧接地接腳 104‧‧‧ Grounding pin

106‧‧‧電力供應接腳 106‧‧‧Power supply pin

108‧‧‧數位控制電路 108‧‧‧Digital Control Circuit

110‧‧‧串列匯流排驅動器 110‧‧‧Synchronous bus driver

112‧‧‧輸入緩衝器電路 112‧‧‧Input buffer circuit

114‧‧‧配置節點 114‧‧‧Configuration node

116A‧‧‧接腳 116A‧‧‧ pin

118B‧‧‧接腳 118B‧‧‧ feet

120‧‧‧電力供應 120‧‧‧Power supply

122‧‧‧供應電壓 122‧‧‧Supply voltage

109‧‧‧電壓偵測電路 109‧‧‧Voltage detection circuit

126‧‧‧匯流排主控器 126‧‧‧ Busbar master

118C‧‧‧接腳 118C‧‧‧ pins

118D‧‧‧接腳 118D‧‧‧ pins

112B‧‧‧輸入緩衝器電路 112B‧‧‧Input buffer circuit

112C‧‧‧輸入緩衝器電路 112C‧‧‧Input buffer circuit

112D‧‧‧輸入緩衝器電路 112D‧‧‧ input buffer circuit

210‧‧‧電阻器 210‧‧‧Resistors

212‧‧‧電阻器 212‧‧‧Resistors

220‧‧‧跳線 220‧‧‧jumper

224‧‧‧跳線 224‧‧‧jumper

圖式圖示說明性具體實施例。圖式未說明所有的具體實施例。可額外地(或替代地)使用其他具體實施例。可省略可為顯然或非必要的細節，以節省空間或更有效率的說明。可使用額外部件或步驟及/或不使用所有所說明的部件或步驟來實施一些具體實施例。在不同圖式中出現相同的編號時，編號代表相同或類似的部件或步驟。 The drawings illustrate illustrative embodiments. The drawings do not illustrate all of the specific embodiments. Other specific embodiments may be used additionally (or alternatively). Details that may or may not be necessary may be omitted to save space or more efficient instructions. Some specific embodiments may be implemented using additional components or steps and/or without all of the illustrated components or steps. When the same number appears in different figures, the numbers represent the same or similar parts or steps.

第1a圖圖示說明與本發明之具體實施例一致之具有可配置式串列介面的積體電路，可配置式串列介面在第一串列匯流排作業模式中耦接至匯流排主控器。 1a illustrates an integrated circuit having a configurable serial interface consistent with a specific embodiment of the present invention, the configurable serial interface coupled to the bus master in the first serial bus operation mode Device.

第1b圖圖示說明與本發明之具體實施例一致之具有可配置式串列介面的積體電路，可配置式串列介面在第二串列匯流排作業模式中耦接至匯流排主控器。 1b illustrates an integrated circuit having a configurable serial interface consistent with a specific embodiment of the present invention, the configurable serial interface coupled to the bus master in the second serial bus operation mode Device.

第2a圖圖示說明具有四個控制接腳的積體電路，四個控制接腳在與本發明之具體實施例一致之一配置中耦接至匯流排主控器。 Figure 2a illustrates an integrated circuit having four control pins that are coupled to the busbar master in one configuration consistent with embodiments of the present invention.

第2b圖圖示說明具有兩個控制接腳的積體電路，兩個控制接腳在與本發明之具體實施例一致之一配置中耦接至匯流排主控器。 Figure 2b illustrates an integrated circuit having two control pins that are coupled to the busbar master in one configuration consistent with embodiments of the present invention.

第3圖圖示說明與本發明之具體實施例一致之電晶體階層可配置式串列介面。 Figure 3 illustrates a transistor level configurable serial interface consistent with embodiments of the present invention.

在下文的詳細說明中，由示例之方式揭示數種特定的細節，以幫助通透瞭解相關揭示內容。然而，應顯然瞭解可不使用此種細節來實施本發明。在其他實例中，已由相對高的階層說明了習知方法、程序、部件及/或電路系統，而未說明其細節，以避免不必要地遮蔽本發明的態樣。 In the following detailed description, numerous specific details are set forth However, it should be apparent that the invention may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described by a relatively high level, and are not described in detail to avoid unnecessarily obscuring aspects of the present invention.

下文所討論的各種範例，相關於可被配置的串列介面。在一個態樣中，串列介面可藉由以兩或更多種不同的方式連接配置接腳，而容納兩或更多種串列協定。在一些具體實施例中，在配置接腳(CONF)處的電壓被連接至供應輸出驅動器電晶體的內部電力供應線，輸出驅動器電晶體用以驅動「高」邏輯位準至至少一個串列輸出接腳。在其他具體實施例中，配置接腳可為浮接或作為邏輯輸入。 The various examples discussed below are related to the serial interface that can be configured. In one aspect, the serial interface can accommodate two or more serial protocols by connecting the configuration pins in two or more different ways. In some embodiments, the voltage at the configuration pin (CONF) is connected to an internal power supply line that supplies the output driver transistor, and the output driver transistor is used to drive the "high" logic level to at least one of the serial outputs. Pin. In other embodiments, the configuration pins can be floating or as a logic input.

現在詳細參照圖示說明於附加圖式中並於下文討論的範例。第1a圖圖示說明在與本發明之具體實施例一致之配置中的積體電路102。積體電路102具有可容納數種串列通訊協定的可配置式串列介面。例如，積體電路102可被耦接至不同的匯流排主控器電路(由方塊126代表)。可配置式串列介面102包含一或更多個輸入節點(例如118B)，輸入節點之每一者耦接至對應的串列匯流排。一或更多個輸出節點(例如116A)耦接至個別的串列匯流排，每一輸出節點(例如116A)具有各別的輸出驅動器(例如110)。可配置式串列介面102包含配置節點114，配置節點114可同時作為對於串列匯流排作業的模式選擇，以及對於至少一個輸出驅動器110的電力源。電壓偵測電路109經配置以偵測在配置接腳 114(CONF)處的匯流排供應電壓的存在與否。例如，電壓偵測電路109偵測配置接腳處的電壓位準是否位於一或更多個預定電壓範圍內。基於此決定，電壓偵測電路109提供模式訊號至內部數位控制電路108，從而指示要在哪個串列匯流排模式下操作。數位控制電路108基於串列匯流排作業來控制串列匯流排驅動器(例如110)與輸入緩衝器電路(例如112)。下文更詳細討論每一方塊。 Reference will now be made in detail to the accompanying drawings drawings Figure 1a illustrates an integrated circuit 102 in a configuration consistent with a particular embodiment of the present invention. The integrated circuit 102 has a configurable serial interface that can accommodate several serial communication protocols. For example, integrated circuit 102 can be coupled to a different bus master circuit (represented by block 126). The configurable serial interface 102 includes one or more input nodes (e.g., 118B), each of which is coupled to a corresponding serial bus. One or more output nodes (e.g., 116A) are coupled to individual serial busses, each output node (e.g., 116A) having a respective output driver (e.g., 110). The configurable serial interface 102 includes a configuration node 114 that can simultaneously serve as a mode selection for a serial bus operation and a power source for at least one output driver 110. Voltage detection circuit 109 is configured to detect the configuration pin The presence or absence of the bus supply voltage at 114 (CONF). For example, voltage detection circuit 109 detects whether the voltage level at the configuration pin is within one or more predetermined voltage ranges. Based on this determination, voltage detection circuit 109 provides a mode signal to internal digital control circuit 108 to indicate in which serial bus mode to operate. Digital control circuit 108 controls the serial bus driver (e.g., 110) and the input buffer circuit (e.g., 112) based on the serial bus operation. Each block is discussed in more detail below.

在第1a圖的範例中，配置接腳114(CONF)被連接至串列匯流排供應電壓122(例如VDDLOGIC)以選擇第一串列匯流排協定(亦即串列匯流排作業模式)。例如，協定可為SPI，或任何使用在串列輸出或狀態線上之經界定高電壓位準的主動驅動的其他串列匯流排協定。另一方面，第1b圖圖示說明在與本發明之另一具體實施例一致之配置中的積體電路102。在第1b圖的範例中，配置接腳114不被連接至第1a圖配置中的串列匯流排供應電壓。相反的，配置接腳114被連接至相當低的電壓。例如，相當低的電壓可為低電壓接腳(VSS)，如第1b圖所示。配置接腳114(CONF)亦可被連接至相同積體電路的另一接腳，或為浮接。例如，藉由將配置接腳連接至不同的電壓，選擇第二串列協定。在一個範例中，第二串列協定可為在串列輸出或狀態線處僅使用開汲極驅動器(例如諸如在I2C協定中)。 In the example of Figure 1a, the configuration pin 114 (CONF) is connected to the serial bus supply voltage 122 (e.g., VDD LOGIC ) to select the first serial bus protocol (i.e., the serial bus operation mode). For example, the agreement can be an SPI, or any other serial bus protocol that uses active drive with a defined high voltage level on the serial output or status line. On the other hand, Fig. 1b illustrates the integrated circuit 102 in a configuration consistent with another embodiment of the present invention. In the example of Figure 1b, the configuration pin 114 is not connected to the serial bus supply voltage in the configuration of Figure 1a. Conversely, the configuration pin 114 is connected to a relatively low voltage. For example, a relatively low voltage can be a low voltage pin ( Vss ), as shown in Figure 1b. Configuration pin 114 (CONF) can also be connected to another pin of the same integrated circuit, or floating. For example, the second serial protocol is selected by connecting the configuration pins to different voltages. In one example, the second tandem protocol can be to use only open-drain drivers at the serial output or status line (eg, such as in the I 2 C protocol).

獨立於配置接腳114(或除了配置接腳114之外)，可基於所支持的串列匯流排協定(串列匯流排作業模式)，提供複數個串列輸入接腳、串列輸出接腳、或串列匯流排控 制或狀態接腳(例如由串列匯流排輸出接腳116A與串列匯流排輸入接腳118B集合地代表)。例如，電力供應接腳106(例如VDD)與接地接腳104(例如VSS)被提供以供應積體電路102的內部數位邏輯電路108。 Independent of the configuration pin 114 (or in addition to the configuration pin 114), a plurality of serial input pins and serial output pins can be provided based on the supported serial bus protocol (serial bus operation mode). Or a serial bus control or status pin (eg, represented by the tandem bus output pin 116A and the tandem bus input pin 118B collectively). For example, power supply pin 106 (eg, VDD) and ground pin 104 (eg, Vss ) are provided to supply internal digital logic circuit 108 of integrated circuit 102.

在一個具體實施例中，存在經配置以偵測在配置接腳114(CONF)處的匯流排供應電壓存在與否的匯流排供應電壓偵測電路109。匯流排供應電壓偵測電路109亦可提供模式選擇邏輯訊號(MODE)至內部數位控制電路108。在一個具體實施例中，模式選擇訊號具有至少兩個狀態，例如邏輯「低」或邏輯「高」。 In one embodiment, there is a bus supply voltage detection circuit 109 configured to detect the presence or absence of a bus supply voltage at the configuration pin 114 (CONF). The bus supply voltage detecting circuit 109 can also provide a mode selection logic signal (MODE) to the internal digital control circuit 108. In a specific embodiment, the mode selection signal has at least two states, such as a logic "low" or a logic "high."

在一個具體實施例中，提供至少一個輸出驅動器電路110。例如在模式選擇邏輯訊號的第一狀態中，輸出節點116A的驅動器電路110可使用施加至配置接腳144的供應電壓(例如在第1a圖範例中的VDDLOGIC)，以驅動「高」邏輯位準至接腳(例如輸出節點116A)。輸出驅動器電路110可藉由提供低歐姆路徑至低供應接腳104(例如VSS或地)以驅動「低」邏輯位準。 In a specific embodiment, at least one output driver circuit 110 is provided. For example, in the first state of the mode select logic signal, the driver circuit 110 of the output node 116A can use the supply voltage applied to the configuration pin 144 (eg, VDD LOGIC in the example of FIG. 1a) to drive the "high" logic bit. Lead to the pin (eg output node 116A). Output driver circuit 110 can drive a "low" logic level by providing a low ohmic path to low supply pin 104 (eg, VSS or ground).

在一個具體實施例中，積體電路102包含至少一個輸入緩衝器電路112。例如，輸入緩衝器電路112可識別接腳118B處的邏輯位準，並提供對應的邏輯訊號至內部數位控制電路102。 In one embodiment, integrated circuit 102 includes at least one input buffer circuit 112. For example, input buffer circuit 112 can identify the logic level at pin 118B and provide a corresponding logic signal to internal digital control circuit 102.

為了更佳瞭解，第1a圖與第1b圖亦圖示電力供應120(可為直流(DC)電力供應)以提供用於積體電路102的供應電壓。再者，圖示說明在串列協定(例如諸如SPI或 I2C)下操作的匯流排主控器電路126。在一個具體實施例中，匯流排主控器電路126為主機系統的部分。例如，匯流排主控器電路126可為由主機系統電力供應122(可為DC電力供應)供電的另一積體電路(諸如微控制器或ASIC)。在一個具體實施例中，電力供應120與122的電壓可為實質上不同。在支援兩個常見匯流排協定(諸如SPI與I2C)的一個具體實施例中，可提供至少四個額外的接腳A(116A)、接腳B(118B)以及接腳C與D(未圖示)。在一個範例中，可根據下列的表一來配置接腳A至D： For better understanding, Figures 1a and 1b also illustrate a power supply 120 (which may be a direct current (DC) power supply) to provide a supply voltage for the integrated circuit 102. Again, the bus master circuit 126 operating under a serial protocol such as, for example, SPI or I 2 C, is illustrated. In one particular embodiment, bus master circuit 126 is part of the host system. For example, bus master circuit 126 may be another integrated circuit (such as a microcontroller or ASIC) that is powered by host system power supply 122 (which may be a DC power supply). In one particular embodiment, the voltages of power supplies 120 and 122 can be substantially different. In the two support common bus protocol (such as SPI and I 2 C) to a particular embodiment, it may be provided at least four additional pins A (116A), pin B (118B), and pins C and D ( Not shown). In one example, pins A through D can be configured according to Table 1 below:

現參照第2a圖，第2a圖圖示說明在與本發明之具體實施例一致之配置中的具有四個控制接腳的積體電路102。在第2a圖範例中，在SPI模式中配置接腳114(CONF)被連接至供應電壓VDDLOGIC，供應電壓VDDLOGIC可為來自供應主機系統的連接至SPI匯流排的微控制器或ASIC 126的相同的供應電壓源122。在一個具體實施例中，匯流排供應電壓偵測電路109偵測接腳114(CONF)處VDDLOGIC的存在。例如，內部邏輯電路102可經由MODE訊號來配置，而使接腳116A作為串列資料輸出(SO)、接腳118B作為串列時脈輸入(SCK)、接腳118C作為串列資料輸入(SI)、且接腳118D作為晶片選擇輸入(/CS)(晶片選擇輸入在SPI系統 中可為低態有效)。在第2a圖的範例中，所有在接腳116A至118D上的線被連接至匯流排主控器126。然而，在一些於匯流排上具有多於一個裝置(例如除了主控器之外)的SPI系統中，SO與SI線可與其他SPI裝置菊鏈連接(daisy chained)。 Referring now to Figure 2a, Figure 2a illustrates an integrated circuit 102 having four control pins in a configuration consistent with a particular embodiment of the present invention. In the example of Figure 2a, the configuration pin 114 (CONF) is connected to the supply voltage VDD LOGIC in the SPI mode, and the supply voltage VDD LOGIC can be from the supply host system to the microcontroller or ASIC 126 connected to the SPI bus. The same supply voltage source 122. In one embodiment, bus supply voltage detection circuit 109 detects the presence of VDD LOGIC at pin 114 (CONF). For example, the internal logic circuit 102 can be configured via the MODE signal, and the pin 116A is used as the serial data output (SO), the pin 118B is used as the serial clock input (SCK), and the pin 118C is used as the serial data input (SI). And pin 118D acts as a wafer select input (/CS) (the wafer select input can be active low in the SPI system). In the example of Figure 2a, all of the lines on pins 116A through 118D are connected to bus bar master 126. However, in some SPI systems with more than one device on the bus (eg, in addition to the master), the SO and SI lines can be daisy chained with other SPI devices.

例如在SPI模式中，除了作為配置輸入以配置串列介面的數位電路108之外，配置接腳114(CONF)亦可作為電力供應接腳。例如，相關聯於串列匯流排的至少一個輸出驅動器電路110可由配置接腳114來供電。在SPI模式的情況中，至少在接腳116A處之用於串列資料輸出訊號(SO)的接腳驅動器是由連接至配置接腳114的電壓VDDLOGIC來供電。配置接腳的雙重用途(例如做為電力源與模式選擇)，有益地減少了接腳數目(或釋放接腳，以供其他目的來使用)。 For example, in the SPI mode, the configuration pin 114 (CONF) can also function as a power supply pin in addition to the digital circuit 108 that is configured as a configuration input to configure the serial interface. For example, at least one output driver circuit 110 associated with the serial bus bar can be powered by configuration pin 114. In the case of the SPI mode, at least the pin driver for the serial data output signal (SO) at pin 116A is powered by the voltage VDD LOGIC connected to the configuration pin 114. The dual use of the configuration pins (for example, as a power source and mode selection) beneficially reduces the number of pins (or releases the pins for other purposes).

可選地(未圖示於第2a圖)，輸入緩衝器電路112B、112C以及112D(例如在第2a圖範例中於接腳118B、118C以及118D上所見)亦可由連接至配置接腳114的電壓VDDLOGIC來供電。在一個具體實施例中，藉由適當地縮放輸入緩衝器電路112B至112D中使用的電子部件，可設定輸入邏輯臨限電壓，而在串列匯流排上得到最佳的雜訊抗擾性。在一個具體實施例中，類似於施密特觸發器(Schmitt Trigger)的電路可做為輸入緩衝器電路。 Alternatively (not shown in FIG. 2a), input buffer circuits 112B, 112C, and 112D (as seen, for example, on pins 118B, 118C, and 118D in the example of FIG. 2a) may also be coupled to configuration pin 114. The voltage VDD LOGIC is used to supply power. In one embodiment, by properly scaling the electronic components used in input buffer circuits 112B through 112D, the input logic threshold voltage can be set to achieve the best noise immunity on the serial bus. In a specific embodiment, a circuit similar to a Schmitt Trigger can be used as an input buffer circuit.

由連接至配置接腳114的電壓供電經適當縮放的輸入緩衝器電路(或施密特觸發器)，有益地允許輸入緩衝器電路(或施密特觸發器)的邏輯臨限電壓位準自動追蹤配置 接腳114上的供應電壓。考慮到此，在本發明領域中具有通常知識者將輕易瞭解如何適當縮放CMOS反相器的PMOS與NMOS的寬度與長度比(W/L)，以得到最佳的雜訊抗擾性。 The properly scaled input buffer circuit (or Schmitt trigger) is powered by a voltage connected to the configuration pin 114, advantageously allowing the logic threshold voltage level of the input buffer circuit (or Schmitt trigger) to be automatically Tracking configuration Supply voltage on pin 114. In view of this, those of ordinary skill in the art will readily understand how to properly scale the PMOS to NMOS width to length ratio (W/L) of a CMOS inverter for optimum noise immunity.

第2b圖圖示說明與本發明之具體實施例一致之具有四個控制接腳並能容納I2C模式的積體電路102。在第2b圖範例中，在I2C模式中配置接腳114(CONF)可被連接至相當低於VDDLOGIC的電壓(諸如在負供應電壓或地接腳104(例如VSS)上的電位)，或為浮接。例如，跳線方塊220可提供兩種可能性：接地(安裝跳線)或浮接(無跳線)。 Figure 2b illustrates an integrated circuit 102 having four control pins and capable of accommodating an I 2 C mode consistent with embodiments of the present invention. In the example of Figure 2b, the configuration pin 114 (CONF) in the I 2 C mode can be connected to a voltage that is relatively lower than the VDD LOGIC (such as the potential on the negative supply voltage or ground pin 104 (eg, VSS)) Or for floating. For example, jumper block 220 can provide two possibilities: ground (install jumper) or float (no jumper).

在一個具體實施例中，匯流排供應電壓偵測電路109偵測到在配置接腳114處不存在VDDLOGIC。在匯流排供應電壓偵測電路109的輸出處的MODE訊號，可用於實施數種功能。例如，藉由使用MODE訊號，內部數位邏輯電路108可經配置，而使接腳116A作為串列資料輸入與輸出(SDA)、接腳118B作為串列時脈輸入(SCL)、接腳118C作為第一位址選擇輸入AS1、且接腳118D作為第二位址選擇輸入AS2。接腳116A的雙向功能性，可由輸入緩衝器112A來達成，輸入緩衝器112A為了簡潔說明而未圖示於第2a圖中但可存在於積體電路102上。例如，於在接腳116A或另一接腳處不需要雙向資料傳輸能力的作業模式中，不使用輸入緩衝器112A。在一個範例中，位址選擇輸入AS1與AS2可由第二跳線方塊224連接至VDD或VSS。例如，第二跳線方塊224允許僅由使用這兩個接腳，來選擇上至四個I2C位址。可選地，若輸入AS1與AS2被提供了「浮接」偵測電路，則此種 接頭(例如AS1與AS2)亦可為浮接(例如不安裝跳線)，從而允許僅由兩個接腳選擇許多(例如上至九個)I2C位址。例如，基於符號{0,F,1}在三元邏輯中使用浮接狀態「F」，可識別九個組合00、0F、01、F0、FF、F1、10、1F、11並映射至九個I2C位址。 In one embodiment, bus supply voltage detection circuit 109 detects that VDD LOGIC is not present at configuration pin 114. The MODE signal at the output of the bus supply voltage detecting circuit 109 can be used to implement several functions. For example, by using the MODE signal, the internal digital logic circuit 108 can be configured to have the pin 116A as the serial data input and output (SDA), the pin 118B as the serial clock input (SCL), and the pin 118C. The first address selects input AS1 and pin 118D serves as the second address select input AS2. The bidirectional functionality of pin 116A can be achieved by input buffer 112A. Input buffer 112A is not shown in FIG. 2a for simplicity of description but may be present on integrated circuit 102. For example, in a job mode where bidirectional data transfer capability is not required at pin 116A or another pin, input buffer 112A is not used. In one example, address select inputs AS1 and AS2 may be connected to VDD or VSS by second jumper block 224. For example, the second jumper block 224 allows up to four I 2 C addresses to be selected only by using the two pins. Alternatively, if the inputs AS1 and AS2 are provided with a "floating" detection circuit, such connectors (eg, AS1 and AS2) may also be floating (eg, no jumpers are installed), thereby allowing only two connections. The foot selects a number of (eg up to nine) I 2 C addresses. For example, based on the symbol {0, F, 1} using the floating state "F" in the ternary logic, nine combinations 00, 0F, 01, F0, FF, F1, 10, 1F, 11 can be identified and mapped to nine. I 2 C address.

再看到第2b圖，在又另一具體實施例中，配置接腳114亦可被提供「浮接」偵測電路。例如，加入「浮接」偵測電路，允許兩個跳線方塊220設定(亦即浮接與接地)。這些跳線設定可用以提升可選擇I2C位址的數量至十八個，而不需提升接腳數目。第2b圖的電阻器210與212為習知的上拉電阻器並可從I2C規格書中得知。在一個具體實施例中(例如在I2C模式中)，輸出驅動器電路110操作如開汲極輸出。可由控制電路108得到開汲極輸出。例如，在期望在SDA匯流排線上的邏輯「高」位準時，耦接在輸出驅動器電路110的接腳116A與接腳114之間的驅動器電晶體(未圖示於第2b圖中)不由控制電路108致動。在此情況中，輸出驅動器電路110不從配置接腳114汲取任何電力，且邏輯「高」位準由電阻器212來提供。 Referring again to FIG. 2b, in yet another embodiment, the configuration pin 114 can also be provided with a "floating" detection circuit. For example, adding a "floating" detection circuit allows two jumper blocks 220 to be set (ie, floating and grounded). These jumper settings can be used to increase the number of selectable I 2 C addresses to eighteen without increasing the number of pins. Resistors 210 and 212 of Figure 2b are conventional pull-up resistors and are known from the I 2 C specification. In one embodiment (e.g., in the I 2 C mode), the output driver circuit 110 operates as an open drain output. The open drain output can be obtained by control circuit 108. For example, when it is desired to have a logic "high" level on the SDA bus line, the driver transistor (not shown in Figure 2b) coupled between pin 116A and pin 114 of output driver circuit 110 is not controlled. Circuitry 108 is actuated. In this case, output driver circuit 110 does not draw any power from configuration pin 114, and a logic "high" level is provided by resistor 212.

現參照第3圖，第3圖圖示說明與本發明之具體實施例一致的電晶體層級介面。在第3圖範例中，匯流排供應電壓偵測電路109包含下拉電晶體M1、限流電阻器R1、經配置以偵測「高」與「低」電位的位準偵測器306、以及狀態機312。下拉電晶體M1的源極耦接至低電壓節點(例如Vss、接地、或其他電流汲取節點)。在一個範例中，若下拉電晶 體M1被製為弱(例如藉由具有低W/L比而具有低下拉強度)，則甚至可省略限流電阻器R1。下文說明介面的示例性作業。 Referring now to Figure 3, a third diagram illustrates a transistor level interface consistent with a particular embodiment of the present invention. In the example of FIG. 3, the bus supply voltage detecting circuit 109 includes a pull-down transistor M1, a current limiting resistor R1, a level detector 306 configured to detect "high" and "low" potentials, and a state. Machine 312. The source of pull-down transistor M1 is coupled to a low voltage node (eg, Vss, ground, or other current draw node). In one example, if the pull-down transistor The body M1 is made weak (for example, having a low pull-down strength by having a low W/L ratio), and even the current limiting resistor R1 can be omitted. An exemplary operation of the interface is described below.

例如，狀態機312的第一狀態致動電晶體M1，並將邏輯位準記錄在位準偵測器306的輸出上。狀態機312的第二狀態停用電晶體M1，並將邏輯位準記錄在位準偵測器306的輸出上。若兩個記錄顯示「高」邏輯位準，則狀態機312進入指示在狀態機312輸出處的MODE訊號處的匯流排供應電壓存在的狀態。或者，狀態機312進入指示匯流排供應電壓不存在的狀態。在一個具體實施例中，位準偵測器306為反相器，反相器的PMOS與NMOS比例經過設計，而使跳脫位準(trip level)位於欲在配置接腳114處偵測之有效匯流排供應電壓的最低期望值之下。在另一具體實施例中(未圖示於第3圖中)，位準偵測器306可為比較器，比較器的第一輸入耦接至配置接腳114，且比較器的第二輸入耦接至參考電壓。在又另一具體實施例中，第二比較器輸入耦接至電晶體M1的汲極，而使得在電晶體M1被致動時，比較器偵測跨電晶體R1的電壓降。例如，電壓偵測電路109的決策，可基於流動通過電晶體R1的實際電流，而不基於在配置接腳114上的任何特定電壓位準。 For example, the first state of state machine 312 actuates transistor M1 and records the logic level on the output of level detector 306. The second state of state machine 312 disables transistor M1 and records the logic level on the output of level detector 306. If the two records show a "high" logic level, state machine 312 enters a state indicating the presence of the bus supply voltage at the MODE signal at the output of state machine 312. Alternatively, state machine 312 enters a state indicating that the bus supply voltage is not present. In one embodiment, the level detector 306 is an inverter, and the PMOS and NMOS ratios of the inverter are designed such that the trip level is effective for detection at the configuration pin 114. Below the lowest expected value of the bus supply voltage. In another embodiment (not shown in FIG. 3), the level detector 306 can be a comparator, the first input of the comparator is coupled to the configuration pin 114, and the second input of the comparator Coupling to the reference voltage. In yet another embodiment, the second comparator input is coupled to the drain of the transistor M1 such that when the transistor M1 is actuated, the comparator detects the voltage drop across the transistor R1. For example, the decision of voltage detection circuit 109 may be based on the actual current flowing through transistor R1 without being based on any particular voltage level on configuration pin 114.

例如，輸出驅動器電路110A可包含兩個NMOS電晶體M2與M3。電晶體M2可做為下拉電晶體，且M3可做為上拉電晶體。電晶體M3可直接耦接至配置接腳114以接收所供應的VDDLOGIC電壓(例如在第一作業模式中時)。在一 個具體實施例中，若M3的閘極被驅動得夠高(可由習知於本發明領域中的閘極升壓(gate boost)電路來執行)，則上至VDDLOGIC的完整擺幅是可能的。例如，此對於實施用於多供應電壓域的推拉接腳驅動器的解決方案，可比使用PMOS上拉要簡單，PMOS上拉可增加由寄生雙極性效應所帶來的困難(例如在PMOS汲極或源極超過基極電壓時)。然而，若積體電路300具有大於或等於匯流排上的最高期望電壓的內部電壓源，則電晶體M3可替代性地為PMOS(例如，其中PMOS的基極連接至內部電壓源)。 For example, output driver circuit 110A can include two NMOS transistors M2 and M3. The transistor M2 can be used as a pull-down transistor, and M3 can be used as a pull-up transistor. The transistor M3 can be directly coupled to the configuration pin 114 to receive the supplied VDD LOGIC voltage (eg, when in the first mode of operation). In one embodiment, if the gate of M3 is driven high enough (which can be performed by a gate boost circuit as is conventional in the art), then the full swing up to VDD LOGIC is possible. For example, this solution for implementing push-pull pin drivers for multiple supply voltage domains can be simpler than using PMOS pull-ups, which can increase the difficulties caused by parasitic bipolar effects (such as in PMOS bungee or When the source exceeds the base voltage). However, if integrated circuit 300 has an internal voltage source that is greater than or equal to the highest desired voltage on the bus, then transistor M3 may alternatively be a PMOS (eg, where the base of the PMOS is connected to an internal voltage source).

輸入緩衝器電路112A至112C之每一者，可包含至少一個反相器。在一個範例中，每一反相器包含NMOS電晶體M4與PMOS電晶體M5。輸入緩衝器電路112A至112C的供應電壓(亦即在網路314處)，可藉由使用電子控制切換器304，而在配置接腳114電壓位準或內部電壓320(VINT)之間切換。在一個具體實施例中，內部電壓320(VINT)為供應電壓322(VDD)(例如由供應電壓322(VDD)與切換器304之間的虛線連結所指示)。或者，內部電壓320(VINT)可為適合設定輸入緩衝器電路112A至112C的所需跳脫點的跳脫位準設定電壓。在一個具體實施例中，NMOS源極隨耦器(未圖示)可從供應電壓VDD導出此跳脫位準設定電壓。在一個具體實施例中，可由內部穩壓器提供跳脫位準設定。例如，邏輯電壓跳脫位準可根據I2C匯流排標準來設定。 Each of the input buffer circuits 112A through 112C may include at least one inverter. In one example, each inverter includes an NMOS transistor M4 and a PMOS transistor M5. The supply voltages to input buffer circuits 112A through 112C (i.e., at network 314) can be switched between configuration pin 114 voltage level or internal voltage 320 (VINT) by using electronically controlled switch 304. In one particular embodiment, internal voltage 320 (VINT) is supply voltage 322 (VDD) (eg, as indicated by the dashed link between supply voltage 322 (VDD) and switch 304). Alternatively, internal voltage 320 (VINT) may be a trip level setting voltage suitable for setting the desired trip point of input buffer circuits 112A-112C. In one embodiment, an NMOS source follower (not shown) can derive the trip level setting voltage from the supply voltage VDD. In one embodiment, the trip level setting can be provided by an internal voltage regulator. For example, the logic voltage trip level can be set according to the I 2 C bus bar standard.

在一個具體實施例中，具有位準偵測器306或輸入緩衝器電路112A至112C耦接至其上的接腳(諸如配置接腳 114)，可被提供浮接狀態偵測電路。例如，可將弱推拉驅動器級315耦接至此種接腳。在一個具體實施例中，藉由在電晶體M6與M7輸出處包含串連電阻器R2，或藉由使電晶體M6與M7自身為弱(例如藉由配置小的W/L比)，而使推拉驅動器級(例如315)為弱。 In one embodiment, there is a pin (such as a configuration pin) having a level detector 306 or input buffer circuits 112A-112C coupled thereto. 114), a floating state detection circuit can be provided. For example, the weak push-pull driver stage 315 can be coupled to such a pin. In a specific embodiment, by including the series resistor R2 at the output of the transistors M6 and M7, or by making the transistors M6 and M7 themselves weak (for example by configuring a small W/L ratio) Make the push-pull driver stage (eg 315) weak.

在一個具體實施例中，內部數位邏輯電路108(例如數位控制電路)包含一或更多個狀態機，狀態機交替地致動耦接至接腳(例如118C或114)的電晶體M6與M7，並回應於由輸入緩衝器電路112C或位準偵測器306所偵測之在接腳上的邏輯狀態。例如，電晶體M6與M7被切換以決定輸出對此種刺激如何反應。在一個具體實施例中，回應於切換，若接腳上的兩邏輯狀態保持為「高」，則指示接腳耦接至高邏輯位準。回應於切換，若接腳上的兩邏輯狀態保持為「低」，則指示接腳耦接至低邏輯位準。然而，若偵測到在電晶體M6為開啟時接腳上的邏輯狀態為「高」，且在電晶體M7為開啟時接腳上的邏輯狀態為「低」，則指示接腳為浮接。其他的狀況是無效的且不應發生。在此情況中，可重複偵測程序，直到找到有效狀況，或直到一些錯誤處理程序被輸入。 In a specific embodiment, internal digital logic circuit 108 (eg, a digital control circuit) includes one or more state machines that alternately actuate transistors M6 and M7 coupled to pins (eg, 118C or 114). And in response to the logic state on the pin detected by the input buffer circuit 112C or the level detector 306. For example, transistors M6 and M7 are switched to determine how the output reacts to such stimuli. In one embodiment, in response to the switch, if the two logic states on the pin remain "high," the pin is coupled to a high logic level. In response to the switch, if the two logic states on the pin remain "low", the pin is coupled to the low logic level. However, if it is detected that the logic state on the pin is "high" when the transistor M6 is on, and the logic state on the pin is "low" when the transistor M7 is on, the indicating pin is floating. . Other conditions are invalid and should not occur. In this case, the detection process can be repeated until a valid condition is found, or until some error handler is entered.

在一個具體實施例中，匯流排供應電壓偵測電路109被耦接至(或包含)浮接狀態偵測電路(例如類似於315的電路)。例如，可由此種弱推拉驅動器級代替電晶體M1，並施加如上文所討論的類似偵測程序。例如，先啟動上述匯流排電壓偵測序列，並僅在不存在匯流排電壓時進行浮接狀態偵測序列是有益的。 In one embodiment, the bus supply voltage detection circuit 109 is coupled to (or includes) a floating state detection circuit (eg, a circuit similar to 315). For example, transistor M1 can be replaced by such a weak push-pull driver stage and a similar detection procedure as discussed above can be applied. For example, it may be beneficial to first activate the bus voltage detection sequence and perform a floating state detection sequence only when there is no bus voltage.

在一個具體實施例中，使用內部供應電壓穩壓器(未圖示)，以從VDD供應產生內部供應電壓VINT。換言之，配置接腳114不需提供內部輸入緩衝器供應電壓VINT。有鑑於此，應瞭解可使用額外的類比電路系統與外部電容器，以提供經穩壓的VINT。在又另一具體實施例中，亦可由VINT替代供應電壓接腳322處的VDD，來供電內部數位控制電路108。 In a specific embodiment, an internal supply voltage regulator (not shown) is used to generate an internal supply voltage VINT from the VDD supply. In other words, the configuration pin 114 does not need to provide an internal input buffer supply voltage VINT. In view of this, it should be understood that additional analog circuitry and external capacitors can be used to provide a regulated VINT. In yet another embodiment, the internal digital control circuit 108 can also be powered by VINT instead of VDD at the supply voltage pin 322.

本文所討論的部件、步驟、特徵、物件、益處與優點僅為說明性。這些部件、步驟、特徵、物件、益處與優點，以及相關的討論，全不意為以任何方式限制保護範圍。亦思量了數種其他的具體實施例。這些其他的具體實施例，包含具有較少的、額外的、及/或不同的部件、步驟、特徵、物件、益處與優點的具體實施例。這些其他的具體實施例，亦包含其中部件及/或步驟被不同地設置及/或排序的具體實施例。例如，可使用雙極性電晶體(例如PNP或NPN)來代替MOS電晶體。可使用PNP代替NPN，且可使用PMOS代替NMOS。因此，本發明僅由附加申請專利範圍來限制。 The components, steps, features, objects, benefits, and advantages discussed herein are merely illustrative. These components, steps, features, objects, benefits and advantages, and related discussions are not intended to limit the scope of the protection in any way. Several other specific embodiments have also been considered. These other specific embodiments include specific embodiments with fewer, additional, and/or different components, steps, features, objects, advantages and advantages. These other specific embodiments also include specific embodiments in which the components and/or steps are variously arranged and/or ordered. For example, a bipolar transistor (such as PNP or NPN) can be used instead of the MOS transistor. PNP can be used instead of NPN, and PMOS can be used instead of NMOS. Accordingly, the invention is limited only by the scope of the appended claims.

102‧‧‧積體電路 102‧‧‧Integrated circuit

104‧‧‧接地接腳 104‧‧‧ Grounding pin

106‧‧‧電力供應接腳 106‧‧‧Power supply pin

108‧‧‧數位控制電路 108‧‧‧Digital Control Circuit

110‧‧‧串列匯流排驅動器 110‧‧‧Synchronous bus driver

112‧‧‧輸入緩衝器電路 112‧‧‧Input buffer circuit

114‧‧‧配置節點 114‧‧‧Configuration node

116A‧‧‧接腳 116A‧‧‧ pin

118B‧‧‧接腳 118B‧‧‧ feet

120‧‧‧電力供應 120‧‧‧Power supply

122‧‧‧供應電壓 122‧‧‧Supply voltage

109‧‧‧電壓偵測電路 109‧‧‧Voltage detection circuit

126‧‧‧匯流排主控器 126‧‧‧ Busbar master

Claims (19)

一種可配置式串列介面，包含：一配置節點；一或更多個輸入節點，該一或更多個輸入節點之每一者耦接至一各別的串列匯流排；一或更多個輸出節點，該一或更多個輸出節點之每一者耦接至一各別的串列匯流排；至少一個驅動器，該至少一個驅動器經配置以驅動一各別的輸出節點；一電壓偵測電路，該電壓偵測電路耦接至該配置節點，且該電壓偵測電路可操作以偵測在該配置節點處的一電壓，其中：該可配置式串列介面可操作以基於在該配置節點處偵測到的該電壓來設定一串列匯流排作業模式；且在至少一個串列匯流排作業模式中，該配置節點經配置為一模式選擇輸入以及對於一輸出節點之至少一個驅動器的一電力源兩者。 A configurable serial interface comprising: a configuration node; one or more input nodes, each of the one or more input nodes coupled to a respective serial bus; one or more Output nodes, each of the one or more output nodes being coupled to a respective serial bus; at least one driver configured to drive a respective output node; a voltage detect Measuring circuit, the voltage detecting circuit is coupled to the configuration node, and the voltage detecting circuit is operable to detect a voltage at the configuration node, wherein: the configurable serial interface is operable to be based on Configuring the voltage detected at the node to set a serial bus operation mode; and in at least one serial bus operation mode, the configuration node is configured as a mode selection input and at least one driver for an output node One of the power sources. 如請求項1所述之可配置式串列介面，其中該配置節點為：(i)耦接至一接地；(ii)耦接至一供應電壓位準(VDDLOGIC)；或(iii)浮接。 The configurable serial interface as claimed in claim 1, wherein the configuration node is: (i) coupled to a ground; (ii) coupled to a supply voltage level (VDD LOGIC ); or (iii) floating Pick up. 如請求項1所述之可配置式串列介面，其中：在一第一串列匯流排作業模式中，一輸出節點的該至少一個輸出驅動器經配置以提供一輸出電壓，該輸出電壓實質上等於在該配置節點處的該電壓；且在一第二串列匯流排作業模式中，一輸出節點的該至少一個輸出驅動器經配置為一開汲極。 The configurable serial interface of claim 1, wherein: in a first tandem bus operation mode, the at least one output driver of an output node is configured to provide an output voltage, the output voltage being substantially Equal to the voltage at the configuration node; and in a second tandem bus operation mode, the at least one output driver of an output node is configured as an open drain. 如請求項3所述之可配置式串列介面，其中：該第一串列匯流排作業模式為串列周邊介面(SPI)，且該第二串列匯流排作業模式為雙線介面(I2C)。 The configurable serial interface of claim 3, wherein: the first serial bus operation mode is a serial peripheral interface (SPI), and the second serial bus operation mode is a two-line interface (I 2 C). 如請求項3所述之可配置式串列介面，其中在一第二串列匯流排作業模式中：一第一輸出節點係操作為一串列資料輸入/輸出(SDA)接腳；一第一輸入節點係操作為一串列時脈輸入(SCL)接腳；一第二輸入節點係操作為一第一位址選擇輸入(AS1)；且一第三輸入節點係操作為一第二位址選擇輸入(AS2)。 The configurable serial interface of claim 3, wherein in a second serial bus operation mode: a first output node operates as a serial data input/output (SDA) pin; An input node operates as a serial clock input (SCL) pin; a second input node operates as a first address selection input (AS1); and a third input node operates as a second bit Address selection input (AS2). 如請求項1所述之可配置式串列介面，其中一邏輯臨限位準係基於該配置節點處的該電壓。 The configurable serial interface of claim 1, wherein a logic threshold is based on the voltage at the configuration node. 如請求項1所述之可配置式串列介面，該可配置式串列 介面進一步包含至少一個輸入緩衝器，每一輸入緩衝器具有一輸入，該輸入耦接至一各別的輸入節點。 The configurable serial interface as claimed in claim 1, the configurable serial The interface further includes at least one input buffer, each input buffer having an input coupled to a respective input node. 如請求項7所述之可配置式串列介面，其中該至少一個輸入緩衝器係配置為一施密特觸發器(Schmitt Trigger)。 The configurable serial interface of claim 7, wherein the at least one input buffer is configured as a Schmitt Trigger. 如請求項1所述之可配置式串列介面，該可配置式串列介面進一步包含一浮接偵測電路，該浮接偵測電路耦接至至少一個輸入節點。 The configurable serial interface of claim 1, the configurable serial interface further comprising a floating detection circuit coupled to the at least one input node. 如請求項1所述之可配置式串列介面，該可配置式串列介面進一步包含一浮接偵測電路，該浮接偵測電路耦接至該配置節點。 The configurable serial interface of claim 1, further comprising a floating detection circuit coupled to the configuration node. 如請求項1所述之可配置式串列介面，其中該電壓偵測電路包含：一下拉電晶體，該下拉電晶體的汲極耦接至該配置節點，且該下拉電晶體的源極耦接至一第一電壓節點；一狀態機，該狀態機耦接至該下拉電晶體的一閘極；以及一位準偵測器，該位準偵測器耦接於該下拉電晶體的該汲極與該狀態機之間。 The configurable serial interface of claim 1, wherein the voltage detecting circuit comprises: a pull-down transistor, a drain of the pull-down transistor is coupled to the configuration node, and a source coupling of the pull-down transistor Connected to a first voltage node; a state machine coupled to a gate of the pull-down transistor; and a quasi-detector coupled to the pull-down transistor The bungee is between the state machine and the state machine. 如請求項11所述之可配置式串列介面，其中該位準偵測 器包含一反相器，該反相器具有一PMOS與一NMOS。 The configurable serial interface as described in claim 11, wherein the level detection The device includes an inverter having a PMOS and an NMOS. 如請求項1所述之可配置式串列介面，該可配置式串列介面進一步包含一數位邏輯電路，該數位邏輯電路具有一或更多個狀態機。 The configurable serial interface of claim 1, the configurable serial interface further comprising a digital logic circuit having one or more state machines. 一種配置一串列介面的方法，該串列介面具有至少一個輸出驅動器，該方法包含以下步驟：決定在一配置接腳處的一電壓；在所決定的該電壓位於一第一範圍內時，進入一第一串列匯流排作業模式，該第一串列匯流排作業模式包含：使用在該配置接腳處的該電壓作為一模式選擇輸入；以及使用在該配置接腳處的該電壓作為對於該至少一個輸出驅動器的一電力供應；以及在所決定的該電壓位於一第二範圍內時，進入一第二串列匯流排作業模式中，該第二串列匯流排作業模式包含：配置該輸出驅動器為一開汲極。 A method of configuring a serial interface, the serial interface having at least one output driver, the method comprising the steps of: determining a voltage at a configuration pin; and when the determined voltage is within a first range, Entering a first serial bus operation mode, the first serial bus operation mode includes: using the voltage at the configuration pin as a mode selection input; and using the voltage at the configuration pin as a power supply to the at least one output driver; and when the determined voltage is within a second range, entering a second serial bus operation mode, the second serial bus operation mode includes: configuring The output driver is an open drain. 如請求項14所述之方法，其中：該第一串列匯流排作業模式為串列周邊介面(SPI)，且該第二串列匯流排作業模式為雙線介面(I2C)。 The method of claim 14, wherein the first serial bus operation mode is a serial peripheral interface (SPI), and the second serial bus operation mode is a two-line interface (I 2 C). 如請求項14所述之方法，其中進入一第二串列匯流排作業模式包含以下步驟：配置一第一輸出節點為一串列資料輸入/輸出(SDA)接腳；配置一第一輸入節點為一串列時脈輸入(SCL)接腳；配置一第二輸入節點為一第一位址選擇輸入(AS1)；且配置一第三輸入節點為一第二位址選擇輸入(AS2)。 The method of claim 14, wherein entering a second serial bus operation mode comprises the steps of: configuring a first output node as a serial data input/output (SDA) pin; configuring a first input node A serial clock input (SCL) pin; a second input node is configured as a first address selection input (AS1); and a third input node is configured as a second address selection input (AS2). 如請求項14所述之方法，該方法進一步包含以下步驟：基於該配置接腳的該電壓來調整一邏輯臨限位準。 The method of claim 14, the method further comprising the step of adjusting a logical threshold level based on the voltage of the configuration pin. 如請求項14所述之方法，該方法進一步包含以下步驟：決定該配置接腳是否為浮接。 The method of claim 14, the method further comprising the step of determining whether the configuration pin is floating. 如請求項14所述之方法，該方法進一步包含以下步驟：決定一位址選擇輸入是否為浮接。 The method of claim 14, the method further comprising the step of determining whether the address selection input is a floating connection.
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