TWI577998B - Semiconductor transport test fixture - Google Patents
Semiconductor transport test fixture Download PDFInfo
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- TWI577998B TWI577998B TW101117565A TW101117565A TWI577998B TW I577998 B TWI577998 B TW I577998B TW 101117565 A TW101117565 A TW 101117565A TW 101117565 A TW101117565 A TW 101117565A TW I577998 B TWI577998 B TW I577998B
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Description
本發明是關於一種搬送半導體之半導體搬送測試治具，尤其是關於適用於窄間距的BGA型半導體的搬送及事前測試之半導體搬送測試治具。 The present invention relates to a semiconductor transfer test jig for transporting semiconductors, and more particularly to a semiconductor transfer test jig suitable for transport and pre-test of narrow-pitch BGA type semiconductors.
半導體積體電路(以下稱「IC」)日益發展高積體化，但將IC應用於製品之際，通常嵌入製品前會實施機能測試、燒入測試等的事前測試。 Semiconductor integrated circuits (hereinafter referred to as "IC") are increasingly developed, but when ICs are applied to products, pre-tests such as functional tests and burn-in tests are usually performed before the products are embedded.
另外，在事前測試中，一般係將IC各別裝置於半導體搬送測試治具後，將複數個半導體搬送測試治具以搭載於搬送框之狀態實施搬送及事前測試。 In addition, in the pre-test, the ICs are transported to the test fixtures, and a plurality of semiconductor transport test fixtures are generally carried in the transport frame and carried out beforehand.
因此，為了迅速地進行事前測試，將事前測試對象的IC和半導體測試裝置(以下稱「IC測試器」)藉由半導體搬送測試治具及測試用插座確實地連接變得重要。 Therefore, in order to perform the pre-test, the IC and the semiconductor test device (hereinafter referred to as "IC tester") of the test object are reliably connected by the semiconductor transfer test jig and the test socket.
且，搬送過程中IC從半導體搬送測試治具脫落的情況時，須藉由停止半導體測試裝置的手動操作來修復，導致半導體測試裝置的運行率降低，因此防止IC的脫落亦變得重要。 In addition, when the IC is removed from the semiconductor transfer test fixture during the transfer, it is necessary to stop the manual operation of the semiconductor test device, and the operation rate of the semiconductor test device is lowered. Therefore, it is important to prevent the IC from falling off.
已有各式各樣可應用於IC的事前測試之半導體搬送測試治具被提案(例如，參照專利文獻1及專利文件2)。 A variety of semiconductor transfer test fixtures that can be applied to ICs for prior testing have been proposed (for example, refer to Patent Document 1 and Patent Document 2).
亦即，參照專利文獻1中，揭示有本體為框狀，且具 有夾持IC的上面及下面的夾持機構(閂鎖器)之半導體搬送測試治具。 That is, referring to Patent Document 1, it is disclosed that the body is frame-shaped and has A semiconductor transfer test fixture having a clamping mechanism (latch) for holding the upper and lower sides of the IC.
又，參照專利文獻2中，揭示有本體為框狀，且具有夾持IC的上面的夾持機構(閂鎖器)，及在框狀的底部有支撐IC的裝置支撐部之半導體搬送測試治具。 Further, Patent Document 2 discloses a semiconductor transfer test in which a main body has a frame shape and has a clamping mechanism (latch) for holding the IC, and a device supporting portion for supporting the IC at the bottom of the frame. With.
專利文獻1：日本特開2009-139370號公報 Patent Document 1: Japanese Laid-Open Patent Publication No. 2009-139370
專利文獻2：日本特開2010-266344號公報 Patent Document 2: Japanese Laid-Open Patent Publication No. 2010-266344
近年，IC的外部連接端子的小徑化、窄間距化日益發展，尤其係在使用焊錫球作為外部連接端子的BGA(Ball Grid Array)型IC或LGA(Land Grid Array)型IC中，外部連接端子的間距間隔從習知技術中的1.0~0.65毫米間距縮小至0.5毫米間距以下。 In recent years, the diameter and narrow pitch of the external connection terminals of ICs have been increasing, especially in BGA (Ball Grid Array) type ICs or LGA (Land Grid Array) type ICs using solder balls as external connection terminals. The pitch of the terminals is reduced from 1.0 to 0.65 mm pitch in the prior art to less than 0.5 mm pitch.
但，揭示於專利文獻1及專利文獻2之半導體搬送測試治具係使IC的外部連接端子和事前測試用插座的接點接腳直接接觸的形式，因應外部連接端子的間距窄小化，事前測試用插座本身的接點接腳也有必要成為窄間距，因此有事前測試用插座亦變為高價位之課題。 However, the semiconductor transfer test jig disclosed in Patent Document 1 and Patent Document 2 is such that the external connection terminal of the IC and the contact pin of the pre-test socket are in direct contact with each other, and the pitch of the external connection terminal is narrowed, beforehand. It is also necessary to have a narrow pitch for the contact pins of the test socket itself, so that the test socket beforehand also becomes a problem of high price.
另外，揭示於專利文獻1及專利文獻2之半導體搬送 測試治具係以閂鎖器或窄細的裝置支撐部夾持IC之構造，因此IC恐怕有在搬送過程脫落的可能之課題。 Further, the semiconductor transfer disclosed in Patent Document 1 and Patent Document 2 Since the test fixture is configured to hold the IC by a latch or a narrow device support portion, the IC may have a problem of falling off during the transport process.
本發明，係鑑於上述課題而研究者，其目的為提供不僅能完全地將IC脫落的風險排除，並且即使是應用於具有窄間距的外部連接端子之IC的情況下，亦未必須將事前測試用插座進行窄間距化之半導體搬送測試治具。 The present invention has been made in view of the above problems, and an object thereof is to provide a risk of not only completely eliminating the risk of IC falling off, but also in the case of application to an IC having a narrow pitch external connection terminal. A semiconductor transfer test fixture with a narrow pitch using a socket.
本發明的半導體搬送測試治具係具備框部及底面薄膜，該框部可供具有外部連接端子的半導體積體電路***內側；該底面薄膜被黏貼於前述框部的下面，且在表面形成「與前述外部連接端子接觸」的第1焊墊，在內部形成「與所對應的前述第1焊墊通電連接，並與測試用插座接觸」的第2焊墊；前述框部具有「當前述半導體積體電路被***前述框部的內側壁時，突出於前述半導體積體電路上方」的閂鎖器。 The semiconductor transport test fixture of the present invention includes a frame portion and a bottom film which can be inserted into the inside of the semiconductor integrated circuit having external connection terminals; the bottom film is adhered to the lower surface of the frame portion and formed on the surface. The first pad that is in contact with the external connection terminal has a second pad that is electrically connected to the corresponding first pad and is in contact with the test socket, and the frame portion has "the semiconductor When the integrated circuit is inserted into the inner side wall of the frame portion, the latch protrudes above the semiconductor integrated circuit.
依據上述構成，能達成完全地解決搬送過程中的IC之脫落。 According to the above configuration, it is possible to completely solve the drop of the IC during the transfer.
本發明之半導體搬送測試治具，其前述底面薄膜係以具有柔軟性的材料來製造。 In the semiconductor transport test fixture of the present invention, the bottom film is made of a flexible material.
依據上述構成，能達成使IC的外部連接端子與第1焊墊、及第2焊墊與測試用插座確實地接觸。 According to the above configuration, it is possible to reliably contact the external connection terminal of the IC with the first pad and the second pad and the test socket.
本發明之半導體搬送測試治具，其前述第1焊墊和前述第2焊墊的配置圖型相異。 In the semiconductor transfer test fixture of the present invention, the arrangement pattern of the first pad and the second pad is different.
依據上述構成，即使是應用於具有窄間距的外部連接端子之IC的情況下，變得未必須要將事前測試用插座進行窄間距化。 According to the above configuration, even in the case of an IC applied to an external connection terminal having a narrow pitch, it is not necessary to narrow the pitch of the test socket beforehand.
本發明的半導體搬送測試治具，其前述框部及前述底面薄膜具有：與設置在前述測試用插座上預先決定之位置的定位銷接合的定位孔。 In the semiconductor transport test fixture of the present invention, the frame portion and the bottom film have positioning holes that are joined to positioning pins provided at predetermined positions on the test socket.
依據上述構成，能達成將半導體搬送測試治具和測試用插座確實地定位。 According to the above configuration, it is possible to reliably position the semiconductor transport test jig and the test socket.
本發明之半導體搬送測試治具，其前述第1焊墊各別為環形、分離形、或圓形、亦或是多角錐形。 In the semiconductor transport test fixture of the present invention, the first pads are each ring-shaped, separated, or circular, or polygonal.
依據上述構成，能達成改善IC的外部連接端子和第1焊墊之接近性。 According to the above configuration, the proximity of the external connection terminal of the IC and the first pad can be improved.
根據本發明之半導體搬送測試治具，不僅能達成完全地防止搬送過程中IC的脫落，並且即使是應用於0.5毫米間距以下的窄間距的BGA型半導體的情況下，變得未必須要將事前測試用插座進行窄間距化。 According to the semiconductor transfer test jig of the present invention, not only can the IC be prevented from falling off during the transfer process, but even if it is applied to a narrow pitch BGA type semiconductor having a pitch of 0.5 mm or less, it becomes unnecessary to The test socket is narrowly pitched.
在以下的實施例中，說明關於IC的外部連接端子為BGA(焊錫球)時之情形，但本發明也可適用於IC的外部連接端子為LGA(地柵陣列)時之情況。 In the following embodiments, the case where the external connection terminal of the IC is a BGA (solder ball) will be described, but the present invention is also applicable to the case where the external connection terminal of the IC is an LGA (ground grid array).
第1圖係表示本發明之半導體搬送測試治具的安裝於搬送框的狀態之斜視圖，鋁製的搬送框1係具有複數個(例如8×4個)的安裝部，且搭載IC5之半導體搬送測試治具2以螺絲固定於各安裝部上。 1 is a perspective view showing a state in which the semiconductor transport test fixture of the present invention is attached to a transfer frame, and the aluminum transfer frame 1 has a plurality of (for example, 8 × 4) mounting portions and a semiconductor equipped with IC5. The transport test fixture 2 is screwed to each mounting portion.
第2圖係本發明之半導體搬送測試治具的上面斜視圖(a)及下面斜視圖(b)，半導體搬送測試治具2的框部21為樹脂製，且形成IC5被***於凹陷部之構造。 2 is a top perspective view (a) and a lower oblique view (b) of the semiconductor transport test fixture of the present invention, and the frame portion 21 of the semiconductor transport test fixture 2 is made of resin, and the IC 5 is formed to be inserted into the recessed portion. structure.
本體的內側壁22係由傾斜壁221和垂直壁222組成。另外，傾斜壁221係以易於引入IC5且開口朝上方漸大而傾斜形成，垂直壁222係以間隔空隙(例如0.1毫米以下)且包圍IC5的側面而形成。 The inner side wall 22 of the body is composed of an inclined wall 221 and a vertical wall 222. Further, the inclined wall 221 is formed to be inclined so as to be easily introduced into the IC 5 and the opening is gradually enlarged upward, and the vertical wall 222 is formed by a gap (for example, 0.1 mm or less) and surrounding the side surface of the IC 5.
又，傾斜壁221上的至少一處形成有當IC進入垂直壁222內部時，突出於IC上方之閂鎖器23。 Further, at least one portion of the inclined wall 221 is formed with a latch 23 that protrudes above the IC when the IC enters the inside of the vertical wall 222.
該閂鎖器23係藉由押下覆蓋於框部21的上面之控制板24，被引入傾斜壁221的內部，以成為可***IC的狀態之方式構成。 The latch 23 is introduced into the inclined wall 221 by pressing the control panel 24 that covers the upper surface of the frame portion 21 so as to be insertable into the IC.
亦即，將IC5***半導體搬送治具2時係押下控制板24，且閂鎖器23被引入傾斜壁221中之狀態。 That is, when the IC 5 is inserted into the semiconductor transport jig 2, the control board 24 is pushed down, and the latch 23 is introduced into the inclined wall 221.
另外，將IC5沿傾斜壁221***，嵌入於垂直壁222的內側。 Further, the IC 5 is inserted along the inclined wall 221 and embedded in the inner side of the vertical wall 222.
IC5的***後，解除控制板24的押下使閂鎖器23突出於IC5的上方。藉此防止搬送過程中IC從半導體搬送治具2彈出。 After the insertion of the IC 5, the release of the control board 24 is released to cause the latch 23 to protrude above the IC 5. Thereby, the IC is prevented from being ejected from the semiconductor transport jig 2 during the transfer.
第3圖係本發明的第1實施方式之半導體搬送測試治具和事前測試用插座的部分剖面圖。並且，由於事前測試用插座可適用公眾所知悉者，因此省略斷面構造的記載。 Fig. 3 is a partial cross-sectional view showing a semiconductor transfer test jig and a pre-test test socket according to the first embodiment of the present invention. Further, since the pre-test socket is applicable to the public, the description of the cross-sectional structure is omitted.
半導體搬送測試治具2的底面，以被黏著於框部21的下面之底面薄膜25覆蓋，以防止IC從半導體搬送測試治具2的底面的脫落之方式而形成。 The bottom surface of the semiconductor transport test fixture 2 is covered with a bottom film 25 adhered to the lower surface of the frame portion 21 to prevent the IC from being detached from the bottom surface of the semiconductor transport test fixture 2.
底面薄膜25係以黏著劑黏貼於框部21的底面而構成，且底面薄膜25係以受到損傷的情況時亦可交換之構成而形成。 The bottom film 25 is formed by adhering an adhesive to the bottom surface of the frame portion 21, and the bottom film 25 is formed by being exchanged when damaged.
又，底面薄膜25，上面具有與IC下面的焊錫球51接觸之IC側焊墊26(第1焊墊)，下面具有與從事前測試用插座向上突出的接點接腳接觸之插座側焊墊27(第2焊墊)。 Further, the bottom film 25 has an IC side pad 26 (first pad) which is in contact with the solder ball 51 on the lower surface of the IC, and a socket side pad which is in contact with the contact pin which protrudes upward from the front test socket. 27 (2nd pad).
將底面薄膜25黏貼於框部21的底面時，對於框部21來說有必要將IC側焊墊26的位置以IC5和垂直壁222間的空隙以下的精確度來定位。 When the bottom film 25 is adhered to the bottom surface of the frame portion 21, it is necessary for the frame portion 21 to position the IC-side pad 26 with an accuracy equal to or less than the gap between the IC 5 and the vertical wall 222.
第4圖係黏貼底面薄膜的狀態的半導體搬送測試治具之下面斜視圖，在底面薄膜25及半導體搬送測試治具2的框部21至少有2處穿孔設置有定位孔29。 4 is a perspective view of the semiconductor transport test fixture in a state in which the bottom film is adhered, and the positioning holes 29 are formed in at least two places in the bottom film 25 and the frame portion 21 of the semiconductor transport test fixture 2.
押下控制板24將閂鎖器23引入傾斜壁221的內部之狀態下，若將IC5從半導體搬送測試治具2的上部***，IC5會藉由傾斜壁221引導而到達由垂直壁222和底面薄膜25所包圍之區域。 When the control panel 24 is pressed to introduce the latch 23 into the inside of the inclined wall 221, if the IC 5 is inserted from the upper portion of the semiconductor transport test fixture 2, the IC 5 is guided by the inclined wall 221 to reach the vertical wall 222 and the bottom film. 25 surrounded by the area.
由於IC的側面和垂直壁222的空隙被設定成極為狹 窄(例如，0.1毫米以下)，因此配置於IC5的底面的焊錫球51變成與底面薄膜25的上面的IC側焊墊26確實地接觸。 Since the side of the IC and the gap of the vertical wall 222 are set to be extremely narrow Since it is narrow (for example, 0.1 mm or less), the solder ball 51 disposed on the bottom surface of the IC 5 is surely brought into contact with the IC side pad 26 on the upper surface of the bottom film 25.
設置於底面薄膜25的上面的IC側焊墊26和設置於底面薄膜25的下面的插座側焊墊27，係藉由垂直地貫通底面薄膜25內部的導電路28而通電地結合。 The IC side pad 26 provided on the upper surface of the bottom film 25 and the socket side pad 27 provided on the lower surface of the bottom film 25 are electrically connected by a conductive circuit 28 that vertically penetrates the inside of the bottom film 25.
事前測試用插座6係藉由固定構件62將底座61押下於基板(未圖示)而被固定於基板上。 The pre-test socket 6 is fixed to the substrate by pressing the base 61 on a substrate (not shown) by a fixing member 62.
接點接腳63屹立於事前測試用插座6的上面6a，且事前測試用插座6的底座61上屹立有貫通固定構件62之定位銷64。 The contact pin 63 stands on the upper surface 6a of the pre-test socket 6, and the positioning pin 64 penetrating the fixing member 62 stands on the base 61 of the pre-test socket 6.
將搭載IC5的半導體搬送測試治具2搬送到測試用插座6，藉由使穿孔於底面薄膜25及半導體搬送測試治具2的框部21上的定位孔29和定位銷64接合，能使插座側焊墊27和接點接腳63確實地接觸。 The semiconductor transfer test fixture 2 on which the IC 5 is mounted is transported to the test socket 6, and the socket is punched into the bottom film 25 and the positioning hole 29 of the frame portion 21 of the semiconductor transport test fixture 2 to be engaged with the positioning pin 64. The side pad 27 and the contact pin 63 are surely in contact.
該結果，IC5和IC測試器(未圖示)成為通電地連接。 As a result, the IC5 and the IC tester (not shown) are electrically connected.
另外，在本實施方式中，IC側焊墊26的正下方存在插座側焊墊27，且有必要使事前測試用插座6的接點接腳63的配置圖型與焊錫球51的配置圖形相同。 Further, in the present embodiment, the socket-side pad 27 is present directly under the IC-side pad 26, and it is necessary to make the arrangement pattern of the contact pins 63 of the pre-test socket 6 the same as the arrangement pattern of the solder balls 51. .
又，底面薄膜25係使用聚酯、聚亞醯胺等的具有柔軟性之聚合物薄膜作為材料，且希望其因應IC側焊墊與焊錫球51接觸時、及插座側焊墊與接點接腳63接觸時之壓力而柔軟地變形。 Further, the bottom film 25 is made of a flexible polymer film such as polyester or polyimide, and it is desirable that the IC side pad is in contact with the solder ball 51 and the socket side pad and the contact are connected. The pressure at the time of contact of the foot 63 is softly deformed.
第5圖係IC側焊墊26的形狀的上面圖(上段)及橫剖面圖(下段)，希望其與焊錫球51確實地接觸，且形成環形(a)、分離形(b)、亦或是含圓錐的多角錐形(c)。 Fig. 5 is a top view (upper section) and a cross-sectional view (lower section) of the shape of the IC side pad 26, and it is desirable to make sure contact with the solder ball 51, and form a ring shape (a), a separation shape (b), or It is a polygonal cone (c) with a cone.
在此，分離形係指等間隔地配置複數個端子於未滿焊錫球51的最大直徑的直徑的圓周上之形狀，(b)係表示配置4個正方形端子的情況。 Here, the separate shape refers to a shape in which a plurality of terminals are arranged on the circumference of the diameter of the maximum diameter of the solder balls 51 at equal intervals, and (b) shows a case where four square terminals are arranged.
(第2實施方式) (Second embodiment)
第6圖係本發明的第2實施方式的半導體搬送測試治具和事前測試用插座的部分剖面圖，唯有底面薄膜的構成不同。 Fig. 6 is a partial cross-sectional view showing the semiconductor transfer test jig and the pre-test test socket according to the second embodiment of the present invention, except that the configuration of the bottom film is different.
亦即，第2實施方式的底面薄膜35，其配置於薄膜上面的IC側焊墊36和配置於薄膜下面的插座側焊墊37的配置圖形相異。 In other words, in the bottom film 35 of the second embodiment, the arrangement pattern of the IC side pad 36 disposed on the upper surface of the film and the socket side pad 37 disposed on the lower surface of the film is different.
因此，將IC側焊墊36和插座側焊墊37連接之導電路38係從IC側焊墊36正下方垂直地貫通底面薄膜35，且水平方向地延伸於底面薄膜下面至插座側焊墊37。 Therefore, the conductive circuit 38 connecting the IC side pad 36 and the socket side pad 37 vertically penetrates the bottom surface film 35 from directly under the IC side pad 36, and extends horizontally from the bottom surface film to the socket side pad 37. .
依據本實施方式，可達成將事前測試用插座6的接點接腳63的配置間隔比IC5的焊錫球51的配置間隔更加擴展，可抑制事前測試用插座6的製作費用。 According to the present embodiment, the arrangement interval of the contact pins 63 of the pre-test socket 6 can be further expanded than the arrangement interval of the solder balls 51 of the IC 5, and the manufacturing cost of the pre-test socket 6 can be suppressed.
另外，其他的構造係和第1實施方式相同，因此省略說明。 In addition, since other structures are the same as those of the first embodiment, the description thereof is omitted.
第7圖係本發明的第3實施方式的半導體搬送測試治具和事前測試用插座的部分剖面圖，係使用多層構造的薄膜作為底面薄膜。 Fig. 7 is a partial cross-sectional view showing a semiconductor transfer test jig and a pre-test test socket according to a third embodiment of the present invention, and a film having a multilayer structure is used as a bottom film.
亦即，第3實施方式的底面薄膜45，其連接IC側焊墊46和插座側焊墊47之導電路48在多層底面薄膜的內部水平方向地延伸。 In other words, in the bottom film 45 of the third embodiment, the conductive circuit 48 that connects the IC side pad 46 and the socket side pad 47 extends horizontally inside the multilayer bottom film.
依據本實施方式，可達成將事前測試用插座6的接點接腳63的配置間隔比IC5的焊錫球51的配置間隔更加擴展，可抑制事前測試用插座6的製作費用。 According to the present embodiment, the arrangement interval of the contact pins 63 of the pre-test socket 6 can be further expanded than the arrangement interval of the solder balls 51 of the IC 5, and the manufacturing cost of the pre-test socket 6 can be suppressed.
另外，其他的構造係和第1實施方式相同，因此省略說明。 In addition, since other structures are the same as those of the first embodiment, the description thereof is omitted.
本發明之半導體搬送測試治具係可應用於窄間距的BGA型IC的搬送及事前測試，可在產業上利用。 The semiconductor transfer test fixture of the present invention can be applied to the transfer and pre-test of a narrow-pitch BGA type IC, and can be utilized industrially.
1‧‧‧搬送框 1‧‧‧Transport box
2‧‧‧半導體搬送治具 2‧‧‧Semiconductor transport fixture
3‧‧‧事前測試用插座 3‧‧‧Pre-test test socket
4‧‧‧固定器 4‧‧‧fixer
5‧‧‧IC(半導體積體電路) 5‧‧‧IC (semiconductor integrated circuit)
21‧‧‧框部 21‧‧‧ Frame Department
22‧‧‧內側壁 22‧‧‧ inner side wall
23‧‧‧閂鎖器 23‧‧‧Latch
24‧‧‧控制板 24‧‧‧Control panel
25‧‧‧底面薄膜 25‧‧‧ bottom film
26、36、46‧‧‧IC側焊墊(第1焊墊) 26, 36, 46‧‧‧IC side pads (1st pad)
27、37、47‧‧‧插座側焊墊(第2焊墊) 27, 37, 47‧‧‧ socket side pads (2nd pad)
28、38、48‧‧‧導電路 28, 38, 48‧‧ ‧ circuit
29‧‧‧定位孔 29‧‧‧Positioning holes
51‧‧‧焊錫球 51‧‧‧ solder balls
63‧‧‧接點接腳 63‧‧‧Contact pins
64‧‧‧定位銷 64‧‧‧Locating pins
221‧‧‧傾斜壁 221‧‧‧ sloping wall
222‧‧‧垂直壁 222‧‧‧ vertical wall
第1圖係表示本發明之半導體搬送測試治具的安裝於搬送框的狀態之斜視圖。 Fig. 1 is a perspective view showing a state in which the semiconductor transfer test jig of the present invention is attached to a transfer frame.
第2圖係本發明之半導體搬送測試治具的上面斜視圖(a)及下面斜視圖(b)。 Fig. 2 is a top perspective view (a) and a lower oblique view (b) of the semiconductor transport test fixture of the present invention.
第3圖係本發明的第1實施方式之半導體搬送測試治具和事前測試用插座的嵌合前之部分剖面圖。 Fig. 3 is a partial cross-sectional view showing the semiconductor transfer test fixture and the pre-test test socket of the first embodiment of the present invention before being fitted.
第4圖係裝置底面薄膜的半導體搬送測試治具之下面斜視圖。 Figure 4 is a bottom perspective view of the semiconductor transfer test fixture of the bottom film of the device.
第5圖係IC側焊墊的形狀的上面圖(上段)及橫剖面圖(下段)。 Fig. 5 is a top view (upper section) and a cross-sectional view (lower section) of the shape of the IC side pad.
第6圖係本發明的第2實施方式之半導體搬送測試治具和事前測試用插座的嵌合前之部分剖面圖。 Fig. 6 is a partial cross-sectional view showing the semiconductor transfer test fixture and the pre-test test socket before the fitting of the second embodiment of the present invention.
第7圖係本發明的第3實施方式之半導體搬送測試治具和事前測試用插座的嵌合前之部分剖面圖。 Fig. 7 is a partial cross-sectional view showing the semiconductor transfer test fixture and the pre-test test socket before the fitting of the third embodiment of the present invention.
21‧‧‧框部 21‧‧‧ Frame Department
24‧‧‧控制板 24‧‧‧Control panel
25‧‧‧底面薄膜 25‧‧‧ bottom film
27‧‧‧插座側焊墊(第2焊墊) 27‧‧‧Socket side pad (2nd pad)
29‧‧‧定位孔 29‧‧‧Positioning holes
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101117565A TWI577998B (en) | 2012-05-17 | 2012-05-17 | Semiconductor transport test fixture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101117565A TWI577998B (en) | 2012-05-17 | 2012-05-17 | Semiconductor transport test fixture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201348717A TW201348717A (en) | 2013-12-01 |
| TWI577998B true TWI577998B (en) | 2017-04-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW101117565A TWI577998B (en) | 2012-05-17 | 2012-05-17 | Semiconductor transport test fixture |
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| Country | Link |
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| TW (1) | TWI577998B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009139370A (en) * | 2007-12-03 | 2009-06-25 | Samsung Electronics Co Ltd | Test carrier, test device having the same, and test method of semiconductor device |
| TWM386640U (en) * | 2010-01-11 | 2010-08-11 | Hon Hai Prec Ind Co Ltd | Electrical connector |
| CN101825650A (en) * | 2009-03-02 | 2010-09-08 | 台湾薄膜电晶体液晶显示器产业协会 | Joint detecting structure and joint structure |
| TW201037314A (en) * | 2009-04-13 | 2010-10-16 | Nichepac Technology Inc | A singulated bare die testing fixture |
| JP2010266344A (en) * | 2009-05-15 | 2010-11-25 | Elpida Memory Inc | Conveying carrier tool for semiconductor device testing device |
-
2012
- 2012-05-17 TW TW101117565A patent/TWI577998B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009139370A (en) * | 2007-12-03 | 2009-06-25 | Samsung Electronics Co Ltd | Test carrier, test device having the same, and test method of semiconductor device |
| CN101825650A (en) * | 2009-03-02 | 2010-09-08 | 台湾薄膜电晶体液晶显示器产业协会 | Joint detecting structure and joint structure |
| TW201037314A (en) * | 2009-04-13 | 2010-10-16 | Nichepac Technology Inc | A singulated bare die testing fixture |
| JP2010266344A (en) * | 2009-05-15 | 2010-11-25 | Elpida Memory Inc | Conveying carrier tool for semiconductor device testing device |
| TWM386640U (en) * | 2010-01-11 | 2010-08-11 | Hon Hai Prec Ind Co Ltd | Electrical connector |
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| Publication number | Publication date |
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| TW201348717A (en) | 2013-12-01 |
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